W83791D

W83791D/W83791G Winbond H/W Monitoring IC W83791D/G W83791D/W83791G Data Sheet Revision History PAGES DATES VERSION VERSION ON WEB MAIN CONTENTS 1 2 3 n.a. n.a. P.7 P.34 P.43/44 01/Jan 01/Jan 0.5 0.51 n.a. n.a. n.a. All version before 0.50 are for internal use. First publication. (1) Revise SLOTOCC# pin description. (2) Add SMI# /IRQ for Voltage/Fan description. Register Index 1Ah~1Fh revised. This update is for C version IC. 1) Add EVNTRAP1-5 polarity (Index Ah ) 2) Add VID protection control bit (Index15h bit5) 3) Add FAN1-3/PWMOUT1-3 as GPIn data register. (Index 95h/97h) 4) SMARTFANTM step up/down time registers exchanged. 5) Add a bit (Index A6 bit7) to know either speech or GPIO function did you use. 6) Pin44 (SMI#/LEDOUT) is a multifunction, it is programmable. 7) EVENTRAP can as GPIO by programming Index A6h bit0-4 . 8) Updated V0.17 schematics adding LEDOUT circuit for SMI# (Pin 44) Repaginate datasheet Change all version include version on web to 1.0 Add lead-free package version 4 5 01/Mar 01/May 0.6 0.7 n.a. n.a. P. 40 P. 42 P. 60/61 P. 58/59 P. 66 P. 66 P. 66 P. 87 6 7 8 All pages n.a. n.a. 01/Aug 02/Apr 06/Apr 0.71 1.0 1.1 n.a. 1.0 1.1 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. -I- Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G Table of Contents1. 2. GENERAL DESCRIPTION............................................................................................................ 1 FEATURES.................................................................................................................................... 3 2.1 Monitoring Items .................................................................................................................. 3 2.2 Address Resolution Protocol (ARP) and Alert-Standard Forum (ASF) ............................... 3 2.3 Speech Items ....................................................................................................................... 3 2.4 Actions Enabling .................................................................................................................. 3 2.5 Enhance Monitoring VID function ........................................................................................ 4 2.6 General ................................................................................................................................ 4 2.7 Package ............................................................................................................................... 4 KEY SPECIFICATIONS................................................................................................................. 4 PIN CONFIGURATION.................................................................................................................. 5 PIN DESCRIPTION ....................................................................................................................... 6 FUNCTION DESCRIPTION ........................................................................................................ 11 6.1 General Description ........................................................................................................... 11 6.2 Access Interface ................................................................................................................ 11 6.2.1 The first serial bus access timing ....................................................................................... 11 General Description............................................................................................................ 12 Event Trigger Queue .......................................................................................................... 12 Connection of EEPROM..................................................................................................... 14 Speaker Output .................................................................................................................. 14 3. 4. 5. 6. 6.3 Speech Function ................................................................................................................ 12 6.3.1 6.3.2 6.3.3 6.3.4 6.4 6.5 6.6 Address Resolution Protocol (ARP) Introduction............................................................... 15 ASF (Alert Standard Format) Introduction ......................................................................... 17 6.5.1 6.6.1 6.6.2 Platform Event Trap (PET) ................................................................................................. 17 Monitor over 4.096V voltage:.............................................................................................. 20 Monitor negative voltage: ................................................................................................... 20 Fan speed count................................................................................................................. 21 Fan speed control............................................................................................................... 22 Smart Fan Control .............................................................................................................. 23 Monitor temperature from thermistor: ................................................................................. 25 Monitor temperature from Pentium IITM thermal diode or bipolar transistor 2N3904 ......... 25 SMI# interrupt for W83791D Voltage.................................................................................. 25 SMI# interrupt for W83791D Fan........................................................................................ 26 SMI# interrupt for W83791D/G temperature sensor 1/2/3 .................................................. 26 Over-Temperature (OVT#) for W83791D/G temperature sensor 1/2/3............................... 27 Analog Inputs ..................................................................................................................... 19 6.7 FAN Speed Count and FAN Speed Control ...................................................................... 21 6.7.1 6.7.2 6.7.3 6.8 Temperature Measurement Machine................................................................................. 24 6.8.1 6.8.2 6.8.3 6.8.4 6.8.5 6.8.6 7. CONTROL AND STATUS REGISTER........................................................................................ 29 7.1 Speech Flash Memory Address Registers ⎯ Index 00h-02h (Bank 0)............................. 29 7.2 Speech Flash Memory Data Registers ⎯ Index 03h-06h (Bank 0) .................................. 29 7.3 Speech Flash Memory Control Register ⎯ Index 07h (Bank 0)........................................ 29 7.4 Event Trigger Timeout Register ⎯ Index 08h (Bank 0)..................................................... 30 Publication Release Date: April 14, 2006 Revision 1.1 - II - W83791D/G 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 7.28 7.29 7.30 7.31 7.32 7.33 7.34 7.35 7.36 7.37 7.38 7.39 7.40 7.41 7.42 7.43 7.44 7.45 7.46 Speech Programmable Trigger Register ⎯ Index 09h (Bank 0) ....................................... 30 Speech Input Trigger Property Register ⎯ Index 0Ah (Bank 0) ....................................... 31 Reserved Register ⎯ Index 0Bh (Bank 0)......................................................................... 31 VID and VCORE voltage Property Register ⎯ Index 0Ch (Bank 0) ................................. 31 Speech Flash Memory Read Data Registers ⎯ Index 0Dh-0Eh (Bank 0)........................ 31 Reserved Register ⎯ Index 0Fh (Bank 0)......................................................................... 31 VID Control/Status Register ⎯ Index 10h (Bank 0) .......................................................... 31 Entry Disable VID Output Control Register ⎯ Index 11h (Bank 0) ................................... 32 VID Output Tolerance/Limit Register ⎯ Index 12h (Bank 0)............................................. 32 GPIO Control Register I ⎯ Index 13h (Bank 0)................................................................. 32 GPIO Data/Status Register I ⎯ Index 14h (Bank 0) ......................................................... 33 GPIO Control Register II ⎯ Index 15h (Bank 0)................................................................ 33 GPIO Output Data and Status Register II ⎯ Index 16h (Bank 0) ..................................... 34 LED Control Register ⎯ Index 17h (Bank 0)..................................................................... 34 User Defined Registers ⎯ Index 18h-1Ch (Bank 0).......................................................... 35 Speech Control Register 1 ⎯ Index 1Dh (Bank 0)............................................................ 35 Speech Control Register 2 ⎯ Index 1Eh (Bank 0) ............................................................ 36 Speech Control Register 3 ⎯ Index 1Fh (Bank 0) ............................................................ 36 Value RAM ⎯ Index 20h- 3Fh (Bank 0) ............................................................................ 37 Configuration Register ⎯ Index 40h (Bank 0) ................................................................... 38 Interrupt Status Register 1 ⎯ Index 41h (Bank 0)............................................................. 39 Interrupt Status Register 2 ⎯ Index 42h (Bank 0)............................................................. 39 SMI# Mask Register 1 ⎯ Index 43h (Bank 0) ................................................................... 40 SMI# Mask Register 2 ⎯ Index 44h (Bank 0) ................................................................... 40 IRQ Mask Register 1 ⎯ Index 45h (Bank 0) ..................................................................... 41 IRQ Mask Register 2 ⎯ Index 46h (Bank 0) ..................................................................... 41 VID/Fan Divisor Register ⎯ Index 47h (Bank 0) ............................................................... 42 Serial Bus Address Register ⎯ Index 48h (Bank 0).......................................................... 42 Voltage ID (VID4) & Device ID ⎯ Index 49h (Bank 0) ...................................................... 42 Temperature 2 and Temperature 3 Serial Bus Address Register ⎯ Index4Ah (Bank 0).. 43 Pin Control Register ⎯ Index4Bh (Bank 0) ....................................................................... 43 SMI#/OVT# Property Select ⎯ Index 4Ch (Bank 0).......................................................... 44 FAN 1- 3 IN/OUT and BEEP Control Register ⎯ Index 4Dh (Bank 0)............................. 45 Bank Select ⎯ Index 4Eh (Bank 0) ................................................................................... 46 Winbond Vendor ID ⎯ Index 4Fh (Bank 0) ....................................................................... 46 Winbond Test Register ⎯ Index 50h - 55h (Bank 0)......................................................... 46 BEEP Control Register 1 ⎯ Index 56h (Bank 0) ............................................................... 46 BEEP Control Register 2 ⎯ Index 57h (Bank 0) ............................................................... 47 Chip ID ⎯ Index 58h (Bank 0).......................................................................................... 47 Diode Selection Register ⎯ Index 59h (Bank 0) ............................................................... 47 Reserved ⎯ Index 5Ah - (Bank 0).................................................................................... 48 FANIN 4/5 Control ⎯ Index 5Bh (Bank 0) ......................................................................... 48 Publication Release Date: April 14, 2006 Revision 1.1 - III - W83791D/G 7.47 FAN 4/5 Divisor Control ⎯ Index 5Ch (Bank 0) ................................................................ 48 7.48 VBAT Monitor Control Register ⎯ Index 5Dh (Bank 0)..................................................... 49 7.49 ACPI Temperature Increment Register ⎯ Index 5Eh ....................................................... 49 7.50 Reserved ⎯ Index 5Fh (Bank 0) ....................................................................................... 50 7.51 FAN 1 Pre-Scale Register ⎯ Index 80h (Bank 0) ............................................................. 50 7.52 FAN 1 Duty Cycle Select Register ⎯ 81h (Bank 0) .......................................................... 50 7.53 FAN 2 Pre-Scale Register ⎯ Index 82h (Bank 0) ............................................................. 51 7.54 FAN2 Duty Cycle Select Register ⎯ Index 83h (Bank 0).................................................. 51 7.55 FAN 1/2 Configuration Register ⎯ Index 84h (Bank 0)..................................................... 51 7.56 Fan 1 Target Temperature Register/Target Fan 1 Speed Control Register ⎯ Index 85h (Bank 0) ....................................................................................................................................... 52 7.57 Fan 2 Target Temperature Register/Target Fan 2 Speed Control Register ⎯ Index 86h (Bank 0) ....................................................................................................................................... 53 7.58 Tolerance of Fan1/2 Target Temperature or Speed Register ⎯ Index 87h (Bank0) ........ 53 7.59 Fan 1 PWM Stop Duty Cycle Register ⎯ Index 88h (Bank 0) .......................................... 54 7.60 Fan 2 PWM Stop Duty Cycle Register ⎯ 89h (Bank 0) .................................................... 54 7.61 Fan 1 Start-up Duty Cycle Register ⎯ Index 8Ah (Bank 0) .............................................. 54 7.62 Fan 2 Start-up Duty Cycle Register ⎯ Index 8Bh (Bank 0) .............................................. 54 7.63 Fan 1 Stop Time Register ⎯ Index 8Ch (Bank 0) ............................................................. 54 7.64 Fan 2 Stop Time Register ⎯ Index 8Dh (Bank 0) ............................................................. 55 7.65 Fan 1/2/3 Step Down Time Register ⎯ Index 8Eh (Bank 0) ............................................. 55 7.66 Fan 1/2/3 Step Up Time Register ⎯ Index 8Fh (Bank 0).................................................. 55 7.67 Temperature Sensor 1 (VTIN1) Offset Register ⎯ Index 90h (Bank 0)............................ 55 7.68 Temperature Sensor 2 (VTIN2) Offset Register ⎯ Index 91h (Bank 0)............................ 56 7.69 Temperature Sensor 3 (VTIN3) Offset Register ⎯ Index 92h (Bank 0)............................ 56 7.70 FAN 3 Pre-Scale Register ⎯ Index 93h (Bank 0) ............................................................. 57 7.71 FAN 3 Duty Cycle Select Register ⎯ Index 94h (Bank 0)................................................. 57 7.72 FAN 3 Configuration Register ⎯ Index 95h (Bank 0)........................................................ 58 7.73 Fan 3 Target Temperature Register/Target Fan 3 Speed Control Register ⎯ Index 96h (Bank 0) ....................................................................................................................................... 58 7.74 Tolerance of Fan 3 Target Temperature or Speed Register ⎯ Index 97h (Bank 0) ......... 59 7.75 Fan 3 PWM Stop Duty Cycle Register ⎯ Index 98h (Bank 0) .......................................... 59 7.76 Fan 3 Start-up Duty Cycle Register ⎯ Index 99h (Bank 0)............................................... 60 7.77 Fan 3 Stop Time Register ⎯ Index 9Ah (Bank 0) ............................................................. 60 7.78 Interrupt Status Register III ⎯ Index 9Bh (Bank 0) ........................................................... 60 7.79 SMI# Mask Register III ⎯ Index 9Ch (Bank 0).................................................................. 61 7.80 Interrupt Mask Register III ⎯ Index 9Dh (Bank 0)............................................................. 61 7.81 FAN4_PRE_SCALE register ⎯ Index 9Eh (Bank 0)......................................................... 62 7.82 FAN5_PRE_SCALE register ⎯ Index 9Fh (Bank 0) ......................................................... 62 7.83 FAN 4 Duty Cycle Select Register—A0h (Bank 0) ............................................................ 63 7.84 FAN 5 Duty Cycle Select Register—A1h (Bank 0) ............................................................ 63 7.85 BEEP Control Register 3 ⎯ Index A3h (Bank 0)............................................................... 63 Publication Release Date: April 14, 2006 Revision 1.1 - IV - W83791D/G 7.86 Speech Flash Memory Read Data Registers ⎯ Index A4h-A5h (Bank 0) ........................ 64 7.87 EVNTRAP1- 5 and GPIO 5-9 Select ⎯ Index A6h (Bank 0)............................................. 64 7.88 Flash Page count ⎯ Index A7h (Bank 0) .......................................................................... 65 7.89 Real Time Hardware Status Register I ⎯ Index A9h (Bank 0).......................................... 65 7.90 Real Time Hardware Status Register II ⎯ Index AAh (Bank 0) ........................................ 65 7.91 Real Time Hardware Status Register III ⎯ Index ABh (Bank 0) ....................................... 66 7.92 Revered ⎯ Index AC - AFh (Bank 0) ................................................................................ 67 7.93 Value RAM 2⎯ Index B0h – B7h (BANK 0) ...................................................................... 67 7.94 Temperature Sensor 2 Temperature (High Byte) Register ⎯ Index C0h (Bank 0)........... 67 7.95 Temperature Sensor 2 Temperature (Low Byte) Register ⎯ Index C1h (Bank 0)............ 67 7.96 Temperature Sensor 2 Configuration Register ⎯ Index C2h (Bank 0) ............................. 68 7.97 Temperature Sensor 2 Hysteresis (High Byte) Register ⎯ Index C3h (Bank 0)............... 68 7.98 Temperature Sensor 2 Hysteresis (Low Byte) Register ⎯ Index C4h (Bank 0) ............... 68 7.99 Temperature Sensor 2 Over-temperature (High Byte) Register ⎯ Index C5h (Bank 0)... 68 7.100 Temperature Sensor 2 Over-temperature (Low Byte) Register ⎯ Index C6h (Bank 0).... 68 7.101 Temperature Sensor 3 Temperature (High Byte) Register ⎯ Index C8h (Bank 0)........... 69 7.102 Temperature Sensor 3 Temperature (Low Byte) Register ⎯ Index C9h (Bank 0)............ 69 7.103 Temperature Sensor 3 Configuration Register ⎯ Index CAh (Bank 0)............................. 69 7.104 Temperature Sensor 3 Hysteresis (High Byte) Register ⎯ Index CBh (Bank 0) .............. 69 7.105 Temperature Sensor 3 Hysteresis (Low Byte) Register ⎯ Index CCh (Bank 0)............... 69 7.106 Temperature Sensor 3 Over-temperature (High Byte) Register ⎯ Index CDh (Bank 0) .. 70 7.107 Temperature Sensor 3 Over-temperature (Low Byte) Register ⎯ Index CEh (Bank 0) ... 70 ARP (ADDRESS RESOLUTION PROTOCOL) USE REGISTER DEFINED.............................. 71 8.1 Unique Device Identifier (UDID) -- 20h-2Fh (Bank 1)........................................................ 71 8.2 ASF Sensor Environmental Event ..................................................................................... 72 8.2.1 8.2.2 8.2.3 8.2.4 Temperature: Get Event Data message ............................................................................. 72 Voltage: Get Event Data message ..................................................................................... 75 Fan: Get Event Data message ........................................................................................... 77 Case Intrusion: Get Event Data message .......................................................................... 79 ASF Upper/Lower Temperature Registers: ........................................................................ 80 Sensor device: (SMBus Address, Read/Write)................................................................... 81 Relative Entity ID Table: ..................................................................................................... 81 Entity Instance Register...................................................................................................... 82 8. 8.3 ASF Response Registers ⎯ Index 40h-7Fh (Bank 1)...................................................... 80 8.3.1 8.3.2 8.3.3 8.3.4 9. 8.4 BJT RT-Table - 50h-57h (Bank 7) ⎯ TEST mode only..................................................... 82 ELECTRICAL CHARACTERISTICS ........................................................................................... 83 9.1 Absolute Maximum Ratings ............................................................................................... 83 9.2 DC Characteristics ............................................................................................................. 83 9.3 AC Characteristics ............................................................................................................. 85 9.3.1 Serial Bus Timing Diagram................................................................................................. 85 10. 11. HOW TO READ THE TOP MARKING ........................................................................................ 86 PACKAGE SPECIFICATION....................................................................................................... 87 -V- Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 1. GENERAL DESCRIPTION W83791D/G is an evolving version of the W83782D/G --- Winbond's most popular hardware status monitoring IC. Besides the conventional functions of W83782D/G, W83791D/G uniquely provides several innovative features such as speech function, ASF sensor compliant, SMBus 2.0 ARP command compatible, VID table selection trapping, and 5VID output control. Conventionally, W83791D/G can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stably and efficiently. As for data access, W83791D/G provides slave SMBus 2.0 interface which can reply PEC (Packet Error Code) when as ASF sensor. An 8-bit analog-to-digital converter (ADC) was built inside W83791D/G. W83791D/G can simultaneously monitor 10 analog voltage inputs (including power VDD/5VSB monitoring), 5 fan tachometer inputs, 3 remote temperatures, and one case open detection signal. The sense of remote temperature can be performed by thermistors, 2N3904 NPN-type transistors, or directly from IntelTM CPU with thermal diode output. W83791D/G provides 3 PWM (pulse width modulation) outputs for two modes of smart fan control- Thermal CruiseTM mode and Speed Cruise mode. Under Thermal mode, temperatures of CPU and the system can be maintained within specific CruiseTM programmable ranges under the hardware control. Speed Cruise , namely, is to keep the fan operate in the specific programmable r.p.m. As for warning mechanism, W83791D/G provides speech voice warning, beep tone warning, and SMI#, OVT#, IRQ signals for system protection events. Additionally, 5 VID inputs are provided to read the VID of CPU (i.e. PentiumTM II/III) if applicable. These VID inputs provide the information of Vcore voltage that CPU expects. Furthermore, W83791D/G provides programmable VID output control to alter the voltage CPU consumes. W83791D/G also uniquely provides an optional feature: early stage (before BIOS was loaded) beep / speech warning to detect if the fatal elements present --- Vcore or +3.3V voltage fail and thus the system can not be boomed up. If the VSB power on setting refers to Intel VRM 9.x, the VID table within W83791D/G will be according to the new one. W83791D/G also has 2 specific pins to provide selectable address setting for application of multiple devices (up to 4 devices) wired through I2CTM interface. W83791D/G speech function is enabled by building in a programmable speech synthesizer with a 9-bit current DAC output as well as a connectable external flash memory for storing voice data. W83791D/G supports 1 CPU present or absent event trap, 5 external event traps, 17 hardware monitor event traps (10 analog voltage, 3 fan tachometer, 3 remote temperature, 1 case open) and 128 internal programmable event traps, amounting to 151 different speech outputs. If more than two events happen simultaneously, the priority set is: SLOTOCC# > EVNTRP1 > EVNTRP2 > EVNTRP3 > EVNTRP4 > EVNTRP5 > 128 Programmable events (Bank0 index 09h) > 17 Hardware status events. Voice data stored in the external flash memory interface with Winbond W55FXX is flexible to change by Winbond application software and on-line programming flash data is provided also. Besides, an external resistor is added to provide ring oscillator. When you do not use the speech function, W83791D/G provides a set of flexible I/O control functions to the system designer through a set of General Purpose I/O ports. These GPIO ports may serve as simple I/O or may be individually configured to provide a pre-defined alternate function. If pin 9 (SPEECH_SEL) is trapped to high at VSB power on, this function will be active. -1- Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G W83791D/G can uniquely serve as an ASF sensor to respond to ASF master’s request for the implementation of network management in OS-absent state. Through W83791D/G compliance with ASF sensor spec, network server is able to monitor the environmental status of the client in OS-absent state by PET frame values returned from W83791D/G, such as temperatures, voltages, fan speed, and case open. Moreover, W83791D/G supports SMBus 2.0 ARP command to solve the problem of address conflicts by dynamically assigning a new unique address to W83791D/G after W83791D/G’s UDID is sent. Through the application software or BIOS, the users can read all the monitored parameters of the system from time to time. A pop-up warning can also be activated when the monitored item is out of the proper/preset range. The application software could be Winbond's Hardware DoctorTM, IntelTM LDCM (LanDesk Client Management), or other management application software. Besides, the users can set up the upper and lower limits (alarm thresholds) of these monitored parameters and activate one programmable and maskable interrupts. An optional beep tone could be used as a warning signal when the monitored parameters are out of the preset range. -2- Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 2. FEATURES 2.1 Monitoring Items • 10 voltage inputs --- Typical for VCORE, +3.3V, +12V, -12V, +5V, -5V, +5VSB, VBAT, and two reserved • 5 fan speed monitoring inputs • 3 temperature inputs from remote thermistors, 2N3904 NPN-type transistors or PentiumTM II (Deschutes) thermal diode output • Case open detection input • WATCHDOG comparison of all monitored values • Programmable hysteresis and setting points (alarm thresholds) for all monitored items 2.2 • • • • • Address Resolution Protocol (ARP) and Alert-Standard Forum (ASF) Support System Management Bus (SMBus) version 2.0 specification Comply with hardware sensor slave ARP (Address Resolution Protocol) Response sensor type ARP command Response ASF command --- Get Event Data , Get Event Status Comply with ASF sensors (Monitoring fan speed, voltage, temperature, and case open) 2.3 • • • • • • • • • • Speech Items Programmable speech synthesizer with new high fidelity synthesis algorithm Build in 8-bit current D/A converter 1 CPU present or absent trigger input 5 External trigger inputs 128 Internal programmable trigger inputs 17 H/W Monitor event trigger inputs Programmable 0-255 seconds timeout trigger inputs for firmware or software Instruction cycle is +31 degree C 01,1110 => +30 degree C : 00,0001 => +1 degree C 00,0000 => +0 degree C 11,1111 => -1 degree C 11,1110 => -2 degree C : 10,0000 => -32 degree - 55 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 7.68 Temperature Sensor 2 (VTIN2) Offset Register ⎯ Index 91h (Bank 0) Power on default: 00h BIT NAME ATTRIBUTE DESCRIPTION 7-6 5-0 Reserved OFFSET2[5:0] R/W R/W Reserved. Temperature2 (VTIN2) base temperature. The temperature is added by both monitor value and offset value. 01,1111 => +31 degree C 01,1110 => +30 degree C : 00,0001 => +1 degree C 00,0000 => +0 degree C 11,1111 => -1 degree C 11,1110 => -2 degree C : 10,0000 => -32 degree 7.69 Temperature Sensor 3 (VTIN3) Offset Register ⎯ Index 92h (Bank 0) Power-on default: 00h BIT NAME ATTRIBUTE DESCRIPTION 7-6 5-0 Reserved OFFSET3[5:0] R/W R/W Reserved. Temperature3 (VTIN3) base temperature. The temperature is added by both monitor value and offset value. 01,1111 => +31 degree C 01,1110 => +30 degree C : 00,0001 => +1 degree C 00,0000 => +0 degree C 11,1111 => -1 degree C 11,1110 => -2 degree C : 10,0000 => -32 degree - 56 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 7.70 FAN 3 Pre-Scale Register ⎯ Index 93h (Bank 0) Power on default: 01h BIT NAME ATTRIBUTE DESCRIPTION 7 PWM_CLK_SEL3 R/W PWM 3 Input Clock Select. This bit select Fan 3 input clock to pre-scale divider. 0: 3 MHz 1: 125 KHz Fan 3 Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 0 transfers the input clock directly to counter. The maximum divider is 128 (7Fh). 00h : divider is 1 01h : divider is 2 02h : divider is 3 : : 6-0 PRE_SCALE3[6:0] R/W PWM frequency = (Input clock / pre-scale) / 256 7.71 FAN 3 Duty Cycle Select Register ⎯ Index 94h (Bank 0) Power on default: FFh BIT NAME ATTRIBUTE DESCRIPTION 7-0 F3_DC[7:0] R/W Fan 3 Duty Cycle. This 8-bit register determines the number of input clock cycles, out of 256-cycle period, during which the PWM output is high. During smart fan3 control mode, read this register would return smart fan duty cycle. 00h: PWM output is always logical Low. FFh: PWM output is always logical High. XXh: PWM output logical High percentage is (XX/256*100%) during one cycle. - 57 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 7.72 FAN 3 Configuration Register ⎯ Index 95h (Bank 0) Power on default: 00h BIT NAME ATTRIBUTE DESCRIPTION 7 PWM3INV RO PWMOUT3 input value if PWMOUT3 as GPIn. Return ‘1’, the pin 23 status is logic high signal. Read ‘0’, pin23 is logic low signal. PWMOUT2 input value if PWMOUT2 as GPIn. Return ‘1’, the pin 11 status is logic high signal. Read ‘0’, pin11 is logic low signal. PWMOUT1 input value if PWMOUT1 as GPIn. Return ‘1’, the pin 10 status is logic high signal. Read ‘0’, pin10 is logic low signal. Reserved FAN 3 PWM Control Type. 00 - Manual PWM Control. (Default) 01 - Thermal Cruise mode. 10 - Fan Speed Cruise Mode. 11 - Reserved. Reserved Enable Fan 3 as Output Buffer. Set to 1, FANPWM3 can drive logical high or logical low. Default Pin 23 (PWMOUT3) is open-drain. 6 PWM2INV RO 5 PWM1INV RO 4 3-2 Reserved FAN3_TYPE Reserved R/W 1 0 Reserve FAN3_OB R/W R/W 7.73 Fan 3 Target Temperature Register/Target Fan 3 Speed Control Register ⎯ Index 96h (Bank 0) Power on default: 00h VTIN3 target temperature register for Thermal Cruise mode. BIT NAME ATTRIBUTE DESCRIPTION 7 6-0 Reserved FAN_TAR_T3[6:0] R/W R/W Reserved. Fan 3 Target Temperature. Only for Thermal Cruise mode. When the temperature 3 over the target temperature add tolerance temperature, the smart fan 3 duty cycle will up count until the duty cycle obtain to FFh. DESCRIPTION Fan 3 target speed register for Fan Speed Cruise mode. BIT NAME ATTRIBUTE 7-0 FAN_TAR_CNT3 [7:0] R/W Target Fan 3 Speed Control. Only for Fan Speed Cruise Mode. When the fan 3 monitored Fan 3 Count over the target Fan Count add tolerance, the fan duty cycle will up/down count until the duty cycle have been corresponding the monitored speed count. Publication Release Date: April 14, 2006 Revision 1.1 - 58 - W83791D/G 7.74 Tolerance of Fan 3 Target Temperature or Speed Register ⎯ Index 97h (Bank 0) Power on default: 00h Tolerance of VTIN3 target temperature register BIT NAME ATTRIBUTE DESCRIPTION 7 FAN3INV RO FAN 3 input value if FANINC3 sets to 1. Return ‘1’, the pin 18 status is logic high signal. Read ‘0’, pin18 is logic low signal. FAN 2 input value if FANINC2 sets to 1. Return ‘1’, the pin 19 status is logic high signal. Read ‘0’, pin19 is logic low signal. FAN 1 input value if FANINC1 sets to 1. Return ‘1’, the pin 20 status is logic high signal. Read ‘0’, pin20 is logic low signal. Reserved Tolerance of Fan 3 Target Temperature. Only for Thermal Cruise mode. 6 FAN2INV RO 5 FAN1INV RO 4 3-0 Reserved TOL_T3[3:0] Reserved R/W Tolerance of Fan 3 target speed register. BIT NAME ATTRIBUTE DESCRIPTION 7 FAN3INV RO FAN 3 input value if FANINC3 sets to 1. Return ‘1’, the pin 18 status is logic high signal. Read ‘0’, pin18 is logic low signal. FAN 2 input value if FANINC2 sets to 1. Return ‘1’, the pin 19 status is logic high signal. Read ‘0’, pin19 is logic low signal. FAN 1 input value if FANINC1 sets to 1. Return ‘1’, the pin 20 status is logic high signal. Read ‘0’, pin20 is logic low signal. Reserved Tolerance of Fan 3 Target Speed Count. Only for Fan Speed Cruise mode. 6 FAN2INV RO 5 FAN1INV RO 4 3-0 Reserved TOL_FS3[3:0] Reserved R/W 7.75 Fan 3 PWM Stop Duty Cycle Register ⎯ Index 98h (Bank 0) Power on default: 01h BIT NAME STOP_DC3[7:0] ATTRIBUTE DESCRIPTION 7-0 R/W In Thermal Cruise mode, PWM duty will be 0 if it decreases to under this value. This register should be written a nonzero minimum PWM stop duty cycle. - 59 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 7.76 Fan 3 Start-up Duty Cycle Register ⎯ Index 99h (Bank 0) Power on default: 01h BIT NAME ATTRIBUTE DESCRIPTION 7-0 START_DC3[7:0] R/W In Thermal Cruise mode, PWM duty will increase from 0 to this register value to provide a minimum duty cycle to turn on the fan. This register should be written a fan start-up duty cycle. 7.77 Fan 3 Stop Time Register ⎯ Index 9Ah (Bank 0) Power on default: 3Ch BIT NAME STOP_TIME3[7:0] ATTRIBUTE DESCRIPTION 7-0 R/W In Thermal Cruise mode, this register determines the time of which PWM duty is from stop duty cycle to 0 duty cycle. The unit of this register is 0.1 second. The default value is 6 seconds. 7.78 Interrupt Status Register III ⎯ Index 9Bh (Bank 0) Power on default: 00h BIT NAME ATTRIBUTE DESCRIPTION 7 6 5 4 3 2 Reserved FAN5 FAN4 VBAT VSB TART3 Read Only Read Only Read Only Read Only Read Only Reserved. A one indicates the fan count limit of FAN5 has been exceeded. A one indicates the fan count limit of FAN4 has been exceeded. A one indicates a high or low limit of VBAT has been exceeded. A one indicates a high or low limit of VSB has been exceeded. Target Temperature 3 Status. A one indicates VTIN3 with Fan 3 full speed can not be in the specific range after 3 minutes. Target Temperature 2 Statue. A one indicates VTIN2 temperature with Fan 2 full speed can not be in the specific range after 3 minutes. Target Temperature 1 Statue. A one indicates VTIN1 temperature with Fan 1 full speed can not be in the specific range after 3 minutes. 1 TART2 Read Only 0 TART1 Read Only - 60 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 7.79 SMI# Mask Register III ⎯ Index 9Ch (Bank 0) Power on default: 00h BIT NAME ATTRIBUTE DESCRIPTION 7 6 5 4 3 2 1 0 Reserved FAN5 FAN4 VBAT VSB TART3 TART2 TART1 R/W R/W R/W R/W R/W R/W R/W Reserved. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. A one disables the corresponding interrupt status bit for SMI# interrupt. (Target temperature 3) A one disables the corresponding interrupt status bit for SMI# interrupt. (Target temperature 2) A one disables the corresponding interrupt status bit for SMI# interrupt. (Target temperature 1) 7.80 Interrupt Mask Register III ⎯ Index 9Dh (Bank 0) Power on default: 00h BIT NAME ATTRIBUTE DESCRIPTION 7 6 5 4 3 2 1 0 Reserved FAN5 FAN4 VBAT VSB TART3 TART2 TART1 R/W R/W R/W R/W R/W R/W R/W Reserved. A one disables the corresponding interrupt status bit for IRQ interrupt. A one disables the corresponding interrupt status bit for IRQ interrupt. A one disables the corresponding interrupt status bit for IRQ interrupt. A one disables the corresponding interrupt status bit for IRQ interrupt. A one disables the corresponding interrupt status bit for IRQ interrupt. (Target temperature 3) A one disables the corresponding interrupt status bit for IRQ interrupt. (Target temperature 2) A one disables the corresponding interrupt status bit for IRQ interrupt. (Target temperature 1) - 61 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 7.81 FAN4_PRE_SCALE register ⎯ Index 9Eh (Bank 0) Power on default: 01h BIT NAME ATTRIBUTE DESCRIPTION 7 PWM_CLK_SEL4 R/W PWM 4 Input Clock Select. This bit select Fan 4 input clock to pre-scale divider. 0: 3 MHz 1: 125 KHz Fan 4 Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 0 transfers the input clock directly to counter. The maximum divider is 128 (7Fh). 00h : divider is 1 01h : divider is 2 02h : divider is 3 : : 6:0 PRE_SCALE4 [6:0] R/W PWM frequency = (Input clock / pre-scale) / 256 7.82 FAN5_PRE_SCALE register ⎯ Index 9Fh (Bank 0) Power on default: 01h BIT NAME ATTRIBUTE DESCRIPTION 7 PWM_CLK_SEL5 Read /Write PWM 5 Input Clock Select. This bit select Fan 5 input clock to pre-scale divider. 0: 3 MHz 1: 125 KHz Fan 5 Input Clock Pre-Scale. The divider of input clock is the number defined by pre-scale. Thus, writing 0 transfers the input clock directly to counter. The maximum divider is 128 (7Fh). 00h : divider is 1 01h : divider is 2 02h : divider is 3 : : 6:0 PRE_SCALE5[6:0] Read /Write PWM frequency = (Input clock / pre-scale) / 256 - 62 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 7.83 FAN 4 Duty Cycle Select Register—A0h (Bank 0) Power on default: FFh BIT NAME ATTRIBUTE DESCRIPTION 7-0 F4_DC[7:0] R/W Fan 4 Duty Cycle. This 8-bit register determines the number of input clock cycles, out of 256-cycle period, during which the PWM output is high. During smart fan3 control mode, read this register would return smart fan duty cycle. 00h: PWM output is always logical Low. FFh: PWM output is always logical High. XXh: PWM output logical High percentage is (XX/256*100%) during one cycle. 7.84 FAN 5 Duty Cycle Select Register—A1h (Bank 0) Power on default: FFh BIT NAME ATTRIBUTE DESCRIPTION 7-0 F5_DC[7:0] R/W Fan 5 Duty Cycle. This 8-bit register determines the number of input clock cycles, out of 256-cycle period, during which the PWM output is high. During smart fan3 control mode, read this register would return smart fan duty cycle. 00h: PWM output is always logical Low. FFh: PWM output is always logical High. XXh: PWM output logical High percentage is (XX/256*100%) during one cycle. 7.85 BEEP Control Register 3 ⎯ Index A3h (Bank 0) Power on default: 00h ; Reset by MR. BIT NAME ATTRIBUTE DESCRIPTION 7 6 5 EN_USER_ BP FAN5_BP FAN4_BP R/W R/W R/W User defines BEEP output function. Write 1, the BEEP is always active. Write 0, this function is inactive. (Default 0) Enable BEEP output from FAN5 Write 1; enable BEEP output. Set 0 (default value), it will be disable BEEP tone output. Enable BEEP output from FAN4. Write 1; enable BEEP output. Set 0 (default value), it will be disable BEEP tone output. Enable BEEP output from Target temperature 3. Write 1; enable BEEP output. Set 0 (default value), it will be disable BEEP tone output. Enable BEEP output from Target temperature 2. Write 1; enable BEEP output. Set 0 (default value), it will be disable BEEP tone output. 4 EN_TART3 _BP EN_TART2 _BP R/W 3 R/W - 63 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G BEEP Control Register 3 ⎯ Index A3h (Bank 0) , continued BIT NAME ATTRIBUTE DESCRIPTION 2 EN_TART1_BP R/W Enable BEEP output from Target temperature 1. Write 1; enable BEEP output. Set 0 (default value), it will be disable BEEP tone output. Enable BEEP output from V-Core B. Write 1; enable BEEP output, which is default value. Enable BEEP Output from V-Core A if the monitor value exceeds the limits value. Write 1, enable BEEP output, which is default value. 1 0 EN_VBAT_BP EN_VSB_BP R/W R/W 7.86 Speech Flash Memory Read Data Registers ⎯ Index A4h-A5h (Bank 0) Power on default: 00h INDEX NAME ATTRIBUTE DESCRIPTION A4h A5h SPEECHRD2 SPEECHRD3 RO RO Speech Flash Read Data 2. Speech flash reading data bits [23:16]. Speech Flash Read Data 3. Speech flash reading data bits [31:24]. 7.87 BIT EVNTRAP1- 5 and GPIO 5-9 Select ⎯ Index A6h (Bank 0) NAME ATTRIBUTE DESCRIPTION Power on default: 00h 7 6 5 4 3 2 1 0 GPIO_SEL SMI_LEDOUT Reserved EVNT5_GPIO9 EVNT4_GPIO8 EVNT3_GPIO7 EVNT2_GPIO6 EVNT1_GPIO5 R/W R/W Reserved R/W R/W R/W R/W R/W Write ‘1’ select to pin 1 as GPIO9 function when using speech. Default is ‘0’. Note: Index 15h bit6=’0’ if use GPIO function at this pin. Write ‘1’ select to pin 48 as GPIO8 function when using speech. Default is ‘0’. Note: Index 15h bit6=’0’ if use GPIO function at this pin. Write ‘1’ select to pin 47 as GPIO7 function when using speech. Default is ‘0’. Note: Index 15h bit6=’0’ if use GPIO function at this pin. Write ‘1’ select to pin 46 as GPIO6 function when using speech. Default is ‘0’. Note: Index 15h bit6=’0’ if use GPIO function at this pin. Write ‘1’ select to pin 45 as GPIO5 function when using speech. Default is ‘0’. Write ‘1’ to this bit then read it, if return ‘0’ means speech function else means GPIO function. Select SMI# or LEDOUT function at pin 44. Default is SMI# function. - 64 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 7.88 Flash Page count ⎯ Index A7h (Bank 0) Power on default: 00h; Reset by MR. BIT NAME ATTRIBUTE DESCRIPTION 7-5 4-0 Reserved Page count RO Reserved Flash (W55FXX) size of each page is 512K, so read these bits may know the flash size when finish page coding program. 7.89 Real Time Hardware Status Register I ⎯ Index A9h (Bank 0) Power on default: 00h; Reset by MR. BIT NAME ATTRIBUTE DESCRIPTION 7 6 5 4 3 2 1 0 FAN2 FAN1 TEMP2 TEMP1 5VDD +3.3VIN VINR0 Vcore Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is in the limit range. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Set 1, the voltage of +5V is over the limit value. Set 0, the voltage of +5V is in the limit range. Set 1, the voltage of +3.3V is over the limit value. Set 0, the voltage of +3.3V is in the limit range. Set 1, the voltage of VINR0 is over the limit value. Set 0, the voltage of VINR0 is in the limit range. Set 1, the voltage of VCORE is over the limit value. Set 0, the voltage of VCORE is in the limit range. 7.90 Real Time Hardware Status Register II ⎯ Index AAh (Bank 0) Power on default: 00h; Reset by MR. BIT NAME ATTRIBUTE DESCRIPTION 7 6 5 4 Revered VINR1 TEMP3 Chassis Intrusion Read Only Read Only Read Only Read Only Reserved. Set 1, the voltage of VINR1 is over the limit value. Set 0, the voltage of VINR1 is in the limit range. Set 1, the voltage of temperature sensor is over the limit value. Set 0, the voltage of temperature sensor is in the limit range. Set 1, the case open sensor is sensed the high value. Set 0, the case open signal is low. - 65 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G Real Time Hardware Status Register II ⎯ Index AAh (Bank 0), continued. BIT NAME ATTRIBUTE DESCRIPTION 3 2 1 0 FAN3 -5VIN -12VIN +12VIN Read Only Read Only Read Only Read Only Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is during the limit range. Set 1, the voltage of -5V is over the limit value. Set 0, the voltage of -5V is during the limit range. Set 1, the voltage of -12V is over the limit value. Set 0, the voltage of -12V is during the limit range. Set 1, the voltage of +12V is over the limit value. Set 0, the voltage of +12V is in the limit range. 7.91 Real Time Hardware Status Register III ⎯ Index ABh (Bank 0) Power on default: 00h; Reset by MR. BIT NAME ATTRIBUTE DESCRIPTION 7 6 5 4 3 2 Reserved FAN5 FAN4 VBAT VSB TART3 Read Only Read Only Read Only Read Only Read Only Reserved. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is during the limit range. Set 1, the fan speed counter is over the limit value. Set 0, the fan speed counter is during the limit range. Set 1, the voltage of VBAT is over the limit value. Set 0, the voltage of VBAT is during the limit range. Set 1, the voltage of VSB is over the limit value. Set 0, the voltage of VSB is in the limit range. Set 1, when target temperature 3 with Fan 3 full speed can not be in the range after 3 minutes. Set 0, the temperature or speed is in the specific range. Set 1, when target temperature 2 with Fan 2 full speed can not be in the range after 3 minutes. Set 0, the temperature or speed is in the specific range. Set 1, when target temperature 1 with Fan 3 full speed can not be in the range after 3 minutes. Set 0, the temperature or speed is in the specific range. 1 TART2 Read Only 0 TART1 Read Only - 66 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 7.92 Revered ⎯ Index AC - AFh (Bank 0) 7.93 Value RAM 2⎯ Index B0h – B7h (BANK 0) ADDRESS A6-A0 AUTO-INCREMENT DESCRIPTION B0h B1h B2h B3h B4-B5h B6-7h B8-B9h BAh BBh BC BD BE-BFh 5VSB reading VBAT reading VINR1 reading Reserved 5VSB High/Low Limit VBAT High/ Low Limit VINR1 High/ Low Limit. FAN4 count reading FAN5 count reading FAN4 limit count FAN5 limit count Revered 7.94 Temperature Sensor 2 Temperature (High Byte) Register ⎯ Index C0h (Bank 0) BIT NAME ATTRIBUTE DESCRIPTION 7-0 TEMP2 Read Only Temperature of VTIN 2, which is high byte. 7.95 Temperature Sensor 2 Temperature (Low Byte) Register ⎯ Index C1h (Bank 0) BIT NAME ATTRIBUTE DESCRIPTION 7 6-0 TEMP2 Reserved Read Only Read Only Temperature of VTIN2, which is low byte. Read 0. - 67 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 7.96 Temperature Sensor 2 Configuration Register ⎯ Index C2h (Bank 0) Power on default: 00h; Reset by MR BIT NAME ATTRIBUTE DESCRIPTION 7-5 4-3 2:1 0 Reserved FAULT Reserved STOP2 R/W R/W Reserved Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Reserved When set to 1 the sensor will stop monitor. 7.97 Temperature Sensor 2 Hysteresis (High Byte) Register ⎯ Index C3h (Bank 0) Power on default: 4Bh; Reset by MR BIT NAME ATTRIBUTE DESCRIPTION 7-0 THYST2 R/W Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. 7.98 Temperature Sensor 2 Hysteresis (Low Byte) Register ⎯ Index C4h (Bank 0) Power on default: 00h; Reset by MR BIT NAME ATTRIBUTE DESCRIPTION 7 6-0 THYST2 Reserved R/W Read Only Temperature hysteresis bit 0, which is low Byte. Read 0 7.99 Temperature Sensor 2 Over-temperature (High Byte) Register ⎯ Index C5h (Bank 0) Power on default: 50h; Reset by MR BIT NAME ATTRIBUTE DESCRIPTION 7-0 TOVF2 R/W Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. 7.100 Temperature Sensor 2 Over-temperature (Low Byte) Register ⎯ Index C6h (Bank 0) Power on default: 00h; Reset by MR. BIT NAME ATTRIBUTE DESCRIPTION 7 6-0 TOVF2 Reserved R/W Read Only Over-temperature bit 0, which is low Byte. Read 0 - 68 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 7.101 Temperature Sensor 3 Temperature (High Byte) Register ⎯ Index C8h (Bank 0) BIT NAME ATTRIBUTE DESCRIPTION 7-0 TEMP3 Read Only Temperature of VTIN3, which is high byte. 7.102 Temperature Sensor 3 Temperature (Low Byte) Register ⎯ Index C9h (Bank 0) BIT NAME ATTRIBUTE DESCRIPTION 7 6-0 TEMP3 Reserved Read Only Read Only Temperature of VTIN3, which is low byte. Read 0. 7.103 BIT Temperature Sensor 3 Configuration Register ⎯ Index CAh (Bank 0) NAME ATTRIBUTE DESCRIPTION Power on default: 00h; Reset by MR. 7-5 4-3 2:1 0 Reserved FAULT Reserved STOP3 R/W R/W R/W Reserved Number of faults to detect before setting OVT# output to avoid false tripping due to noise. Reserved When set to 1 the sensor will stop monitor. 7.104 Temperature Sensor 3 Hysteresis (High Byte) Register ⎯ Index CBh (Bank 0) Power on default: 4Bh; Reset by MR. BIT NAME ATTRIBUTE DESCRIPTION 7-0 THYST3 R/W Temperature hysteresis bit 8-1, which is High Byte. The temperature default 75 degree C. 7.105 Temperature Sensor 3 Hysteresis (Low Byte) Register ⎯ Index CCh (Bank 0) Poweron default: 00h; Reset by MR. BIT NAME ATTRIBUTE DESCRIPTION 6-0 7 Reserved THYST3 Read Only R/W Read 0 Temperature hysteresis bit 0, which is low Byte. - 69 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 7.106 Temperature Sensor 3 Over-temperature (High Byte) Register ⎯ Index CDh (Bank 0) Power on default: 50h; Reset by MR. BIT NAME ATTRIBUTE DESCRIPTION 7-0 OVTF3 R/W Over-temperature bit 8-1, which is High Byte. The temperature default 80 degree C. 7.107 Temperature Sensor 3 Over-temperature (Low Byte) Register ⎯ Index CEh (Bank 0) Power on default: 00h; Reset by MR. BIT NAME ATTRIBUTE DESCRIPTION 7 6-0 OVTF3 Reserved R/W Over-temperature bit 0, which is low Byte. Reserved - 70 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 8. ARP (ADDRESS RESOLUTION PROTOCOL) USE REGISTER DEFINED 8.1 Unique Device Identifier (UDID) -- 20h-2Fh (Bank 1) In order to provide a mechanism to isolate each device for the purpose of address assignment each device must implement a unique device identifier (UDID). This 128-bit number is comprised of the following fields: 1 Byte Device Capabilities Bank 1 Index 20h 1 Byte Version/ Revision Bank 1 Index 21h 2 Byte 2 Byte 2 Byte Interface Bank 1 26h-27h 2 Byte Subsystem Vendor ID Bank 1 28h-29h 2 Byte Subsystem Device ID Bank 1 2Ah-2Bh 4 Byte Vendor Specific ID Bank 1 2Ch-2Fh Vendor ID Device ID Bank 1 22h-23h Bank 1 24h-25h INDEX ATTRIBUTE DESCRIPTIONS 20h 21h 22-23h 24-25h 26-27h R/W R/W R/W R/W R/W Device Capabilities (DEV_CAP capabilities. See detail SMBus 2.0. [7:0]). Describes the device’s Version/Revision (VERSION [7:0]). UDID version number and silicon revision identification. See detail SMBus2.0 Tues. Vendor ID (VENDOR_ID [15:0]). The device manufacturer’s ID as assigned by the SBS Implementers’ Forum or the PCI SIG. Device ID (DEV_ID [15:0]). The device ID as assigned by the device manufacturer (identified by the Vendor ID field). Interface (INTERFACE [15:0]). Identifies the protocol layer interfaces supported over the SMBus connection by the device. For example, ASF and IPMI. Subsystem Vendor ID (SVENDOR_ID [15:0]). This field may hold a value derived from any of several sources: 1. The device manufacturer’s ID as assigned by the SBS Implementers’ Forum or the PCI SIG. 2. The device OEM’s ID as assigned by the SBS Implementers’ Forum or the PCI SIG. 3. A value that, in combination with the Subsystem Device ID, can be used to identify an organization or industry group that has defined a particular common device interface specification. Subsystem Device ID (SDEV_ID [15:0]). The subsystem ID identifies a specific interface, implementation, or device. The Subsystem ID is defined by the party identified by the Subsystem Vendor ID field. Vendor Specific ID (SPEC_ID [31:0]). A unique number per device. See detail SMBus 2.0. 28-29h R/W 2A-2Bh R/W 2C-2Fh R/W - 71 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 8.2 ASF Sensor Environmental Event The document in ASF specification version 0.73 has indicated the listed table is presented as a guide only (Section 3.3.5.1 Page 8). It is not intended to represent a complete list of the possible environmental events from a system. The definition of the Event is shown as follow. 8.2.1 Temperature: Get Event Data message In the W83791D/G, it has three temperatures for monitoring System Board, CPU1, and CPU2. The listed table show that have the entity ID, entity instance, event source type, event type, event offset, and so on. ASF PACKET DATA TEMPERATURE 1 Event sensor type Event type Event offset 0x01 (Temperature sensor) Threshold-based: 0x01h. The W83971D/G does not implement “generic severity”. Event Status: 011b (Asserted, Send) (iii) Upper Temp. 0x01:Threshold-based 0x09: Upper critical going high Event Status: 011b (Asserted, Send) (v) (iv) 0x01:Threshold-based 0x08: Upper Critical, going low (Reserved) 0x01:Threshold-based 0x02: Lower critical, going low (ii) 0x01:Threshold-based 0x07: Upper non-critical going high Lower Temp 0x01:Threshold-based (i) 0x01:Threshold-based 0x01: Lower Non-critical Going high (Reserved) (vi) 0x00: Lower non-critical, going low Event Status: 010b (Deasserted, Send) Event sensor type: 0x01 (Temperature) Event Type: 0x01 (Threshold-based) Event source type Sensor device The W83791D/G is complying ASF 1.0 specification and the value is 0x68. The ASF specification indicates that the Sensor Device is the SMBus address of the sensor that caused the event for the PET Frame. Therefore, the Sensor Device of the W83791D/G is APR assigned address. Temperature 1: 0Eh (Don’t use 00h and FFh. Therefore 01h Temperature 2: 0Fh Temperature 3: 10h VIN0). Sensor number - 72 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G Temperature: Get Event Data message, continued. ASF PACKET DATA TEMPERATURE 1 Entity ID Temperature 1: 07h (System board) Temperature 2/3: 03h (Processor) These are defined in Table 28-11 of IPMI v1.0 specification. This value is programmable because that may be used in add-in-card or connected to other device. Temperature 1: 01h (main system board). Temperature 2: 01h (Processor 1) Temperature 3: 02h (Processor 2) These are programmable. Temperature 1: 0Dh (zero-based) Temperature 2: 0Eh Temperature 3: 0Fh Status Value Status type Description Byte Count 0Bh Entity instance Event status index Event status 0000_0010b Deasserted (send) Refer as above figure. 0000_0011b Asserted (send) 0000_0111b Event Status End W83791D/G will respond 0Bh all relative information. When event status index 02h is more than 10h, the machine will be ended the transmission. The reference table of ASF 0.64 is shown as following. Event Severity Monitor (0x01): That is represented the monitored temperature is under the lower temperature. Non Critical (0x08): that is represented the temperature is located between the lower and upper temperature. Critical Condition (0x10): that is represented the monitored temperature is over the upper temperature. Critical Condition (0x10) Upper Temp. Non Critical (0x08) Lower Temp. Monitor (0x01) - 73 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G Entity ID and Instance (Default): ENTITY ID ENTITY INSTANCE (PROGRAMMABLE) (PROGRAMMABLE) SENSOR IN W83791D/G EVENT EVENT STATUS NUMBER INDEX EVENT SENSOR TYPE 07h (System Board) 01h 01h 01h 01h 01h 01h 01h 01h 01h 01h 03h (Processor) 01h 01h 01h 02h 02h 02h 23h (System Chassis) 01h +3.3VIN +5VIN +12VIN -12VIN -5VIN VSB VBAT VINR0 FAN1 Temperature1 VCORE FAN2 Temperature 2 VINR1 FAN3 Temperature 3 Case Intrusion 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Dh 00h 0Bh 0Eh 01h 0Ch 0Fh 10h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Eh 01h 0Ch 0Fh 02h 0Dh 10h 11h 02h (Voltage) 02h 02h 02h 02h 02h 02h 02h 04h (Fan) 01h (Temperature) 02h 04h 01h 02h 04h 01h 05h (Chassis Intrusion) - 74 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 8.2.2 Voltage: Get Event Data message In the W83791D/G, it has three temperatures for monitoring System Board, CPU1, and CPU2. The listed table show that have the entity ID, entity instance, event source type, event type, event offset, and so on. ASF PACKET DATA VOLTAGE INPUT Event sensor type Event type Event offset 02h (Voltage sensor) Discrete (Generic Severity): 07h (i) 07h: Discrete (Generic Severity) 02h: Transition to Critical from less severe Event Status: 011b (Asserted, send) High voltage 07h: Discrete (Generic Severity) 07h: Monitor Low voltage Event Status: 010b (Deasserted, send) 07h: Discrete (Generic Severity) (ii) 02h: Transition to Critical from less severe Event Status: 011b (Asserted, send) Event sensor type: 02h (Voltage) Event Type: 07h (Discrete, Generic Severity) Event source type Sensor device The W83791D/G is complying ASF 1.0 specification and the value is 0 x 68. The ASF specification indicates that the Sensor Device is the SMBus address of the sensor that caused the event for the PET Frame. Therefore, the Sensor Device of the W83791D/G is APR assigned address. The number is shown as following: Voltage Sensor VCORE VINR0 +3.3VIN +5VIN +12VIN -12VIN -5VIN VSB VBAT VINR1 Sensor Number 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah Sensor number - 75 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G Voltage: Get Event Data message, continued. ASF PACKET DATA VOLTAGE INPUT Entity ID The Entity ID is shown as following. Voltage Sensor Entity ID VCORE 03h (Processor) VINR0 07h (System board) +3.3VIN +5VIN +12VIN -12VIN -5VIN VSB VBAT VINR1 03h (Processor) These ID are defined in Table 28-11 of IPMI v1.0 specification. This value is programmable because that may be used in add-in-card or connected to other device. The Entity Instance is shown as following. Sensor Entity Instance VCORE 01h (Processor 1) VINR0 01h (Main system board) +3.3VIN +5VIN +12VIN -12VIN -5VIN VSB VBAT VINR1 02h (Processor 2) VCORE: 00h VINR0: 01h +3.3VIN: 02h +5VIN : 03h +12VIN: 04h -12VIN: 05h -5VIN: 06h VSB: 07h VBAT: 08h VINR1: 09h Entity instance Event status index - 76 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G Voltage: Get Event Data message, continued. ASF PACKET DATA VOLTAGE INPUT Event status Event Severity 0Bh W83791D/G will respond 0Bh all relative information. 0000_0111b Event Status End When event status index 02h is more than 0Fh, the machine will be ended the transmission. The reference table of ASF 0.64 is shown as following. Monitor (0x01): That is represented the monitored voltage is during the limit value. Critical Condition (0x10): that is represented the monitored voltage is over the limit value. Critical Condition (0x10) Upper Volt. Monitor (0x01) Lower Volt. Critical Condition (0x10) Status type Status Value 0000_0010b Desserted (send) 0000_0011b Asserted (send) Description Byte Count 8.2.3 Fan: Get Event Data message In the W83791D/G, it has three temperatures for monitoring System Board, CPU1, and CPU2. The listed table show that have the entity ID, entity instance, event source type, event type, event offset, and so on. ASF PACKET DATA FAN CLOCK INPUT Event sensor type Event type Event offset 04h (Fan speed sensor) Discrete (Generic Severity): 07h (i) 05h: 'digital' Discrete (Generic Severity) 00h: Limit Not Exceeded Event Status: 010b (Deasserted, send) High Speed (Low Count) Fan Limit Lower Speed (High Count) Event Status: 011b (Asserted, send) 05h: 'digital' Discrete (Generic Severity) 01h: Limit Exceeded Event sensor type: 04h (Fan) Event Type: 05h ('digital ' Discrete, Generic Severity) - 77 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G Fan: Get Event Data message, continued. ASF PACKET DATA FAN CLOCK INPUT Event source type Sensor device Sensor number The W83791D/G is complying ASF 1.0 specification and the value is 0 x 68. The ASF specification indicates that the Sensor Device is the SMBus address of the sensor that caused the event for the PET Frame. Therefore, the Sensor Device of the W83791D/G is APR assigned address. The number is shown as following: Fan Sensor Sensor Number FAN 1 0Bh FAN 2 0Ch FAN 3 0Dh The Entity ID is shown as following. Voltage Sensor Entity ID (default) FAN 1 07h (System board) FAN 2 03h (Processor) FAN 3 These ID are defined in Table 28-11 of IPMI v1.0 specification. This value is programmable because that may be used in add-in-card or connected to other device. The Entity Instance is shown as following. Fan Sensor Entity Instance (default) FAN 1 01h (Main system board) FAN 2 01h (Processor 1) FAN 3 02h (Processor 2) FAN1 : 0Ah FAN2 : 0Bh FAN3 : 0Ch Status Value Status type Description Byte Count 0Bh W83791D/G will respond 0Bh all relative information. When event status index 02h is more than 0Fh, the machine will be ended the transmission. Entity ID Entity instance Event status index Event status 0000_0010b Deasserted (send) 0000_0011b Asserted (send) 0000_0111b Event Status End The reference table of ASF 0.64 is shown as following. - 78 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G Fan: Get Event Data message, continued. ASF PACKET DATA FAN CLOCK INPUT Event Severity Monitor (0x01): That is represented the monitored fan count is under the limit count. Critical Condition (0x10): that is represented the monitored fan count is over the limit count. Monitor (0x01) Upper Speed Fan Speed Lower Speed Critical Condition (0x10) 8.2.4 Case Intrusion: Get Event Data message In the W83791D/G, it has three temperatures for monitoring System Board. The listed table show that have the entity ID, entity instance, event source type, event type, event offset, and so on. ASF PACKET DATA CASE INTRUSION INPUT Event sensor type Event type Event offset 05h (Chassis Intrusion) ‘digital’ Discrete (Generic Severity): 03h (i) 03h: 'digital' Discrete (Generic Severity) 00h: State Deasserted Event Status: 010b (Deasserted, send) Event Status: 011b (Asserted, send) Logic Low Logic High 03h: 'digital' Discrete (Generic Severity) 01h: Asserted (Case Intruded) Event sensor type: 05h (Case Intruded) Event Type: 03h ('digital ' Discrete, Generic Severity) Event source type Sensor device The W83791D/G is complying ASF 1.0 specification and the value is 0 x 68. The ASF specification indicates that the Sensor Device is the SMBus address of the sensor that caused the event for the PET Frame. Therefore, the Sensor Device of the W83791D/G is APR assigned address. The sensor number for case intruded is 11h The Entity ID is 23h for case intruded These ID are defined in Table 28-11 of IPMI v1.0 specification. This value is programmable because that may be used in add-in-card or connected to other device. Sensor number Entity ID - 79 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G Case Intrusion: Get Event Data message, continued. ASF PACKET DATA CASE INTRUSION INPUT Entity instance Event status index Event status Event Severity The Entity Instance is 01h for (Main system board) 0x0D (W83791D/G sensor index) Status type Description Status Byte Value Count 0000_0010b Deasserted (send) 0Bh 0000_0011b Asserted (send) W83791D/G will respond 0Bh all relative information. 0000_0111b Event Status End When event status index 02h is more than 0Fh, the machine will be ended the transmission. The reference table of ASF 0.64 is shown as following. Monitor (0x01): That is represented the monitored CASEOPEN is logic Low Critical Condition (0x10): that is represented the monitored CASEOPEN is logic High. Logic High Monitor (0x01) Critical Condition (0x10) Logic Low Case Intruded Input Pin 8.3 ASF Response Registers ⎯ Index 40h-7Fh (Bank 1) 8.3.1 ASF Upper/Lower Temperature Registers: Generic/Upper/Under temperature INDEX DESCRIPTION DEFAULT TEMPERATURE 40h 41h 42h 43h 44h 45h 46h-4Eh Non-critical temperature of temperature sensor 1 setting. Critical Temperature of temperature sensor 1 setting Non-critical temperature of temperature sensor 2 setting. Critical Temperature of temperature sensor 2 setting Non-critical temperature of temperature sensor 3 setting. Critical Temperature of temperature sensor 3 setting Reserved 4Bh (75 Centigrade) 50h (80 Centigrade) 4Bh 50h 4Bh 50h Reserved. Note: When read index 45h (Bank 1) have to use index 46h (Bank 1). - 80 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 8.3.2 4Fh Sensor device: (SMBus Address, Read/Write) DESCRIPTION DEFAULT VALUE INDEX Sensor Device SMBus Address assigned by ARP 00h 8.3.3 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h Relative Entity ID Table: MONITOR ITEM DEFAULT ENTITY ID INDEX VIN0 (VCORE) VIN1 (VINR0) VIN2 (+3.3VIN) VIN3 (+5 VIN) VIN4 (+12VIN) VIN5 (-12VIN) VIN6 (-5VIN) VSB VBAT VINR1 FAN1 FAN2 FAN3 Temperature 1 Temperature 2 Temperature 3 Chassis Intrusion Reserved 3 (CPU) 7 (System Board) 7 (System Board) 7 (System Board) 7 (System Board) 7 (System Board) 7 (System Board) 7 (System Board) 7 (System Board) 3 (CPU) 7 (System Board) 3 (CPU) 3 (CPU) 7 (System Board) 3 (CPU) 3 (CPU) 23 (System Chassis) Reserved 61h-6Fh Table of Entity ID defined in PET 1.0 or IPMI 1.0 ENTITY DEFINITION ENTITY ID CPU System Memory module System Chassis Fan/Cooling device Memory device 3 7 8 23 29 32 - 81 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 8.3.4 Entity Instance Register Maximum number of instance is 15 INDEX BIT ENTITY ENTITY INSTANCE (DEFAULT VALUE) 70h 71h 72h 73h 74 h 75h 76h 77h 78h VIN0(Vcore) VIN1(VINR0) VIN3 (+5VIN) VIN4 (+12VIN) VIN5 (-12VIN) VIN6 (-5VIN) VIN7(VSB) VIN8(VBAT) VIN9(VINR1) FAN1 FAN2 FAN3 TEMP1 TEMP2 TEMP3 Reserved Chassis 1 (Processor 1_CPU1). 1 (System board 1). 1 (System board 1). 1 (System board 1). 1 (System board 1). 1 (System board 1). 1 (System board 1). 1 (System board 1). 2 (Processor 2_CPU2). 1 (System board 1). 1 (Processor 1_CPU1). 2 (Processor 2_CPU2) 1 (System board 1) 1 (Processor 1) 2 (Processor 2) 0 1 (System Chassis) VIN2 (+3.3VIN) 1 (System board 1). The Entity for a given event varies according to what entity the environmental sensor is monitoring. For example, a typical managed system board can have temperature monitoring associated with the system board and with the main processor. Thus, the Entity IDs and Entity Instance values for these would be Entity ID=7, Entity Instance=1 for ‘main system board’ and Entity ID=3, Entity Instance=1 for ‘processor 1’, respectively. 8.4 BJT RT-Table - 50h-57h (Bank 7) ⎯ TEST mode only Bank 7 registers 50h-57h are BJT table for Winbond test. User doesn’t use these registers. - 82 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETER RATING UNIT Power Supply Voltage Input Voltage Operating Temperature Storage Temperature -0.5 to 7.0 -0.5 to VDD+0.5 0 to +70 -55 to +150 V V °C °C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 9.2 DC Characteristics PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS (Ta = 0° C to 70° C, VDD = 5V ± 10%, VSS = 0V) I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V μA μA IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V I/O12ts - TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger level input Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VtVt+ VTH VOL VOH ILIH ILIL 2.4 +10 -10 0.5 1.6 0.5 0.8 2.0 1.2 0.4 1.1 2.4 V V V V V μA μA VDD = 5 V VDD = 5 V VDD = 5 V IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V - 83 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G DC Characteristics, continued. PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS OUT12t - TTL level output pin with source-sink capability of 12 mA Output Low Voltage Output High Voltage VOL VOH 2.4 0.4 V V IOL = 12 mA IOH = -12 mA OD8 - Open-drain output pin with sink capability of 8 mA Output Low Voltage VOL 0.4 V IOL = 8 mA OD12 - Open-drain output pin with sink capability of 12 mA Output Low Voltage VOL 0.4 V IOL = 12 mA OD48 - Open-drain output pin with sink capability of 48 mA Output Low Voltage VOL 0.4 V IOL = 48 mA INt - TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage INts VIL VIH ILIH ILIL 2.0 +10 -10 0.8 V V μA μA VIN = VDD VIN = 0 V - TTL level Schmitt-triggered input pin VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 +10 -10 1.1 2.4 V V V μA μA VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Input High Leakage Input Low Leakage - 84 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 9.3 9.3.1 AC Characteristics Serial Bus Timing Diagram t SCL t tR R SCL t HD;SDA t SU;DAT t SU;STO SDA IN VALID DATA t HD;DAT SDA OUT Serial Bus Timing Diagram Serial Bus Timing PARAMETER SYMBOL MIN. MAX. UNIT SCL clock period Start condition hold time Stop condition setup-up time DATA to SCL setup time DATA to SCL hold time SCL and SDA rise time SCL and SDA fall time t SCL tHD;SDA tSU;STO tSU;DAT tHD;DAT tR tF - 10 4.7 4.7 120 5 1.0 300 uS uS uS nS nS uS nS - 85 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 10. HOW TO READ THE TOP MARKING The top marking of W83791D W83791D 025AA Left: Winbond logo 1st line: Type number W83791D, D means LQFP (Thickness = 1.4 mm). 2nd line: Tracking code 025 A A 025: packages made in 2000, week 25 A: assembly house ID; A means ASE, O means OSE A: IC revision; A means version A, B means version B The top marking of W83791G W83791G 025AA Left: Winbond logo 1st line: Type number W83791G, G means lead-free package. 2nd line: Tracking code 025 A A 025: packages made in 2000, week 25 A: assembly house ID; A means ASE, O means OSE A: IC revision; A means version A, B means version B - 86 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G 11. PACKAGE SPECIFICATION (48-pin LQFP) HD D 36 25 Symbol Dimension in inch Min. Nom. Max. Dimension in mm Min. --0.05 1.35 0.17 0.09 Nom. ----1.40 0.20 --7.00 7.00 0.50 9.00 9.00 Max. 1.60 0.15 1.45 0.27 0.20 37 24 E HE 48 13 1 e b 12 A A1 A2 b c D E e HD HE L L1 y 0 Notes: c 0.45 0.60 1.00 0.75 --0 0.08 3.5 --7 A2 A1 y A Seating Plane See Detail F L L1 Detail F 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec. - 87 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G VOLTAGE SENSING CPUVCOA GTLVOLT 3VCC R1 10K R2 10K R3 10K +12VIN +12V R4 28K 1% R6 +5V R 34K 1%/791D 0 /782D R8 5VSB R 5.1K 1%/782D 0 /791D R10 R R9 R7 R R5 10K 1% VINR1 R 50K 1%/791D GNDA R GNDA R R R VCORE VINR0 3VIN /782D : Only for W83782D /791D : Only for W83791D 3VCC R30 R 4.7K 330 R31 R 4.7K SMDAT SMCLK R33 R 330 SDA SCL R R32 L1 INDUCTOR FB/791D +5VSB C1 CAP 10u/791D GNDA C2 CAP 0.1u/791D +5VSB GNDA R 7.5K 1%/782D R11 232K 1% -12VIN R -12V +5V 56K 1% VREF L2 INDUCTOR FB/782D C3 CAP 10u/782D R12 R R13 120K 1% -5VIN ADRMSELIN R R GNDA C4 CAP 0.1u/782D -5V R14 VCORE VINR0 3VIN VINR1 +12VIN -12VIN VBAT +5VSB -5VIN GNDA BEEP VID3 56K 1% 3VSB 36 35 34 33 32 31 30 29 28 27 26 25 U1 IRQ/GPIO10 R VCORE VINR0 +3.3VIN VINR1 +12VIN -12VIN VBAT +5VSB -5VIN GNDA BEEP VID3 0/782D R16 0/791D VREF T3 T2 T1 37 38 39 40 41 42 43 44 45 46 47 48 R15 R 10K/791D R17 24 23 22 21 20 19 18 17 16 15 14 13 VID2 OUT3/VID90 SDA SCL FAN1IN FAN2IN FAN3IN CASEOPEN GNDD VDD C5 VCC SLOTOCC# R 0/791D R19 MR# R 0/782D R? SMI# R? LED 0 SMI#/LED R18 FAN4IN 0/791D R22 0/791D R23 FAN5IN 0/791D R24 0/791D (FAN) (FAN) 0/791D EVNT2/A1 VID0 OVT# SMI#/LED EVNTRAP5/GPIO9/PWMOUT5 EOP/GPIO11 REXT ADDR/GPIO0 CLKOUT/GPIO1 DATA/GPIO2 CTRL/GPIO3 MODE/GPIO4 SPEAKER/LED/SPEECH_SEL PWMOUT1/A0 PWMOUT2/A1 VID1 (EVNT2) EVNT1/A2 VREF VTIN3/PIITD3 VTIN2/PIITD2 VTIN1/PIITD1 VID0 OVT# IRQ/GPIO10 SMI#/LEDOUT EVNTRAP1/GPIO5 EVNTRAP2/GPIO6/FANIN4 EVNTRAP3/GPIO7/FANIN5 EVNTRAP4/GPIO8/PWMOUT4 VID2 PWMOUT3/VID_V90 SDA SCL FANIN1 FANIN2 FANIN3 VID4 CASEOPEN SLOTOCC# GNDD VDD (From PII/PIII CPU) 0: means CPU is present 1: means CPU is absent VID4 EVNT3/A0 CAP 10u C6 CAP 0.1u (EVNT3) R25 0/791D (EVNT4) R26 R 0/791D (FAN) R27 0/782D R GNDA GNDA GNDD EVNT4 PWMOUT4 1 2 3 4 5 6 7 8 9 10 11 12 L3 INDUCTOR FB W83791D EOP/IOW# REXT/CLKIN ADDR/D7 CKOUT/D6 DATA/D5 CTRL/D4 MODE/D3 SPK/D2 PWMOUT1/D1 PWMOUT2/D0 VID1 SMI#/LEDOUT function circuit 5VSB 3VCC R? 270 TO CHIPSET R20 R 4.7K R21 R 4.7K OVT# R129 0 R28 R29 CS# Select one of the two setting.(FOR 782D) Set A2-A0 as 3 lowest order bits of ISA address bus ADRMSELIN SA2 SA1 SA0 R35 R36 R37 0 0 0 R R R EVNT1/A2 EVNT2/A1 EVNT3/A0 0/791D 0/791D (EVNT5) (FAN) Beep Circuits VCC R38 R 100 LS1 R34 EVNT5/IOR# PWMOUT5 220K/ 791D R LED Q? MOSFET N 2N7000 5VSB R? 1K D? LED { THRM# EXTSMI# SMI# R39 R 10K R130 0/791d,B 2 U7A 1 R131 0/791d,B SMI# BUZZER Set A2-A0 as bit2, bit1, bit0 of 7 bit I2C address setting VCC IA2 IA1 IA0 ADRMSELIN R41 R42 R43 0 0 0 R R R EVNT1/A2 EVNT2/A1 EVNT3/A0 BEEP R40 R 510 !!Only for 791D ver B. 7404 /791d, B Q1 NPN 3904 WINBOND ELECTRONICS CORP. Title W83782D-W83791D Application Circuit Rev 0.2 Sheet 1 of 5 Size Document Number Custom Date: Tuesday, May 22, 2001 - 88 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G Temperature Sensing RT1 PWM Circuit for FAN1-3 speed control VSB R44 4.7K R46 1K Q3 PWMOUT1/D1 R51 R 0 MOSFET N 2N7002 R R Q2 PNP 3906 C7 47u + JP1 3 2 1 HEADER 3 D1 DIODE 1N4148 +12V 10K 1% R45 R 47K/791D VREF R47 R T (for system) 10K 1% R49 R THERMISTOR RT2 R48 R 4.7K R50 27K R R52 R 10K FAN1IN T 10K 1% (for cpu1) (for cpu2) 10K 1% R53 R THERMISTOR RT3 T 10K 1% 10K 1% T1 T2 T3 THERMISTOR R45,R61 in order to trap address be A0=1,A1=0 GNDA R54 4.7K R55 1K Q5 PWMOUT2/D0 R60 30K 1% CAPACITOR C9 3300p R R58 R 0 D+ MOSFET N 2N7002 R R Q4 PNP 3906 +12V Measuring CPU temperature by either thermistor or diode. VREF T2 GNDA D2 DIODE 1N4148 JP2 + C8 47u 3 2 1 HEADER 3 R56 R 4.7K R57 27K R R59 R 10K FAN2IN (from PII/PIII CPU) D- R61 R 47K/791D +12V R63 R RT4 T 10K 1% R62 R R Q6 PNP 3906 JP3 + C10 47u 3 2 1 HEADER 3 D3 DIODE 1N4148 VREF 10K 1% THERMISTOR (for cpu2) 4.7K R64 1K T2 GNDA OUT3/VID90 R67 R 0 R65 R 4.7K R66 27K R R68 R 10K FAN3IN Q7 MOSFET N 2N7002 PWM Circuit for FAN4-5 speed control when select these pin to PWMOUT/FAN function +12V R69 4.7K R70 1K R75 PWMOUT4 Q9 R 0 MOSFET N 2N7002 R R Q8 PNP 3906 JP4 + C11 47u 3 2 1 HEADER 3 D4 DIODE 1N4148 Select VID Table R71 R 4.7K R73 27K R R76 R 10K FAN4IN R72 VSB R 47K /791D R74 47K /791D R OUT3/VID90 OUT3/VID90 Select one of the two VID Table setting. 0:Old VID Table(VRM 8.3) 1:New VID Table(VRM 9.0) +12V R77 4.7K R78 1K R81 PWMOUT5 Q11 R 0 MOSFET N 2N7002 R R Q10 PNP 3906 JP5 + C12 47u 3 2 1 HEADER 3 D5 DIODE 1N4148 R79 R 4.7K R80 27K R R82 R 10K FAN5IN WINBOND ELECTRONICS CORP. Title W83782D-W83791D Application Circuit Rev 0.2 Sheet 2 of 5 Size Document Number Custom Date: Tuesday, May 22, 2001 - 89 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G CPU Voltage ID input/output 3VCC R83 R 10K R84 R 10K R85 R 10K R86 R 10K R87 R 10K Circuits for 782D EVNT5/IOR# IOR# IOW# CLKIN VID4 VID3 VID2 VID1 VID0 R88 R R89 R R90 R R91 R R92 R R94 R R96 R R98 R R100R R102R R103R 0 0 0 0 0 0 0 0 0 0 0 EOP/IOW# REXT/CKLIN ADDR/D7 CKOUT/D6 DATA/D5 CTRL/D4 MODE/D3 SPK/D2 PWMOUT1/D1 PWMOUT2/D0 PIIVID4 PIIVID3 PIIVID2 PIIVID1 PIIVID0 R93 R95 R97 R99 R101 1K 1K 1K 1K 1K SD[0..7] VID0 VID1 VID2 VID3 VID4 (From CPU) } To Power Regulator Case Open Circuits R104 R R106 R 2M/782D R109 R 0/782D S1 CASEOPEN SW 0/782D VBAT R105 R 0/791D C13 CAP 1000p /791D CASEOPEN R110 R 0/791D R111 R 2.2M/791D 74HC14 /791D U2B 4 3 These two inverters consume VBAT 74HC14 /791D U2A 1 2 R107 R 10K/791D R108 R CASEOPEN 0/791D WINBOND ELECTRONICS CORP. Title W83782D-W83791D Application Circuit Size B Date: Document Number Tuesday, May 22, 2001 Sheet 3 of 5 Rev 0.2 - 90 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G Select SPEECH / LED Function by one of three cricuits. / 791D 1. VCC C14 SPK/D2 R112 510 1uF/16V 2. 3. R113 270 VCC C15 LINE_OUT_L LS2 1uF/16V R114 8 ohm SPEAKER SPK/D2 R115 510 C17 0.1uF Q12 NPN 8050D LINE_OUT_R 1uF/16V R116 470K C19 100pF C16 100pF J1 D6 LED From AC' 97 Codec (W83971D) 470K LINE_OUT SPK/D2 Q13 MOSFET N 2N7000 C18 (LED FUNCTION) (SPEECH FUNCTION) (SPEECH FUNCTION) Connect to serial FLASH EEPROM (W55FXX) /791D VCC R117 EOP/IOW# 0/791D VCC R118 EOP/IOW# CTRL/D4 R120 R124 ADDR/D7 0/791D 0/791D 0/791D 1 2 3 4 U3 EOP CTRL VSS ADDR MODE VDD CLK DATA W55F10 8 7 6 5 R119 0/791D MODE/D3 U4 1 0/791D 2 3 ADDR/D7 R127 0/791D 4 8 7 6 5 R121 MODE VDD CLK DATA W55F10 0/791D MODE/D3 0/791D CKOUT/D6 R126 R128 0/791D DATA/D5 1 2 3 4 U5 EOP CTRL VSS ADDR MODE VDD CLK DATA W55F10 8 7 6 5 1 2 3 4 U6 EOP CTRL VSS ADDR MODE VDD CLK DATA W55F10 8 7 6 5 0/791D CKOUT/D6 R122 CTRL/D4 R125 0/791D DATA/D5 R123 EOP CTRL VSS ADDR Connect 1 FLASH Connect 2 or more FLASH WINBOND ELECTRONICS CORP. Title W83782D-W83791D Application Circuit Size Document Number Custom Date: Tuesday, May 22, 2001 Sheet 4 of 5 Rev 0.2 - 91 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G REV 0.1 0.15 0.16 Decription First Publication Add FAN/PWMOUT4-5 circuit Change R34 connect to 5VSB 1. Change R32/R33 value to 330 ohm 2. Modify R34 value as 220K ohm 3. Change SMI# (pin 44) circuit. This update is for B version. Update Pin44 (SMI#/LEDOUT) circuit. This update is for C version. 0.17 0.2 WINBOND ELECTRONICS CORP. Title Size A Date: W83782D-W83791D Application circuit Document Number Tuesday, May 22, 2001 Sheet 5 of 5 Rev 0.2 - 92 - Publication Release Date: April 14, 2006 Revision 1.1 W83791D/G Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owner Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 93 - Publication Release Date: April 14, 2006 Revision 1.1