W9412G2IB

W9412G2IB 1M × 4 BANKS × 32 BITS GDDR SDRAM Table of Contents1. GENERAL DESCRIPTION .................................................................................................................................4 2. FEATURES ........................................................................................................................................................4 3. KEY PARAMETERS...........................................................................................................................................5 4. BALL CONFIGURATION....................................................................................................................................6 5. BALL DESCRIPTION .........................................................................................................................................7 6. BLOCK DIAGRAM..............................................................................................................................................9 7. FUNCTIONAL DESCRIPTION .........................................................................................................................10 7.1 7.2 Power Up Sequence...........................................................................................................................10 Command Function ............................................................................................................................11 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 Bank Activate Command ......................................................................................................11 Bank Precharge Command ..................................................................................................11 Precharge All Command ......................................................................................................11 Write Command ...................................................................................................................11 Write with Auto-precharge Command ..................................................................................11 Read Command ...................................................................................................................11 Read with Auto-precharge Command ..................................................................................11 Mode Register Set Command ..............................................................................................12 Extended Mode Register Set Command ..............................................................................12 No-Operation Command ......................................................................................................12 Burst Read Stop Command..................................................................................................12 Device Deselect Command ..................................................................................................12 Auto Refresh Command .......................................................................................................12 Self Refresh Entry Command...............................................................................................13 Self Refresh Exit Command .................................................................................................13 Data Write Enable /Disable Command .................................................................................13 Read Operation ..................................................................................................................................13 Write Operation ..................................................................................................................................14 Precharge...........................................................................................................................................14 Burst Termination ...............................................................................................................................14 Refresh Operation ..............................................................................................................................14 Power Down Mode .............................................................................................................................15 Input Clock Frequency Change during Precharge Power Down Mode...............................................15 Mode Register Operation ...................................................................................................................15 7.10.1 7.10.2 Burst Length field (A2 to A0) ................................................................................................16 Addressing Mode Select (A3)...............................................................................................16 -1- Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 7.10.3 7.10.4 7.10.5 7.10.6 7.10.7 8.1 8.2 8.3 8.4 8.5 8.6 9.1 9.2 9.3 9.4 9.5 9.6 9.7 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 CAS Latency field (A6 to A4)................................................................................................17 DLL Reset bit (A8) ................................................................................................................17 Mode Register /Extended Mode register change bits (BA0, BA1) ........................................17 Extended Mode Register field ..............................................................................................18 Reserved field ......................................................................................................................18 8. OPERATION MODE.........................................................................................................................................19 Simplified Truth Table.........................................................................................................................19 Function Truth Table ..........................................................................................................................20 Function Truth Table, continued .........................................................................................................21 Function Truth Table, continued .........................................................................................................22 Function Truth Table for CKE.............................................................................................................23 Simplified Stated Diagram ..................................................................................................................24 Absolute Maximum Ratings ................................................................................................................25 Recommended DC Operating Conditions ..........................................................................................25 Capacitance .......................................................................................................................................26 Leakage and Output Buffer Characteristics........................................................................................26 DC Characteristics..............................................................................................................................27 AC Characteristics and Operating Condition ......................................................................................28 AC Test Conditions.............................................................................................................................29 Command Input Timing ......................................................................................................................32 Timing of the CLK Signals ..................................................................................................................32 Read Timing (Burst Length = 4) .........................................................................................................33 Write Timing (Burst Length = 4)..........................................................................................................34 DM, DATA MASK (W9412G2IB) ........................................................................................................35 Mode Register Set (MRS) Timing.......................................................................................................36 Extend Mode Register Set (EMRS) Timing ........................................................................................37 Auto-precharge Timing (Read Cycle, CL = 2).....................................................................................38 Auto-precharge Timing (Read cycle, CL = 2), continued ....................................................................39 9. ELECTRICAL CHARACTERISTICS.................................................................................................................25 10. TIMING WAVEFORMS ....................................................................................................................................32 10.10 Auto-precharge Timing (Write Cycle) .................................................................................................40 10.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) ................................................................................41 10.12 Burst Read Stop (BL = 8) ...................................................................................................................41 10.13 Read Interrupted by Write & BST (BL = 8) .........................................................................................42 10.14 Read Interrupted by Precharge (BL = 8) ............................................................................................42 10.15 Write Interrupted by Write (BL = 2, 4, 8) .............................................................................................43 10.16 Write Interrupted by Read (CL = 2, BL = 8) ........................................................................................43 10.17 Write Interrupted by Read (CL = 3, BL = 4) ........................................................................................44 10.18 Write Interrupted by Precharge (BL = 8).............................................................................................44 -2- Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) ...........................................................................45 10.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) ...........................................................................45 10.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) ...........................................................................46 10.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) ...........................................................................46 10.23 Auto Refresh Cycle.............................................................................................................................47 10.24 Precharge/Activate Power Down Mode Entry and Exit Timing ...........................................................47 10.25 Input Clock Frequency Change during Precharge Power Down Mode Timing...................................47 10.26 Self Refresh Entry and Exit Timing.....................................................................................................48 11. PACKAGE SPECIFICATION............................................................................................................................49 11.1 144L LFBGA (12X12X1.40 mm^3, Ø=0.5mm) ...................................................................................49 12. REVISION HISTORY .......................................................................................................................................50 -3- Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 1. GENERAL DESCRIPTION W9412G2IB is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM); organized as 1,048,576 words × 4 banks × 32 bits. W9412G2IB delivers a data bandwidth of up to 500M words per second (-4). To fully comply with the personal computer industrial standard, W9412G2IB is sorted into following speed grades: -4, -5, -5I, -6 and -6I. The -4 is compliant to the DDR500/CL3 or CL4 specification. The -5/-5I is compliant to the DDR400/CL3 specification (-5I grade which is guaranteed to support -40°C ~ 85°C). The -6/-6I is compliant to the DDR333/CL2.5 specification (-6I grade which is guaranteed to support -40°C ~ 85°C). All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. Write and Read data are synchronized with the both edges of DQS (Data Strobe). By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9412G2IB is ideal for any high performance applications. 2. FEATURES • • • • • • • • • • • • • • • • 2.5V ±0.2V Power Supply for DDR 333/400 2.5V ±0.1V Power Supply for DDR500 Up to 250 MHz Clock Frequency Double Data Rate architecture; two data transfers per clock cycle Differential clock inputs (CLK and CLK ) DQS is edge-aligned with data for Read; center-aligned with data for Write CAS Latency: 2, 2.5, 3 and 4 Burst Length: 2, 4 and 8 Auto Refresh and Self Refresh Precharged Power Down and Active Power Down Write Data Mask Write Latency = 1 15.6µS Refresh interval (4K/64 mS Refresh) Maximum burst refresh cycle: 8 Interface: SSTL_2 Packaged in 144L LFBGA, using Lead free materials with RoHS compliant -4- Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 3. KEY PARAMETERS SYMBOL DESCRIPTION CL = 2 CL = 2.5 MIN./MAX. Min. Max. Min. Max. Min. Max. Min. Max. Min. Min. Max. Max. Max. Max. Max. Max. -4 4 nS 12 nS 4 nS 12 nS 40 nS 48 nS 160 mA 180 mA 240 mA 270 mA 210 mA 3 mA -5/-5I 7.5 nS 12 nS 6 nS 12 nS 5 nS 12 nS 40 nS 50 nS 150 mA 170 mA 220 mA 250 mA 200 mA 3 mA -6/-6I 7.5 nS 12 nS 6 nS 12 nS 6 nS 12 nS 42 nS 54 nS 140 mA 160 mA 200 mA 230 mA 190 mA 3 mA tCK Clock Cycle Time CL = 3 CL = 4 tRAS tRC IDD0 IDD1 IDD4R IDD4W IDD5 IDD6 Active to Precharge Command Period Active to Ref/Active Command Period Operating Current: One Bank Active-Precharge Operating Current: One Bank Active-Read-Precharge Burst Operation Read Current Burst Operation Write Current Auto Refresh Current Self-Refresh Current -5- Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 4. BALL CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 A B C D E F G H J K L M DQS0 DM0 VSSQ DQ3 DQ2 DQ0 DQ31 DQ29 DQ28 VSSQ DM3 DQS3 DQ4 VDDQ NC VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ NC VDDQ DQ27 DQ6 DQ5 VSSQ VSSQ VSSQ VDD VDD VSSQ VSSQ VSSQ DQ26 DQ25 DQ7 VDDQ VDD VSS VSSQ VSS VSS VSSQ VSS VDD VDDQ DQ24 DQ17 DQ16 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ15 DQ14 DQ19 DQ18 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ13 DQ12 DQS2 DM2 NC VSSQ VSS VSS VSS VSS VSSQ NC DM1 DQS1 DQ21 DQ20 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ11 DQ10 DQ22 DQ23 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ9 DQ8 /CAS /WE VDD VSS A10 VDD VDD RFU (A12) VSS VDD NC NC /RAS NC NC BA1 A2 A11 A9 A5 RFU (BA2) CK /CK DSF/ NC MCL /CS NC BA0 A0 A1 A3 A4 A6 A7 A8/AP CKE VREF -6- Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 5. BALL DESCRIPTION BALL LOCATION PIN NAME M4-M10, L5-L8, K5 M3, L4 A4-A9,B1,B5,B8, B12,C1,C2,C11,C1 2,D1,D12,E1,E2,E1 DQ0−DQ31 1,E12,F1,F2,F11,F1 2,H1,H2,H11,H12,J 1,J2,J11,J12 A1,A12,G1,G12 DQS0−DQS3 Data Input/ Output The DQ0−DQ31 input and output data are synchronized with both edges of DQS. A0−A11 BA0, BA1 FUNCTION Address Bank Address DESCRIPTION Multiplexed pins for row and column address. Row address: A0−A11. Column address: A0−A7. (A8 is used for Auto-precharge) Select bank to activate during row address latch time, or bank to read/write during column address latch time. Data Strobe DQS is Bi-directional signal. DQS is input signal during write operation and output signal during read operation. It is Edge-aligned with read data, Center-aligned with write data. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. M1 CS RAS , CAS , Chip Select K1,K2,L1 WE Command Inputs Command inputs (along with CS ) define the command being entered. Write mask DM is an input mask signal for writes data. When DM is asserted “high” in burst write, the input data is masked. DM is synchronized with both edges of DQS. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of CLK . CKE controls the clock activation and deactivation. CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CLK, CLK and CKE are disabled during POWER-DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. A2,A11,G2,G11 DM0−DM3 CLK, CLK L10,L11 Differential clock inputs M11 CKE Clock Enable M12 C6,C7,D3,D10,K3,K 6, K7,K10 VREF VDD Reference Voltage VREF is reference voltage for inputs. Power ( +2.5V ) Power for logic circuit inside DDR SDRAM. -7- Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB BALL DESCRIPTION, continued BALL LOCATION PIN NAME D4,D6,D7,D9, E5~E8,F5~F8,G5~ G8,H5~H8,J5~J8,K 4,K9 B2,B4,B6,B7, B9,B11,D2,D11,E3, E10,F3,F10,H3,H10 ,J3,J10 A3,A10,C3~C5, C8~C10,D5,D8,E4, E9,F4,F9,G4,G9,H4 ,H9,J4,J9 B3,B10,G3,G10,K1 1,K12,L2,L3,L12,M 2 K8,L9 VSS FUNCTION Ground DESCRIPTION Ground for logic circuit inside DDR SDRAM. VDDQ Power ( + 2.5V ) for Separated power from VDD, used for output buffer, to improve noise immunity. I/O buffer VSSQ Ground for I/O buffer Separated ground from VSS, used for output buffer, to improve noise immunity. NC RFU No Connection No Connection No connection Reserved for Future Use. -8- Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 6. BLOCK DIAGRAM CLK CLK DLL CLOCK BUFFER CKE CS RAS CAS WE CONTRO L SIGNAL GENERATO R COMMAND DECODER COLUMN DECODER COLUMN DECODER ROW DECODER A8 CELL ARRAY BANK #0 ROW DECODER CELL ARRAY BANK #1 A0 ADDRESS MODE REGISTER SENSE AMPLIFIER SENSE AMPLIFIER A7 A9, A10, A11 BA0 BA1 BUFFER PREFETCH REGISTER DATA CONTROL CIRCUIT REFRESH COUNTER COLUMN COUNTER DQ BUFFER DQ0 DQn DQSn DMn COLUMN DECODER COLUMN DECODER ROW DECODER CELL ARRAY BANK #2 ROW DECODER CELL ARRAY BANK #3 SENSE AMPLIFIER SENSE AMPLIFIER NOTE: The cell array configuration is 4096 * 256 * 32 -9- Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 7. FUNCTIONAL DESCRIPTION 7.1 Power Up Sequence (1) Apply power and attempt to CKE at a low state ( ≤ 0.2V), all other inputs may be undefined 1) Apply VDD before or at the same time as VDDQ. 2) Apply VDDQ before or at the same time as VTT and VREF. Start Clock and maintain stable condition for 200 µS (min.). After stable power and clock, apply NOP and take CKE high. Issue precharge command for all banks of the device. Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type. Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8. (An additional 200 cycles(min) of clock are required for DLL Lock before any executable command applied.) Issue precharge command for all banks of the device. Issue two or more Auto Refresh commands. Issue MRS-Initialize device operation with the reset DLL bit deactivated A8 to low. (2) (3) (4) (5) (6) (7) (8) (9) CLK CLK ANY CMD 2 Clock min. Command PREA tRP EMRS 2 Clock min. MRS 2 Clock min. PREA tRP AREF tRFC 200 Clock min. AREF tRFC MRS Inputs maintain stable for 200 µS min. Enable DLL DLL reset with A8 = High Disable DLL reset with A8 = Low Initialization sequence after power-up - 10 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 7.2 7.2.1 Command Function Bank Activate Command ( RAS = “L”, CAS = “H”, WE = “H”, BA0, BA1 = Bank, A0 to A11 = Row Address) The Bank Activate command activates the bank designated by the BA (Bank address) signal. Row addresses are latched on A0 to A11 when this command is issued and the cell data is read out of the sense amplifiers. The maximum time that each bank can be held in the active state is specified as tRAS (max). After this command is issued, Read or Write operation can be executed. 7.2.2 Bank Precharge Command ( RAS = “L”, CAS = “H”, WE = “L”, BA0, BA1 = Bank, A8 = “L”, A0 to A7, A9 to A11 = Don’t Care) The Bank Precharge command percharges the bank designated by BA. The precharged bank is switched from the active state to the idle state. 7.2.3 Precharge All Command ( RAS = “L”, CAS = “H”, WE = “L”, BA0, BA1 = Don’t Care, A8 = “H”, A0 to A7, A9 to A11 = Don’t Care) The Precharge All command precharges all banks simultaneously. Then all banks are switched to the idle state. 7.2.4 Write Command ( RAS = “H”, CAS = “L”, WE = “L”, BA0, BA1 = Bank, A8 = “L”, A0 to A7 = Column Address) The write command performs a Write operation to the bank designated by BA. The write data are latched at both edges of DQS. The length of the write data (Burst Length) and column access sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write operation. 7.2.5 Write with Auto-precharge Command ( RAS = “H”, CAS = “L”, WE = “L”, BA0, BA1 = Bank, A8 = “H”, A0 to A7 = Column Address) The Write with Auto-precharge command performs the Precharge operation automatically after the Write operation. This command must not be interrupted by any other commands. 7.2.6 Read Command ( RAS = “H”, CAS = “L”, WE = “H”, BA0, BA1 = Bank, A8 = “L”, A0 to A7 = Column Address) The Read command performs a Read operation to the bank designated by BA. The read data are synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Read operation. 7.2.7 Read with Auto-precharge Command ( RAS = “H”, CAS = ”L”, WE = ”H”, BA0, BA1 = Bank, A8 = ”H”, A0 to A7 = Column Address) The Read with Auto-precharge command automatically performs the Precharge operation after the Read operation. Publication Release Date: Aug. 30, 2010 Revision A06 - 11 - W9412G2IB 1) READA ≥ tRAS (min) – (BL/2) x tCK Internal precharge operation begins after BL/2 cycle from Read with Auto-precharge command. 2) tRCD(min) ≤ READA < tRAS(min) – (BL/2) x tCK Data can be read with shortest latency, but the internal Precharge operation does not begin until after tRAS (min) has completed. This command must not be interrupted by any other command. 7.2.8 Mode Register Set Command ( RAS = “L”, CAS = “L”, WE = “L”, BA0 = “L”, BA1 = “L”, A0 to A11 = Register Data) The Mode Register Set command programs the values of CAS Latency, Addressing Mode, Burst Length and DLL reset in the Mode Register. The default values in the Mode Register after powerup are undefined, therefore this command must be issued during the power-up sequence. Also, this command can be issued while all banks are in the idle state. Refer to the table for specific codes. 7.2.9 Extended Mode Register Set Command ( RAS = “L”, CAS = “L”, WE = “L”, BA0 = “H”, BA1 = “L”, A0 to A11 = Register data) The Extended Mode Register Set command can be implemented as needed for function extensions to the standard (SDR-SDRAM). Currently the only available mode in EMRS is DLL enable/disable, decoded by A0. The default value of the extended mode register is not defined; therefore this command must be issued during the power-up sequence for enabling DLL. Refer to the table for specific codes. 7.2.10 No-Operation Command ( RAS = “H”, CAS = “H”, WE = “H”) The No-Operation command simply performs no operation (same command as Device Deselect). 7.2.11 Burst Read Stop Command ( RAS = “H”, CAS = “H”, WE = “L”) The Burst stop command is used to stop the burst operation. This command is only valid during a Burst Read operation. 7.2.12 Device Deselect Command ( CS = “H”) The Device Deselect command disables the command decoder so that the RAS , CAS , WE and Address inputs are ignored. This command is similar to the No-Operation command. 7.2.13 Auto Refresh Command ( RAS = “L”, CAS = “L”, WE = “H”, CKE = “H”, BA0, BA1, A0 to A11 = Don’t Care) AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS– BEFORE–RAS (CBR) refresh in previous DRAM types. This command is non-persistent, so it must be issued each time a refresh is required. - 12 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB The refresh addressing is generated by the internal refresh controller. This makes the address bits ”Don’t Care” during an AUTO REFRESH command. The DDR SDRAM requires AUTO REFRESH cycles at an average periodic interval of tREFI (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 * tREFI. 7.2.14 Self Refresh Entry Command ( RAS = “L”, CAS = “L”, WE = “H”, CKE = “L”, BA0, BA1, A0 to A11 = Don’t Care) The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH, and is automatically enabled upon exiting SELF REFRESH. Any time the DLL is enabled a DLL Reset must follow and 200 clock cycles should occur before a READ command can be issued. Input signals except CKE are “Don’t Care” during SELF REFRESH. Since CKE is an SSTL_2 input, VREF must be maintained during SELF REFRESH. 7.2.15 Self Refresh Exit Command (CKE = “H”, CS = “H” or CKE = “H”, RAS = “H”, CAS = “H”) The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command. The use of SELF REFREH mode introduces the possibility that an internally timed event can be missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an extra auto refresh command is recommended. 7.2.16 Data Write Enable /Disable Command (DM = “L/H” or DM0−DM3 = “L/H”) During a Write cycle, the DM0−DM3, DMs signal functions as Data Mask and can control every word of the input data. The DM0 signal controls DQ0 to DQ7, DM1 signal controls DQ8 to DQ15, DM2 signal controls DQ16 to DQ23 and DM3 signal controls DQ24 to DQ31. 7.3 Read Operation Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after tRCD from the Bank Activate command, the data is read out sequentially, synchronized with both edges of DQS (Burst Read operation). The initial read data becomes available after CAS Latency from the issuing of the Read command. The CAS Latency must be set in the Mode Register at power-up. When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst operation is terminated. When the Read with Auto-precharge command is issued, the Precharge operation is performed automatically after the Read cycle, then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Refer to the diagrams for Read operation. Publication Release Date: Aug. 30, 2010 Revision A06 - 13 - W9412G2IB 7.4 Write Operation Issuing the Write command after tRCD from the bank activate command. The input data is latched sequentially, synchronizing with both edges (rising & falling) of DQS after the Write command (Burst write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at power-up. When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated. When the Write with Auto-precharge command is issued, the Precharge operation is performed automatically after the Write cycle, then the bank is switched to the idle state, The Write with Autoprecharge command cannot be interrupted by any other command for the entire burst data duration. Refer to the diagrams for Write operation. 7.5 Precharge There are two Commands, which perform the precharge operation (Bank Precharge and Precharge All). When the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. The Bank Precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. The maximum time each bank can be held in the active state is specified as tRAS (max). Therefore, each bank must be precharged within tRAS(max) from the bank activate command. The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed only for the active bank and the precharge bank is then switched to the idle state. 7.6 Burst Termination When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after clock cycle of (CAS Latency) from the Precharge command. When the Burst Write cycle is interrupted by the Precharge command, the input circuit is reset at the same clock cycle at which the precharge command is issued. In this case, the DM signal must be asserted “high” during tWR to prevent writing the invalided data to the cell array. When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read operation is terminated. The Burst read Stop command is not supported during a write burst operation. Refer to the diagrams for Burst termination. 7.7 Refresh Operation Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation must be performed 4096 times (rows) within 64mS. The period between the Auto Refresh command and the next command is specified by tRFC. Self Refresh mode enter issuing the Self Refresh command (CKE asserted “low”), while all banks are in the idle state. The device is in Self Refresh mode for as long as CKE held “low”. In the case of distributed Auto Refresh commands, distributed auto refresh commands must be issued every 15.6 µS and the last distributed Auto Refresh commands must be performed within 15.6 µS before entering the self refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed within 15.6 µS. In Self Refresh mode, all input/output buffers are disabled, - 14 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh operation. 7.8 Power Down Mode Two types of Power Down Mode can be performed on the device: Active Power Down Mode and Precharge Power Down Mode. When the device enters the Power Down Mode, all input/output buffers are disabled resulting in low power dissipation (except CKE buffer). Power Down Mode enter asserting CKE “low” while the device is not running a burst cycle. Taking CKE “high” can exit this mode. When CKE goes high, a No operation command must be input at next CLK rising edge. Refer to the diagrams for Power Down Mode. 7.9 Input Clock Frequency Change during Precharge Power Down Mode DDR SDRAM input clock frequency can be changed under following condition: DDR SDRAM must be in precharged power down mode with CKE at logic LOW level. After a minimum of 2 clocks after CKE goes LOW, the clock frequency may change to any frequency between minimum and maximum operating frequency specified for the particular speed grade. During an input clock frequency change, CKE must be held LOW. Once the input clock frequency is changed, a stable clock must be provided to DRAM before precharge power down mode may be exited. The DLL must be RESET via EMRS after precharge power down exit. An additional MRS command may need to be issued to appropriately set CL etc. After the DLL relock time, the DRAM is ready to operate with new clock frequency. 7.10 Mode Register Operation The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A11 and BA0, BA1 address inputs. The Mode Register designates the operation mode for the read or write cycle. The register is divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time in clock cycle (4) DLL reset field to reset the DLL (5) Regular/Extended Mode Register filed to select a type of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended function (DLL enable/Disable mode). The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the Mode Register Set command must be issued before power operation. - 15 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 7.10.1 Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2, 4, 8 words. A2 A1 A0 BURST LENGTH 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x Reserved 2 words 4 words 8 words Reserved 7.10.2 Addressing Mode Select (A3) The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the A3 bit is “0”, Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both addressing Mode support burst length 2, 4 and 8 words. A3 ADDRESSING MODE 0 1 • Addressing Sequence of Sequential Mode Sequential Interleave A column access is performed by incrementing the column address input to the device. The address is varied by the Burst Length as the following. Addressing Sequence of Sequential Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 2 words (address bits is A0) not carried from A0 to A1 4 words (address bit A0, A1) Not carried from A1 to A2 8 words (address bits A2, A1 and A0) Not carried from A2 to A3 - 16 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB • Addressing Sequence of Interleave Mode A Column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following. Address Sequence for Interleave Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 words 4 words 8 words 7.10.3 CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values of CAS Latency depend on the frequency of CLK. A6 A5 A4 CAS LATENCY 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved Reserved 2 3 4 Reserved 2.5 Reserved 7.10.4 DLL Reset bit (A8) This bit is used to reset DLL. When the A8 bit is “1”, DLL is reset. 7.10.5 Mode Register /Extended Mode register change bits (BA0, BA1) These bits are used to select MRS/EMRS. BA1 0 0 1 BA0 0 1 x A11−A0 Regular MRS Cycle Extended MRS Cycle Reserved - 17 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 7.10.6 Extended Mode Register field 1) DLL Switch field (A0) This bit is used to select DLL enable or disable A0 DLL 0 1 2) Output Driver Strength Control field (A6, A1) Enable Disable The 100%, 60% and 30% or matched impedance driver strength are required Extended Mode Register Set (EMRS) as the following: A6 A1 BUFFER STRENGTH 0 0 1 1 0 1 0 1 100% Strength 60% Strength Reserved 30% Strength 7.10.7 Reserved field • Test mode entry bit (A7) This bit is used to enter Test mode and must be set to “0” for normal operation. • Reserved bits (A9, A10, A11) These bits are reserved for future operations. They must be set to “0” for normal operation. - 18 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 8. OPERATION MODE The following table shows the operation commands. 8.1 Simplified Truth Table COMMAND DEVICE STATE CKEn-1 CKEn DM (4) SYM. BA0,BA1 A8 A0-A7 A9A11 CS L L L L L L L L L L L H L L H RAS L L L H H H H L L H H X L L X H X H X H X X CAS H H H L L L L L L H H X L L X H X H X H X X WE H L L L L H H L L H L X H H X X X X X X X X ACT PRE PREA WRIT WRITA READ READA MRS EMRS NOP BST DSL AREF SELF SELEX Bank Active Bank Precharge Precharge All Write Write with Autoprecharge Read Read with Autoprecharge Mode Register Set Extended Mode Register Set No Operation Burst Read Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit Idle (3) (3) H H H X X X X X X X X X X X X H L H X X X X X X X X X X X X X X X V V X V V V V L, L H, L X X X X X X V L H L H L H C V X X X X X X V X X V V V V C V X X X X X X Any Any Active (3) H H H H H H H H H H H L Active (3) Active Active Idle Idle Any (3) (3) Active Any Idle Idle Idle (Self Refresh) Idle/ (5) Active Any (Power Down) Active Active L H L H PD Power Down Mode Entry Power Down Mode Exit Data Write Enable Data Write Disable H L X X X X PDEX L H H H X X X L H X X X X X X X X X L X X WDE WDD Notes: 1. V = Valid X = Don’t Care L = Low level H = High level 2. CKEn signal is input level when commands are issued. CKEn-1 signal is input level one clock cycle before the commands are issued. 3. These are state designated by the BA0, BA1 signals. 4. DM0−DM3 (W9412G2IB). 5. Power Down Mode can not entry in the burst cycle. - 19 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 8.2 Function Truth Table CS RAS H L L Idle L L L L L H L L Row Active L L L L L H L L L Read L L L L L H L L L Write L L L L L X H H H L L L L X H H H L L L L X H H H H L L L L X H H H H L L L L (Note 1) CURRENT STATE CAS X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L WE X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L ADDRESS X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code COMMAND DSL NOP/BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP/BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS NOP NOP ILLEGAL ILLEGAL Row activating NOP ACTION NOTES 3 3 Refresh or Self refresh Mode register accessing NOP NOP Begin read: Determine AP Begin write: Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop Term burst, new read: Determine AP ILLEGAL ILLEGAL Term burst, precharging ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL Term burst, start read: Determine AP Term burst, start read: Determine AP ILLEGAL Term burst, Precharging ILLEGAL ILLEGAL 2 2 4 4 3 5 6 3 6, 7 6 3 8 - 20 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 8.3 Function Truth Table, continued CS H L L Read with Autoprecharge L L L L L L H L L Write with Autoprecharge L L L L L L H L L L Precharging L L L L L H L L L Row Activating L L L L L CURRENT STATE RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L ADDRESS X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code COMMAND DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS ACTION Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Idle after tRP NOP-> Idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after tRP ILLEGAL ILLEGAL NOP-> Row active after tRCD NOP-> Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOTES 3 3 3 3 3 3 3 3 3 3 3 - 21 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 8.4 Function Truth Table, continued CS RAS CAS H L L L L L L L L Write Recovering with Autoprecharge H L L L L L L L L Refreshing H L L L L L Mode Register Accessing H L L L L X H H H H L L L L X H H H H L L L L X H H H L L X H H H L X H H L L H H L L X H H L L H H L L X H H L H L X H H L X CURRENT STATE Write Recovering WE X H L H L H L H L X H L H L H L H L X H L H X X X H L X X ADDRESS X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code X X X BA, CA, A8 BA, CA, A8 BA, RA BA, A8 X Op-Code X X X X X X X X X X X DSL NOP BST COMMAND ACTION NOP->Row active after tWR NOP->Row active after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP->Enter precharge after tWR NOP->Enter precharge after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP->Idle after tRC NOP->Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP->Row after tMRD NOP->Row after tMRD ILLEGAL ILLEGAL ILLEGAL NOTES READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/WRIT ACT/PRE/PREA AREF/SELF/MRS/EMRS 3 3 3 3 3 3 3 3 DSL NOP BST READ/WRIT ACT/PRE/PREA/ARE F/SELF/MRS/EMRS Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle. 2. Illegal if any bank is not idle. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. Illegal if tRCD is not satisfied. 5. Illegal if tRAS is not satisfied. 6. Must satisfy burst interrupt condition. 7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. Must mask preceding data which don’t satisfy tWR Remark: H = High level, L = Low level, X = High or Low level (Don’t Care), V = Valid data - 22 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 8.5 Function Truth Table for CKE CKE n-1 H L Self Refresh L L L L H Power Down L L H H H All banks Idle H H H L H H H Row Active H H H L Any State Other Than Listed Above H CURRENT STATE n X H H H H L X H L H L L L L L X H L L L L L X H CS X H L L L X X X X X H L L L L X X H L L L L X X RAS X X H H L X X X X X X H L H L X X X H L H L X X CAS X X H L X X X X X X X H L L X X X X H L L X X X WE X X X X X X X X X X X X H X X X X X X H X X X X ADDRESS X X X X X X X X X X X X X X X X X X X X X X X X INVALID ACTION NOTES Exit Self Refresh->Idle after tXSNR Exit Self Refresh->Idle after tXSNR ILLEGAL ILLEGAL Maintain Self Refresh INVALID Exit Power down->Idle after tIS Maintain power down mode Refer to Function Truth Table Enter Power down Enter Power down Self Refresh ILLEGAL ILLEGAL Power down Refer to Function Truth Table Enter Power down Enter Power down ILLEGAL ILLEGAL ILLEGAL Power down Refer to Function Truth Table 3 3 2 2 1 Notes: 1. Self refresh can enter only from the all banks idle state. 2. Power Down occurs when all banks are idle; this mode is referred to as precharge power down. 3. Power Down occurs when there is a row active in any bank; this mode is referred to as active power down. Remark: H = High level, L = Low level, X = High or Low level (Don’t Care), V = Valid data - 23 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 8.6 Simplified Stated Diagram SELF REFRESH SREF SREFX IDLE MRS/EMRS MODE REGISTER SET AREF AUTO REFRESH PD PDEX ACT ACTIVE POWERDOWN POWER DOWN PDEX PD ROW ACTIVE BST Read Read Write Write Write Read Read Write A Write A Read A Read A Read A PRE Write A PRE PRE Read A POWER APPLIED POWER ON PRE PRE CHARGE Automatic Sequence Command Sequence - 24 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETER SYMBOL RATING UNIT Input/Output Voltage Power Supply Voltage Operating Temperature (-4/-5/-6) Operating Temperature (-5I/-6I) Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current VIN, VOUT VDD, VDDQ TOPR TOPR TSTG TSOLDER PD IOUT -0.3 ~ VDDQ + 0.3 -0.3 ~ 3.6 0 ~ 70 -40 ~ 85 -55 ~ 150 260 1 50 V V °C °C °C °C W mA Note: Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 9.2 Recommended DC Operating Conditions PARAMETER Power Supply Voltage (for -5/-5I/-6/-6I) Power Supply Voltage (for -4) I/O Buffer Supply Voltage (for -5/-5I/-6/-6I) I/O Buffer Supply Voltage (for -4) Input reference Voltage Termination Voltage (System) Input High Voltage (DC) Input Low Voltage (DC) Differential Clock DC Input Voltage Input Differential Voltage. CLK and CLK inputs (DC) Input High Voltage (AC) Input Low Voltage (AC) Input Differential Voltage. CLK and CLK inputs (AC) Differential AC input Cross Point Voltage Differential Clock AC Middle Point (TA = 0 to 70°C for -4/-5/-6, TA = -40 to 85°C for -5I/-6I) SYM. VDD VDD VDDQ VDDQ VREF VTT VIH (DC) VIL (DC) VICK (DC) VID (DC) VIH (AC) VIL (AC) VID (AC) VX (AC) VISO (AC) MIN. 2.3 2.4 2.3 2.4 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 VREF + 0.31 0.7 VDDQ/2 - 0.2 VDDQ/2 - 0.2 TYP. 2.5 2.5 2.5 2.5 0.50 x VDDQ VREF - MAX. 2.7 2.6 2.7 2.6 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 VREF - 0.31 VDDQ + 0.6 VDDQ/2 + 0.2 VDDQ/2 + 0.2 UNIT V V V V V V V V V V V V V V V NOTES 2 2 2 2 2, 3 2, 8 2 2 15 13, 15 2 2 13, 15 12, 15 14, 15 Notes: Undershoot Limit: VIL (min) = -1.5V with a pulse width < 5 nS Overshoot Limit: VIH (max) = VDDQ +1.5V with a pulse width < 5 nS VIH (DC) and VIL (DC) are levels to maintain the current logic state. VIH (AC) and VIL (AC) are levels to change to the new logic state. - 25 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 9.3 Capacitance DELTA (MAX.) 0.5 0.25 0.5 - (VDD = VDDQ = 2.5V ±0.2V, f = 1 MHz, TA = 25 °C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V) SYMBOL CIN CCLK CI/O CNC PARAMETER Input Capacitance (except for CLK pins) Input Capacitance (CLK pins) DQ, DQS, DM Capacitance NC Pin Capacitance MIN. 2.0 3.0 1.5 - MAX. 4.0 5.5 5.5 1.5 UNIT pF pF pF pF Notes: These parameters are periodically sampled and not 100% tested. The NC pins have additional capacitance for adjustment of the adjacent pin capacitance. 9.4 Leakage and Output Buffer Characteristics PARAMETER Input Leakage Current (0V < VIN < VDDQ, All other pins not under test = 0V) Output Leakage Current (Output disabled, 0V < VOUT < VDDQ) Output High Voltage (under AC test load condition) Output Low Voltage (under AC test load condition) Output Minimum Source DC Current Output Minimum Sink DC Current Output Minimum Source DC Current Output Minimum Sink DC Current Output Minimum Source DC Current Output Minimum Sink DC Current 60% Strength 30% Strength 100% Strength SYMBOL II (L) IO (L) VOH VOL IOH (DC) IOL (DC) IOH (DC) IOL (DC) IOH (DC) IOL (DC) MIN. -2 -5 VTT +0.76 -15.2 15.2 -10.4 10.4 -7.2 7.2 MAX. 2 5 VTT -0.76 - UNIT µA µA V V mA mA mA mA mA mA NOTES 4, 6 4, 6 5 5 5 5 - 26 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 9.5 DC Characteristics PARAMETER Operating current: One Bank Active-Precharge; tRC = tRC min; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle Operating current: One Bank Active-Read-Precharge; Burst = 2; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA; Address and control inputs changing once per clock cycle. Precharge Power Down standby current: All Banks Idle; Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM Idle standby current: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs changing once per clock cycle; Vin > VIH min or Vin < VIL max for DQ, DQS and DM Active Power Down standby current: One Bank Active; Power down mode; CKE < VIL max; tCK = tCK min Active standby current: CS > VIH min; CKE > VIH min; One Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating current: Burst = 2; Reads; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL=3; tCK = tCK min; IOUT = 0mA Operating current: Burst = 2; Write; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL = 3; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle Auto Refresh current: tRC = tRFC min Self Refresh current: CKE < 0.2V Random Read current: 4 Banks Active Read with activate every 20nS, Auto-Precharge Read every 20 nS; Burst = 4; tRCD = 3; IOUT = 0mA; DQ, DM and DQS inputs changing twice per clock cycle; Address changing once per clock cycle SYM. MAX. -4 160 -5/-5I 150 -6/-6I 140 UNIT NOTES IDD0 mA 7 IDD1 IDD2P 180 170 160 mA 7, 9 30 30 30 mA IDD2N 45 45 45 mA 7 IDD3P 30 30 30 mA IDD3N 60 60 60 mA 7 IDD4R 240 220 200 mA 7, 9 IDD4W IDD5 IDD6 IDD7 270 210 3 340 250 200 3 320 230 190 3 300 mA mA mA mA 7 7 - 27 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 9.6 SYM. tRC tRFC tRAS tRCDRD tRCDWR tRAP tCCD tRP tRRD tWR tDAL AC Characteristics and Operating Condition PARAMETER Active to Ref/Active Command Period Ref to Ref/Active Command Period Active to Precharge Command Period RAS to CAS delay for Read RAS to CAS delay for Write -4 MIN. 48 60 40 5 3 16 1 16 12 3 4 4 -0.6 -0.6 0.45 0.45 min (tCL,tCH) tHP -0.5 0.9 0.4 0.4 0.4 1.75 0.4 0.4 0.2 0.2 0 0.6 0.6 1.1 0.6 12 12 0.6 0.6 0.4 0.55 0.55 70000 -5/-5I MAX. MIN. 50 70 40 4 2 15 1 15 10 3 7.5 6 5 -0.7 -0.6 0.45 0.45 min, (tCL,tCH) tHP -0.5 0.9 0.4 0.4 0.4 1.75 0.4 0.4 0.2 0.2 0 0.6 0.6 1.1 0.6 12 12 12 0.7 0.6 0.4 0.55 0.55 100000 -6/-6I MIN. 54 70 42 3 100000 MAX. MAX. UNIT NOTES nS tCK 2 18 1 18 12 2 7.5 6 6 -0.7 -0.6 12 12 12 0.7 16 0.6 0.4 0.45 0.45 min, (tCL,tCH) tHP -0.5 0.9 0.4 0.4 0.4 1.75 0.4 0.4 0.2 0.2 0 nS 0.6 0.6 tCK 11 nS 1.1 0.6 tCK 11 nS 0.55 0.55 tCK 11 nS tCK 18 nS tCK nS Active to Read with Auto-precharge Enable Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time Auto-precharge Write Recovery + Precharge Time CL = 2 tCK CLK Cycle Time CL = 2.5 CL = 3 CL = 4 tAC tDQSCK tDQSQ tCH tCL tHP tQH tRPRE tRPST tDS tDH tDIPW tDQSH tDQSL tDSS tDSH tWPRES Data Access Time from CLK, CLK DQS Output Access Time from CLK, CLK Data Strobe Edge to Output Data Edge Skew CLk High Level Width CLK Low Level Width CLK Half Period (minimum of actual tCH, tCL) DQ Output Data Hold Time from DQS DQS Read Preamble Time DQS Read Postamble Time DQ and DM Setup Tim DQ and DM Hold Time DQ and DM Input Pulse Width (for each input) DQS Input High Pulse Width DQS Input Low Pulse Width DQS Falling Edge to CLK Setup Time DQS Falling Edge Hold Time from CLK Clock to DQS Write Preamble Set-up Time - 28 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB AC Characteristics and Operating Condition, continued SYM. tWPREH tWPST tDQSS tIS tIH tHZ tLZ tT(SS) tWTR tXSNR tXSRD tREFi tMRD PARAMETER Clock to DQS Write Preamble Hold Time DQS Write Postamble Time Write Command to First DQS Latching Transition Input Setup Time Input Hold Time Data-out CLK, CLK Data-out CLK, CLK SSTL Input Transition Internal Write to Read Command Delay Exit Self Refresh to non-Read Command Exit Self Refresh to Read Command Refresh Interval Time (4K/64mS) Mode Register Set Cycle Time Low-impedance Time from High-impedance Time from -4 MIN. 0.25 0.4 0.72 0.75 0.75 0.7 -0.7 0.5 2 72 200 15.6 8 10 0.7 1.5 0.6 1.25 -5/-5I MAX. MIN. 0.25 0.4 0.72 0.75 0.75 0.7 -0.7 0.5 2 75 200 15.6 12 0.7 1.5 0.6 1.25 -6/-6I MIN. 0.25 0.4 0.75 0.8 0.8 0.7 -0.7 0.5 1 75 200 15.6 0.7 1.5 0.6 1.25 MAX. MAX. UNIT NOTES tCK 11 nS tCK nS tCK µS nS 17 9.7 AC Test Conditions PARAMETER SYMBOL VALUE UNIT Input High Voltage (AC) Input Low Voltage (AC) Input Reference Voltage Termination Voltage Input Signal Peak to Peak Swing Differential Clock Input Reference Voltage Input Difference Voltage. CLK and CLK Inputs (AC) Input Signal Minimum Slew Rate Output Timing Measurement Reference Voltage VIH VIL VREF VTT VSWING VR VID (AC) SLEW VOTR VREF + 0.31 VREF - 0.31 0.5 x VDDQ 0.5 x VDDQ 1.0 Vx (AC) 1.5 1.0 0.5 x VDDQ V V V V V V V V/nS V - 29 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB VDDQ VIH min (AC) V SWING (MAX) VREF VTT 50 Ω VIL max (AC) VSS T T Output Output V(out) 30pF SLEW = (VIH min (AC) - VILmax (AC)) / T Timing Reference Load Notes: (1) (2) (3) (4) (5) (6) (7) (8) (9) Conditions outside the limits listed under “Absolute Maximum Ratings” may cause permanent damage to the device. All voltages are referenced to VSS, VSSQ. ( 2.5V±0.1V for DDR500) Peak to peak AC noise on VREF may not exceed ±2% VREF(DC). VOH = 1.95V, VOL = 0.35V VOH = 1.9V, VOL = 0.4V The values of IOH(DC) is based on VDDQ = 2.3V and VTT = 1.19V. The values of IOL(DC) is based on VDDQ = 2.3V and VTT = 1.11V. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK and tRC. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF. These parameters depend on the output loading. Specified values are obtained with the output open. (10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed slope. (11) IF the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., tDQSS = 0.75 × tCK, tCK = 7.5 nS, 0.75 × 7.5 nS = 5.625 nS is rounded up to 5.6 nS.) (12) VX is the differential clock cross point voltage where input timing measurement is referenced. (13) VID is magnitude of the difference between CLK input level and CLK input level. (14) VISO means {VICK(CLK)+VICK( CLK )}/2. (15) Refer to the figure below. - 30 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB CLK VX CLK VICK VSS VID(AC) VICK VX VX VICK VX VICK VX VID(AC) 0 V Differential VISO VISO(min) VSS VISO(max) (16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock. (17) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. (18) tDAL = (tWR/tCK) + (tRP/tCK) - 31 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10. TIMING WAVEFORMS 10.1 Command Input Timing tCK tCK CLK CLK tCH tCL tIS CS tIH tIS RAS tIH tIS CAS tIH tIS WE tIH tIS A0~A11 BA0,1 tIH Refer to the Command Truth Table 10.2 Timing of the CLK Signals - 32 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.3 Read Timing (Burst Length = 4) tCH CLK tCL tCK CLK tIS CMD tIH READ tIS ADD Col tIH tDQSCK CAS Latency = 2 DQS Hi-Z Preamble tDQSQ Output (Data) Hi-Z tAC tLZ tDQSCK CAS Latency = 3 DQS tRPRE Hi-Z Preamble tDQSQ Output (Data) Hi-Z tAC tLZ tQH tQH tDQSQ tDQSCK tRPRE tDQSCK tRPST Hi-Z Postamble tDQSQ Hi-Z QA0 DA0 QA1 DA1 QA2 DA2 QA3 DA3 tHZ tDQSCK tDQSCK tRPST Hi-Z tQH tQH tDQSQ Postamble tDQSQ Hi-Z QA0 DA0 QA1 DA1 QA2 DA2 QA3 DA3 tHZ Notes: The correspondence of DQS0−DQS3 to DQ. (W9412G2IB) DQS0 DQS1 DQS2 DQS3 DQ0−7 DQ8−15 DQ16−23 DQ24−31 - 33 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.4 Write Timing (Burst Length = 4) tC H CLK tC L tC K CLK t IS t IH CM D W RIT t IS tIH tD SH t D SS t D SH t D SS ADD Col x32 device t W PR ES tW PR EH t D Q SH t DQ SL t D Q SH t W PST DQ S0 Pream ble tD S tD H tD S tD H tD S Postam ble tD H DQ 0~7 t D Q SS t W PR ES DA0 t D SH t D Q SH t W PR EH DA1 t D SS t DQ SL DA2 t D SH t D Q SH DA3 t D SS t W PST DQ S3 Pream ble tD S tD H DA0 t D Q SS DA1 DA2 Postam ble tD S t DH tD S tD H DQ 24~31 DA3 Note: x32 has four DQSs. (DQS0 for lower byte and DQS3 for upper byte) - 34 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.5 DM, DATA MASK (W9412G2IB) CLK CLK CMD W RIT DQS0 t DS tDS t DH t DH DM0 t DIPW DQ0~DQ7 D0 D1 t DIPW Masked D3 DQS3 t DS DM3 t DS tDH t DH t DIPW DQ24~DQ31 D0 Masked D2 D3 tDIPW - 35 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.6 Mode Register Set (MRS) Timing CLK CLK tMRD CMD MRS NEXT CMD ADD Register Set data A0 A2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 "0" "0" "0" "0" "0" Mode Register Set or Extended Mode Register Set Reserved "0" Reserved DLL Reset CAS Latency Addressing Mode Burst Length 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A3 0 1 A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A8 0 1 BA1 0 0 1 1 BA0 0 1 0 1 A4 0 1 0 1 0 1 0 1 A0 0 1 0 1 0 1 0 1 Burst Length Sequential Reserved 2 4 8 Interleaved Reserved 2 4 8 Reserved Reserved Addressing Mode Sequential Interleaved CAS Latency Reserved 2 3 4 Reserved 2.5 Reserved DLL Reset No Yes MRS or EMRS Regular MRS cycle Extended MRS cycle Reserved * "Reserved" should stay "0" during MRS cycle. - 36 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.7 Extend Mode Register Set (EMRS) Timing CLK CLK tMRD CMD EMRS NEXT CMD ADD Register Set data A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 DLL Switch Buffer Strength "0" "0" Reserved "0" "0" "0" "0" "0" Reserved "0" "0" "0" "0" "0" Mode Register Set or Extended Mode Register Set BA1 0 0 1 1 Buffer Strength A6 0 0 1 1 A0 0 1 DLL Switch Enable Disable A1 0 1 0 1 Buffer Strength 100% Strength 60% Strength Reserved 30% Strength BA0 0 1 0 1 MRS or EMRS Regular MRS cycle Extended MRS cycle * "Reserved" should stay "0" during EMRS cycle. - 37 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.8 Auto-precharge Timing (Read Cycle, CL = 2) 1) tRCD (READA) ≥ tRAS (min) – (BL/2) × tCK tRAS CLK CLK BL=2 CMD ACT READA AP tRP ACT DQS DQ Q0 Q1 BL=4 CMD ACT READA AP ACT DQS DQ Q0 Q1 Q2 Q3 BL=8 CMD ACT READA AP ACT DQS DQ Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Notes: CL=2 shown; same command operation timing with CL=2.5 and CL=3 In this case, the internal precharge operation begin after BL/2 cycle from READA command. Represents the start of internal precharging. The Read with Auto-precharge command cannot be interrupted by any other command. AP - 38 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.9 Auto-precharge Timing (Read cycle, CL = 2), continued 2) tRCD/RAP(min) ≤ tRCD (READA) < tRAS (min) – (BL/2) × tCK Notes: CL2 shown; same command operation timing with CL = 2.5, CL=3. In this case, the internal precharge operation does not begin until after tRAS (min) has command. AP Represents the start of internal precharging. The Read with Auto-precharge command cannot be interrupted by any other command. - 39 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.10 Auto-precharge Timing (Write Cycle) CLK CLK tDAL BL=2 CMD WRITA AP ACT DQS DQ D0 D1 tDAL BL=4 CMD WRITA AP ACT DQS DQ D0 D1 D2 D3 tDAL BL=8 CMD WRITA AP ACT DQS DQ D0 D1 D2 D3 D4 D5 D6 D7 The Write with Auto-precharge command cannot be interrupted by any other command. AP Represents the start of internal precharging. - 40 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) 10.12 Burst Read Stop (BL = 8) - 41 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.13 Read Interrupted by Write & BST (BL = 8) Burst Read cycle must be terminated by BST Command to avoid I/O conflict. 10.14 Read Interrupted by Precharge (BL = 8) CLK CLK CMD READ PRE CAS Latency = 2 DQS CAS Latency DQ Q0 Q1 Q2 Q3 Q4 Q5 CAS Latency = 3 DQS CAS Latency DQ Q0 Q1 Q2 Q3 Q4 Q5 - 42 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.15 Write Interrupted by Write (BL = 2, 4, 8) 10.16 Write Interrupted by Read (CL = 2, BL = 8) CLK CLK CMD WRIT READ DQS DM tWTR DQ D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Data must be masked by DM Data masked by READ command, DQS input ignored. - 43 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.17 Write Interrupted by Read (CL = 3, BL = 4) CLK CLK CMD WRIT READ DQS DM tWTR DQ D0 D1 D2 D3 Q0 Q1 Q2 Q3 Data must be masked by DM 10.18 Write Interrupted by Precharge (BL = 8) CLK CLK CMD WRIT PRE ACT tWR DQS tRP DM DQ D0 D1 D2 D3 D4 D5 D6 D7 Data must be masked by DM Data masked by PRE command, DQS input ignored. - 44 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) CLK CLK tRC(b) tRC(a) tRRD CMD ACTa ACTb READAa READAb ACTa tRRD ACTb tRCD(a) tRAS(a) tRCD(b) tRAS(b) DQS tRP(a) tRP(b) Preamble CL(a) Postamble CL(b) Q0a Q1a Preamble Postamble DQ ACTa/b : Bank Act. CMD of bank a/b READAa/b : Read with Auto Pre.CMD of bank a/b APa/b : Auto Pre. of bank a/b Q0b Q1b APa APb 10.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) CLK CLK tRC(b) tRC(a) tRRD tRRD ACTb tRCD(a) tRAS(a) tRCD(b) tRAS(b) tRP(b) tRP(a) READAa READAb ACTa ACTb CMD ACTa DQS Preamble CL(a) CL(b) Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b Postamble DQ ACTa/b : Bank Act. CMD of bank a/b READAa/b : Read with Auto Pre.CMD of bank a/b APa/b : Auto Pre. of bank a/b APa APb - 45 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) CLK CLK tRC(a) tRRD CMD ACTa ACTb tRCD(a) tRRD ACTc tRRD READAa ACTd tRRD READAb ACTa READAc tRAS(a) tRCD(b) tRAS(b) tRP tRCD(c) tRAS(c) tRCD(d) tRAS(d) DQS Preamble CL(a) Postamble CL(b) Q0a Q1a Q0b Q1b Preamble DQ ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d APa/b/c/d : Auto Pre. of bank a/b/c/d APa APb 10.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) - 46 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.23 Auto Refresh Cycle Note: CKE has to be kept “High” level for Auto-Refresh cycle. 10.24 Precharge/Activate Power Down Mode Entry and Exit Timing Note: 1. If power down occurs when all banks are idle, this mode is referred to as precharge power down. 2. If power down occurs when there is a row active in any bank, this mode is referred to as active power down. 10.25 Input Clock Frequency Change during Precharge Power Down Mode Timing CLK CLK CMD NOP NOP NOP DLL RESET NOP NOP CMD CKE Frequency Change Occurs here tIS tRP 200 clocks Minmum 2 clocks required before changing frequency Stable new clock before power down exit - 47 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 10.26 Self Refresh Entry and Exit Timing CLK CLK tIH CKE tIS tIH tIS CMD PREA NOP tRP SELF SELEX NOP CMD Entry Exit tXSNR tXSRD SELF SELFX NOP ACT NOP READ NOP Entry Exit Note: If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit. - 48 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 11. PACKAGE SPECIFICATION 11.1 144L LFBGA (12X12X1.40 mm^3, Ø=0.5mm) - 49 - Publication Release Date: Aug. 30, 2010 Revision A06 W9412G2IB 12. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A01 A02 A03 A04 A05 A06 Aug. 19, 2008 Sep. 18, 2008 Nov. 20, 2008 Apr. 20, 2009 May 27, 2009 Aug. 30, 2010 All 28 5, 27 4, 25, 30 4, 5, 25, 27~29 4, 5, 25, 27~29 Initial formally data sheet Revise typo error of tRCDRD/tRCDWR AC parameters unit change the unit from nS to tCK Revise all speed grade DC parameter, IDDx values Revise -4 speed grade power supply voltage range from 2.6V ±0.1V to 2.5V ±0.1V Add -6I industrial grade parts Add -5I industrial grade parts Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 50 - Publication Release Date: Aug. 30, 2010 Revision A06