W9412G6CH

W9412G6CH 2M × 4 BANKS × 16 BITS DDR SDRAM Table of Contents1. 2. 3. 4. 5. 6. 7. GENERAL DESCRIPTION .............................................................................................................. 4 FEATURES ...................................................................................................................................... 4 KEY PARAMETERS ........................................................................................................................ 5 PIN CONFIGURATION .................................................................................................................... 6 PIN DESCRIPTION.......................................................................................................................... 7 BLOCK DIAGRAM ........................................................................................................................... 8 FUNCTIONAL DESCRIPTION......................................................................................................... 9 7.1 7.2 Power Up Sequence ............................................................................................................. 9 Command Function ............................................................................................................... 9 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 Bank Activate Command .................................................................................................. 9 Bank Precharge Command .............................................................................................. 9 Precharge All Command .................................................................................................. 9 Write Command................................................................................................................ 9 Write with Auto-precharge Command............................................................................. 10 Read Command ............................................................................................................. 10 Read with Auto-precharge Command ............................................................................ 10 Mode Register Set Command ........................................................................................ 10 Extended Mode Register Set Command ........................................................................ 10 7.2.10 No-Operation Command ................................................................................................ 11 7.2.11 Burst Read Stop Command............................................................................................ 11 7.2.12 Device Deselect Command ............................................................................................ 11 7.2.13 Auto Refresh Command ................................................................................................. 11 7.2.14 Self Refresh Entry Command ......................................................................................... 11 7.2.15 Self Refresh Exit Command ........................................................................................... 12 7.2.16 Data Write Enable /Disable Command ........................................................................... 12 7.3 7.4 7.5 7.6 7.7 7.8 7.9 Read Operation ................................................................................................................... 12 Write Operation ................................................................................................................... 12 Precharge ............................................................................................................................ 13 Burst Termination ................................................................................................................ 13 Refresh Operation ............................................................................................................... 13 Power Down Mode .............................................................................................................. 13 Mode Register Operation .................................................................................................... 14 7.9.1 Burst Length field (A2 to A0) .......................................................................................... 14 -1- Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 7.9.2 7.9.3 7.9.4 7.9.5 7.9.6 7.9.7 Addressing Mode Select (A3) ......................................................................................... 14 CAS Latency field (A6 to A4) .......................................................................................... 16 DLL Reset bit (A8) .......................................................................................................... 16 Mode Register/Extended Mode register change bits (BS0, BS1) ................................... 16 Extended Mode Register field ........................................................................................ 17 Reserved field ................................................................................................................ 17 8. OPERATION MODE ...................................................................................................................... 18 8.1 8.2 8.3 8.4 Simplified Truth Table ......................................................................................................... 18 Function Truth Table ........................................................................................................... 19 Function Truth Table for CKE.............................................................................................. 22 Simplified Stated Diagram................................................................................................... 23 Absolute Maximum Ratings................................................................................................. 24 Recommended DC Operating Conditions........................................................................... 24 Capacitance......................................................................................................................... 25 Leakage and Output Buffer Characteristics ........................................................................ 25 DC Characteristics............................................................................................................... 26 AC Characteristics and Operating Condition ...................................................................... 27 AC Test Conditions.............................................................................................................. 29 9. ELECTRICAL CHARACTERISTICS .............................................................................................. 24 9.1 9.2 9.3 9.4 9.5 9.6 9.7 10. SYSTEM CHARACTERISTICS FOR DDR SDRAM...................................................................... 32 10.1 Table 1: Input Slew Rate for DQ, DQS, and DM................................................................. 32 10.2 Table 2: Input Setup & Hold Time Derating for Slew Rate.................................................. 32 10.3 Table 3: Input/Output Setup & Hold Time Derating for Slew Rate...................................... 32 10.4 Table 4: Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate ...................... 32 10.5 Table 5: Output Slew Rate Characteristics (X16 Devices only).......................................... 32 10.6 Table 6: Output Slew Rate Matching Ratio Characteristics ................................................ 33 10.7 Table 7: AC Overshoot/Undershoot Specification for Address and Control Pins ............... 33 10.8 Table 8: Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins ................ 34 10.9 System Notes: ..................................................................................................................... 35 11. TIMING WAVEFORMS .................................................................................................................. 37 11.1 Command Input Timing ....................................................................................................... 37 11.2 Timing of the CLK Signals................................................................................................... 37 11.3 Read Timing (Burst Length = 4) .......................................................................................... 38 11.4 Write Timing (Burst Length = 4) .......................................................................................... 39 11.5 DM, DATA MASK (W9412G6CH) ....................................................................................... 40 11.6 Mode Register Set (MRS) Timing ....................................................................................... 41 Publication Release Date:Jul. 04, 2007 Revision A06 -2- W9412G6CH 11.7 Extend Mode Register Set (EMRS) Timing......................................................................... 42 11.8 Auto-precharge Timing (Read Cycle, CL = 2) ..................................................................... 43 11.9 Auto-precharge Timing (Read cycle, CL = 2), continued .................................................... 44 11.10 Auto-precharge Timing (Write Cycle) .................................................................................. 45 11.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) ................................................................ 46 11.12 Burst Read Stop (BL = 8) .................................................................................................... 46 11.13 Read Interrupted by Write & BST (BL = 8).......................................................................... 47 11.14 Read Interrupted by Precharge (BL = 8) ............................................................................. 47 11.15 Write Interrupted by Write (BL = 2, 4, 8) ............................................................................. 48 11.16 Write Interrupted by Read (CL = 2, BL = 8) ........................................................................ 48 11.17 Write Interrupted by Read (CL = 3, BL = 4) ........................................................................ 49 11.18 Write Interrupted by Precharge (BL = 8) ............................................................................. 49 11.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) ........................................................... 50 11.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) ........................................................... 50 11.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) ........................................................... 51 11.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) ........................................................... 51 11.23 Auto Refresh Cycle.............................................................................................................. 52 11.24 Active Power Down Mode Entry and Exit Timing................................................................ 52 11.25 Precharged Power Down Mode Entry and Exit Timing ....................................................... 52 11.26 Self Refresh Entry and Exit Timing ..................................................................................... 53 12. PACKAGE SPECIFICATION ......................................................................................................... 54 12.1 66L TSOP – 400 mil ............................................................................................................ 54 13. REVISION HISTORY ..................................................................................................................... 55 -3- Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 1. GENERAL DESCRIPTION W9412G6CH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM); organized as 2M words × 4 banks × 16 bits. Using pipelined architecture and 0.11µm process technology, W9412G6CH delivers a data bandwidth of up to 444M words per second (-45). To fully comply with the personal computer industrial standard, W9412G6CH is sorted into four speed grades: -45, -5, -6 and -75 .The -45 is compliant to the DDR444/CL3 specification, the -5 is compliant to the DDR400/CL3 specification, the -6 is compliant to the DDR333/CL2.5 specification and the -75 is compliant to the DDR266/CL2 specification. All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. Write and Read data are synschronized with the both edges of DQS (Data Strobe). By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9412G6CH is ideal for main memory in high performance applications. 2. FEATURES • • • • • • • • • • • • • • • • • • 2.5V ±0.2V Power Supply for DDR266 2.5V ±0.2V Power Supply for DDR333 2.6V ± 5% Power Supply for DDR400 2.6V ± 5% Power Supply for DDR444 Up to 222 MHz Clock Frequency Double Data Rate architecture; two data transfers per clock cycle Differential clock inputs (CLK and CLK ) DQS is edge-aligned with data for Read; center-aligned with data for Write CAS Latency: 2, 2.5 and 3 Burst Length: 2, 4 and 8 Auto Refresh and Self Refresh Precharged Power Down and Active Power Down Write Data Mask Write Latency = 1 15.6µS Refresh interval (4K / 64 mS Refresh) Maximum burst refresh cycle: 8 Interface: SSTL_2 Packaged in TSOP II 66-pin, 400 mil, 0.65 mm pin pitch, using Pb free with RoHS compliant -4- Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 3. KEY PARAMETERS SYMBOL DESCRIPTION MIN./MAX. -45 -5 -6 -75 tCK CLOCK TIME CYCLE CL = 2 CL = 2.5 CL = 3 Min. Min. Min. Min. Min. Max. Max. Max. 4.5 nS 40 nS 50 nS 140mA 180mA 3 mA 7.5 nS 6 nS 5 nS 40 nS 50 nS 140mA 180mA 3 mA 7.5 nS 6 nS 6 nS 42 nS 54 nS 130mA 170mA 3 mA 7.5 nS 7.5 nS 7.5 nS 45 nS 60 nS 120mA 160mA 3 mA tRAS tRC IDD1 IDD4 IDD6 Active to Precharge Command Period Active to Ref/Active Command Period Operation Current (Single bank) Burst Operation Current Self-Refresh Current -5- Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 4. PIN CONFIGURATION VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC1 VDDQ LDQS NC1 VDD NC1 LDM WE CAS RAS CS NC1 BS0 BS1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC1 VSSQ UDQS NC1 VREF VSS UDM CLK CLK CKE NC1 NC1 A11 A9 A8 A7 A6 A5 A4 VSS -6- Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 5. PIN DESCRIPTION PIN NUMBER 28 − 32, 35 − 41 26, 27 2, 4, 5, 7, 8, 10, 11, 13, 54, 56, 57, 59, 60, 62, 63, 65 16,51 PIN NAME A0 − A11 FUNCTION DESCRIPTION Multiplexed pins for row and column address. Address Row address: A0 − A11. Column address: A0 − A8. (A10 is used for Auto-precharge) Select bank to activate during row address latch time, or bank to read/write during column address latch time. The DQ0 – DQ15 input and output data are synchronized with both edges of DQS. DQS is Bi-directional signal. DQS is input signal during write operation and output signal during read operation. It is Edgealigned with read data, Center-aligned with write data. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command inputs (along with CS ) define the command being entered. When DM is asserted “high” in burst write, the input data is masked. DM is synchronized with both edges of DQS. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of CLK . CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. Power for logic circuit inside DDR SDRAM. Ground for logic circuit inside DDR SDRAM. BS0, BS1 DQ0 − DQ15 LDQS, UDQS Bank Select Data Input/ Output Data Strobe 24 CS RAS , CAS , WE Chip Select 23, 22, 21 20, 47 Command Inputs Write Mask Differential Clock Inputs LDM, UDM CLK, CLK 45, 46 44 49 1, 18, 33 34, 48, 66 3, 9, 15, 55, 61 6, 12, 52, 58, 64 14, 17, 19, 25, 42, 43, 50, 53 CKE VREF VDD VSS VDDQ VSSQ NC1 Clock Enable Reference Voltage VREF is reference voltage for inputs. Power (+2.5V) Ground Power (+2.5V) for Separated power from VDD, used for output buffer, to improve noise. I/O Buffer Ground for I/O Buffer No Connection Separated ground from VSS, used for output buffer, to improve noise. No connection (NC pin should be connected to GND or floating) -7- Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 6. BLOCK DIAGRAM CLK CLK DLL CLOCK BUFFER CKE CS RAS CAS WE CONTRO L SIGNAL GENERATO R COMMAND DECODER COLUMN DECODER COLUMN DECODER ROW DECODER A10 CELL ARRAY BANK #0 ROW DECODER CELL ARRAY BANK #1 A0 ADDRESS MODE REGISTER SENSE AMPLIFIER SENSE AMPLIFIER A9 A11 BS1 BS0 BUFFER PREFETCH REGISTER DATA CONTROL CIRCUIT REFRESH COUNTER COLUMN COUNTER DQ BUFFER DQ0 DQ15 LDQS UDQS LDM UDM COLUMN DECODER COLUMN DECODER ROW DECODER CELL ARRAY BANK #2 ROW DECODER CELL ARRAY BANK #3 SENSE AMPLIFIER SENSE AMPLIFIER NOTE: The cell array configuration is 4096 * 512 * 16 -8- Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 7. FUNCTIONAL DESCRIPTION 7.1 Power Up Sequence (1) Apply power and attempt to CKE at a low state ( ≤ 0.2V), all other inputs may be undefined 1) Apply VDD before or at the same time as VDDQ. 2) Apply VDDQ before or at the same time as VTT and VREF. Start Clock and maintain stable condition for 200 µS (min.). After stable power and clock, apply NOP and take CKE high. Issue precharge command for all banks of the device. Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type. Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8. (An additional 200 cycles(min) of clock are required for DLL Lock before any executable command applied.) Issue precharge command for all banks of the device. Issue two or more Auto Refresh commands. Issue MRS-Initialize device operation with the reset DLL bit deactivated A8 to low. (2) (3) (4) (5) (6) (7) (8) (9) 7.2 7.2.1 Command Function Bank Activate Command ( RAS = “L”, CAS = “H”, WE = “H”, BS0, BS1 = Bank, A0 to A11 = Row Address) The Bank Activate command activates the bank designated by the BS (Bank address) signal. Row addresses are latched on A0 to A11 when this command is issued and the cell data is read out of the sense amplifiers. The maximum time that each bank can be held in the active state is specified as tRAS (max). After this command is issued, Read or Write operation can be executed. 7.2.2 Bank Precharge Command ( RAS = “L”, CAS = “H”, WE = “L”, BS0, BS1 = Bank, A10 = “L”, A0 to A9, A11 = Don’t Care) The Bank Precharge command percharges the bank designated by BS. The precharged bank is switched from the active state to the idle state. 7.2.3 Precharge All Command ( RAS = “L”, CAS = “H”, WE = “L”, BS0, BS1 = Don’t Care, A10 = “H”, A0 to A9, A11 = Don’t Care) The Precharge All command precharges all banks simultaneously. Then all banks are switched to the idle state. 7.2.4 Write Command ( RAS = “H”, CAS = “L”, WE = “L”, BS0, BS1 = Bank, A10 = “L”, A0 to A8 = Column Address) The write command performs a Write operation to the bank designated by BS. The write data are latched at both edges of DQS. The length of the write data (Burst Length) and column access sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write operation. Publication Release Date: Jul. 04, 2007 Revision A06 -9- W9412G6CH 7.2.5 Write with Auto-precharge Command ( RAS = “H”, CAS = “L”, WE = “L”, BS0, BS1 = Bank, A10 = “H”, A0 to A8 = Column Address) The Write with Auto-precharge command performs the Precharge operation automatically after the Write operation. This command must not be interrupted by any other commands. 7.2.6 Read Command ( RAS = “H”, CAS = “L”, WE = “H”, BS0, BS1 = Bank, A10 = “L”, A0 to A8 = Column Address) The Read command performs a Read operation to the bank designated by BS. The read data are synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Read operation. 7.2.7 Read with Auto-precharge Command ( RAS = “H”, CAS = ”L”, WE = ”H”, BS0, BS1 = Bank, A10 = ”H”, A0 to A8 = Column Address) The Read with Auto-precharge command automatically performs the Precharge operation after the Read operation. 1. READA ≥ tRAS (min) – (BL/2) x tCK Internal precharge operation begins after BL/2 cycle from Read with Auto-precharge command. 2. tRCD(min) ≤ READA < tRAS(min) – (BL/2) x tCK Data can be read with shortest latency, but the internal Precharge operation does not begin until after tRAS (min) has completed. This command must not be interrupted by any other command. 7.2.8 Mode Register Set Command ( RAS = “L”, CAS = “L”, WE = “L”, BS0 = “L”, BS1 = “L”, A0 to A11 = Register Data) The Mode Register Set command programs the values of CAS Latency, Addressing Mode, Burst Length and DLL reset in the Mode Register. The default values in the Mode Register after powerup are undefined, therefore this command must be issued during the power-up sequence. Also, this command can be issued while all banks are in the idle state. Refer to the table for specific codes. 7.2.9 Extended Mode Register Set Command ( RAS = “L”, CAS = “L”, WE = “L”, BS0 = “H”, BS1 = “L”, A0 to A11 = Register data) The Extended Mode Register Set command can be implemented as needed for function extensions to the standard (SDR-SDRAM). Currently the only available mode in EMRS is DLL enable/disable, decoded by A0. The default value of the extended mode register is not defined; therefore this command must be issued during the power-up sequence for enabling DLL. Refer to the table for specific codes. - 10 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 7.2.10 No-Operation Command ( RAS = “H”, CAS = “H”, WE = “H”) The No-Operation command simply performs no operation (same command as Device Deselect). 7.2.11 Burst Read Stop Command ( RAS = “H”, CAS = “H”, WE = “L”) The Burst stop command is used to stop the burst operation. This command is only valid during a Burst Read operation. 7.2.12 Device Deselect Command ( CS = “H”) The Device Deselect command disables the command decoder so that the RAS , CAS , WE and Address inputs are ignored. This command is similar to the No-Operation command. 7.2.13 Auto Refresh Command ( RAS = “L”, CAS = “L”, WE = “H”, CKE = “H”, BS0, BS1, A0 to A11 = Don’t Care) AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS– BEFORE–RAS (CBR) refresh in previous DRAM types. This command is non persistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits ”Don’t Care” during an AUTO REFRESH command. The DDR SDRAM requires AUTO REFRESH cycles at an average periodic interval of tREFI (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 * tREFI. 7.2.14 Self Refresh Entry Command ( RAS = “L”, CAS = “L”, WE = “H”, CKE = “L”, BS0, BS1, A0 to A11 = Don’t Care) The SELF REFRESH command can be used to retain data in the DD SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH, and is automatically enabled upon exiting SELF REFRESH. Any time the DLL is enabled a DLL Reset must follow and 200 clock cycles should occur before a READ command can be issued. Input signals except CKE are “Don’t Care” during SELF REFRESH. Since CKE is an SSTL_2 input, VREF must be maintained during SELF REFRESH. - 11 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 7.2.15 Self Refresh Exit Command (CKE = “H”, CS = “H” or CKE = “H”, RAS = “H”, CAS = “H”) The procedure for exiting self refresh requires a sequence of commands. First, CK must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command. The use of SELF REFREH mode introduces the possibility that an internally timed event can be missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an extra auto refresh command is recommended. 7.2.16 Data Write Enable /Disable Command (DM = “L/H” or LDM, UDM = “L/H”) During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to DQ15. 7.3 Read Operation Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after tRCD from the Bank Activate command, the data is read out sequentially, synchronized with both edges of DQS (Burst Read operation). The initial read data becomes available after CAS Latency from the issuing of the Read command. The CAS Latency must be set in the Mode Register at power-up. When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst operation is terminated. When the Read with Auto-precharge command is issued, the Precharge operation is performed automatically after the Read cycle then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Refer to the diagrams for Read operation. 7.4 Write Operation Issuing the Write command after tRCD from the bank activate command. The input data is latched sequentially, synchronizing with both edges(rising & falling) of DQS after the Write command (Burst write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at power-up. When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated. When the Write with Auto-precharge command is issued, the Precharge operation is performed automatically after the Write cycle, then the bank is switched to the idle state, The Write with Autoprecharge command cannot be interrupted by any other command for the entire burst data duration. Refer to the diagrams for Write operation. - 12 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 7.5 Precharge There are two Commands, which perform the precharge operation (Bank Precharge and Precharge All). When the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. The Bank Precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. The maximum time each bank can be held in the active state is specified as tRAS (max). Therefore, each bank must be precharged within tRAS(max) from the bank activate command. The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed only for the active bank and the precharge bank is then switched to the idle state. 7.6 Burst Termination When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after clock cycle of (CAS Latency) from the Precharge command. When the Burst Write cycle is interrupted by the Precharge command, the input circuit is reset at the same clock cycle at which the precharge command is issued. In this case, the DM signal must be asserted “high” during tWR to prevent writing the invalided data to the cell array. When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read operation is terminated. The Burst read Stop command is not supported during a write burst operation. Refer to the diagrams for Burst termination. 7.7 Refresh Operation Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation must be performed 4096 times (rows) within 64mS. The period between the Auto Refresh command and the next command is specified by tRFC. Self Refresh mode enters issuing the Self Refresh command (CKE asserted “low”) while all banks are in the idle state. The device is in Self Refresh mode for as long as CKE held “low”. In the case of distributed Auto Refresh commands, distributed auto refresh commands must be issued every 15.6 µS and the last distributed Auto Refresh commands must be performed within 15.6 µS before entering the self refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed within 15.6 µS. In Self Refresh mode, all input/output buffers are disabled, resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh operation. 7.8 Power Down Mode Two types of Power Down Mode can be performed on the device: Active Standby Power Down Mode and Precharge Standby Power Down Mode. When the device enters the Power Down Mode, all input/output buffers are disabled resulting in low power dissipation (except CKE buffer). Power Down Mode enter asserting CKE “low” while the device is not running a burst cycle. Taking CKE “high” can exit this mode. When CKE goes high, a No operation command must be input at next CLK rising edge. Refer to the diagrams for Power Down Mode. - 13 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 7.9 Mode Register Operation The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A11 and BS0, BS1 address inputs. The Mode Register designates the operation mode for the read or write cycle. The register is divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time in clock cycle (4) DLL reset field to reset the DLL (5) Regular/Extended Mode Register filed to select a type of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended function (DLL enable/Disable mode) The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the Mode Register Set command must be issued before power operation. 7.9.1 Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2, 4 and 8 words. A2 A1 A0 BURST LENGTH 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x Reserved 2 words 4 words 8 words Reserved 7.9.2 Addressing Mode Select (A3) The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the A3 bit is “0”, Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both addressing Mode support burst length 2, 4 and 8 words. A3 ADDRESSING MODE 0 1 Sequential Interleave - 14 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH • Address Sequence of Sequential Mode A column access is performed by incrementing the column address input to the device. The address is varied by the Burst Length as the following. Addressing Sequence of Sequential Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 • n n+1 n+2 n+3 n+4 n+5 n+6 n+7 2 words (address bits is A0) not carried from A0 to A1 4 words (address bit A0, A1) Not carried from A1 to A2 8 words (address bits A2, A1 and A0) Not carried from A2 to A3 Addressing Sequence of Interleave Mode A Column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following. 7.9.2.1. Address Sequence for Interleave Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 words 4 words 8 words - 15 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 7.9.3 CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values of CAS Latency depend on the frequency of CLK. A6 A5 A4 CAS LATENCY 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved Reserved 2 3 Reserved Reserved 2.5 Reserved 7.9.4 DLL Reset bit (A8) This bit is used to reset DLL. When the A8 bit is “1”, DLL is reset. 7.9.5 Mode Register/Extended Mode register change bits (BS0, BS1) BS1 BS0 A11-A0 These bits are used to select MRS/EMRS. 0 0 1 0 1 x Regular MRS Cycle Extended MRS Cycle Reserved - 16 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 7.9.6 Extended Mode Register field This bit is used to select DLL enable or disable A0 DLL 1) DLL Switch field (A0) 0 1 2) Output Driver Size Control field (A1) Enable Disable This bit is used to select Output Driver Size, both Full strength and Half strength are based on JEDEC standard A1 OUTPUT DRIVER 0 1 Full Strength Half Strength 7.9.7 Reserved field • Test mode entry bit (A7) This bit is used to enter Test mode and must be set to “0” for normal operation. • Reserved bits (A9, A10, A11) These bits are reserved for future operations. They must be set to “0” for normal operation. - 17 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 8. OPERATION MODE The following table shows the operation commands. 8.1 Simplified Truth Table Command Device State CKEn-1 CKEn DM(4) BS0, BS1 A10 A0-A9 ,A11 Sym. CS L L L L L L L L L L L H L L H L H L H RAS L L L H H H H L L H H X L L X H X H X H X X CAS H H H L L L L L L H H X L L X H X H X H X X WE H L L L L H H L L H L X H H X X X X X X X X ACT PRE PREA WRIT WRITA READ READA MRS EMRS NOP BST DSL AREF SELF SELEX Bank Active Bank Precharge Precharge All Write Write with Autoprecharge Read Read with Autoprecharge Mode Register Set Extended Mode Register Set No Operation Burst Read Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit Power Down Mode Entry Power Down Mode Exit Data Write Enable Data Write Disable Idle (3) (3) H H H X X X X X X X X X X X X H L H X X X X X X X X X X X X X X X V V X V V V V L, L H, L X X X X X X V L H L H L H C V X X X X X X V X X V V V V C V X X X X X X Any Any Active (3) H H H H H H H H H H H L Active Active (3) (3) Active Idle Idle Any (3) Active Any Idle Idle Idle (Self Refresh) Idle/ (5) Active Any (Power Down) Active Active PD H L X X X X PDEX WDE WDD L H H H X X X L H X X X X X X X X X L X X Notes: 1. V = Valid X = Don’t Care L = Low level H = High level 2. CKEn signal is input level when commands are issued. CKEn-1 signal is input level one clock cycle before the commands are issued. 3. These are state designated by the BS0, BS1 signals. 4. LDM, UDM (W9412G6CH). 5. Power Down Mode can not entry in the burst cycle. - 18 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 8.2 Function Truth Table CS RAS H L L Idle L L L L L H L L Row Active L L L L L H L L L Read L L L L L H L L L Write L L L L L X H H H L L L L X H H H L L L L X H H H H L L L L X H H H H L L L L (Note 1) Current State CAS X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L WE X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L X X Address Command DSL NOP/BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP/BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS NOP NOP ILLEGAL ILLEGAL Row activating NOP Action NOTES BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code 3 3 Refresh or Self refresh Mode register accessing NOP NOP Begin read: Determine AP Begin write: Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop Term burst, new read: Determine AP ILLEGAL ILLEGAL Term burst, Precharging ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL Term burst, start read: Determine AP Term burst, start read: Determine AP ILLEGAL Term burst, Precharging ILLEGAL ILLEGAL 2 2 4 4 3 5 6 3 6, 7 6 3 8 - 19 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH Function Truth Table, continued Current State CS H L L L L L L L L H L L L L L L L L H L L L RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L X X X Address Command DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS Action Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Idle after tRP NOP-> Idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after TRP ILLEGAL ILLEGAL NOP-> Row active after tRCD NOP-> Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOTES Read with Autoprecharge BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code 3 3 Write with Autoprecharge 3 3 3 3 3 Precharging L L L L L H L L L 3 3 3 3 Row Activating L L L L L - 20 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH Function Truth Table, continued Current State CS H L L L L L L L L H L RAS X H H H H L L L L X H H H H L L L L X H H H L L X H H H L CAS X H H L L H H L L X H H L L H H L L X H H L H L X H H L X WE X H L H L H L H L X H L H L H L H L X H L H X X X H L X X X X X Address DSL NOP BST Command Action NOP->Row active after tWR NOP->Row active after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP->Enter precharge after tWR NOP->Enter precharge after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP->Idle after TRC NOP->Idle after TRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP->Row after tMRD NOP->Row after tMRD ILLEGAL ILLEGAL ILLEGAL NOTES Write Recovering BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X X X X X X X X X READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/WRIT ACT/PRE/PREA AREF/SELF/MRS/EMRS 3 3 3 3 Write Recovering with Autoprecharge L L L L L L L H L L L L L H L L L L 3 3 3 3 Refreshing DSL NOP BST READ/WRIT ACT/PRE/PREA/ARE F/SELF/MRS/EMRS Mode Register Accessing Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle. 2. Illegal if any bank is not idle. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BS), depending on the state of that bank. 4. Illegal if tRCD is not satisfied. 5. Illegal if tRAS is not satisfied. 6. Must satisfy burst interrupt condition. 7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. Must mask preceding data which don’t satisfy tWR Remark: H = High level, L = Low level, X = High or Low level (Don’t Care), V = Valid data - 21 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 8.3 Function Truth Table for CKE CKE n-1 n CURRENT STATE CS RAS CAS WE ADDRESS X X X X X X X X X X X X X X X X X X X X X X X X INVALID ACTION NOTES H L Self Refresh L L L L H Power Down L L H H H All banks Idle H H H L H H H Row Active H H H L Any State Other Than Listed Above Notes: X H H H H L X H L H L L L L L X H L L L L L X H X H L L L X X X X X H L L L L X X H L L L L X X X X H H L X X X X X X H L H L X X X H L H L X X X X H L X X X X X X X H L L X X X X H L L X X X X X X X X X X X X X X X H X X X X X X H X X X X Exit Self Refresh->Idle after tXSNR Exit Self Refresh->Idle after tXSNR ILLEGAL ILLEGAL Maintain Self Refresh INVALID Exit Power down->Idle after tIS Maintain power down mode Refer to Function Truth Table Enter Power down Enter Power down Self Refresh ILLEGAL ILLEGAL Power down Refer to Function Truth Table Enter Power down Enter Power down ILLEGAL ILLEGAL ILLEGAL Power down Refer to Function Truth Table 2 2 2 2 2 1 H 1. Self refresh can enter only from the all banks idle state. 2. Power down can enter only from bank idle or row active state. Remark: H = High level, L = Low level, X = High or Low level (Don’t Care), V = Valid data - 22 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 8.4 Simplified Stated Diagram SELF REFRESH SREF SREFX IDLE MRS/EMRS MODE REGISTER SET AREF AUTO REFRESH PD PDEX ACT ACTIVE POWERDOWN POWER DOWN PDEX PD ROW ACTIVE BST Read Read Write Write Write Read Read Write A Write A Read A Read A Read A PRE Write A PRE PRE Read A POWER APPLIED POWER ON PRE PRE CHARGE Automatic Sequence Command Sequence - 23 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETER SYMBOL RATING UNIT Input/Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current VIN, VOUT VDD, VDDQ TOPR TSTG TSOLDER PD IOUT -0.3 ~ VDDQ + 0.3 -0.3 ~ 3.6 0 ~ 70 -55 ~ 150 260 1 50 V V °C °C °C W mA Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 9.2 Recommended DC Operating Conditions PARAMETER Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input reference Voltage Termination Voltage (System) Input High Voltage (DC) Input Low Voltage (DC) Differential Clock DC Input Voltage Input Differential Voltage. CLK and CLK inputs (DC) Input High Voltage (AC) Input Low Voltage (AC) Input Differential Voltage. CLK and CLK inputs (AC) Differential AC input Cross Point Voltage Differential Clock AC Middle Point (TA = 0 to 70°C) SYMBOL VDD VDDQ VREF VTT VIH (DC) VIL (DC) VICK (DC) VID (DC) VIH (AC) VIL (AC) VID (AC) VX (AC) VISO (AC) MIN. 2.3 2.3 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 VREF + 0.31 0.7 VDDQ/2 - 0.2 VDDQ/2 - 0.2 TYP. 2.5 2.5 0.50 x VDDQ VREF - MAX. 2.7 VDD 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 VREF - 0.31 VDDQ + 0.6 VDDQ/2 + 0.2 VDDQ/2 + 0.2 UNIT V V V V V V V V V V V V V NOTES 2 2 2, 3 2, 8 2 2 15 13, 15 2 2 13, 15 12, 15 14, 15 Notes: Undershoot Limit: VIL (min) = -1.2V with a pulse width < 3 nS Overshoot Limit: VIH (max) = VDDQ +1.2V with a pulse width < 3 nS VIH (DC) and VIL (DC) are levels to maintain the current logic state. VIH (AC) and VIL (AC) are levels to change to the new logic state. - 24 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 9.3 Capacitance DELTA (MAX.) 0.5 0.25 0.5 - (VDD = VDDQ = 2.5V ±0.2V, f = 1 MHz, TA = 25 °C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V) SYMBOL CIN CCLK CI/O CNC PARAMETER Input Capacitance (except for CLK pins) Input Capacitance (CLK pins) DQ, DQS, DM Capacitance NC1 Pin Capacitance MIN. 2.0 3.0 1.5 - MAX. 4.0 5.0 5.5 1.5 UNIT pF pF pF pF Notes: These parameters are periodically sampled and not 100% tested. The NC1 pins have additional capacitance for adjustment of the adjacent pin capacitance. 9.4 Leakage and Output Buffer Characteristics PARAMETER Input Leakage Current (0V < VIN < VDDQ, All other pins not under test = 0V) Output Leakage Current (Output disabled, 0V < VOUT < VDDQ) Output High Voltage (under AC test load condition) Output Low Voltage (under AC test load condition) Output Minimum Source DC Current Output Minimum Sink DC Current Output Minimum Source DC Current Output Minimum Sink DC Current Half Strength SYMBOL II (L) IO (L) VOH VOL IOH (DC) IOL (DC) IOH (DC) IOL (DC) MIN. -2 -5 VTT +0.76 Full Strength -15.2 15.2 -10.4 10.4 MAX. 2 5 VTT -0.76 - UNIT µA µA V V mA mA mA mA NOTES 4, 6 4, 6 5 5 - 25 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 9.5 DC Characteristics PARAMETER Operating current: One Bank Active-Precharge; tRC = tRC min; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle Operating current: One Bank Active-Read-Precharge; Burst = 2; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA; Address and control inputs changing once per clock cycle. Precharge Power Down standby current: All Banks Idle; Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM Idle standby current: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs changing once per clock cycle; Vin > VIH min or Vin < VIL max for DQ, DQS and DM Active Power Down standby current: One Bank Active; Power down mode; CKE < VIL max; tCK = tCK min Active standby current: CS > VIH min; CKE > VIH min; One Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating current: Burst = 2; Reads; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL=3; tCK = tCK min; IOUT = 0mA Operating current: Burst = 2; Write; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL = 3; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle Auto Refresh current: tRC = tRFC min Self Refresh current: CKE < 0.2V Random Read current: 4 Banks Active Read with activate every 20nS, Auto-Precharge Read every 20 nS; Burst = 4; tRCD = 3; IOUT = 0mA; DQ, DM and DQS inputs changing twice per clock cycle; Address changing once per clock cycle SYM. MAX. -45 130 -5 130 -6 120 -75 110 UNIT NOTES IDD0 mA 7 IDD1 IDD2P 140 140 130 120 7, 9 20 20 20 20 IDD2N 45 45 45 45 7 IDD3P 20 20 20 20 IDD3N 60 60 60 60 7 IDD4R 180 180 170 160 7, 9 IDD4W IDD5 IDD6 IDD7 180 200 3 320 180 200 3 320 170 190 3 300 160 180 3 280 7 7 tCK = 10ns tRC CK CK tRCD COMMAND ACT READ AP Bank 3 Rowc Col c ACT Bank 1 Row e READ AP Bank 0 Rowd Col d ACT Bank 2 Row f READ AP Bank 1 Rowe Col e ACT Bank 3 Row q READ AP Bank 2 Col f ACT Bank 0 Row h Bank 0 ADDRESS Row d DQS DQ Qa Qa Qb Qb Qb Qb Qc Qc Qc Qc Qd Qd Qd Qd Qe Qe RANDOM READ CURRENT Timing (IDD7) - 26 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 9.6 SYM. tRC tRFC tRAS tRCD tRAP tCCD tRP tRRD tWR tDAL tCK AC Characteristics and Operating Condition PARAMETER Active to Ref/Active Command Period Ref to Ref/Active Command Period Active to Precharge Command Period Active to Read/Write Command Delay Time Active to Read with Auto-precharge Enable Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time Auto-precharge Write Recovery + Precharge Time CL = 2 CLK Cycle Time CL = 2.5 CL = 3 -45 MIN. 54 63 36 18 18 1 18 12 15 30 4.5 -0.7 -0.6 12 0.7 0.6 0.45 0.45 0.45 min (tCL,tCH) tHP-0.55 0.9 0.4 0.4 0.4 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.85 -0.25 0.6 1.15 0.25 1.1 0.6 0.55 0.55 0.45 0.45 min, 70000 -5 MAX. MIN. 50 70 40 15 15 1 15 10 15 35 7.5 6 5 -0.7 -0.6 12 12 12 0.7 100000 MAX. UNIT NOTES nS tCK nS tAC tDQSCK tDQSQ tCH tCL tHP tQH tRPRE tRPST tDS tDH tDIPW tDQSH tDQSL tDSS tDSH tWPRES tWPRE tWPST tDQSS tDSSK Data Access Time from CLK, CLK DQS Output Access Time from CLK, CLK Data Strobe Edge to Output Data Edge Skew CLk High Level Width CLK Low Level Width CLK Half Period (minimum of actual Tch, Tcl) DQ Output Data Hold Time from DQS DQS Read Preamble Time DQS Read Postamble Time DQ and DM Setup Time DQ and DM Hold Time DQ and DM Input Pulse Width (for each input) DQS Input High Pulse Width DQS Input Low Pulse Width DQS Falling Edge to CLK Setup Time DQS Falling Edge Hold Time from CLK Clock to DQS Write Preamble Set-up Time DQS Write Preamble Time DQS Write Postamble Time Write Command to First DQS Latching Transition UDQS – LDQS Skew (x 16) 16 0.6 0.4 0.55 0.55 tCK 11 (tCL,tCH) tHP-0.5 0.9 0.4 0.4 0.4 1.75 0.35 0.35 0.2 0.2 0 0.3 0.4 0.75 -0.25 0.6 1.25 0.25 1.1 0.6 nS tCK 11 nS tCK 11 nS 11 tCK - 27 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH AC Characteristics and Operating Condition, continued SYM. tIS tIH tIPW tHZ tLZ tT(SS) tWTR tXSNR tXSRD tREFI tMRD Input Setup Time Input Hold Time PARAMETER -45 0.75 0.75 2.2 -0.7 -0.7 0.5 2 72 200 15.6 9 10 0.7 0.7 1.5 0.8 0.8 2.2 -0.7 -0.7 0.5 1 75 200 -5 MIN. MAX. MIN. MAX. UNIT NOTES Control & Address Input Pulse Width (for each input) Data-out High-impedance Time from CLK, CLK Data-out Low-impedance Time from CLK, CLK SSTL Input Transition Internal Write to Read Command Delay Exit Self Refresh to non-Read Command Exit Self Refresh to Read Command Refresh Interval Time (4k / 64mS) Mode Register Set Cycle Time 0.7 0.7 1.5 nS tCK nS tCK 15.6 µS nS 17 SYM. tRC tRFC tRAS tRCD tRAP tCCD tRP tRRD tWR tDAL tCK PARAMETER Active to Ref/Active Command Period Ref to Ref/Active Command Period Active to Precharge Command Period Active to Read/Write Command Delay Time Active to Read with Auto-precharge Enable Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time Auto-precharge Write Recovery + Precharge Time CL = 2 CLK Cycle Time CL = 2.5 CL = 3 -6 MIN. 54 70 42 18 18 1 18 12 15 36 7.5 6 6 -0.7 -0.6 7.5 7.5 7.5 0.7 0.6 0.4 0.45 0.45 min, (tCL,TCH) tHP-0.5 0.55 0.55 0.45 0.45 100000 -75 MAX. MIN. 60 70 45 20 20 1 20 15 15 37 12 12 12 -0.75 -0.75 0.75 120000 MAX. UNIT NOTES nS tCK nS tAC Data Access Time from CLK, CLK 16 0.75 0.5 0.55 0.55 tCK 11 tDQSCK DQS Output Access Time from CLK, CLK tDQSQ tCH tCL tHP tQH Data Strobe Edge to Output Data Edge Skew CLk High Level Width CLK Low Level Width CLK Half Period (minimum of actual Tch, Tcl) DQ Output Data Hold Time from DQS Min. (tCL,tCH) tHP-0.75 nS - 28 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH Continued SYM. tRPRE tRPST tDS tDH tDIPW tDQSH tDQSL tDSS tDSH tWPRES tWPRE tWPST tDQSS tDSSK tIS tIH tIPW tHZ tLZ tT(SS) tWTR tXSNR tXSRD tREFI tMRD PARAMETER DQS Read Preamble Time DQS Read Postamble Time DQ and DM Setup Time DQ and DM Hold Time DQ and DM Input Pulse Width (for each input) DQS Input High Pulse Width DQS Input Low Pulse Width DQS Falling Edge to CLK Setup Time DQS Falling Edge Hold Time from CLK Clock to DQS Write Preamble Set-up Time DQS Write Preamble Time DQS Write Postamble Time Write Command to First DQS Latching Transition UDQS – LDQS Skew (x 16) Input Setup Time Input Hold Time Control & Address Input Pulse Width (for each input) Data-out High-impedance Time from CLK, CLK Data-out Low-impedance Time from CLK, CLK SSTL Input Transition Internal Write to Read Command Delay Exit Self Refresh to non-Read Command Exit Self Refresh to Read Command Refresh Interval Time (4k / 64mS) Mode Register Set Cycle Time -6 0.9 0.4 0.4 0.4 1.75 0.35 0.35 0.2 0.2 0 0.3 0.4 0.75 -0.25 0.8 0.8 2.2 -0.7 -0.7 0.5 1 75 200 15.6 12 15 0.7 0.7 1.5 0.6 1.25 0.25 1.1 0.6 0.9 0.4 0.5 0.5 -75 1.1 0.6 MIN. MAX. MIN. MAX. UNIT NOTES tCK 11 nS 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.75 -0.25 0.9 0.9 2.2 -0.75 -0.75 0.5 1 75 200 15.6 0.75 0.75 1.5 tCK nS tCK µS nS 17 nS 1.25 0.25 tCK 11 nS tCK 11 9.7 AC Test Conditions PARAMETER SYMBOL VALUE UNIT Input High Voltage (AC) Input Low Voltage (AC) Input Reference Voltage Termination Voltage Differential Clock Input Reference Voltage Input Difference Voltage. CLK and CLK Inputs (AC) Output Timing Measurement Reference Voltage VIH VIL VREF VTT VR VID (AC) VOTR VREF + 0.31 VREF - 0.31 0.5 x VDDQ 0.5 x VDDQ Vx (AC) 1.5 0.5 x VDDQ V V V V V V V - 29 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH VDDQ VIH min (AC) V SWING (MAX) VREF VTT 50 Ω VIL max (AC) VSS T T Output Output V(out) 30pF SLEW = (VIH min (AC) - VILmax (AC)) / T Timing Reference Load Notes: (1) (2) (3) (4) (5) (6) (7) (8) (9) Conditions outside the limits listed under “Absolute Maximum Ratings” may cause permanent damage to the device. All voltages are referenced to VDD, VDDQ. .( 2.6V± 5% for DDR400 and DDR444) Peak to peak AC noise on VREF may not exceed ±2% VREF(DC). VOH = 1.95V, VOL = 0.35V VOH = 1.9V, VOL = 0.4V The values of IOH(DC) is based on VDDQ = 2.3V and VTT = 1.19V. The values of IOL(DC) is based on VDDQ = 2.3V and VTT = 1.11V. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK and tRC. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF. These parameters depend on the output loading. Specified values are obtained with the output open. (10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed slope. (11) IF the result of nominal calculation with regard to Tck contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., TDQSS = 0.75 × tCK, tCK = 7.5 nS, 0.75 × 7.5 nS = 5.625 nS is rounded up to 5.6 nS.) (12) VX is the differential clock cross point voltage where input timing measurement is referenced. (13) VID is magnitude of the difference between CLK input level and CLK input level. (14) VISO means {VICK(CLK)+VICK( CLK )}/2. (15) Refer to the figure below. - 30 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH CLK VX CLK VICK VSS VID(AC) VICK VX VX VICK VX VICK VX VID(AC) 0 V Differential VISO VISO(min) VSS VISO(max) (16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock. (17) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.. - 31 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 10. SYSTEM CHARACTERISTICS FOR DDR SDRAM The following specification parameters are required in systems using DDR400, DDR333 & DDR266 devices to ensure proper system performance. These characteristics are for system simulation purposes and are guaranteed by design. 10.1 Table 1: Input Slew Rate for DQ, DQS, and DM AC CHARACTERISTICS PARAMETER SYMBOL DDR400 MIN. MAX. DDR333 MIN. MAX. DDR266 MIN. MAX. UNIT NOTES DQ/DM/DQS input slew rate measured between VIH(DC), DCSLEW VIL(DC) and VIL(DC), VIH(DC) 0.5 4.0 0.5 4.0 0.5 4.0 V/nS a, m 10.2 Table 2: Input Setup & Hold Time Derating for Slew Rate INPUT SLEW RATE ΔTIS ΔTIH UNIT NOTES 0.5 V/nS 0.4 V/nS 0.3 V/nS 0 +50 +100 0 0 0 pS pS pS i i i 10.3 Table 3: Input/Output Setup & Hold Time Derating for Slew Rate INPUT SLEW RATE ΔTDS ΔTDH UNIT NOTES 0.5 V/nS 0.4 V/nS 0.3 V/nS 0 +75 +150 0 0 0 pS pS pS k k k 10.4 Table 4: Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate INPUT SLEW RATE ΔTDS ΔTDH UNIT NOTES ±0.0 nS/V ±0.25 nS/V ±0.5 nS/V 0 +50 +100 0 0 0 pS pS pS j j j 10.5 Table 5: Output Slew Rate Characteristics (X16 Devices only) SLEW RATE CHARACTERISTIC TYPICAL RANGE (V/NS) MINIMUM (V/NS) MAXIMUM (V/NS) NOTES Pullup Slew Rate Pulldown Slew Rate 1.2 ~ 2.5 1.2 ~ 2.5 0.7 0.7 5.0 5.0 a, c, d, f, g, h b, c, d, f, g, h - 32 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 10.6 Table 6: Output Slew Rate Matching Ratio Characteristics SLEW RATE CHARACTERISTIC PARAMETER DDR400 MIN. MAX. DDR333 MIN. MAX. DDR266 MIN. MAX. NOTES Output Slew Rate Matching Ratio (Pullup to Pulldown) 0.67 1.5 0.67 1.5 0.67 1.5 e, m 10.7 Table 7: AC Overshoot/Undershoot Specification for Address and Control Pins PARAMETER SPECIFICATION DDR400 DDR333 DDR266 Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to Max. area in Figure 3 The area between the undershoot signal and GND must be less than or equal to Max. area in Figure 3 1.5 V 1.5 V 3.0 V-nS 3.0 V-nS 1.5 V 1.5 V 3.6 V-nS 3.6 V-nS 1.5 V 1.5 V 4.5 V-nS 4.5 V-nS Figure 3: Address and Control AC Overshoot and Undershoot Definition - 33 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 10.8 Table 8: Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins PARAMETER SPECIFICATION DDR400 DDR333 DDR266 Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to Max. area in Figure 4 The area between the undershoot signal and GND must be less than or equal to Max. area in Figure 4 1.2 V 1.2 V 1.44 V-nS 1.44 V-nS 1.2 V 1.2 V 2.25 V-nS 2.25 V-nS 1.2 V 1.2 V 2.4 V-nS 2.4 V-nS VDD Overshoot 5 4 3 2 Max. area 1 0 -1 -2 -3 -4 -5 0 0.5 1.0 1.42 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.68 6.0 6.5 7.0 Time (nS) Max. amplitude = 1.2V GND Max. amplitude = 1.2V Undershoot Figure 4: DQ/DM/DQS AC Overshoot and Undershoot Definition - 34 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 10.9 System Notes: a. Pullup slew rate is characterized under the test conditions as shown in Figure 1. Test point Output 50 Ω VSSQ Figure 1: Pullup slew rate test load b. Pulldown slew rate is measured under the test conditions shown in Figure 2. Figure 2: Pulldown slew rate test load c. Pullup slew rate is measured between (VDDQ/2 - 320 mV ± 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV ± 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example: For typical slew rate, DQ0 is switching For minimum slew rate, all DQ bits are switching worst case pattern For maximum slew rate, only one DQ is switching from either high to low, or low to high The remaining DQ bits remain the same as for previous state d. Evaluation conditions Typical: Minimum: Maximum: 25 oC (T Ambient), VDDQ = nominal, typical process 70 oC (T Ambient), VDDQ = minimum, slow-slow process 0 oC (T Ambient), VDDQ = maximum, fast-fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. Verified under typical conditions for qualification purposes. - 35 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH g. TSOP II package devices only. h. Only intended for operation up to 266 Mbps per pin. i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/nS as shown in Table 2. The Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, fall rate. Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)}-{1/(slew Rate2)} For example: If Slew Rate 1 is 0.5 V/nS and Slew Rate 2 is 0.4 V/nS, then the delta rise, fall rate is -0.5 nS/V. Using the table given, this would result in the need for an increase in tDS and tDH of 100 pS. k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/nS. The I/O slew rate is based on the lesser of the AC-AC slew rate and the DC-DC slew rate. The input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), and similarly for rising transitions. m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. - 36 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 11. TIMING WAVEFORMS 11.1 Command Input Timing tCK tCK CLK CLK tIS CS tIH tCH tCL tIS RAS tIH tIS CAS tIH tIS WE tIH tIS A0~A11 BS0, 1 tIH Refer to the Command Truth Table 11.2 Timing of the CLK Signals CLK CLK tCK CLK CLK VX VX VX VIH VIL tCH tCL VIH VIH(AC) VIL(AC) VIL tT tT - 37 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 11.3 Read Timing (Burst Length = 4) tCH CLK tCL tCK CLK tIS CMD tIH READ tIS tIH ADD Col tDQSCK tDQSCK tRPST Hi-Z Preamble tDQSQ tQH tQH tDQSQ Postamble tDQSQ Hi-Z CAS Latency = 2 Hi-Z DQS tDQSCK tRPRE Output (Data) Hi-Z tAC tLZ QA0 DA0 QA1 DA1 QA2 DA2 QA3 DA3 tHZ tDQSCK tDQSCK tRPST tDQSCK CAS Latency = 3 Hi-Z DQS Preamble tDQSQ Output (Data) Hi-Z tAC tLZ tHZ tQH tQH tDQSQ Postamble tDQSQ Hi-Z tRPRE Hi-Z QA0 DA0 QA1 DA1 QA2 DA2 QA3 DA3 Notes: The correspondence of LDQS, UDQS to DQ. (W9412G6CH) LDQS UDQS DQ0~7 DQ8~15 - 38 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 11.4 Write Timing (Burst Length = 4) tCH CLK tCL tCK CLK CMD WRIT tIS ADD Col tIH tDSH tDSS tDSH tDSS x4, x8 device tWPRES tWPRE Preamble tDS tDQSH tDQSL tDQSH tWPST DQS tDS tDH tDH DA1 tDSH tDQSH tDSS tDQSL DA2 Postamble tDS tDH DA3 tDSH tDQSH tDSS tWPST Input (Data) tDQSS x16 device tWPRES DA0 LDQS tWPRE Preamble tDS tDH tDS tDS tDH DA1 tDSSK tDSH tWPRES tDQSH tWPRE Preamble tDS tDH Postamble tDH DA3 DA2 tDSSK tDSS tDQSL DA3 tDSSK tDSH tDQSH tDSS tWPST tDH Postamble DQ0~7 tDQSS tDSSK DA0 UDQS tDS tDS tDH DQ8~15 DA0 tDQSS tDSH DA1 DA2 Note: x16 has two DQSs (UDQS for upper byte and LDQS for lower byte). Even if one of the 2 bytes is not used, both UDQS and LDQS must be toggled. - 39 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 11.5 DM, DATA MASK (W9412G6CH) C LK CLK CMD W R IT LDQ S tD S tD S tD H tD H LDM t D IP W DQ 0~DQ 7 D0 D1 t D IP W M asked D3 UDQS tD S tD S tD H tD H UDM t D IP W D Q 8~D Q 15 D0 M asked D2 D3 t D IP W - 40 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 11.6 CLK CLK Mode Register Set (MRS) Timing tMRD CMD MRS NEXT CMD ADD Register Set data A0 A2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BS0 BS1 "0" "0" "0" "0" "0" Mode Register Set or Extended Mode Register Set Reserved "0" Reserved DLL Reset CAS Latency Addressing Mode Burst Length 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A3 0 1 A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A8 0 1 BS1 0 0 1 1 BS0 0 1 0 1 A4 0 1 0 1 0 1 0 1 A0 0 1 0 1 0 1 0 1 Burst Length Sequential Reserved 2 4 8 Interleaved Reserved 2 4 8 Reserved Reserved Addressing Mode Sequential Interleaved CAS Latency Reserved 2 3 Reserved 2.5 Reserved DLL Reset No Yes MRS or EMRS Regular MRS cycle Extended MRS cycle Reserved * "Reserved" should stay "0" during MRS cycle. - 41 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 11.7 Extend Mode Register Set (EMRS) Timing CLK CLK tMRD CMD EMRS NEXT CMD ADD Register Set data A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BS0 BS1 "0" "0" DLL Switch Output Driver A0 0 1 DLL Switch Enable Disable A1 "0" "0" "0" Reserved "0" "0" "0" "0" "0" "0" "0" Mode Register Set or Extended Mode Register Set BS1 0 0 1 1 BS0 0 1 0 1 0 1 Output Driver Size Full Strength Half Strength MRS or EMRS Regular MRS cycle Extended MRS cycle * "Reserved" should stay "0" during EMRS cycle. - 42 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 11.8 Auto-precharge Timing (Read Cycle, CL = 2) 1. TRCD (READA) ≥ TRAS (MIN) – (BL/2) × TCK tRAS CLK CLK BL=2 CMD ACT READA AP tRP ACT DQS DQ Q0 Q1 BL=4 CMD ACT READA AP ACT DQS DQ Q0 Q1 Q2 Q3 BL=8 CMD ACT READA AP ACT DQS DQ Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Notes: CL=2 shown; same command operation timing with CL = 2,5 and CL=3 In this case, the internal precharge operation begin after BL/2 cycle from READA command. Represents the start of internal precharging. The Read with Auto-precharge command cannot be interrupted by any other command. AP - 43 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 11.9 Auto-precharge Timing (Read cycle, CL = 2), continued 2. TRCD/RAP(MIN) ≤ TRCD (READA) < TRAS (MIN) – (BL/2) × TCK tRAS CLK CLK BL=2 CMD ACT tRAP tRCD DQS tRP READA AP ACT DQ Q0 Q1 BL=4 CMD ACT tRAP tRCD DQS READA AP ACT DQ Q0 Q1 Q2 Q3 BL=8 CMD ACT tRAP tRCD DQS READA AP ACT DQ Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Notes: CL2 shown; same command operation timing with CL = 2.5, CL=3. In this case, the internal precharge operation does not begin until after tRAS(min) has command. AP Represents the start of internal precharging. The Read with Auto-precharge command cannot be interrupted by any other command. - 44 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 11.10 Auto-precharge Timing (Write Cycle) CLK CLK tDAL BL=2 CMD WRITA AP ACT DQS DQ D0 D1 tDAL BL=4 CMD WRITA AP ACT DQS DQ D0 D1 D2 D3 tDAL BL=8 CMD WRITA AP ACT DQS DQ D0 D1 D2 D3 D4 D5 D6 D7 The Write with Auto-precharge command cannot be interrupted by any other command. AP Represents the start of internal precharging. - 45 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 11.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) CLK CLK CMD ACT READ A READ B READ C READ D READ E tRCD ADD Row Address tCCD COl,Add,A Col,Add,B tCCD Col,Add,C tCCD Col,Add,D tCCD Col,Add,E DQS DQ QA0 QA1 QB0 QB1 QC0 11.12 Burst Read Stop (BL = 8) CLK CLK CMD READ BST CAS Latency = 2 DQS CAS Latency DQ Q0 Q1 Q2 Q3 Q4 Q5 CAS Latency = 3 DQS CAS Latency DQ Q0 Q1 Q2 Q3 Q4 Q5 - 46 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 11.13 Read Interrupted by Write & BST (BL = 8) CLK CLK CAS Latency = 2 CMD READ BST WRIT DQS DQ Q0 Q1 Q2 Q3 Q4 Q5 D0 D1 D2 D3 D4 D5 D6 D7 Burst Read cycle must be terminated by BST Command to avoid I/O conflict. 11.14 Read Interrupted by Precharge (BL = 8) CLK CLK CMD R EAD PR E C AS Latency = 2 DQ S CAS Latency DQ Q0 Q1 Q2 Q3 Q4 Q5 C AS Latency = 3 DQ S C AS Latency DQ Q0 Q1 Q2 Q3 Q4 Q5 - 47 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 11.15 Write Interrupted by Write (BL = 2, 4, 8) CLK CLK CMD ACT WRIT A WRIT B WRIT C WRIT D WRIT E tRCD ADD Row Address tCCD COl. Add. A Col.Add.B tCCD tCCD tCCD Col. Add. E Col. Add. C Col. Add. D DQS DQ DA0 DA1 DB0 DB1 DC0 DC1 DD0 DD1 11.16 Write Interrupted by Read (CL = 2, BL = 8) CLK CLK CMD WRIT READ DQS DM tWTR DQ D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Data must be masked by DM Data masked by READ command, DQS input ignored. - 48 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 11.17 Write Interrupted by Read (CL = 3, BL = 4) CLK CLK CMD WRIT READ DQS DM tWTR DQ D0 D1 D2 D3 Q0 Q1 Q2 Q3 Data must be masked by DM 11.18 Write Interrupted by Precharge (BL = 8) CLK CLK CMD WRIT PRE ACT tWR DQS tRP DM DQ D0 D1 D2 D3 D4 D5 D6 D7 Data masked by PRE command, DQS input ignored. Data must be masked by DM - 49 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 11.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) ∗ tCK = 100 MHz CLK CLK tRC(b) tRC(a) tRRD CMD ACTa ACTb tRCD(a) tRAS(a) tRCD(b) tRAS(b) tRP(b) tRP(a) READAa READAb ACTa tRRD ACTb DQS Preamble CL(a) DQ Q0a Postamble Preamble Postamble CL(b) Q1a Q0b Q1b ACTa/b : Bank Act. CMD of bank a/b READAa/b : Read with Auto Pre.CMD of bank a/b APa/b : Auto Pre. of bank a/b APa APb 11.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) CLK CLK tRC(b) tRC(a) tRRD CMD ACTa ACTb tRCD(a) tRAS(a) tRCD(b) tRAS(b) tRP(b) tRP(a) READAa READAb ACTa tRRD ACTb DQS Preamble CL(a) DQ Q0a Postamble CL(b) Q1a Q2a Q3a Q0b Q1b Q2b Q3b ACTa/b : Bank Act. CMD of bank a/b READAa/b : Read with Auto Pre.CMD of bank a/b APa/b : Auto Pre. of bank a/b APa APb - 50 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 11.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) CLK CLK tRC(a) tRRD CMD ACTa ACTb tRCD(a) tRAS(a) tRCD(b) tRAS(b) tRCD(c) tRAS(c) tRCD(d) tRAS(d) tRP tRRD ACTc tRRD READAa ACTd tRRD READAb ACTa READAc DQS Preamble CL(a) DQ CL(b) Q0a Q1a Q0b Q1b Postamble Preamble ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d APa/b/c/d : Auto Pre. of bank a/b/c/d APa APb 11.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) CLK CLK tRC(a) tRRD CMD ACTa tRCD(a) tRAS(a) tRCD(b) tRAS(b) tRCD(c) tRAS(c) tRCD(d) tRAS(d) tRP(a) ACTb tRRD READAa ACTc tRRD READAb ACTd tRRD READAc ACTa READAd DQS Preamble CL(a) DQ Q0a CL(b) CL(c) Q1a Q0a Q1a Q2a CL(b) Q3a Q0b Q1b Q2b Q3b ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d APa/b/c/d : Auto Pre. of bank a/b/c/d APa APb APc - 51 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 11.23 Auto Refresh Cycle CLK CLK CMD PREA NOP AREF NOP AREF NOP CMD tRP tRFC tRFC CKE has to be kept “High” level for Auto-Refresh cycle. 11.24 Active Power Down Mode Entry and Exit Timing CLK CLK tIH CKE tIS tCK tIH tIS Entry CMD NOP NOP Exit NOP CMD NOP 11.25 Precharged Power Down Mode Entry and Exit Timing CLK CLK tIH CKE tIS tCK tIH tIS Entry CMD NOP NOP Exit NOP CMD NOP - 52 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 11.26 Self Refresh Entry and Exit Timing CLK CLK tIH CKE tIS tCK tIH tIS CMD PREA NOP tRP SELF SELFX NOP CMD Entry Exit tXSNR tXSRD SELF SELFX NOP ACT NOP READ NOP Entry Exit - 53 - Publication Release Date: Jul. 04, 2007 Revision A06 W9412G6CH 12. PACKAGE SPECIFICATION 12.1 66L TSOP – 400 mil E1 E D O O1 L L1 O O1 - 54 - Publication Release Date:Jul. 04, 2007 Revision A06 W9412G6CH 13. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A01 A02 A03 A04 A05 A06 Aug. 07, 2006 Aug. 24, 2006 Sep. 27, 2006 Mar. 09, 2007 May 15, 2007 Jul. 04, 2007 All 10,11,12, 22 26,27 3, 4,24,25 29,30,31, 32,33 54 Formally datasheet Revision over/undershoot range and Refresh description Revision AC timing to JEDEC specification Add the -45 grade Add System AC Characteristics with slew rate and Overshoot/Undershoot Specification detail describes Update the HE/E with package dimensions Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 55 - Publication Release Date: Jul. 04, 2007 Revision A06