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W9425G6JB-5

W9425G6JB-5

  • 厂商:

    WINBOND(华邦)

  • 封装:

    TFBGA-60

  • 描述:

    IC DRAM 256MBIT PARALLEL 60TFBGA

  • 数据手册
  • 价格&库存
W9425G6JB-5 数据手册
W9425G6JB 4 M  4 BANKS  16 BITS DDR SDRAM Table of Contents1. GENERAL DESCRIPTION............................................................................................................. 4 2. FEATURES .................................................................................................................................... 4 3. ORDER INFORMATION ................................................................................................................ 4 4. KEY PARAMETERS ...................................................................................................................... 5 5. BALL CONFIGURATION ............................................................................................................... 6 6. BALL DESCRIPTION ..................................................................................................................... 7 7. BLOCK DIAGRAM ......................................................................................................................... 8 8. FUNCTIONAL DESCRIPTION ....................................................................................................... 9 8.1 Power Up Sequence............................................................................................................ 9 8.2 Command Function ........................................................................................................... 10 8.2.1 Bank Activate Command ........................................................................................ 10 8.2.2 Bank Precharge Command .................................................................................... 10 8.2.3 Precharge All Command ........................................................................................ 10 8.2.4 Write Command ...................................................................................................... 10 8.2.5 Write with Auto-precharge Command .................................................................... 10 8.2.6 Read Command...................................................................................................... 10 8.2.7 Read with Auto-precharge Command .................................................................... 10 8.2.8 Mode Register Set Command ................................................................................ 11 8.2.9 Extended Mode Register Set Command ................................................................ 11 8.2.10 No-Operation Command ........................................................................................ 11 8.2.11 Burst Read Stop Command .................................................................................... 11 8.2.12 Device Deselect Command .................................................................................... 11 8.2.13 Auto Refresh Command ......................................................................................... 11 8.2.14 Self Refresh Entry Command ................................................................................. 12 8.2.15 Self Refresh Exit Command ................................................................................... 12 8.2.16 Data Write Enable /Disable Command ................................................................... 12 8.3 Read Operation ................................................................................................................. 12 8.4 Write Operation ................................................................................................................. 13 8.5 Precharge .......................................................................................................................... 13 8.6 Burst Termination .............................................................................................................. 13 8.7 Refresh Operation ............................................................................................................. 13 8.8 Power Down Mode ............................................................................................................ 14 8.9 Input Clock Frequency Change during Precharge Power Down Mode ............................ 14 -1- Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 8.10 Mode Register Operation .................................................................................................. 14 8.10.1 Burst Length field (A2 to A0) .................................................................................. 14 8.10.2 Addressing Mode Select (A3) ................................................................................. 15 8.10.3 CAS Latency field (A6 to A4) .................................................................................. 16 8.10.4 DLL Reset bit (A8) .................................................................................................. 16 8.10.5 Mode Register /Extended Mode register change bits (BA0, BA1) ......................... 16 8.10.6 Extended Mode Register field ................................................................................ 16 8.10.7 Reserved field ......................................................................................................... 16 9. 10. 11. 12. OPERATION MODE .................................................................................................................... 17 9.1 Simplified Truth Table........................................................................................................ 17 9.2 Function Truth Table ......................................................................................................... 18 9.3 Function Truth Table for CKE ............................................................................................ 21 9.4 Simplified Stated Diagram ................................................................................................. 22 ELECTRICAL CHARACTERISTICS ............................................................................................ 23 10.1 Absolute Maximum Ratings ............................................................................................... 23 10.2 Recommended DC Operating Conditions ......................................................................... 23 10.3 Capacitance ....................................................................................................................... 24 10.4 Leakage and Output Buffer Characteristics ...................................................................... 24 10.5 DC Characteristics............................................................................................................. 25 10.6 AC Characteristics and Operating Condition..................................................................... 26 10.7 AC Test Conditions............................................................................................................ 27 SYSTEM CHARACTERISTICS FOR DDR SDRAM .................................................................... 29 11.1 Table 1: Input Slew Rate for DQ, DQS, and DM ............................................................... 29 11.2 Table 2: Input Setup & Hold Time Derating for Slew Rate ................................................ 29 11.3 Table 3: Input/Output Setup & Hold Time Derating for Slew Rate .................................... 29 11.4 Table 4: Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate .................... 29 11.5 Table 5: Output Slew Rate Characteristics (X16 Devices only) ........................................ 29 11.6 System Notes: ................................................................................................................... 30 TIMING WAVEFORMS ................................................................................................................ 32 12.1 Command Input Timing ..................................................................................................... 32 12.2 Timing of the CLK Signals ................................................................................................. 32 12.3 Read Timing (Burst Length = 4) ........................................................................................ 33 12.4 Write Timing (Burst Length = 4) ........................................................................................ 34 12.5 DM, DATA MASK (W9425G6JB) ...................................................................................... 35 12.6 Mode Register Set (MRS) Timing ..................................................................................... 36 12.7 Extend Mode Register Set (EMRS) Timing ....................................................................... 37 12.8 Auto-precharge Timing (Read Cycle, CL = 2) ................................................................... 38 -2- Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 12.9 Auto-precharge Timing (Read cycle, CL = 2), continued .................................................. 39 12.10 Auto-precharge Timing (Write Cycle) ................................................................................ 40 12.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) .............................................................. 41 12.12 Burst Read Stop (BL = 8) .................................................................................................. 41 12.13 Read Interrupted by Write & BST (BL = 8) ........................................................................ 42 12.14 Read Interrupted by Precharge (BL = 8) ........................................................................... 42 12.15 Write Interrupted by Write (BL = 2, 4, 8) ........................................................................... 43 12.16 Write Interrupted by Read (CL = 2, BL = 8)....................................................................... 43 12.17 Write Interrupted by Read (CL = 3, BL = 4)....................................................................... 44 12.18 Write Interrupted by Precharge (BL = 8) ........................................................................... 44 12.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) ......................................................... 45 12.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) ......................................................... 45 12.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) ......................................................... 46 12.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) ......................................................... 46 12.23 Auto Refresh Cycle............................................................................................................ 47 12.24 Precharged/Active Power Down Mode Entry and Exit Timing .......................................... 47 12.25 Input Clock Frequency Change during Precharge Power Down Mode Timing................. 47 12.26 Self Refresh Entry and Exit Timing ................................................................................... 48 13. PACKAGE SPECIFICATION ....................................................................................................... 49 14. REVISION HISTORY ................................................................................................................... 50 -3- Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 1. GENERAL DESCRIPTION W9425G6JB is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 4,194,304 words  4 banks  16 bits. W9425G6JB delivers a data bandwidth of up to 400M words per second (-5). To fully comply with the personal computer industrial standard, W9425G6JB is sorted into two speed grades: 5 and -5I. The -5/-5I is compliant to the DDR400/CL3 specification (the -5I grade which is guaranteed to support -40°C ~ 85°C). All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. Write and Read data are synchronized with the both edges of DQS (Data Strobe). By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9425G6JB is ideal for main memory in high performance applications. 2. FEATURES  2.5V  0.2V Power Supply  Up to 200 MHz Clock Frequency  Double Data Rate architecture; two data transfers per clock cycle  Differential clock inputs (CLK and CLK )  DQS is edge-aligned with data for Read; center-aligned with data for Write  CAS Latency: 2, 2.5 and 3  Burst Length: 2, 4 and 8  Auto Refresh and Self Refresh  Precharged Power Down and Active Power Down  Write Data Mask  Write Latency = 1  7.8µS refresh interval (8K/ 64 mS refresh)  Maximum burst refresh cycle: 8  Interface: SSTL_2  Packaged in 60 Ball TFBGA (8X13 mm2), using Lead free materials with RoHS compliant 3. ORDER INFORMATION PART NUMBER W9425G6JB-5 W9425G6JB-5I SPEED DDR400/CL3 DDR400/CL3 -4- SELF REFRESH CURRENT (MAX.) OPERATING TEMPERATURE 2 mA 2 mA 0°C ~ 70°C -40°C ~ 85°C Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 4. KEY PARAMETERS SYMBOL DESCRIPTION MIN./MAX. -5/-5I Min. 7.5 nS Max. 12 nS Min. 6 nS Max. 12 nS Min. 5 nS Max. 12 nS CL = 2 tCK Clock Cycle Time CL = 2.5 CL = 3 tRAS Active to Precharge Command Period Min. 40 nS tRC Active to Ref/Active Command Period Min. 55 nS IDD0 Operating Current: One Bank Active-Precharge Max. 65 mA IDD1 Operating Current: One Bank Active-Read-Precharge Max. 80 mA IDD4R Burst Operation Read Current Max. 120 mA IDD4W Burst Operation Write Current Max. 115 mA IDD5 Auto Refresh Current Max. 65 mA IDD6 Self Refresh Current Max. 2 mA -5- Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 5. BALL CONFIGURATION 1 2 3 VSSQ DQ15 VSS DQ14 VDDQ DQ12 DQ10 DQ8 VREF VSSQ VDDQ VSSQ 7 8 9 A VDD DQ0 VDDQ DQ13 B DQ2 VSSQ DQ1 DQ11 C DQ4 D DQ6 E LDQS DQ9 UDQS : Ball Existing : Depopulated Ball Top View (See the balls through the Package) VDDQ DQ3 1 2 3 4 5 6 7 8 9 A 1.0 mm B VSSQ DQ5 C D VDDQ DQ7 E 13.0 mm F VSS UDM F LDM VDD CLK CLK G WE CAS A12 CKE H RAS CS A11 A9 J BA1 BA0 A8 A7 K A0 A10/AP A6 A5 L A2 A1 A4 VSS M VDD A3 NC G H J K L M 0.8 mm 8.0 mm BGA Package Ball Pattern Top View Device Ball Pattern -6- Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 6. BALL DESCRIPTION BALL NUMBER SYMBOL K7, L8, L7, M8, M2, L3, L2, K3, A0  A12 K2, J3, K8, J2, H2 FUNCTION DESCRIPTION Address Multiplexed pins for row and column address. Row address: A0A12. Column address: A0A8. Provide the row address for Bank Activate commands, and the column address and Auto-precharge bit (A10) for Read/Write commands, to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 Low) or all banks (A10 High). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode Register Set command. BA0 and BA1 define which mode register is loaded during the Mode Register Set command (MRS or EMRS). J8, J7 BA0, BA1 Bank Select Select bank to activate during row address latch time, or bank to read/write during column address latch time. A8, B9, B7, C9, C7, D9, D7, E9, E1, D3, D1, C3, C1, B3, B1, A2 DQ0  DQ15 Data Input/ Output The DQ0 – DQ15 input and output data are synchronized with both edges of DQS. E7, E3 LDQS, UDQS Data Strobe DQS is Bi-directional signal. DQS is input signal during write operation and output signal during read operation. It is Edgealigned with read data, Center-aligned with write data. H8 CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. H7, G8, G7 RAS , Command Inputs CAS , WE Command inputs (along with CS ) define the command being entered. LDM, UDM Write Mask When DM is asserted “high” in burst write, the input data is masked. DM is synchronized with both edges of DQS. CLK, CLK Differential Clock Inputs All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of CLK . H3 CKE Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. F1 VREF F8, M7, A7 VDD Power (+2.5V) Power for logic circuit inside DDR SDRAM. A3, F2, M3 VSS Ground Ground for logic circuit inside DDR SDRAM. B2, D2, C8, E8, A9 VDDQ A1, C2, E2, B8, D8 VSSQ Ground for I/O Buffer Separated ground from VSS, used for output buffer, to improve noise. F9 NC No Connection No connection F7, F3 G2, G3 Reference Voltage VREF is reference voltage for inputs. Power (+2.5V) for Separated power from VDD, used for output buffer, to I/O Buffer improve noise. -7- Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 7. BLOCK DIAGRAM CLK CLK DLL CLOCK BUFFER CKE CONTROL CS SIGNAL GENERATOR RAS CAS COMMAND DECODER COLUMN DECODER COLUMN DECODER A10 CELL ARRAY BANK #0 ROW DECODER ROW DECODER WE MODE REGISTER A0 SENSE AMPLIFIER SENSE AMPLIFIER ADDRESS BUFFER PREFETCH REGISTER DQ DATA CONTROL BUFFER DQ0 DQ15 CIRCUIT COLUMN COUNTER COUNTER LDQS UDQS LDM UDM COLUMN DECODER CELL ARRAY BANK #2 COLUMN DECODER ROW DECODER REFRESH ROW DECODER A9 A11 A12 BA0 BA1 CELL ARRAY BANK #1 SENSE AMPLIFIER CELL ARRAY BANK #3 SENSE AMPLIFIER NOTE: The cell array configuration is 8192 * 512 * 16 -8- Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 8. FUNCTIONAL DESCRIPTION 8.1 Power Up Sequence (1) (2) (3) (4) (5) (6) (7) (8) (9) Apply power and attempt to CKE at a low state (  0.2V), all other inputs may be undefined 1) Apply VDD before or at the same time as VDDQ. 2) Apply VDDQ before or at the same time as VTT and VREF. Start Clock and maintain stable condition for 200 µS (min.). After stable power and clock, apply NOP and take CKE high. Issue precharge command for all banks of the device. Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type. Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8. (An additional 200 cycles(min) of clock are required for DLL Lock before any executable command applied.) Issue precharge command for all banks of the device. Issue two or more Auto Refresh commands. Issue MRS-Initialize device operation with the reset DLL bit deactivated A8 to low. CLK CLK Command PREA EMRS tRP MRS 2 Clock min. PREA 2 Clock min. AREF tRP AREF tRFC ANY CMD MRS tRFC 2 Clock min. 200 Clock min. Inputs maintain stable for 200 µS min. Enable DLL Disable DLL reset with A8 = Low DLL reset with A8 = High Initialization sequence after power-up -9- Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 8.2 Command Function 8.2.1 Bank Activate Command ( RAS = "L", CAS = "H", WE = "H", BA0, BA1 = Bank, A0 to A12 = Row Address) The Bank Activate command activates the bank designated by the BA (Bank address) signal. Row addresses are latched on A0 to A12 when this command is issued and the cell data is read out of the sense amplifiers. The maximum time that each bank can be held in the active state is specified as tRAS (max). After this command is issued, Read or Write operation can be executed. 8.2.2 Bank Precharge Command ( RAS = "L", CAS = "H", WE = "L", BA0, BA1 = Bank, A10 = "L", A0 to A9, A11, A12 = Don’t Care) The Bank Precharge command percharges the bank designated by BA. The precharged bank is switched from the active state to the idle state. 8.2.3 Precharge All Command ( RAS = "L", CAS = "H", WE = "L", BA0, BA1 = Don’t Care, A10 = "H", A0 to A9, A11, A12 = Don’t Care) The Precharge All command precharges all banks simultaneously. Then all banks are switched to the idle state. 8.2.4 Write Command ( RAS = "H", CAS = "L", WE = "L", BA0, BA1 = Bank, A10 = "L", A0 to A8 = Column Address) The write command performs a Write operation to the bank designated by BA. The write data are latched at both edges of DQS. The length of the write data (Burst Length) and column access sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write operation. 8.2.5 Write with Auto-precharge Command ( RAS = "H", CAS = "L", WE = "L", BA0, BA1 = Bank, A10 = "H", A0 to A8 = Column Address) The Write with Auto-precharge command performs the Precharge operation automatically after the Write operation. This command must not be interrupted by any other commands. 8.2.6 Read Command ( RAS = "H", CAS = "L", WE = "H", BA0, BA1 = Bank, A10 = "L", A0 to A8 = Column Address) The Read command performs a Read operation to the bank designated by BA. The read data are synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Read operation. 8.2.7 Read with Auto-precharge Command ( RAS = "H", CAS = "L", WE = "H", BA0, BA1 = Bank, A10 = "H", A0 to A8 = Column Address) The Read with Auto-precharge command automatically performs the Precharge operation after the Read operation. - 10 - Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 1) READA  tRAS (min) - (BL/2) x tCK Internal precharge operation begins after BL/2 cycle from Read with Auto-precharge command. 2) tRCD(min)  READA < tRAS(min) - (BL/2) x tCK Data can be read with shortest latency, but the internal Precharge operation does not begin until after tRAS (min) has completed. This command must not be interrupted by any other command. 8.2.8 Mode Register Set Command ( RAS = "L", CAS = "L", WE = "L", BA0 = "L", BA1 = "L", A0 to A12 = Register Data) The Mode Register Set command programs the values of CAS Latency, Addressing Mode, Burst Length and DLL reset in the Mode Register. The default values in the Mode Register after powerup are undefined, therefore this command must be issued during the power-up sequence. Also, this command can be issued while all banks are in the idle state. Refer to the table for specific codes. 8.2.9 Extended Mode Register Set Command ( RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L", A0 to A12 = Register data) The Extended Mode Register Set command can be implemented as needed for function extensions to the standard (SDR-SDRAM). These additional functions include DLL enable/disable, output drive strength selection. The default value of the extended mode register is not defined; therefore this command must be issued during the power-up sequence for enabling DLL. Refer to the table for specific codes. 8.2.10 No-Operation Command ( RAS = "H", CAS = "H", WE = "H") The No-Operation command simply performs no operation (same command as Device Deselect). 8.2.11 Burst Read Stop Command ( RAS = "H", CAS = "H", WE = "L") The Burst stop command is used to stop the burst operation. This command is only valid during a Burst Read operation. 8.2.12 Device Deselect Command ( CS = "H") The Device Deselect command disables the command decoder so that the RAS , CAS , WE and Address inputs are ignored. This command is similar to the No-Operation command. 8.2.13 Auto Refresh Command ( RAS = "L", CAS = "L", WE = "H", CKE = "H", BA0, BA1, A0 to A12 = Don’t Care) AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS– BEFORE–RAS (CBR) refresh in previous DRAM types. This command is non persistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command. The DDR SDRAM requires AUTO REFRESH - 11 - Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB cycles at an average periodic interval of tREFI (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 * tREFI. 8.2.14 Self Refresh Entry Command ( RAS = "L", CAS = "L", WE = "H", CKE = "L", BA0, BA1, A0 to A12 = Don’t Care) The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH, and is automatically enabled upon exiting SELF REFRESH. Any time the DLL is enabled a DLL Reset must follow and 200 clock cycles should occur before a READ command can be issued. Input signals except CKE are “Don’t Care” during SELF REFRESH. Since CKE is a SSTL_2 input, VREF must be maintained during SELF REFRESH. 8.2.15 Self Refresh Exit Command (CKE = "H", CS = "H" or CKE = "H", RAS = "H", CAS = "H") The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command. The use of SELF REFREH mode introduces the possibility that an internally timed event can be missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an extra auto refresh command is recommended. 8.2.16 Data Write Enable /Disable Command (DM = "L/H" or LDM, UDM = "L/H") During a Write cycle, the DM or LDM, UDM signal functions as Data Mask and can control every word of the input data. The LDM signal controls DQ0 to DQ7 and UDM signal controls DQ8 to DQ15. 8.3 Read Operation Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after tRCD from the Bank Activate command, the data is read out sequentially, synchronized with both edges of DQS (Burst Read operation). The initial read data becomes available after CAS Latency from the issuing of the Read command. The CAS Latency must be set in the Mode Register at power-up. When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst operation is terminated. When the Read with Auto-precharge command is issued, the Precharge operation is performed automatically after the Read cycle then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Refer to the diagrams for Read operation. - 12 - Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 8.4 Write Operation Issuing the Write command after tRCD from the bank activate command. The input data is latched sequentially, synchronizing with both edges(rising & falling) of DQS after the Write command (Burst write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at power-up. When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated. When the Write with Auto-precharge command is issued, the Precharge operation is performed automatically after the Write cycle, then the bank is switched to the idle state, The Write with Autoprecharge command cannot be interrupted by any other command for the entire burst data duration. Refer to the diagrams for Write operation. 8.5 Precharge There are two Commands, which perform the precharge operation (Bank Precharge and Precharge All). When the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. The Bank Precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. The maximum time each bank can be held in the active state is specified as tRAS (max). Therefore, each bank must be precharged within tRAS(max) from the bank activate command. The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed only for the active bank and the precharge bank is then switched to the idle state. 8.6 Burst Termination When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after clock cycle of (CAS Latency) from the Precharge command. When the Burst Write cycle is interrupted by the Precharge command, the input circuit is reset at the same clock cycle at which the precharge command is issued. In this case, the DM signal must be asserted "high" during tWR to prevent writing the invalided data to the cell array. When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read operation is terminated. The Burst read Stop command is not supported during a write burst operation. Refer to the diagrams for Burst termination. 8.7 Refresh Operation Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation must be performed 8192 times (rows) within 64mS. The period between the Auto Refresh command and the next command is specified by tRFC. Self Refresh mode enters issuing the Self Refresh command (CKE asserted "low") while all banks are in the idle state. The device is in Self Refresh mode for as long as CKE held "low". In the case of distributed Auto Refresh commands, distributed auto refresh commands must be issued every 7.8 µS and the last distributed Auto Refresh commands must be performed within 7.8 µS before entering the self refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed within 7.8 µS. In Self Refresh mode, all input/output buffers are disabled, - 13 - Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh operation. 8.8 Power Down Mode Two types of Power Down Mode can be performed on the device: Active Standby Power Down Mode and Precharge Standby Power Down Mode. When the device enters the Power Down Mode, all input/output buffers and DLL are disabled resulting in low power dissipation (except CKE buffer). Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking CKE "high" can exit this mode. When CKE goes high, a No operation command must be input at next CLK rising edge. Refer to the diagrams for Power Down Mode. 8.9 Input Clock Frequency Change during Precharge Power Down Mode DDR SDRAM input clock frequency can be changed under following condition: DDR SDRAM must be in precharged power down mode with CKE at logic LOW level. After a minimum of 2 clocks after CKE goes LOW, the clock frequency may change to any frequency between minimum and maximum operating frequency specified for the particular speed grade. During an input clock frequency change, CKE must be held LOW. Once the input clock frequency is changed, a stable clock must be provided to DRAM before precharge power down mode may be exited. The DLL must be RESET via EMRS after precharge power down exit. An additional MRS command may need to be issued to appropriately set CL etc. After the DLL relock time, the DRAM is ready to operate with new clock frequency. 8.10 Mode Register Operation The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A12 and BA0, BA1 address inputs. The Mode Register designates the operation mode for the read or write cycle. The register is divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time in clock cycle (4) DLL reset field to reset the DLL (5) Regular/Extended Mode Register filed to select a type of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended function (DLL enable/Disable mode). The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the Mode Register Set command must be issued before power operation. 8.10.1 Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2, 4, and 8 words. A2 A1 A0 BURST LENGTH 0 0 0 Reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 8 words 1 x x Reserved - 14 - Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 8.10.2 Addressing Mode Select (A3) The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both addressing Mode support burst length 2, 4, and 8 words. A3 ADDRESSING MODE 0 Sequential 1 Interleave 8.10.2.1. Addressing Sequence of Sequential Mode A column access is performed by incrementing the column address input to the device. The address is varied by the Burst Length as the following. Addressing Sequence of Sequential Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 n 2 words (address bits is A0) Data 1 n+1 not carried from A0 to A1 Data 2 n+2 4 words (address bit A0, A1) Data 3 n+3 Not carried from A1 to A2 Data 4 n+4 Data 5 n+5 8 words (address bits A2, A1 and A0) Data 6 n+6 Not carried from A2 to A3 Data 7 n+7 8.10.2.2. Addressing Sequence for Interleave Mode A Column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following. Addressing Sequence of Interleave Mode DATA ACCESS ADDRESS Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 3 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 4 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 5 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 6 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 - 15 - BURST LENGTH 2 words 4 words 8 words Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 8.10.3 CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values of CAS Latency depend on the frequency of CLK. A6 A5 A4 CAS LATENCY 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved Reserved 2 3 Reserved Reserved 2.5 Reserved 8.10.4 DLL Reset bit (A8) This bit is used to reset DLL. When the A8 bit is "1", DLL is reset. 8.10.5 Mode Register /Extended Mode register change bits (BA0, BA1) These bits are used to select MRS/EMRS. BA1 BA0 A12-A0 0 0 1 0 1 x Regular MRS Cycle Extended MRS Cycle Reserved 8.10.6 Extended Mode Register field 1) DLL Switch field (A0) This bit is used to select DLL enable or disable A0 DLL 0 1 Enable Disable 2) Output Driver Size Control field (A6, A1) The 100%, 60% and 30% or matched impedance driver strength are required Extended Mode Register Set (EMRS) as the following: A6 0 0 1 1 A1 0 1 0 1 BUFFER STRENGTH 100% Strength 60% Strength Reserved 30% Strength 8.10.7 Reserved field  Test mode entry bit (A7) This bit is used to enter Test mode and must be set to "0" for normal operation.  Reserved bits (A9, A10, A11, A12) These bits are reserved for future operations. They must be set to "0" for normal operation. - 16 - Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 9. OPERATION MODE The following table shows the operation commands. 9.1 Simplified Truth Table SYM. ACT PRE PREA COMMAND Bank Active Bank Precharge Precharge All DEVICE STATE Idle CKEn-1 CKEn DM (4) BA0, BA1 A10 A12, A11, A9-A0 CS RAS CAS V V L L H H WE (3) H X X V (3) H X X V L X L L H L H X X X H X L L H L H X X V L V L H L L Any Any Write Active (3) WRITA Write with Autoprecharge Active (3) H X X V H V L H L L READ Read Active (3) H X X V L V L H L H Active (3) H X X V H V L H L H H X X L, L L L L L L L L L WRIT READA Read with Autoprecharge MRS Mode Register Set EMRS Extended Mode Register Set Idle Idle H X X H, L Op-Code (6) NOP No Operation Any H X X X X X L H H H BST Burst Read Stop Active H X X X X X L H H L DSL Device Deselect Any H X X X X X H X X X Auto Refresh AREF Idle H H X X X X L L L H SELF Self Refresh Entry Idle H L X X X X L L L H SELEX Self Refresh Exit Idle (Self Refresh) L H X X X X H X X X PD PDEX Power Down Mode Entry Power Down Mode Exit Idle/ (5) Active H L Any (Power Down) L H X X X X X X X X L H H X H X X X L H H X H X X X L H H X WDE Data Write Enable Active H X L X X X X X X X WDD Data Write Disable Active H X H X X X X X X X Notes 1. V = Valid X = Don’t Care L = Low level H = High level. 2. CKEn signal is input level when commands are issued CKEn-1 signal is input level one clock cycle before the commands are issued 3. These are state designated by the BA0, BA1 signals. 4. LDM, UDM (W9425G6JB) 5. Power Down Mode can not entry in the burst cycle. 6. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0, BA1 are reserved; A0~A12 provide the op-code to be written to the selected Mode Register (MRS or EMRS). - 17 - Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 9.2 Function Truth Table (Note 1) CURRENT STATE Idle Row Active Read Write CS RAS CAS WE ADDRESS COMMAND ACTION NOTES H X X X X DSL NOP L H H X X NOP/BST NOP L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT Row activating L L H L BA, A10 PRE/PREA NOP L L L H X AREF/SELF Refresh or Self refresh 2 L L L L Op-Code MRS/EMRS Mode register accessing 2 H X X X X DSL NOP L H H X X NOP/BST NOP L H L H BA, CA, A10 READ/READA Begin read: Determine AP 4 L H L L BA, CA, A10 WRIT/WRITA Begin write: Determine AP 4 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PREA Precharge 5 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST Burst stop L H L H BA, CA, A10 READ/READA Term burst, new read: Determine AP L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE/PREA Term burst, precharging L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST ILLEGAL L H L H BA, CA, A10 READ/READA Term burst, start read: Determine AP 6, 7 L H L L BA, CA, A10 WRIT/WRITA Term burst, start read: Determine AP 6 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PREA Term burst, precharging 8 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL - 18 - 6 3 Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB Function Truth Table, continued CURRENT STATE Read with Autoprecharge Write with Autoprecharge Precharging Row Activating ADDRESS COMMAND ACTION NOTES CS RAS CAS H X X X X DSL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PREA ILLEGAL L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL Continue burst to end L H H H X NOP Continue burst to end L H H L X BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL L H L L BA, CA, A10 WRIT/WRITA ILLEGAL L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL WE H X X X X DSL NOP-> Idle after tRP L H H H X NOP NOP-> Idle after tRP L H H L X BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PREA Idle after tRP L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL NOP-> Row active after tRCD L H H H X NOP NOP-> Row active after tRCD L H H L X BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL - 19 - Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB Function Truth Table, continued CURRENT STATE Write Recovering Write Recovering with Autoprecharge Refreshing Mode Register Accessing ADDRESS COMMAND ACTION NOTES CS RAS CAS H X X X X DSL NOP->Row active after tWR L H H H X NOP NOP->Row active after tWR L H H L X BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL WE L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL NOP->Enter precharge after tWR L H H H X NOP NOP->Enter precharge after tWR L H H L X BST ILLEGAL L H L H BA, CA, A10 READ/READA ILLEGAL 3 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3 L L H H BA, RA ACT ILLEGAL 3 L L H L BA, A10 PRE/PREA ILLEGAL 3 L L L H X AREF/SELF ILLEGAL L L L L Op-Code MRS/EMRS ILLEGAL H X X X X DSL NOP->Idle after tRC L H H H X NOP NOP->Idle after tRC L H H L X BST ILLEGAL L H L H X READ/WRIT ILLEGAL L L H X X ACT/PRE/PREA ILLEGAL L L L X X AREF/SELF/MRS/EMRS ILLEGAL H X X X X DSL NOP->Row after tMRD L H H H X NOP NOP->Row after tMRD L H H L X BST ILLEGAL L H L X X READ/WRIT ILLEGAL L L X X X ACT/PRE/PREA/ARE F/SELF/MRS/EMRS ILLEGAL Notes 1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle. 2. Illegal if any bank is not idle. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. 4. Illegal if tRCD is not satisfied. 5. Illegal if tRAS is not satisfied. 6. Must satisfy burst interrupt condition. 7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. Must mask preceding data which don’t satisfy tWR Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data - 20 - Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 9.3 Function Truth Table for CKE CURRENT STATE Self Refresh Power Down All banks Idle Row Active Any State Other Than Listed Above CKE n-1 n CS RAS CAS W E ADDRESS ACTION H X X X X X X INVALID L H H X X X X Exit Self Refresh->Idle after tXSNR L H L H H X X Exit Self Refresh->Idle after tXSNR L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X Maintain Self Refresh H X X X X X X INVALID L H X X X X X Exit Power down->Idle after tIS NOTES L L X X X X X Maintain power down mode H H X X X X X Refer to Function Truth Table H L H X X X X Enter Power down 2 H L L H H X X Enter Power down 2 H L L L L H X Self Refresh 1 H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Power down H H X X X X X Refer to Function Truth Table H L H X X X X Enter Power down 3 H L L H H X X Enter Power down 3 H L L L L H X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Power down H H X X X X X Refer to Function Truth Table Notes 1. Self refresh can enter only from the all banks idle state. 2. Power Down occurs when all banks are idle; this mode is referred to as precharge power down. 3. Power Down occurs when there is a row active in any bank; this mode is referred to as active power down. Remark: H = High level, L = Low level, X = High or Low level (Don’t care), V = Valid data - 21 - Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 9.4 Simplified Stated Diagram SELF REFRESH SREF SREFX MRS/EMRS MODE REGISTER SET AREF IDLE AUTO REFRESH PD PDEX ACT POWER DOWN ACTIVE POWERDOWN PDEX PD ROW ACTIVE Write BST Read Write Read Read Write Read Read A Write A Read A Write A Read A PRE Write A POWER APPLIED POWER ON PRE PRE PRE Read A PRE CHARGE Automatic Sequence Command Sequence - 22 - Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 10. ELECTRICAL CHARACTERISTICS 10.1 Absolute Maximum Ratings PARAMETER SYMBOL RATING UNIT VIN, VOUT -0.5 ~ VDDQ +0.5 V Voltage on Input Pins Relative to VSS VIN -1 ~ 3.6 V Voltage on VDD Supply Relative to VSS VDD -1 ~ 3.6 V Voltage on VDDQ Supply Relative to VSS VDDQ -1 ~ 3.6 V Operating Temperature (-5) TOPR 0 ~ 70 °C Operating Temperature (-5I) TOPR -40 ~ 85 °C Storage Temperature TSTG -55 ~ 150 °C TSOLDER 260 °C PD 1 W IOUT 50 mA Voltage on I/O Pins Relative to VSS Soldering Temperature (10s) Power Dissipation Short Circuit Output Current Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 10.2 Recommended DC Operating Conditions (TA = 0 to 70°C for -5, TA = -40 to 85°C for -5I) SYMBOL MIN. TYP. MAX. UNIT NOTES VDD Supply Voltage 2.3 2.5 2.7 V 2 VDDQ Supply Voltage for I/O Buffer 2.3 2.5 2.7 V 2 VREF Input reference Voltage 0.49 x VDDQ 0.50 x VDDQ 0.51 x VDDQ V 2, 3 VTT Termination Voltage (System) VREF - 0.04 VREF VREF + 0.04 V 2, 8 VIH (DC) Input High Voltage (DC) VREF + 0.15 - VDDQ + 0.3 V 2 VIL (DC) Input Low Voltage (DC) -0.3 - VREF - 0.15 V 2 Differential Clock DC Input Voltage -0.3 - VDDQ + 0.3 V 15 0.36 - VDDQ + 0.6 V 13, 15 VICK (DC) VID (DC) PARAMETER Input Differential Voltage. CLK and CLK inputs (DC) VIH (AC) Input High Voltage (AC) VREF + 0.31 - - V 2 VIL (AC) Input Low Voltage (AC) - - VREF - 0.31 V 2 0.7 - VDDQ + 0.6 V 13, 15 Differential AC input Cross Point Voltage VDDQ/2 - 0.2 - VDDQ/2 + 0.2 V 12, 15 Differential Clock AC Middle Point VDDQ/2 - 0.2 - VDDQ/2 + 0.2 V 14, 15 VID (AC) VX (AC) VISO (AC) Input Differential Voltage. CLK and CLK inputs (AC) Notes: Undershoot Limit: VIL (min) = -1.5V with a pulse width < 5 nS Overshoot Limit: VIH (max) = VDDQ +1.5V with a pulse width < 5 nS VIH (DC) and VIL (DC) are levels to maintain the current logic state. VIH (AC) and VIL (AC) are levels to change to the new logic state. - 23 - Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 10.3 Capacitance (VDD = VDDQ = 2.5V  0.2V, f = 1 MHz, TA = 25°C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V) MIN. MAX. DELTA (MAX.) UNIT Input Capacitance (except for CLK pins) 1.5 2.5 0.5 pF CCLK Input Capacitance (CLK pins) 1.5 2.5 0.25 pF CI/O DQ, DQS, DM Capacitance 3.5 4.5 0.5 pF SYMBOL CIN PARAMETER Note: These parameters are periodically sampled and not 100% tested. 10.4 Leakage and Output Buffer Characteristics SYMBOL PARAMETER MIN. MAX. UNIT II (L) Input Leakage Current Any input 0V < VIN < VDD, VREF Pin 0V < VIN < 1.35V (All other pins not under test = 0V) -2 2 µA IO (L) Output Leakage Current (Output disabled, 0V < VOUT < VDDQ) -5 5 µA VOH Output High Voltage (under AC test load condition) VTT +0.76 - V VOL Output Low Voltage (under AC test load condition) - VTT -0.76 V IOH Output Levels: Full drive option High Current (VOUT = VDDQ - 0.373V, min. VREF, min. VTT -15 - mA 4, 6 IOL Low Current (VOUT = 0.373V, max. VREF, max. VTT) 15 - mA 4, 6 IOHR Output Levels: Reduced drive option - 60% High Current (VOUT = VDDQ - 0.763V, min. VREF, min. VTT -9 - mA 5 IOLR Low Current (VOUT = 0.763V, max. VREF, max. VTT) 9 - mA 5 NOTES IOHR(30) Output Levels: Reduced drive option - 30% High Current (VOUT = VDDQ – 1.056V, min. VREF, min. VTT -4.5 - mA 5 IOLR(30) Low Current (VOUT = 1.056V, max. VREF, max. VTT) 4.5 - mA 5 - 24 - Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 10.5 DC Characteristics SYM. IDD0 IDD1 IDD2P MAX. -5/-5I PARAMETER Operating current: One Bank Active-Precharge; tRC = tRC min; tCK = tCK min; DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles Operating current: One Bank Active-Read-Precharge; Burst = 4; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA; Address and control inputs changing once per clock cycle Precharge Power Down standby current: All Banks Idle; Power down mode; CKE < VIL max; tCK = tCK min; Vin = (0.5 x VDDQ) for DQ, DQS and DM Idle floating standby current: IDD2F CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs changing once per clock cycle; Vin = (0.5 x VDDQ) for DQ, DQS and DM Idle standby current: IDD2N CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs changing once per clock cycle; Vin > VIH min or Vin < VIL max for DQ, DQS and DM Idle quiet standby current: IDD2Q CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs stable; Vin = (0.5 x VDDQ) for DQ, DQS and DM Active Power Down standby current: One Bank Active; Power down mode; CKE < VIL max; tCK = tCK min; Vin = (0.5 x VDDQ) for DQ, DQS and DM Active standby current: IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 NOTES 65 7 80 7, 9 5 20 7 20 7 20 7 mA 20 CS > VIH min; CKE > VIH min; One Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating current: Burst = 2; Reads; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL=2; tCK = tCK min; IOUT = 0mA Operating current: Burst = 2; Writes; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL = 2; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle Auto Refresh current: tRC = tRFC min Self Refresh current: CKE < 0.2V; external clock on; tCK = tCK min Random Read current: 4 Banks Active Read with activate every 20nS, Auto-Precharge Read every 20 nS; Burst = 4; tRCD = 3; IOUT = 0mA; DQ, DM and DQS inputs changing twice per clock cycle; Address changing once per clock cycle - 25 - UNIT 30 7 120 7, 9 115 7 65 7 2 175 Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 10.6 AC Characteristics and Operating Condition SYM. -5/-5I PARAMETER MIN. tRC tRFC tRAS tRCD tRAP tCCD tRP tRRD tWR Active to Ref/Active Command Period Ref to Ref/Active Command Period Active to Precharge Command Period Active to Read/Write Command Delay Time Active to Read with Auto-precharge Enable Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time tDAL Auto-precharge Write Recovery + Precharge Time tCK CLK Cycle Time tAC Data Access Time from CLK, CLK -0.7 0.7 tDQSCK DQS Output Access Time from CLK, CLK -0.6 0.6 tDQSQ tCH tCL tHP tQH tRPRE tRPST tDS tDH tDIPW tDQSH tDQSL tDSS tDSH tWPRES tWPRE tWPST tDQSS tIS tIH tIS tIH tIPW Data Strobe Edge to Output Data Edge Skew CLk High Level Width CLK Low Level Width CLK Half Period (minimum of actual tCH, tCL) DQ Output Data Hold Time from DQS DQS Read Preamble Time DQS Read Postamble Time DQ and DM Setup Time DQ and DM Hold Time DQ and DM Input Pulse Width (for each input) DQS Input High Pulse Width DQS Input Low Pulse Width DQS Falling Edge to CLK Setup Time DQS Falling Edge Hold Time from CLK Clock to DQS Write Preamble Set-up Time DQS Write Preamble Time DQS Write Postamble Time Write Command to First DQS Latching Transition Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) Control & Address Input Pulse Width (for each input) CL = 2 CL = 2.5 CL = 3 55 70 40 15 15 1 15 10 15 (tWR/tCK) + (tRP/tCK) 7.5 6 5 MAX. 0.45 0.45 Min. (tCL,tCH) tHP-0.5 0.9 0.4 0.4 0.4 1.75 0.35 0.35 0.2 0.2 0 0.25 0.4 0.72 0.6 0.6 0.7 0.7 2.2 70000 NOTES nS tCK nS tCK 18 nS 16 12 12 12 0.4 0.55 0.55 16 tCK 11 11 nS 1.1 0.6 tCK 11 11 nS tCK 11 11 11 11 nS 0.6 1.25 tCK 11 11 11 19, 21-23 19, 21-23 20-23 20-23 nS tHZ Data-out High-impedance Time from CLK, CLK tLZ Data-out Low-impedance Time from CLK, CLK -0.7 0.7 SSTL Input Transition Internal Write to Read Command Delay Exit Self Refresh to non-Read Command Exit Self Refresh to Read Command Refresh Time (8k/64mS) Mode Register Set Cycle Time 0.5 2 75 200 1.5 tT(SS) tWTR tXSNR tXSRD tREFI tMRD UNIT 0.7 7.8 10 - 26 - tCK nS tCK µS nS 17 Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB 10.7 AC Test Conditions PARAMETER SYMBOL VALUE UNIT Input High Voltage (AC) VIH VREF + 0.31 V Input Low Voltage (AC) VIL VREF - 0.31 V Input Reference Voltage VREF 0.5 x VDDQ V Termination Voltage VTT 0.5 x VDDQ V Differential Clock Input Reference Voltage VR Vx (AC) V VID (AC) 1.5 V VOTR 0.5 x VDDQ V Input Difference Voltage. CLK and CLK Inputs (AC) Output Timing Measurement Reference Voltage VTT VDDQ VIH min (AC) V SWING (MAX) VREF 50 Ω VIL max (AC) VSS T T Output Output V(out) 30pF SLE W = (VIH min (AC) - VILmax (AC)) / T Timing Reference Load Notes: (1) Conditions outside the limits listed under “Absolute Maximum Ratings” may cause permanent damage to the device. (2) All voltages are referenced to VSS, VSSQ. (3) Peak to peak AC noise on VREF may not exceed 2% VREF(DC). (4) VOH = 1.95V, VOL = 0.35V (5) VOH = 1.9V, VOL = 0.4V (6) The values of IOH(DC) is based on VDDQ = 2.3V and VTT = 1.19V. The values of IOL(DC) is based on VDDQ = 2.3V and VTT = 1.11V. (7) These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK and tRC. (8) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF. (9) These parameters depend on the output loading. Specified values are obtained with the output open. (10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed slope. (11) IF the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., tDQSS = 1.25  tCK, tCK = 5 nS, 1.25  5 nS = 6.25 nS is rounded up to 6.2 nS.) - 27 - Publication Release Date: Oct. 04, 2012 Revision A03 W9425G6JB (12) VX is the differential clock cross point voltage where input timing measurement is referenced. (13) VID is magnitude of the difference between CLK input level and CLK input level. (14) VISO means {VICK(CLK)+VICK( CLK )}/2. (15) Refer to the figure below. CLK VX VX VX VX VICK VICK VX VID(AC) CLK VICK VICK VSS VID(AC) 0 V Differential VISO VISO(min) VISO(max) VSS (16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock. (17) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. (18) tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For -5 speed grade at CL=2.5 and tCK=6 nS tDAL = ((15 nS / 6 nS) + (15 nS / 6 nS)) clocks = ((3) + (3)) clocks = 6 clocks (19) For command/address input slew rate ≥1.0 V/nS. (20) For command/address input slew rate ≥0.5 V/nS and
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