W9425G8EH

W9425G8EH 8M × 4 BANKS × 8 BITS DDR SDRAM Table of Contents1. 2. 3. 4. 5. 6. 7. GENERAL DESCRIPTION .............................................................................................................. 4 FEATURES...................................................................................................................................... 4 KEY PARAMETERS........................................................................................................................ 5 PIN CONFIGURATION.................................................................................................................... 6 PIN DESCRIPTION ......................................................................................................................... 7 BLOCK DIAGRAM........................................................................................................................... 8 FUNCTIONAL DESCRIPTION ........................................................................................................ 9 7.1 7.2 Power Up Sequence.............................................................................................................. 9 Command Function ............................................................................................................. 10 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16 Bank Activate Command ...................................................................................................... 10 Bank Precharge Command .................................................................................................. 10 Precharge All Command ...................................................................................................... 10 Write Command ................................................................................................................... 10 Write with Auto-precharge Command .................................................................................. 10 Read Command ................................................................................................................... 10 Read with Auto-precharge Command .................................................................................. 10 Mode Register Set Command .............................................................................................. 11 Extended Mode Register Set Command .............................................................................. 11 No-Operation Command ...................................................................................................... 11 Burst Read Stop Command.................................................................................................. 11 Device Deselect Command .................................................................................................. 11 Auto Refresh Command ....................................................................................................... 11 Self Refresh Entry Command............................................................................................... 12 Self Refresh Exit Command ................................................................................................. 12 Data Write Enable /Disable Command ................................................................................. 12 7.3 7.4 7.5 7.6 7.7 7.8 7.9 Read Operation ................................................................................................................... 12 Write Operation ................................................................................................................... 13 Precharge ............................................................................................................................ 13 Burst Termination ................................................................................................................ 13 Refresh Operation ............................................................................................................... 13 Power Down Mode .............................................................................................................. 14 Input Clock Frequency Change during Precharge Power Down Mode .............................. 14 7.10.1 Burst Length field (A2 to A0) ................................................................................................ 14 7.10 Mode Register Operation .................................................................................................... 14 -1- Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 7.10.2 7.10.3 7.10.4 7.10.5 7.10.6 7.10.7 Addressing Mode Select (A3)............................................................................................... 15 CAS Latency field (A6 to A4)................................................................................................ 16 DLL Reset bit (A8) ................................................................................................................ 16 Mode Register /Extended Mode register change bits (BS0, BS1) ........................................ 16 Extended Mode Register field .............................................................................................. 16 Reserved field ...................................................................................................................... 16 8. OPERATION MODE...................................................................................................................... 17 8.1 8.2 8.3 8.4 Simplified Truth Table.......................................................................................................... 17 Function Truth Table ........................................................................................................... 18 Function Truth Table for CKE.............................................................................................. 21 Simplified Stated Diagram................................................................................................... 22 Absolute Maximum Ratings................................................................................................. 23 Recommended DC Operating Conditions ........................................................................... 23 Capacitance......................................................................................................................... 24 Leakage and Output Buffer Characteristics ........................................................................ 24 DC Characteristics............................................................................................................... 25 AC Characteristics and Operating Condition....................................................................... 26 AC Test Conditions.............................................................................................................. 27 9. ELECTRICAL CHARACTERISTICS ............................................................................................. 23 9.1 9.2 9.3 9.4 9.5 9.6 9.7 10. SYSTEM CHARACTERISTICS FOR DDR SDRAM ..................................................................... 30 10.1 Table 1: Input Slew Rate for DQ, DQS, and DM................................................................. 30 10.2 Table 2: Input Setup & Hold Time Derating for Slew Rate.................................................. 30 10.3 Table 3: Input/Output Setup & Hold Time Derating for Slew Rate...................................... 30 10.4 Table 4: Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate ...................... 30 10.5 Table 5: Output Slew Rate Characteristics (X8 Devices only) ............................................ 30 10.6 Table 6: Output Slew Rate Matching Ratio Characteristics ................................................ 31 10.7 Table 7: AC Overshoot/Undershoot Specification for Address and Control Pins ............... 31 10.8 Table 8: Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins ................ 32 10.9 System Notes: ..................................................................................................................... 33 11. TIMING WAVEFORMS.................................................................................................................. 35 11.1 Command Input Timing ....................................................................................................... 35 11.2 Timing of the CLK Signals................................................................................................... 35 11.3 Read Timing (Burst Length = 4) .......................................................................................... 36 11.4 Write Timing (Burst Length = 4) .......................................................................................... 37 11.5 DM, DATA MASK (W9425G8EH) ....................................................................................... 38 11.6 Mode Register Set (MRS) Timing ....................................................................................... 39 11.7 Extend Mode Register Set (EMRS) Timing......................................................................... 40 Publication Release Date: Jul. 04, 2008 Revision A01 -2- W9425G8EH 11.8 Auto-precharge Timing (Read Cycle, CL = 2) ..................................................................... 41 11.9 Auto-precharge Timing (Read cycle, CL = 2), continued .................................................... 42 11.10 Auto-precharge Timing (Write Cycle) .................................................................................. 43 11.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) ................................................................ 44 11.12 Burst Read Stop (BL = 8) .................................................................................................... 44 11.13 Read Interrupted by Write & BST (BL = 8).......................................................................... 45 11.14 Read Interrupted by Precharge (BL = 8) ............................................................................. 45 11.15 Write Interrupted by Write (BL = 2, 4, 8) ............................................................................. 46 11.16 Write Interrupted by Read (CL = 2, BL = 8)......................................................................... 46 11.17 Write Interrupted by Read (CL = 3, BL = 4)......................................................................... 47 11.18 Write Interrupted by Precharge (BL = 8) ............................................................................. 47 11.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) ........................................................... 48 11.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) ........................................................... 48 11.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) ........................................................... 49 11.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) ........................................................... 49 11.23 Auto Refresh Cycle.............................................................................................................. 50 11.24 Precharge/Activate Power Down Mode Entry and Exit Timing ........................................... 50 11.25 Input Clock Frequency Change during Precharge Power Down Mode Timing................... 50 11.26 Self Refresh Entry and Exit Timing ..................................................................................... 51 12. PACKAGE SPECIFICATION......................................................................................................... 52 12.1 TSOP 66 lI – 400 mil ........................................................................................................... 52 13. REVISION HISTORY..................................................................................................................... 53 -3- Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 1. GENERAL DESCRIPTION W9425G8EH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR SDRAM), organized as 8,388,608 words × 4 banks × 8 bits. W9425G8EH delivers a data bandwidth of up to 400M words per second (-5). To fully comply with the personal computer industrial standard, W9425G8EH is sorted into three speed grades: -5, -6 and -75. The -5 is compliant to the DDR400/CL3 specification, the -6 is compliant to the DDR333/CL2.5 specification and the -75 is compliant to the DDR266/CL2 specification. All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. Write and Read data are synchronized with the both edges of DQS (Data Strobe). By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9425G8EH is ideal for main memory in high performance applications. 2. FEATURES • • • • • • • • • • • • • • • 2.5V ±0.2V Power Supply for DDR266/DDR333/DDR400 Up to 200 MHz Clock Frequency Double Data Rate architecture; two data transfers per clock cycle Differential clock inputs (CLK and CLK ) DQS is edge-aligned with data for Read; center-aligned with data for Write CAS Latency: 2, 2.5 and 3 Burst Length: 2, 4 and 8 Auto Refresh and Self Refresh Precharged Power Down and Active Power Down Write Data Mask Write Latency = 1 7.8µS refresh interval (8K/64mS refresh) Maximum burst refresh cycle: 8 Interface: SSTL_2 Packaged in TSOP II 66-pin, using Lead free materials with RoHS compliant -4- Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 3. KEY PARAMETERS SYMBOL DESCRIPTION CL = 2 tCK Clock Cycle Time CL = 2.5 CL = 3 tRAS tRC IDD0 IDD1 IDD4R IDD4W IDD5 IDD6 Active to Precharge Command Period Active to Ref/Active Command Period Operating Current: One Bank Active-Precharge Operating Current: One Bank Active-Read-Precharge Burst Operation Read Current Burst Operation Write Current Auto Refresh Current Self Refresh Current MIN./MAX. Min. Max. Min. Max. Min. Max. Min. Min. Max. Max. Max. Max. Max. Max. -5 7.5 nS 12 nS 6 nS 12 nS 5 nS 12 nS 40 nS 55 nS 110 mA 150 mA 180 mA 180 mA 190 mA 3 mA -6 7.5 nS 12 nS 6 nS 12 nS 6 nS 12 nS 42 nS 60 nS 110 mA 150 mA 170 mA 170 mA 190 mA 3 mA -75 7.5 nS 12 nS 7.5 nS 12 nS 7.5 nS 12 nS 45 nS 67.5 nS 110 mA 150 mA 160 mA 160 mA 190 mA 3 mA -5- Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 4. PIN CONFIGURATION VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS NC BS0 BS1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS -6- Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 5. PIN DESCRIPTION PIN NUMBER 28 − 32, 35 − 42 26, 27 2, 5, 8, 11, 56, 59, 62, 65 51 PIN NAME A0 − A12 FUNCTION Address DESCRIPTION Multiplexed pins for row and column address. Row address: A0 − A12. Column address: A0 − A9. (A10 is used for Auto-precharge) Select bank to activate during row address latch time, or bank to read/write during column address latch time. The DQ0 – DQ7 input and output data are synchronized with both edges of DQS. DQS is Bi-directional signal. DQS is input signal during write operation and output signal during read operation. It is Edgealigned with read data, Center-aligned with write data. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command inputs (along with CS ) define the command being entered. When DM is asserted "high" in burst write, the input data is masked. DM is synchronized with both edges of DQS. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of CLK . BS0, BS1 DQ0 − DQ7 DQS Bank Select Data Input/ Output Data Strobe 24 CS Chip Select Command Inputs Write Mask Differential Clock Inputs 23, 22, 21 47 RAS , CAS , WE DM 45, 46 CLK, CLK 44 49 1, 18, 33 34, 48, 66 3, 9, 15, 55, 61 6, 12, 52, 58, 64 4, 7, 10, 13, 14, 16, 17, 19, 20, 25, 43, 50, 53, 54, 57, 60, 63 CKE VREF VDD VSS VDDQ VSSQ CKE controls the clock activation and deactivation. When CKE Clock Enable is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. Reference Voltage Power (+2.5) Ground VREF is reference voltage for inputs. Power for logic circuit inside DDR SDRAM. Ground for logic circuit inside DDR SDRAM. Power (+2.5V) Separated power from VDD, used for output buffer, to improve for I/O Buffer noise. Ground for I/O Separated ground from VSS, used for output buffer, to improve noise. Buffer No Connection No connection. (NC pin should be connected to GND or floating) NC -7- Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 6. BLOCK DIAGRAM CLK CLK DLL CLOCK BUFFER CKE CONTROL CS RAS CAS WE COMMAND SIGNAL GENERATOR DECODER COLUMN DECODER COLUMN DECODER ROW DECODER A10 CELL ARRAY BANK #0 ROW DECODER CELL ARRAY BANK #1 A0 A9 A11 A12 BS0 BS1 ADDRESS BUFFER MODE REGISTER SENSE AMPLIFIER SENSE AMPLIFIER PREFETCH REGISTER DATA CONTROL CIRCUIT REFRESH COUNTER COLUMN COUNTER DQ BUFFER DQ0 DQ7 DQS DM COLUMN DECODER COLUMN DECODER ROW DECODER CELL ARRAY BANK #2 ROW DECODER CELL ARRAY BANK #3 SENSE AMPLIFIER SENSE AMPLIFIER NOTE: The cell array configuration is 8192 * 1024 * 8 -8- Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 7. FUNCTIONAL DESCRIPTION 7.1 Power Up Sequence (1) Apply power and attempt to CKE at a low state ( ≤ 0.2V), all other inputs may be undefined 1) Apply VDD before or at the same time as VDDQ. 2) Apply VDDQ before or at the same time as VTT and VREF. Start Clock and maintain stable condition for 200 µS (min.). After stable power and clock, apply NOP and take CKE high. Issue precharge command for all banks of the device. Issue EMRS (Extended Mode Register Set) to enable DLL and establish Output Driver Type. Issue MRS (Mode Register Set) to reset DLL and set device to idle with bit A8. (An additional 200 cycles(min) of clock are required for DLL Lock before any executable command applied.) Issue precharge command for all banks of the device. Issue two or more Auto Refresh commands. Issue MRS-Initialize device operation with the reset DLL bit deactivated A8 to low. (2) (3) (4) (5) (6) (7) (8) (9) CLK CLK ANY CMD 2 Clock min. Command PREA tRP EMRS 2 Clock min. MRS 2 Clock min. PREA tRP AREF tRFC 200 Clock min. AREF tRFC MRS Inputs maintain stable for 200 µS min. Enable DLL DLL reset with A8 = High Disable DLL reset with A8 = Low Initialization sequence after power-up -9- Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 7.2 7.2.1 Command Function Bank Activate Command ( RAS = "L", CAS = "H", WE = "H", BS0, BS1 = Bank, A0 to A12 = Row Address) The Bank Activate command activates the bank designated by the BS (Bank address) signal. Row addresses are latched on A0 to A12 when this command is issued and the cell data is read out of the sense amplifiers. The maximum time that each bank can be held in the active state is specified as tRAS (max). After this command is issued, Read or Write operation can be executed. 7.2.2 Bank Precharge Command ( RAS = "L", CAS = "H", WE = "L", BS0, BS1 = Bank, A10 = "L", A0 to A9, A11, A12 = Don’t Care) The Bank Precharge command percharges the bank designated by BS. The precharged bank is switched from the active state to the idle state. 7.2.3 Precharge All Command ( RAS = "L", CAS = "H", WE = "L", BS0, BS1 = Don’t Care, A10 = "H", A0 to A9, A11, A12 = Don’t Care) The Precharge All command precharges all banks simultaneously. Then all banks are switched to the idle state. 7.2.4 Write Command ( RAS = "H", CAS = "L", WE = "L", BS0, BS1 = Bank, A10 = "L", A0 to A9 = Column Address) The write command performs a Write operation to the bank designated by BS. The write data are latched at both edges of DQS. The length of the write data (Burst Length) and column access sequence (Addressing Mode) must be in the Mode Register at power-up prior to the Write operation. 7.2.5 Write with Auto-precharge Command ( RAS = "H", CAS = "L", WE = "L", BS0, BS1 = Bank, A10 = "H", A0 to A9 = Column Address) The Write with Auto-precharge command performs the Precharge operation automatically after the Write operation. This command must not be interrupted by any other commands. 7.2.6 Read Command ( RAS = "H", CAS = "L", WE = "H", BS0, BS1 = Bank, A10 = "L", A0 to A9 = Column Address) The Read command performs a Read operation to the bank designated by BS. The read data are synchronized with both edges of DQS. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Read operation. 7.2.7 Read with Auto-precharge Command ( RAS = "H", CAS = ”L”, WE = ”H”, BS0, BS1 = Bank, A10 = ”H”, A0 to A9 = Column Address) The Read with Auto-precharge command automatically performs the Precharge operation after the Read operation. - 10 - Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 1) READA ≥ tRAS (min) - (BL/2) x tCK Internal precharge operation begins after BL/2 cycle from Read with Auto-precharge command. 2) tRCD(min) ≤ READA < tRAS(min) - (BL/2) x tCK Data can be read with shortest latency, but the internal Precharge operation does not begin until after tRAS (min) has completed. This command must not be interrupted by any other command. 7.2.8 Mode Register Set Command ( RAS = "L", CAS = "L", WE = "L", BS0 = "L", BS1 = "L", A0 to A12 = Register Data) The Mode Register Set command programs the values of CAS Latency, Addressing Mode, Burst Length and DLL reset in the Mode Register. The default values in the Mode Register after powerup are undefined, therefore this command must be issued during the power-up sequence. Also, this command can be issued while all banks are in the idle state. Refer to the table for specific codes. 7.2.9 Extended Mode Register Set Command ( RAS = "L", CAS = "L", WE = "L", BS0 = "H", BS1 = "L", A0 to A12 = Register data) The Extended Mode Register Set command can be implemented as needed for function extensions to the standard (SDR-SDRAM). These additional functions include DLL enable/disable, output drive strength selection. The default value of the extended mode register is not defined; therefore this command must be issued during the power-up sequence for enabling DLL. Refer to the table for specific codes. 7.2.10 No-Operation Command ( RAS = "H", CAS = "H", WE = "H") The No-Operation command simply performs no operation (same command as Device Deselect). 7.2.11 Burst Read Stop Command ( RAS = "H", CAS = "H", WE = "L") The Burst stop command is used to stop the burst operation. This command is only valid during a Burst Read operation. 7.2.12 Device Deselect Command ( CS = "H") The Device Deselect command disables the command decoder so that the RAS , CAS , WE and Address inputs are ignored. This command is similar to the No-Operation command. 7.2.13 Auto Refresh Command ( RAS = "L", CAS = "L", WE = "H", CKE = "H", BS0, BS1, A0 to A12 = Don’t Care) AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS– BEFORE–RAS (CBR) refresh in previous DRAM types. This command is non persistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. This makes the address bits ”Don’t Care” during an AUTO REFRESH command. The DDR SDRAM requires AUTO REFRESH cycles at an average periodic interval of Publication Release Date: Jul. 04, 2008 Revision A01 - 11 - W9425G8EH tREFI (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, and the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 8 * tREFI. 7.2.14 Self Refresh Entry Command ( RAS = "L", CAS = "L", WE = "H", CKE = "L", BS0, BS1, A0 to A12 = Don’t Care) The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH, and is automatically enabled upon exiting SELF REFRESH. Any time the DLL is enabled a DLL Reset must follow and 200 clock cycles should occur before a READ command can be issued. Input signals except CKE are “Don’t Care” during SELF REFRESH. Since CKE is an SSTL_2 input, VREF must be maintained during SELF REFRESH. 7.2.15 Self Refresh Exit Command (CKE = "H", CS = "H" or CKE = "H", RAS = "H", CAS = "H") The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command. The use of SELF REFREH mode introduces the possibility that an internally timed event can be missed when CKE is raised for exit from self refresh mode. Upon exit from SELF REFRESH an extra auto refresh command is recommended. 7.2.16 Data Write Enable /Disable Command (DM = "L/H") During a Write cycle, the DM signal functions as Data Mask and can control every word of the input data. The DM signal controls DQ0 to DQ7. 7.3 Read Operation Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after tRCD from the Bank Activate command, the data is read out sequentially, synchronized with both edges of DQS (Burst Read operation). The initial read data becomes available after CAS Latency from the issuing of the Read command. The CAS Latency must be set in the Mode Register at power-up. When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst operation is terminated. When the Read with Auto-precharge command is issued, the Precharge operation is performed automatically after the Read cycle, then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Refer to the diagrams for Read operation. - 12 - Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 7.4 Write Operation Issuing the Write command after tRCD from the bank activate command. The input data is latched sequentially, synchronizing with both edges(rising & falling) of DQS after the Write command (Burst write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at power-up. When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated. When the Write with Auto-precharge command is issued, the Precharge operation is performed automatically after the Write cycle, then the bank is switched to the idle state, The Write with Autoprecharge command cannot be interrupted by any other command for the entire burst data duration. Refer to the diagrams for Write operation. 7.5 Precharge There are two Commands, which perform the precharge operation (Bank Precharge and Precharge All). When the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. The Bank Precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. The maximum time each bank can be held in the active state is specified as tRAS (max). Therefore, each bank must be precharged within tRAS(max) from the bank activate command. The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed only for the active bank and the precharge bank is then switched to the idle state. 7.6 Burst Termination When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after clock cycle of (CAS Latency) from the Precharge command. When the Burst Write cycle is interrupted by the Precharge command, the input circuit is reset at the same clock cycle at which the precharge command is issued. In this case, the DM signal must be asserted "high" during tWR to prevent writing the invalided data to the cell array. When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read operation is terminated. The Burst read Stop command is not supported during a write burst operation. Refer to the diagrams for Burst termination. 7.7 Refresh Operation Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation must be performed 8192 times (rows) within 64mS. The period between the Auto Refresh command and the next command is specified by tRFC. Self Refresh mode enters issuing the Self Refresh command (CKE asserted "low") while all banks are in the idle state. The device is in Self Refresh mode for as long as CKE held "low". In the case of distributed Auto Refresh commands, distributed auto refresh commands must be issued every 7.8 µS and the last distributed Auto Refresh commands must be performed within 7.8 µS before entering the self refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed within 7.8 µS. In Self Refresh mode, all input/output buffers are disabled, Publication Release Date: Jul. 04, 2008 Revision A01 - 13 - W9425G8EH resulting in lower power dissipation (except CKE buffer). Refer to the diagrams for Refresh operation. 7.8 Power Down Mode Two types of Power Down Mode can be performed on the device: Active Standby Power Down Mode and Precharge Standby Power Down Mode. When the device enters the Power Down Mode, all input/output buffers and DLL are disabled resulting in low power dissipation (except CKE buffer). Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking CKE "high" can exit this mode. When CKE goes high, a No operation command must be input at next CLK rising edge. Refer to the diagrams for Power Down Mode. 7.9 Input Clock Frequency Change during Precharge Power Down Mode DDR SDRAM input clock frequency can be changed under following condition: DDR SDRAM must be in precharged power down mode with CKE at logic LOW level. After a minimum of 2 clocks after CKE goes LOW, the clock frequency may change to any frequency between minimum and maximum operating frequency specified for the particular speed grade. During an input clock frequency change, CKE must be held LOW. Once the input clock frequency is changed, a stable clock must be provided to DRAM before precharge power down mode may be exited. The DLL must be RESET via EMRS after precharge power down exit. An additional MRS command may need to be issued to appropriately set CL etc. After the DLL relock time, the DRAM is ready to operate with new clock frequency. 7.10 Mode Register Operation The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks are in the idle state. The data to be set in the Mode Register is transferred using the A0 to A12 and BS0, BS1 address inputs. The Mode Register designates the operation mode for the read or write cycle. The register is divided into five filed: (1) Burst Length field to set the length of burst data (2) Addressing Mode selected bit to designate the column access sequence in a Burst cycle (3) CAS Latency field to set the assess time in clock cycle (4) DLL reset field to reset the DLL (5) Regular/Extended Mode Register filed to select a type of MRS (Regular/Extended MRS). EMRS cycle can be implemented the extended function (DLL enable/Disable mode). The initial value of the Mode Register (including EMRS) after power up is undefined; therefore the Mode Register Set command must be issued before power operation. 7.10.1 Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2, 4 and 8 words. A2 A1 A0 BURST LENGTH 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x Reserved 2 words 4 words 8 words Reserved Publication Release Date: Jul. 04, 2008 Revision A01 - 14 - W9425G8EH 7.10.2 Addressing Mode Select (A3) The Addressing Mode can be one of two modes; Interleave mode or Sequential Mode, When the A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both addressing Mode support burst length 2, 4 and 8 words. A3 ADDRESSING MODE 0 1 7.10.2.1. Addressing Sequence of Sequential Mode Sequential Interleave A column access is performed by incrementing the column address input to the device. The address is varied by the Burst Length as the following. Addressing Sequence of Sequential Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 2 words (address bits is A0) not carried from A0 to A1 4 words (address bit A0, A1) Not carried from A1 to A2 8 words (address bits A2, A1 and A0) Not carried from A2 to A3 7.10.2.2. Addressing Sequence for Interleave Mode A Column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following. Address Sequence for Interleave Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 words 4 words 8 words - 15 - Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 7.10.3 CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values of CAS Latency depend on the frequency of CLK. A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS LATENCY Reserved Reserved 2 3 Reserved Reserved 2.5 Reserved 7.10.4 DLL Reset bit (A8) This bit is used to reset DLL. When the A8 bit is "1", DLL is reset. 7.10.5 Mode Register /Extended Mode register change bits (BS0, BS1) These bits are used to select MRS/EMRS. BS1 0 0 1 BS0 0 1 x A12-A0 Regular MRS Cycle Extended MRS Cycle Reserved 7.10.6 Extended Mode Register field 1) DLL Switch field (A0) This bit is used to select DLL enable or disable A0 0 1 DLL Enable Disable 2) Output Driver Size Control field (A1) This bit is used to select Output Driver Size, both Full strength and Half strength are based on JEDEC standard. A1 0 1 OUTPUT DRIVER Full Strength Half Strength 7.10.7 Reserved field • Test mode entry bit (A7) This bit is used to enter Test mode and must be set to "0" for normal operation. • Reserved bits (A9, A10, A11, A12) These bits are reserved for future operations. They must be set to "0" for normal operation. Publication Release Date: Jul. 04, 2008 Revision A01 - 16 - W9425G8EH 8. OPERATION MODE The following table shows the operation commands. 8.1 Simplified Truth Table COMMAND DEVICE STATE CKEn-1 CKEn DM (4) SYM. BS0, BS1 A10 A12, A11, A9-A0 CS RAS CAS WE ACT PRE PREA WRIT WRITA READ READA MRS EMRS NOP BST DSL AREF SELF SELEX Bank Active Bank Precharge Precharge All Write Write with Autoprecharge Read Read with Autoprecharge Mode Register Set Extended Mode Register Set No Operation Burst Read Stop Device Deselect Auto Refresh Self Refresh Entry Self Refresh Exit Power Down Mode Entry Power Down Mode Exit Data Write Enable Data Write Disable Idle (3) (3) H H H X X X X X X X X X X X X H L H X X X X X X X X X X X X X X X V V X V V V V L, L H, L X X X X X X V L H L H L H C V X X X X X X V X X V V V V C V X X X X X X L L L L L L L L L L L H L L H L H L H L X X L L L H H H H L L H H X L L X H X H X H X X H H H L L L L L L H H X L L X H X H X H X X H L L L L H H L L H L X H H X X X X X X X X Any Any Active Active Active Active Idle Idle Any Active Any Idle Idle Idle (Self Refresh) Idle/ (5) Active Any (Power Down) Active Active (3) H H H H H H H H H H H L (3) (3) (3) PD H L X X X X PDEX WDE WDD Notes: L H H H X X X L H X X X X X X X X X 1. V = Valid X = Don’t Care L = Low level H = High level 2. CKEn signal is input level when commands are issued. CKEn-1 signal is input level one clock cycle before the commands are issued. 3. These are state designated by the BS0, BS1 signals. 4. LDM, UDM (W9425G8EH). 5. Power Down Mode can not entry in the burst cycle. - 17 - Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 8.2 Function Truth Table CS RAS H L L Idle L L L L L H L L Row Active L L L L L H L L L Read L L L L L H L L L Write L L L L L X H H H L L L L X H H H L L L L X H H H H L L L L X H H H H L L L L (Note 1) CURRENT STATE CAS X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L WE ADDRESS COMMAND ACTION NOTES X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code DSL NOP/BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP/BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS NOP NOP ILLEGAL ILLEGAL Row activating NOP Refresh or Self refresh Mode register accessing NOP NOP Begin read: Determine AP Begin write: Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop Term burst, new read: Determine AP ILLEGAL ILLEGAL Term burst, precharging ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL Term burst, start read: Determine AP Term burst, start read: Determine AP ILLEGAL Term burst, precharging ILLEGAL ILLEGAL 6, 7 6 3 8 3 6 4 4 3 5 2 2 3 3 - 18 - Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH Function Truth Table, continued CURRENT STATE CS H L L L L L L L L H L L L L L L L L H L L L RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L WE ADDRESS COMMAND ACTION NOTES X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Continue burst to end Continue burst to end ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP-> Idle after tRP NOP-> Idle after tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after tRP ILLEGAL ILLEGAL NOP-> Row active after tRCD NOP-> Row active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL 3 3 3 3 3 3 3 3 3 3 3 Read with Autoprecharge Write with Autoprecharge Precharging L L L L L H L L L L L L L L Row Activating - 19 - Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH Function Truth Table, continued CURRENT STATE CS RAS CAS WE ADDRESS COMMAND ACTION NOTES H L L Write Recovering L L L L L L H L L Write Recovering with Autoprecharge L L L L L L H L Refreshing L L L L H Mode Register Accessing L L L L X H H H H L L L L X H H H H L L L L X H H H L L X H H H L X H H L L H H L L X H H L L H H L L X H H L H L X H H L X X H L H L H L H L X H L H L H L H L X H L H X X X H L X X X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X BS, CA, A10 BS, CA, A10 BS, RA BS, A10 X Op-Code X X X X X X X X X X X DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/READA WRIT/WRITA ACT PRE/PREA AREF/SELF MRS/EMRS DSL NOP BST READ/WRIT ACT/PRE/PREA AREF/SELF/MRS/EMRS NOP->Row active after tWR NOP->Row active after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP->Enter precharge after tWR NOP->Enter precharge after tWR ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP->Idle after tRC NOP->Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP->Row after tMRD NOP->Row after tMRD ILLEGAL ILLEGAL ILLEGAL 3 3 3 3 3 3 3 3 DSL NOP BST READ/WRIT ACT/PRE/PREA/ARE F/SELF/MRS/EMRS Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle. 2. Illegal if any bank is not idle. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BS), depending on the state of that bank. 4. Illegal if tRCD is not satisfied. 5. Illegal if tRAS is not satisfied. 6. Must satisfy burst interrupt condition. 7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements. 8. Must mask preceding data which don’t satisfy tWR. Remark: H = High level, L = Low level, X = High or Low level (Don’t Care), V = Valid data - 20 - Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 8.3 Function Truth Table for CKE CKE n-1 n CURRENT STATE CS RAS CAS X H L L L X X X X X H L L L L X X H L L L L X X X X H H L X X X X X X H L H L X X X H L H L X X X X H L X X X X X X X H L L X X X X H L L X X X WE X X X X X X X X X X X X H X X X X X X H X X X X ADDRESS X X X X X X X X X X X X X X X X X X X X X X X X INVALID ACTION NOTES H L Self Refresh L L L L H Power Down L L H H H All banks Idle H H H L H H H Row Active H H H L Any State Other Than Listed Above Notes: H X H H H H L X H L H L L L L L X H L L L L L X H Exit Self Refresh->Idle after tXSNR Exit Self Refresh->Idle after tXSNR ILLEGAL ILLEGAL Maintain Self Refresh INVALID Exit Power down->Idle after tIS Maintain power down mode Refer to Function Truth Table Enter Power down Enter Power down Self Refresh ILLEGAL ILLEGAL Power down Refer to Function Truth Table Enter Power down Enter Power down ILLEGAL ILLEGAL ILLEGAL Power down Refer to Function Truth Table 3 3 2 2 1 1. Self refresh can enter only from the all banks idle state. 2. Power Down occurs when all banks are idle; this mode is referred to as precharge power down. 3. Power Down occurs when there is a row active in any bank; this mode is referred to as active power down. Remark: H = High level, L = Low level, X = High or Low level (Don’t Care), V = Valid data - 21 - Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 8.4 Simplified Stated Diagram SELF REFRESH SREF SREFX IDLE MRS/EMRS MODE REGISTER SET AREF AUTO REFRESH PD PDEX ACT ACTIVE POWERDOWN POWER DOWN PDEX PD ROW ACTIVE BST Read Read Write Write Write Read Read Write A Write A Read A Read A Read A PRE Write A PRE PRE Read A POWER APPLIED POWER ON PRE PRE CHARGE Automatic Sequence Command Sequence - 22 - Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETER SYMBOL RATING UNIT Input/Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current VIN, VOUT VDD, VDDQ TOPR TSTG TSOLDER PD IOUT -0.3 ~ VDDQ + 0.3 -0.3 ~ 3.6 0 ~ 70 -55 ~ 150 260 1 50 V V °C °C °C W mA Note: Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 9.2 Recommended DC Operating Conditions PARAMETER Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input reference Voltage Termination Voltage (System) Input High Voltage (DC) Input Low Voltage (DC) Differential Clock DC Input Voltage Input Differential Voltage. CLK and CLK inputs (DC) Input High Voltage (AC) Input Low Voltage (AC) Input Differential Voltage. CLK and CLK inputs (AC) Differential AC input Cross Point Voltage Differential Clock AC Middle Point (TA = 0 to 70°C) SYMBOL VDD VDDQ VREF VTT VIH (DC) VIL (DC) VICK (DC) VID (DC) VIH (AC) VIL (AC) VID (AC) VX (AC) VISO (AC) MIN. 2.3 2.3 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 VREF + 0.31 0.7 VDDQ/2 - 0.2 VDDQ/2 - 0.2 TYP. 2.5 2.5 0.50 x VDDQ VREF - MAX. 2.7 2.7 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 VREF - 0.31 VDDQ + 0.6 VDDQ/2 + 0.2 VDDQ/2 + 0.2 UNIT NOTES V V V V V V V V V V V V V 2 2 2, 3 2, 8 2 2 15 13, 15 2 2 13, 15 12, 15 14, 15 Notes: Undershoot Limit: VIL (min) = -1.5V with a pulse width < 5 nS Overshoot Limit: VIH (max) = VDDQ +1.5V with a pulse width < 5 nS VIH (DC) and VIL (DC) are levels to maintain the current logic state. VIH (AC) and VIL (AC) are levels to change to the new logic state. - 23 - Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 9.3 Capacitance DELTA (MAX.) 0.5 0.25 0.5 - (VDD = VDDQ = 2.5V ±0.2V, f = 1 MHz, TA = 25 °C, VOUT (DC) = VDDQ/2, VOUT (Peak to Peak) = 0.2V) SYMBOL CIN CCLK CI/O CNC PARAMETER Input Capacitance (except for CLK pins) Input Capacitance (CLK pins) DQ, DQS, DM Capacitance NC Pin Capacitance MIN. 2.0 2.0 4.0 - MAX. 3.0 3.0 5.0 1.5 UNIT pF pF pF pF Notes: These parameters are periodically sampled and not 100% tested. 9.4 Leakage and Output Buffer Characteristics PARAMETER Input Leakage Current (0V < VIN < VDDQ, All other pins not under test = 0V) Output Leakage Current (Output disabled, 0V < VOUT < VDDQ) Output High Voltage (under AC test load condition) Output Low Voltage (under AC test load condition) Output Minimum Source DC Current Output Minimum Sink DC Current Output Minimum Source DC Current Output Minimum Sink DC Current Half Strength Full Strength SYMBOL II (L) IO (L) VOH VOL IOH (DC) IOL (DC) IOH (DC) IOL (DC) MIN. -2 -5 VTT +0.76 -15.2 15.2 -10.4 10.4 MAX. 2 5 VTT -0.76 - UNIT NOTES µA µA V V mA mA mA mA 4, 6 4, 6 5 5 - 24 - Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 9.5 DC Characteristics PARAMETER Operating current: One Bank Active-Precharge; tRC = tRC min; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and control inputs changing once per clock cycle Operating current: One Bank Active-Read-Precharge; Burst = 2; tRC = tRC min; CL = 3; tCK = tCK min; IOUT = 0 mA; Address and control inputs changing once per clock cycle. Precharge Power Down standby current: All Banks Idle; Power down mode; CKE < VIL max; tCK = tCK min; Vin = VREF for DQ, DQS and DM Idle floating standby current: CS > VIH min; All Banks Idle; CKE > VIH min; Address and other control inputs changing once per clock cycle; Vin = VREF for DQ, DQS and DM Idle standby current: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs changing once per clock cycle; Vin > VIH min or Vin < VIL max for DQ, DQS and DM Idle quiet standby current: CS > VIH min; All Banks Idle; CKE > VIH min; tCK = tCK min; Address and other control inputs stable; Vin > VREF for DQ, DQS and DM Active Power Down standby current: One Bank Active; Power down mode; CKE < VIL max; tCK = tCK min Active standby current: CS > VIH min; CKE > VIH min; One Bank Active-Precharge; tRC = tRAS max; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Operating current: Burst = 2; Reads; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL=3; tCK = tCK min; IOUT = 0mA Operating current: Burst = 2; Write; Continuous burst; One Bank Active; Address and control inputs changing once per clock cycle; CL = 3; tCK = tCK min; DQ, DM and DQS inputs changing twice per clock cycle Auto Refresh current: tRC = tRFC min Self Refresh current: CKE < 0.2V Random Read current: 4 Banks Active Read with activate every 20nS, Auto-Precharge Read every 20 nS; Burst = 4; tRCD = 3; IOUT = 0mA; DQ, DM and DQS inputs changing twice per clock cycle; Address changing once per clock cycle SYM. IDD0 IDD1 IDD2P IDD2F MAX. -5 110 150 20 -6 110 150 20 -75 110 150 20 UNIT NOTES 7 7, 9 45 45 40 7 IDD2N 45 45 40 7 IDD2Q IDD3P IDD3N 40 20 40 20 35 mA 20 7 70 70 65 7 IDD4R 180 170 160 7, 9 IDD4W IDD5 IDD6 IDD7 180 190 3 300 170 190 3 300 160 190 3 300 7 7 - 25 - Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH 9.6 AC Characteristics and Operating Condition PARAMETER Active to Ref/Active Command Period Ref to Ref/Active Command Period Active to Precharge Command Period Active to Read/Write Command Delay Time Active to Read with Auto-precharge Enable Read/Write(a) to Read/Write(b) Command Period Precharge to Active Command Period Active(a) to Active(b) Command Period Write Recovery Time Auto-precharge Write Recovery + Precharge Time CL = 2 tCK CLK Cycle Time CL = 2.5 CL = 3 tAC tDQSCK tDQSQ tCH tCL tHP tQH tRPRE tRPST tDS tDH tDIPW tDQSH tDQSL tDSS tDSH tWPRES Data Access Time from CLK, CLK DQS Output Access Time from CLK, CLK Data Strobe Edge to Output Data Edge Skew CLk High Level Width CLK Low Level Width CLK Half Period (minimum of actual tCH, tCL) DQ Output Data Hold Time from DQS DQS Read Preamble Time DQS Read Postamble Time DQ and DM Setup Time DQ and DM Hold Time DQ and DM Input Pulse Width (for each input) DQS Input High Pulse Width DQS Input Low Pulse Width DQS Falling Edge to CLK Setup Time DQS Falling Edge Hold Time from CLK Clock to DQS Write Preamble Set-up Time 0.45 0.45 min (tCL,tCH) tHP -0.5 0.9 0.4 0.4 0.4 1.75 0.35 0.35 0.2 0.2 0 1.1 0.6 -5 MIN. 55 70 40 15 15 1 15 10 15 7.5 6 5 -0.7 -0.6 12 12 12 -0.7 0.6 0.4 0.55 0.55 0.45 0.45 min, (tCL,tCH) tHP -0.55 0.9 0.4 0.45 0.45 1.75 0.35 0.35 0.2 0.2 0 1.1 0.6 70000 MAX. MIN. 60 72 42 18 15 1 18 12 15 7.5 6 6 -0.7 -0.6 12 12 12 0.7 0.6 0.45 0.55 0.55 0.45 0.45 min, (tCL,tCH) tHP -0.75 0.9 0.4 0.5 0.5 1.75 0.35 0.35 0.2 0.2 0 nS tCK 11 nS 1.1 0.6 tCK 11 nS 100000 -6 MAX. MIN. 67.5 75 45 20 15 1 20 15 15 7.5 7.5 7.5 -0.75 -0.75 12 12 12 0.75 0.75 5 0.55 0.55 tCK 11 nS 16 tCK 18 nS tCK 100000 nS -75 MAX. UNIT NOTES SYM. tRC tRFC tRAS tRCD tRAP tCCD tRP tRRD tWR tDAL - 26 - Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH AC Characteristics and Operating Condition, continued SYM. tWPRE tWPST tDQSS tIS tIH tIS tIH tIPW tHZ tLZ tT(SS) tWTR tXSNR tXSRD tREFi tMRD PARAMETER DQS Write Preamble Time DQS Write Postamble Time -5 MIN. 0.25 0.4 0.6 1.25 MAX. MIN. 0.25 0.4 0.75 0.75 0.75 0.8 0.8 2.2 0.7 0.7 1.5 -0.7 -0.7 0.5 1 75 200 7.8 10 12 7.8 15 0.7 0.7 1.5 0.6 1.25 -6 MAX. MIN. 0.25 0.4 0.75 0.9 0.9 1.0 1.0 2.2 -0.75 -0.75 0.5 1 75 200 7.8 0.75 0.75 1.5 tCK nS tCK µS nS 17 nS 0.6 1.25 19, 21-23 19, 21-23 20-23 20-23 tCK 11 -75 MAX. UNIT NOTES Write Command to First DQS Latching 0.72 Transition Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) Control & Address Input Pulse Width (for each input) Data-out CLK, CLK Data-out CLK, CLK SSTL Input Transition Internal Write to Read Command Delay Exit Self Refresh to non-Read Command Exit Self Refresh to Read Command Refresh Interval Time (8k/ 64mS) Mode Register Set Cycle Time Low-impedance Time from High-impedance Time from 0.6 0.6 0.7 0.7 2.2 -0.7 -0.7 0.5 2 75 200 9.7 AC Test Conditions PARAMETER SYMBOL VALUE UNIT Input High Voltage (AC) Input Low Voltage (AC) Input Reference Voltage Termination Voltage Differential Clock Input Reference Voltage Input Difference Voltage. CLK and CLK Inputs (AC) Output Timing Measurement Reference Voltage VIH VIL VREF VTT VR VID (AC) VOTR VREF + 0.31 VREF - 0.31 0.5 x VDDQ 0.5 x VDDQ Vx (AC) 1.5 0.5 x VDDQ V V V V V V V - 27 - Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH VDDQ VIH min (AC) V SWING (MAX) VREF VTT 50 Ω VIL max (AC) VSS T T Output Output V(out) 30pF SLEW = (VIH min (AC) - VILmax (AC)) / T Timing Reference Load Notes: (1) (2) (3) (4) (5) (6) (7) (8) (9) Conditions outside the limits listed under “Absolute Maximum Ratings” may cause permanent damage to the device. All voltages are referenced to VSS, VSSQ. Peak to peak AC noise on VREF may not exceed ±2% VREF(DC). VOH = 1.95V, VOL = 0.35V VOH = 1.9V, VOL = 0.4V The values of IOH(DC) is based on VDDQ = 2.3V and VTT = 1.19V. The values of IOL(DC) is based on VDDQ = 2.3V and VTT = 1.11V. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK and tRC. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors is expected to be set equal to VREF and must track variations in the DC level of VREF. These parameters depend on the output loading. Specified values are obtained with the output open. (10) Transition times are measured between VIH min(AC) and VIL max(AC).Transition (rise and fall) of input signals have a fixed slope. (11) IF the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., tDQSS = 0.75 × tCK, tCK = 7.5 nS, 0.75 × 7.5 nS = 5.625 nS is rounded up to 5.6 nS.) (12) VX is the differential clock cross point voltage where input timing measurement is referenced. (13) VID is magnitude of the difference between CLK input level and CLK input level. (14) VISO means {VICK(CLK)+VICK( CLK )}/2. (15) Refer to the figure below. - 28 - Publication Release Date: Jul. 04, 2008 Revision A01 W9425G8EH CLK VX CLK VICK VSS VID(AC) VICK VX VX VICK VX VICK VX VID(AC) 0 V Differential VISO VISO(min) VSS VISO(max) (16) tAC and tDQSCK depend on the clock jitter. These timing are measured at stable clock. (17) A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. (18) tDAL = (tWR/tCK) + (tRP/tCK) (19) For command/address input slew rate ≥1.0 V/nS. (20) For command/address input slew rate ≥0.5 V/nS and