W94AD2KBJX5E

W94AD6KB / W94AD2KB 1Gb Mobile LPDDR Table of Contents1. 2. 3. 4. GENERAL DESCRIPTION ................................................................................................................................. 4 FEATURES ........................................................................................................................................................ 4 ORDER INFORMATION .................................................................................................................................... 5 BALL CONFIGURATION .................................................................................................................................... 6 4.1 Ball Assignment: LPDDR x16 ............................................................................................................... 6 4.2 Ball Assignment: LPDDR x32 ............................................................................................................... 6 5. BALL DESCRIPTION ......................................................................................................................................... 7 5.1 Signal Descriptions ............................................................................................................................... 7 5.2 Addressing Table.................................................................................................................................. 8 6. BLOCK DIAGRAM.............................................................................................................................................. 9 6.1 Block Diagram ...................................................................................................................................... 9 6.2 Simplified State Diagram .................................................................................................................... 10 7. FUNCTIONAL DESCRIPTION ......................................................................................................................... 11 7.1 Initialization ......................................................................................................................................... 11 7.1.1 Initialization Flow Diagram.................................................................................................... 12 7.1.2 Initialization Waveform Sequence ........................................................................................ 13 7.2 Mode Register Set Operation ............................................................................................................. 13 7.3 Mode Register Definition .................................................................................................................... 14 7.3.1 Burst Length ......................................................................................................................... 14 7.3.2 Burst Definition ..................................................................................................................... 15 7.3.3 Burst Type ............................................................................................................................ 16 7.3.4 Read Latency ....................................................................................................................... 16 7.4 Extended Mode Register Description ................................................................................................. 16 7.4.1 Extended Mode Register Definition ...................................................................................... 17 7.4.2 Partial Array Self Refresh ..................................................................................................... 17 7.4.3 Automatic Temperature Compensated Self Refresh ............................................................ 17 7.4.4 Output Drive Strength ........................................................................................................... 17 7.5 Status Register Read ......................................................................................................................... 18 7.5.1 SRR Register Definition........................................................................................................ 18 7.5.2 Status Register Read Timing Diagram ................................................................................. 19 7.6 Commands ......................................................................................................................................... 20 7.6.1 Basic Timing Parameters for Commands ............................................................................. 20 7.6.2 Truth Table – Commands.................................................................................................. 20 7.6.3 Truth Table - DM Operations ................................................................................................ 21 7.6.4 Truth Table – CKE............................................................................................................. 21 7.6.5 Truth Table - Current State Bank n - Command to Bank n ................................................... 22 7.6.6 Truth Table - Current State Bank n, Command to Bank m ................................................... 23 8. OPERATION .................................................................................................................................................... 25 8.1 Deselect ............................................................................................................................................. 25 8.2 No Operation ...................................................................................................................................... 25 8.2.1 NOP Command .................................................................................................................... 25 8.3 Mode Register Set .............................................................................................................................. 26 8.3.1 Mode Register Set Command .............................................................................................. 26 8.3.2 Mode Register Set Command Timing................................................................................... 26 Publication Release Date: Oct. 02, 2014 Revision: A01-005 -1- W94AD6KB / W94AD2KB 8.4 Active.................................................................................................................................................. 27 8.4.1 Active Command .................................................................................................................. 27 8.4.2 Bank Activation Command Cycle ......................................................................................... 28 8.5 Read ................................................................................................................................................... 28 8.5.1 Read Command ................................................................................................................... 28 8.5.2 Basic Read Timing Parameters ............................................................................................ 29 8.5.3 Read Burst Showing CAS Latency ....................................................................................... 30 8.5.4 Read to Read ....................................................................................................................... 30 8.5.5 Consecutive Read Bursts ..................................................................................................... 30 8.5.6 Non-Consecutive Read Bursts ............................................................................................. 31 8.5.7 Random Read Bursts ........................................................................................................... 32 8.5.8 Read Burst Terminate .......................................................................................................... 32 8.5.9 Read to Write ....................................................................................................................... 33 8.5.10 Read to Precharge ............................................................................................................... 34 8.5.11 Burst Terminate of Read ...................................................................................................... 35 8.6 Write ................................................................................................................................................... 35 8.6.1 Write Command ................................................................................................................... 35 8.6.2 Basic Write Timing Parameters ............................................................................................ 36 8.6.3 Write Burst (min. and max. tDQSS) ...................................................................................... 37 8.6.4 Write to Write........................................................................................................................ 37 8.6.5 Concatenated Write Bursts................................................................................................... 38 8.6.6 Non-Concatenated Write Bursts ........................................................................................... 38 8.6.7 Random Write Cycles ........................................................................................................... 39 8.6.8 Write to Read ....................................................................................................................... 39 8.6.9 Non-Interrupting Write to Read ............................................................................................. 39 8.6.10 Interrupting Write to Read .................................................................................................... 40 8.6.11 Write to Precharge ............................................................................................................... 40 8.6.12 Non-Interrupting Write to Precharge ..................................................................................... 40 8.6.13 Interrupting Write to Precharge ............................................................................................ 41 8.7 Precharge ........................................................................................................................................... 41 8.7.1 Precharge Command ........................................................................................................... 42 8.8 Auto Precharge................................................................................................................................... 42 8.9 Refresh Requirements........................................................................................................................ 42 8.10 Auto Refresh ...................................................................................................................................... 43 8.10.1 Auto Refresh Command ....................................................................................................... 43 8.10.2 Auto Refresh Cycles Back-to-Back ...................................................................................... 43 8.11 Self Refresh ........................................................................................................................................ 44 8.11.1 Self Refresh Command ........................................................................................................ 44 8.11.2 Self Refresh Entry and Exit .................................................................................................. 45 8.12 Power Down ....................................................................................................................................... 46 8.12.1 Power-Down Entry and Exit .................................................................................................. 46 8.13 Deep Power Down.............................................................................................................................. 47 8.13.1 Deep Power-Down Entry and Exit ........................................................................................ 47 8.14 Clock Stop .......................................................................................................................................... 48 8.14.1 Clock Stop Mode Entry and Exit ........................................................................................... 48 9. ELECTRICAL CHARACTERISTICS................................................................................................................. 49 9.1 Absolute Maximum Ratings ................................................................................................................ 49 Publication Release Date: Oct. 02, 2014 Revision: A01-005 -2- W94AD6KB / W94AD2KB 9.2 9.3 Input / Output Capacitance ................................................................................................................. 49 Electrical Characteristics and AC/DC Operating Conditions ............................................................... 50 9.3.1 Electrical Characteristics and AC/DC Operating Conditions ................................................. 50 9.4 DC Characteristics.............................................................................................................................. 51 9.4.1 IDD Specification and Test Conditions (x16) ........................................................................ 51 9.4.2 IDD Specification and Test Conditions (x32) ........................................................................ 52 9.5 AC Characteristics and Operating Condition ...................................................................................... 54 9.5.1 CAS Latency Definition (With CL = 3) .................................................................................. 56 9.5.2 Output Slew Rate Characteristics ......................................................................................... 57 9.5.3 AC Overshoot/Undershoot Specification .............................................................................. 57 9.5.4 AC Overshoot and Undershoot Definition............................................................................. 57 10. PACKAGE DIMENSIONS ................................................................................................................................ 58 10.1 LPDDR x16 ........................................................................................................................................ 58 10.2 LPDDR x32 ........................................................................................................................................ 59 11. REVISION HISTORY ....................................................................................................................................... 60 Publication Release Date: Oct. 02, 2014 Revision: A01-005 -3- W94AD6KB / W94AD2KB 1. GENERAL DESCRIPTION W94AD6KB / W94AD2KB is a high-speed Low Power double data rate synchronous dynamic random access memory (LPDDR SDRAM), An access to the LPDDR SDRAM is burst oriented. Consecutive memory location in one page can be accessed at a burst length of 2, 4, 8 and 16 when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the LPDDR SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the pre-charging time. By setting programmable Mode Registers, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. The device supports special low power functions such as Partial Array Self Refresh (PASR) and Automatic Temperature Compensated Self Refresh (ATCSR). 2. FEATURES  VDD = 1.7~1.95V  Differential clock inputs (CK and CK )  VDDQ = 1.7~1.95V  Bidirectional, data strobe (DQS)  Data width: x16 / x32  CAS Latency: 2 and 3  Clock rate: 200MHz (-5),166MHz (-6)  Burst Length: 2, 4, 8 and 16  Standard Self Refresh Mode  Burst Type: Sequential or Interleave  Partial Array Self-Refresh(PASR)  64 ms Refresh period  Auto Temperature Compensated Self Refresh (ATCSR)  Interface: LVCMOS compatible  Support package:  Power Down Mode  Deep Power Down Mode (DPD Mode) 60 balls VFBGA (x16)  Programmable output buffer driver strength 90 balls VFBGA (x32)  Operating Temperature Range  Four internal banks for concurrent operation  Data mask (DM) for write data Extended: -25°C ~ +85°C  Clock Stop capability during idle periods Industrial: -40°C ~ +85°C  Auto Pre-charge option for each burst access  Double data rate for data output Publication Release Date: Oct. 02, 2014 Revision: A01-005 -4- W94AD6KB / W94AD2KB 3. ORDER INFORMATION PART NUMBER VDD/VDDQ I/O WIDTH TYPE OTHERS W94AD6KBHX5I 1.8V/1.8V 16 60VFBGA 200MHz, -40°C~85°C W94AD6KBHX5E 1.8V/1.8V 16 60VFBGA 200MHz, -25°C~85°C W94AD2KBJX5I 1.8V/1.8V 32 90VFBGA 200MHz, -40°C~85°C W94AD2KBJX5E 1.8V/1.8V 32 90VFBGA 200MHz, -25°C~85°C W94AD6KBHX6I 1.8V/1.8V 16 60VFBGA 166MHz, -40°C~85°C W94AD6KBHX6E 1.8V/1.8V 16 60VFBGA 166MHz, -25°C~85°C W94AD2KBJX6I 1.8V/1.8V 32 90VFBGA 166MHz, -40°C~85°C W94AD2KBJX6E 1.8V/1.8V 32 90VFBGA 166MHz, -25°C~85°C Publication Release Date: Oct. 02, 2014 Revision: A01-005 -5- W94AD6KB / W94AD2KB 4. BALL CONFIGURATION 4.1 Ball Assignment: LPDDR x16 A B C D E F 1 VSS VDDQ VSSQ VDDQ VSSQ VSS 2 DQ15 DQ13 DQ11 DQ9 UDQS UDM G CKE CK H A9 J K A6 VSS 60 BALL VFBGA 3 4 5 6 VSSQ DQ14 DQ12 DQ10 DQ8 NC 7 VDDQ DQ1 DQ3 DQ5 DQ7 A13 8 DQ0 DQ2 DQ4 DQ6 LDQS LDM 9 VDD VSSQ VDDQ VSSQ VDDQ VDD CK WE CAS RAS A11 A12 CS BA0 BA1 A7 A4 A8 A5 A10/AP A2 A0 A3 A1 VDD (Top View) Ball Configuration 4.2 Ball Assignment: LPDDR x32 A B C D E F 1 VSS VDDQ VSSQ VDDQ VSSQ VDD 2 DQ31 DQ29 DQ27 DQ25 DQS3 DM3 G CKE CK H A9 J K L M N P R A6 A4 VSSQ VDDQ VSSQ VDDQ VSS 90 BALL VFBGA 3 4 5 6 VSSQ DQ30 DQ28 DQ26 DQ24 NC 7 VDDQ DQ17 DQ19 DQ21 DQ23 NC 8 DQ16 DQ18 DQ20 DQ22 DQS2 DM2 9 VDD VSSQ VDDQ VSSQ VDDQ VSS CK WE CAS RAS A11 A12 CS BA0 BA1 A7 DM1 DQS1 DQ9 DQ11 DQ13 DQ15 A8 A5 DQ8 DQ10 DQ12 DQ14 VSSQ A10/AP A2 DQ7 DQ5 DQ3 DQ1 VDDQ A0 DM0 DQS0 DQ6 DQ4 DQ2 DQ0 A1 A3 VDDQ VSSQ VDDQ VSSQ VDD (Top View) Ball Configuration Publication Release Date: Oct. 02, 2014 Revision: A01-005 -6- W94AD6KB / W94AD2KB 5. BALL DESCRIPTION 5.1 Signal Descriptions SIGNAL NAME TYPE FUNCTION A [n:0] Input Address BA0, BA1 Input Bank Select DQ0~DQ15 (×16) DQ0~DQ31 (×32) I/O Data Input/ Output DESCRIPTION Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. The address inputs also provide the opcode during a MODE REGISTER SET command. A10 is used for Auto Pre-charge Select. Define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Data bus: Input / Output. CS enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are CS Input RAS Input CAS Input WE Input UDM, LDM (x16); DM0 to DM3 (x32) CK / CK Input Input Chip Select masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Row Address RAS , CAS and WE (along with CS ) define the Strobe command being entered. Column Address Referred to RAS . Strobe Write Enable Input Mask Clock Inputs Referred to RAS . Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading matches the DQ and DQS loading. x16: LDM: DQ0 - DQ7, UDM: DQ8 – DQ15 x32: DM0: DQ0 - DQ7, DM1: DQ8 – DQ15, DM2: DQ16 – DQ23, DM3: DQ24 – DQ31. CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK .Input and output data is referenced to the crossing of CK and CK (both directions of crossing). Internal clock signals are derived from CK/ CK . Publication Release Date: Oct. 02, 2014 Revision: A01-005 -7- W94AD6KB / W94AD2KB SIGNAL NAME TYPE FUNCTION CKE Input LDQS,UDQS (x16); DQS0~DQ3 (x32) I/O VDD VSS Supply Supply VDDQ Supply VSSQ Supply NC - 5.2 DESCRIPTION CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE, POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN Clock Enable (row ACTIVE in any bank). CKE is synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE, are disabled during power down and self refresh mode which are contrived for low standby power consumption. Output with read data, input with write data. Edgealigned with read data, centered with write data. Used to capture write data. Data Strobe x16: LDQS: DQ0~DQ7; UDQS: DQ8~DQ15. x32: DQS0: DQ0~DQ7; DQS1: DQ8~DQ15; DQS2: DQ16~DQ23; DQS3: DQ24~DQ31. Power Power supply for input buffers and internal circuit. Ground Ground for input buffers and internal circuit. Power for I/O Power supply separated from VDD, used for output Buffer drivers to improve noise. Ground for I/O Ground for output drivers. Buffer No Connect No internal electrical connection is present. Addressing Table Item 1Gb Number of banks 4 Bank address balls BA0,BA1 Auto precharge ball A10/AP x16 Row addresses A0-A13 Column addresses A0-A9 tREFI (µS) x32 7.8 Row addresses A0-A12 Column addresses A0-A9 tREFI (µS) 7.8 Publication Release Date: Oct. 02, 2014 Revision: A01-005 -8- W94AD6KB / W94AD2KB 6. BLOCK DIAGRAM 6.1 Block Diagram CK CK CLOCK BUFFER CKE CONTROL CS RAS SIGNAL GENERATOR COMMAND CAS DECODER COLUMN DECODER A10 COLUMN DECODER ROW DECODER ROW DECODER WE CELL ARRAY BANK #0 MODE REGISTER A0 CELL ARRAY BANK #1 SENSE AMPLIFIER SENSE AMPLIFIER ADDRESS BUFFER DQ0~15 (x16) DATA CONTROL DQ COLUMN COUNTER COUNTER UDM, LDM (x16) DM0~3 (x32) UDQS, LDQS (x16) DQS0~3 (x32) COLUMN DECODER COLUMN DECODER ROW DECODER REFRESH CELL ARRAY BANK #2 SENSE AMPLIFIER DQ0~31 (x32) BUFFER CIRCUIT ROW DECODER An BA0 BA1 CELL ARRAY BANK #3 SENSE AMPLIFIER Publication Release Date: Oct. 02, 2014 Revision: A01-005 -9- W94AD6KB / W94AD2KB 6.2 Simplified State Diagram Power applied Power On Self Refresh DPDSX Deep Power Down Precharge All Bank SRR Read Read REFS REFSX SRR DPDS Idle All banks precharged MRS MRS EMRS Auto Refresh REFA CKEL CKEH Precharge Power Down ACT Active Power Down CKEH CKEL Burst Stop Row Active READ WRITE BST WRITE READ WRITEA WRITE READA READ WRITEA READA READ READA PRE WRITE A PRE PRE PRE Precharge PREALL READ A Automatic Sequence Command Sequence ACT=Active EMRS=Ext. Mode Reg. Set REFSX=Exit Self Refresh BST=Burst Terminate MRS=Mode Register Set READ=Read w/o Auto Precharge CKEL=Enter Power-Down PRE=Precharge READA=Read with Auto Precharge CKEH=Exit Power-Down PREALL=Precharge All Bank WRITE=Write w/o Auto Precharge DPDS=Enter Deep Power-Down REFA=Auto Refresh WRITEA=Write with Auto Precharge DPDSX=Exit Deep Power-Down REFS=Enter Self Refresh SRR = Status Register Read Note: Use caution with this diagram.It is indented to provide a floorplan of the possible state transitions and commands to control them,not alldetails.In particular situations involving more than one bank are not captured in full detall. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 10 - W94AD6KB / W94AD2KB 7. FUNCTIONAL DESCRIPTION 7.1 Initialization LPDDR SDRAM must be powered up and initialized in a predefined manner. Operations procedures other than those specified may result in undefined operation. If there is any interruption to the device power, the initialization routine should be followed. The steps to be followed for device initialization are listed below. The Mode Register and Extended Mode Register do not have default values. If they are not programmed during the initialization sequence, it may lead to unspecified operation. The clock stop feature is not available until the device has been properly initialized from Step 1 through 11.  Step 1: Provide power, the device core power (VDD) and the device I/O power (VDDQ) must be brought up simultaneously to prevent device latch-up. Although not required, it is recommended that VDD and VDDQ are from the same power source. Also assert and hold Clock Enable (CKE) to a LVCMOS logic high level.  Step 2: Once the system has established consistent device power and CKE is driven high, it is safe to apply stable clock.  Step 3: There must be at least 200μS of valid clocks before any command may be given to the DRAM. During this time NOP or DESELECT commands must be issued on the command bus.  Step 4: Issue a PRECHARGE ALL command.  Step 5: Provide NOPs or DESELECT commands for at least tRP time.  Step 6: Issue an AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time. Issue the second AUTO REFRESH command followed by NOPs or DESELECT command for at least tRFC time. Note as part of the initialization sequence there must be two Auto Refresh commands issued. The typical flow is to issue them at Step 6, but they may also be issued between steps 10 and 11.  Step 7: Using the MRS command, program the base mode register. Set the desired operation modes.  Step 8: Provide NOPs or DESELECT commands for at least tMRD time.  Step 9: Using the MRS command, program the extended mode register for the desired operating modes. Note the order of the base and extended mode register programmed is not important.  Step 10: Provide NOP or DESELECT commands for at least tMRD time.  Step 11: The DRAM has been properly initialized and is ready for any valid command. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 11 - W94AD6KB / W94AD2KB 7.1.1 Initialization Flow Diagram 1 VDD and VDDQ Ramp: CKE must be held high 2 Apply stable clocks 3 Wait at least 200µs with NOP or DESELECT on command bus 4 PRECHARGE ALL 5 Assert NOP or DESELCT for tRP time 6 Issue two AUTO REFRESH commands each followed by NOP or DESELECT commands for tRFC time 7 Configure Mode Register 8 Assert NOP or DESELECT for tMRD time 9 Configure Extended Mode Register 10 Assert NOP or DESELECT for tMRD time 11 LPDDR SDRAM is ready for any valid command Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 12 - W94AD6KB / W94AD2KB 7.1.2 Initialization Waveform Sequence VDD VDDQ 200µs tCK tRP tRFC tRFC tMRD tMRD CK CK CKE Command NOP PRE ARF Address A10 All Banks ARF MRS MRS ACT CODE CODE RA CODE CODE RA BA0,BA1 BA BA0 = L BA1 = L BA0 = L BA1 = H DM DQ, DQS (High-Z) Load Mode Reg. VDD / VDDQ powered up Clock stable Load Ext. Mode Reg. = Don't Care 7.2 Mode Register Set Operation The Mode Register is used to define the specific mode of operation of the LPDDR SDRAM. This definition includes the definition of a burst length, a burst type, a CAS latency as shown in the following figure. The Mode Register is programmed via the MODE REGISTER SET command (with BA0=0 and BA1=0) and will retain the stored information until it is reprogrammed, the device goes into Deep Power Down mode, or the device loses power. Mode Register bits A0-A2 specify the burst length, A3 the type of burst (sequential or interleave), A4A6 the CAS latency. A logic 0 should be programmed to all the undefined addresses bits to ensure future compatibility. The Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 13 - W94AD6KB / W94AD2KB 7.3 Mode Register Definition BA1 BA0 An...A7 (see Note 1) 0 0 0 (see Note 2) A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved A6 A5 A4 CAS Latency A3 0 1 Burst Type Sequential Interleave A3 A2 BT A1 A0 Burst Length A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Address Bus Mode Register Burst Length Reserved 2 4 8 16 Reserved Reserved Reserved NOTE: 1.MSB depends on LPDDR SDRAM density. 2.Alogic 0 should be programmed to all unused / undefined address bits to future compatibility. 7.3.1 Burst Length Read and write accesses to the LPDDR SDRAM are burst oriented, with the burst length and burst type being programmable. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1−An when the burst length is set to two, by A2−An when the burst length is set to 4, by A3−An when the burst length is set to 8 (where An is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both read and write bursts. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 14 - W94AD6KB / W94AD2KB 7.3.2 BURST LENGTH Burst Definition STARTING COLUMN ADDRESS A3 A2 A1 0 0–1 0–1 1 1–0 1–0 0 0 0–1–2–3 0–1–2–3 0 1 1–2–3–0 1–0–3–2 1 0 2–3–0–1 2–3–0–1 1 1 3–0–1–2 3–2–1–0 0 0 0 0–1–2–3–4–5–6–7 0–1–2–3–4–5–6–7 0 0 1 1–2–3–4–5–6–7–0 1–0–3–2–5–4–7–6 0 1 0 2–3–4–5–6–7–0–1 2–3–0–1–6–7–4–5 0 1 1 3–4–5–6–7–0–1–2 3–2–1–0–7–6–5–4 1 0 0 4–5–6–7–0–1–2–3 4–5–6–7–0–1–2–3 1 0 1 5–6–7–0–1–2–3–4 5–4–7–6–1–0–3–2 1 1 0 6–7–0–1–2–3–4–5 6–7–4–5–2–3–0–1 1 1 1 7–0–1–2–3–4–5–6 7–6–5–4–3–2–1–0 0 0 0 0 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F 0 0 0 1 1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 1-0-3-2-5-4-7-6-9-8-B-A-D-C-F-E 0 0 1 0 2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 2-3-0-1-6-7-4-5-A-B-8-9-E-F-C-D 0 0 1 1 3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 3-2-1-0-7-6-5-4-B-A-9-8-F-E-D-C 0 1 0 0 4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 4-5-6-7-0-1-2-3-C-D-E-F-8-9-A-B 0 1 0 1 5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 5-4-7-6-1-0-3-2-D-C-F-E-9-8-B-A 0 1 1 0 6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 6-7-4-5-2-3-0-1-E-F-C-D-A-B-8-9 0 1 1 1 7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0-F-E-D-C-B-A-9-8 1 0 0 0 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 1 0 0 1 9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 9-8-B-A-D-C-F-E-1-0-3-2-5-4-7-6 1 0 1 0 A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 A-B-8-9-E-F-C-D-2-3-0-1-6-7-4-5 1 0 1 1 B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A B-A-9-8-F-E-D-C-3-2-1-0-7-6-5-4 1 1 0 0 C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B C-D-E-F-8-9-A-B-4-5-6-7-0-1-2-3 1 1 0 1 D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C D-C-F-E-9-8-B-A-5-4-7-6-1-0-3-2 1 1 1 0 E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D E-F-C-D-A-B-8-9-6-7-4-5-2-3-0-1 1 1 1 1 F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E F-E-D-C-B-A-9-8-7-6-5-4-3-2-1-0 2 4 8 16 A0 ORDER OF ACCESSES WITHIN A BURST (HEXADECIMAL NOTATION) SEQUENTIAL INTERLEAVED Notes: 1. 2. 3. 4. For a burst length of two, A1-An selects the two data element block; A0 selects the first access within the block. For a burst length of four, A2-An selects the four data element block; A0-A1 selects the first access within the block. For a burst length of eight, A3-An selects the eight data element block; A0-A2 selects the first access within the block. For the burst length of sixteen, A4-An selects the sixteen data element block; A0-A3 selects the first access within the block. 5. Whenever a boundary of the block is reached within a given sequence, the following access wraps within the block. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 15 - W94AD6KB / W94AD2KB 7.3.3 Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in the previous table. 7.3.4 Read Latency The CAS latency is the delay between the registration of a READ command and the availability of the first piece of output data. The latency should be set to 2 or 3 clocks, as shown in section 7.3 Mode Register Definition figure. If a READ command is registered at a clock edge n and the latency is 3 clocks, the first data element will be valid at n + 2 tCK + tAC. If a READ command is registered at a clock edge n and the latency is 2 clocks, the first data element will be valid at n + tCK + tAC. 7.4 Extended Mode Register Description The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include output drive strength selection and Partial Array Self Refresh (PASR). PASR is effective in Self Refresh mode only. The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA1=1 and BA0=0) and will retain the stored information until it is reprogrammed, the device is put in Deep Power Down mode, or the device loses power. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation. Address bits A0-A2 specify PASR, A5-A7 the Driver Strength. A logic 0 should be programmed to all the undefined addresses bits to ensure future compatibility. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 16 - W94AD6KB / W94AD2KB 7.4.1 Extended Mode Register Definition BA1 BA0 An...A8 (see Note 1) A7 ~ A5 1 0 0 (see Note 2) DS A4 A3 A2 Reserved A1 A0 Address Bus PASR Extended Mode Register PASR A7 A6 A5 Drive Strength A2 A1 A0 0 0 0 Full Strength Driver 0 0 0 All banks 0 0 1 Half Strength Driver 0 0 1 1/2 array (BA1=0) 0 1 0 Quarter Strength Driver 0 1 0 0 1 1 Octant Strength Driver 0 1 1 1 0 Three-Quarters Strength Driver 1 0 0 Reserved 1 0 1 Reserved 0 1/4 array (BA1=BA0=0) Reserved 1 1 0 Reserved 1 1 1 Reserved NOTES: 1.MSB depends on mobile DDR SDRAM density. 2.A logic 0 should be programmed to all unused / undefined bits to ensure future compatibility. 7.4.2 Partial Array Self Refresh With partial array self refresh (PASR), the self refresh may be restricted to a variable portion of the total array. The whole array (default), 1/2 array, or 1/4 array could be selected. Data outside the defined area will be lost. Address bits A0 to A2 are used to set PASR. 7.4.3 Automatic Temperature Compensated Self Refresh The device has an Automatic Temperature Compensated Self Refresh feature. It automatically adjusts the refresh rate based on the device temperature without any register update needed. 7.4.4 Output Drive Strength The drive strength could be set to full, half, quarter, octant, and three-quarter strength via address bits A5, A6 and A7. The half drive strength option is intended for lighter loads or point-to-point environments. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 17 - W94AD6KB / W94AD2KB 7.5 Status Register Read Status Register Read (SRR) is an optional feature in JEDEC, and it is implemented in this device. With SRR, a method is defined to read registers from the device. The encoding for an SRR command is the same as a MRS with BA[1:0]=“01”. The address pins (A[n:0]) encode which register is to be read. Currently only one register is defined at A[n:0]=0. The sequence to perform an SRR command is as follows:  All reads/writes must be completed  All banks must be closed  MRS with BA=01 is issued (SRR)  Wait tSRR  Read issued to any bank/page  CAS latency cycles later the device returns the registers data as it would a normal read  The next command to the device can be issued tSRC after the Read command was issued. The burst length for the SRR read is always fixed to length 2. 7.5.1 SRR Register Definition Default: (A[n:0] = 0) X~DQ16 DQ15~DQ13 DQ12 DQ11 DQ10~DQ8 DQ7~DQ4 DQ3~DQ0 Density Reserved DQ15 DQ14 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 DT DW Refresh Rate Rising Edge of DQ Bus Revision Manufacturer Identification Identification SRR Register 0 DQ13 Density DQ3 DQ2 DQ1 DQ0 Manufacturer 0 1 0 1 0 1 0 1 128 256 512 1024 2048 Reserved Reserved 64 1 0 0 0 Winbond DQ12 Device Type DQ11 DW 0 1 LPDDR Reserved 0 1 16 bits 32 bits DQ7:4 Revision ID (See Note 1) Note 1 : The manufacture’s revision number starts at ‘0000’ and increments by ‘0001’ each time a change in the manufacturer’s specification (AC timings, or feature set), IBIS (pull up or pull down characteristics), or process occurs. DQ10 DQ9 DQ8 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Refresh Rate Reserved Reserved Reserved Reserved 1 0.5 0.25 Reserved Note 2 : The refresh rate multiplier is based on the memory’s temperature sensor. Note 3 : Required average periodic refresh interval = tREFI * multiplier. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 18 - W94AD6KB / W94AD2KB 7.5.2 Status Register Read Timing Diagram tSRC tSRR tRP CK CK Command CMD BA1,BA0 An~A0 NOP MRS NOP READ NOP NOP NOP CMD 01 0 CL=3 DQS DQ DQ:Reg out PCHA, or PCH = Don’t Care Notes: 1. 2. 3. 4. 5. 6. 7. SRR can only be issued after power-up sequence is complete. SRR can only be issued with all banks precharged. SRR CL is unchanged from value in the mode register. SRR BL is fixed at 2. tSRR = 2 (min). tSRC = CL + 1; (min time between read to next valid command) No commands other than NOP and DES are allowed between the SRR and the READ. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 19 - W94AD6KB / W94AD2KB 7.6 Commands All commands (address and control signals) are registered on the positive edge of clock (crossing of CK going high and CK going low). 7.6.1 Basic Timing Parameters for Commands tCK tCH tCL CK CK tIS tIH Input Valid Valid Valid = Don't Care NOTE: Input = A0–An, BA, CKE, CS, RAS, CAS, WE 7.6.2 Truth Table – Commands NAME (FUNCTION) CS RAS CAS WE BA A10/AP ADDR NOTES DESELECT (NOP) H X X X X X X 2 NO OPERATION (NOP) L H H H X X X 2 ACTIVE (Select Bank and activate row) L L H H Valid Row Row READ (Select bank and column and start read burst) L H L H Valid L Col READ with AP (Read Burst with Auto Precharge) L H L H Valid H Col WRITE (Select bank and column and start write burst) L H L L Valid L Col WRITE with AP (Write Burst with Auto Precharge) L H L L Valid H Col 3 BURST TERMINATE L H H L X X X 4, 5 PRECHARGE (Deactivate row in selected bank) L L H L Valid L X 6 PRECHARGE ALL (Deactivate rows in all banks) L L H L X H X 6 AUTO REFRESH or enter SELF REFRESH L L L H X X X 7, 8, 9 MODE REGISTER SET L L L L Valid Op-code 3 10 Notes: 1. All states and sequences not shown are illegal or reserved. 2. DESELECT and NOP are functionally interchangeable. 3. Auto precharge is non-persistent. A10 High enables Auto precharge, while A10 Low disables Auto precharge. 4. Burst Terminate applies to only Read bursts with Auto precharge disabled. This command is undefined and should not be used for Read with Auto precharge enabled, and for Write bursts. 5. This command is BURST TERMINATE if CKE is High and DEEP POWER DOWN entry if CKE is Low. 6. If A10 is low, bank address determines which bank is to be precharged. If A10 is high, all banks are precharged and BA0~BA1 are don’t care. 7. This command is AUTO REFRESH if CKE is High and SELF REFRESH if CKE is low. 8. All address inputs and I/O are ‘don’t care’ except for CKE. Internal refresh counters control bank and row addressing. 9. All banks must be precharged before issuing an AUTO-REFRESH or SELF REFRESH command. 10. BA0 and BA1 value select between MRS and EMRS. 11. CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER-DOWN. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 20 - W94AD6KB / W94AD2KB 7.6.3 Truth Table - DM Operations FUNCTION DM DQ NOTES Write Enable L Valid 1 Write Inhibit H X 1 Note: 1. Used to mask write data, provided coincident with the corresponding data. 7.6.4 Truth Table – CKE CKEn-1 CKEn CURRENT STATE COMMAND n ACTION n NOTES L L Power Down X Maintain Power Down L L Self Refresh X Maintain Self Refresh L L Deep Power Down X Maintain Deep Power Down L H Power Down NOP or DESELECT Exit Power Down 5, 6, 9 L H Self Refresh NOP or DESELECT Exit Self Refresh 5, 7, 10 L H Deep Power Down NOP or DESELECT Exit Deep Power Down 5, 8 H L All Banks Idle NOP or DESELECT Precharge Power Down Entry 5 H L Bank(s) Active NOP or DESELECT Active Power Down Entry 5 H L All Banks Idle AUTO REFRESH Self Refresh Entry H L All Banks Idle BURST TERMINATE Enter Deep Power Down H H See the other Truth Tables Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of LPDDR immediately prior to clock edge n. 3. COMMAND n is the command registered at clock edge n, and ACTION n is the result of COMMAND n. 4. All states and sequences not shown are illegal or reserved. 5. DESELECT and NOP are functionally interchangeable. 6. Power Down exit time (tXP) should elapse before a command other than NOP or DESELECT is issued. 7. SELF REFRESH exit time (tXSR) should elapse before a command other than NOP or DESELECT is issued. 8. The Deep Power-Down exit procedure must be followed as discussed in the Deep Power-Down section of the Functional Description. 9. The clock must toggle at least once during the tXP period. 10. The clock must toggle at least once during the tXSR time. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 21 - W94AD6KB / W94AD2KB 7.6.5 Truth Table - Current State Bank n - Command to Bank n CURRENT CS STATE RAS CAS WE COMMAND ACTION NOTES H X X X DESELECT NOP or Continue previous operation L H H H No Operation NOP or Continue previous operation L L H H ACTIVE Select and activate row L L L H AUTO REFRESH Auto refresh 10 L L L L MRS Mode register set 10 L H L H READ Select column & start read burst L H L L WRITE Select column & start write burst L L H L PRECHARGE Deactivate row in bank or banks 4 L H L H READ Select column & start new read burst 5, 6 L H L L WRITE Select column & start write burst 5, 6, 13 L L H L PRECHARGE Truncate read burst, start precharge L H H L BURST TERMINATE Burst terminate 11 L H L H READ Select column & start read burst 5, 6, 12 L H L L WRITE Select column & start new write burst 5, 6 L L H L PRECHARGE Truncate write burst, start precharge 12 Any Idle Row Active Read (Auto precharge Disabled) Write (Auto precharge Disabled) Notes: 1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or Power Down. 2. DESELECT and NOP are functionally interchangeable. 3. All states and sequences not shown are illegal or reserved. 4. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging. 5. A command other than NOP should not be issued to the same bank while a READ or WRITE burst with Auto Precharge is enabled. 6. The new Read or Write command could be Auto Precharge enabled or Auto Precharge disabled. 7. Current State Definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 8. The following states must not be interrupted by a command issued to the same bank. DESEDECT or NOP commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and this table, and according to next table. Precharging: Starts with the registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when t RCD is met. Once tRCD is met, the bank will be in the ‘row active’ state. Read with AP Enabled: Starts with the registration of the READ command with Auto Precharge enabled and ends when tRP has been met. Once tRP has been met, the bank will be in the idle state. Write with AP Enabled: Starts with registration of a WRITE command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 22 - W94AD6KB / W94AD2KB 9. The following states must not be interrupted by any executable command; DESEDECT or NOP commands must be applied to each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when t RFC is met. Once tRFC is met, the LPDDR will be in an ‘all banks idle’ state. Accessing Mode Register: starts with registration of a MODE REGISTER SET command and ends when tMRD has been met. Once tMRD is met, the LPDDR will be in an ‘all banks idle’ state. Precharging All: starts with the registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. 10. Not bank-specific; requires that all banks are idle and no bursts are in progress. 11. Not bank-specific. BURST TERMINATE affects the most recent READ burst, regardless of bank. 12. Requires appropriate DM masking. 13. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ prior to asserting a WRITE command. 7.6.6 Truth Table - Current State Bank n, Command to Bank m CURRENT STATE CS RAS CAS WE COMMAND ACTION NOTES H X X X DESELECT NOP or Continue previous Operation L H H H NOP NOP or Continue previous Operation X X X X ANY Any command allowed to bank m L L H H ACTIVE Select and activate row L H L H READ Select column & start read burst 8 L H L L WRITE Select column & start write burst 8 L L H L PRECHARGE Precharge L L H H ACTIVE Select and activate row L H L H READ Select column & start new read burst 8 L H L L WRITE Select column & start write burst 8,10 L L H L PRECHARGE Precharge L L H H ACTIVE Select and activate row L H L H READ Select column & start read burst 8, 9 L H L L WRITE Select column & start new write burst 8 L L H L PRECHARGE Precharge L L H H ACTIVE Select and activate row L H L H READ Select column & start new read burst 5, 8 L H L L WRITE Select column & start write burst 5, 8, 10 L L H L PRECHARGE Precharge L L H H ACTIVE Select and activate row L H L H READ Select column & start read burst 5, 8 L H L L WRITE Select column & start new write burst 5, 8 L L H L PRECHARGE Precharge Any Idle Row Activating, Active, or Precharging Read with Auto Precharge disabled Write with Auto Precharge disabled Read with Auto Precharge Write with Auto Precharge Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 23 - W94AD6KB / W94AD2KB Notes: 1. The table applies when both CKEn-1 and CKEn are HIGH, and after tXSR or tXP has been met if the previous state was Self Refresh or Power Down. 2. DESELECT and NOP are functionally interchangeable. 3. All states and sequences not shown are illegal or reserved. 4. Current State Definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 5. Read with AP enabled and Write with AP enabled: The read with Auto Precharge enabled or Write with Auto Precharge enabled states can be broken into two parts: the access period and the precharge period. For Read with AP, the precharge period is defined as if the same burst was executed with Auto Precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all the data in the burst. For Write with Auto precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period, of the Read with Auto Precharge enabled or Write with Auto Precharge enabled states, ACTIVE, PRECHARGE, READ, and WRITE commands to the other bank may be applied; during the access period, only ACTIVE and PRECHARGE commands to the other banks may be applied. In either case, all other related limitations apply (e.g. contention between READ data and WRITE data must be avoided). 6. AUTO REFRESH, SELF REFRESH, and MODE REGISTER SET commands may only be issued when all bank are idle. 7. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 8. READs or WRITEs listed in the Command column include READs and WRITEs with Auto Precharge enabled and READs and WRITEs with Auto Precharge disabled. 9. Requires appropriate DM masking. 10. A WRITE command may be applied after the completion of data output, otherwise a BURST TERMINATE command must be issued to end the READ prior to asserting a WRITE command. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 24 - W94AD6KB / W94AD2KB 8. OPERATION 8.1 Deselect The DESELECT function ( CS = High) prevents new commands from being executed by the LPDDR SDRAM. The LPDDR SDRAM is effectively deselected. Operations already in progress are not affected. 8.2 No Operation The NO OPERATION (NOP) command is used to perform a NOP to a LPDDR SDRAM that is selected ( CS = Low). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. 8.2.1 NOP Command CK CK CKE (High) CS RAS CAS WE Address BA0,BA1 = Don't Care Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 25 - W94AD6KB / W94AD2KB 8.3 Mode Register Set The Mode Register and the Extended Mode Register are loaded via the address inputs. The MODE REGISTER SET command can only be issued when all banks are idle and no bursts are in progress, and a subsequent executable command cannot be issued until tMRD is met. 8.3.1 Mode Register Set Command CK CK CKE (High) CS RAS CAS WE Address Code BA0,BA1 Code = Don't Care 8.3.2 Mode Register Set Command Timing CK CK Command MRS NOP Valid tMRD Address Code Valid = Don't Care NOTE: Code = Mode Register / Extended Mode Register selection (BA0, BA1) and op-code (A0-An) Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 26 - W94AD6KB / W94AD2KB 8.4 Active Before any READ or WRITE commands can be issued to a bank in the LPDDR SDRAM, a row in that bank must be opened. This is accomplished by the ACTIVE command: BA0 and BA1 select the bank, and the address inputs select the row to be activated. More than one bank can be active at any time. Once a row is open, a READ or WRITE command could be issued to that row, subject to the tRCD specification. A subsequent ACTIVE command to another row in the same bank can only be issued after the previous row has been closed. The minimum time interval between two successive ACTIVE commands on the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between two successive ACTIVE commands on different banks is defined by tRRD. The row remains active until a PRECHARGE command (or READ or WRITE command with Auto Precharge) is issued to the bank. A PRECHARGE (or READ with Auto Precharge or Write with Auto Precharge) command must be issued before opening a different row in the same bank. 8.4.1 Active Command CK CK CKE (High) CS RAS CAS WE Address BA0,BA1 RA BA = Don't Care BA = Bank Address RA = Row Address Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 27 - W94AD6KB / W94AD2KB 8.4.2 Bank Activation Command Cycle CK CK Command ACT Address Row Row Col BA0, BA1 BA x BA y BA y NOP ACT NOP tRRD NOP RD/WR NOP tRCD = Don't Care 8.5 Read The READ command is used to initiate a burst read access to an active row, with a burst length as set in the Mode Register. BA0 and BA1 select the bank, and the address inputs select the starting column location. The value of A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed will be precharged at the end of the read burst; if Auto Precharge is not selected, the row will remain open for subsequent accesses. 8.5.1 Read Command CK CK CKE (High) CS RAS CAS WE Address CA Enable AP A10 AP Disable AP BA0,BA1 BA = Don't Care BA = Bank Address CA = Column Address AP = Auto Precharge The basic Read timing parameters for DQs are shown in following figure; they apply to all Read operations. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 28 - W94AD6KB / W94AD2KB 8.5.2 Basic Read Timing Parameters tCK tCK tCH tCL CK CK tDQSCK tDQSCK tACmax tRPST tRPRE DQS tDQSQmax tAC tHZ DQ tACmin DQS DO n+1 DO n tLZ DO n+3 DO n+2 tQH tQH tDQSCK tDQSCK tRPST tRPRE tDQSQmax tHZ tAC DQ DO n tLZ tQH 1) DO n = Data Out from column n 2) All DQ are valid tAC after the CK edge. All DQ are valid tDQSQ after the DQS edge, regardless of tAC DO n+1 DO n+2 DO n+3 tQH = Don't Care During Read bursts, DQS is driven by the LPDDR SDRAM along with the output data. The initial Low state of the DQS is known as the read preamble; the Low state coincident with last data-out element is known as the read postamble. The first data-out element is edge aligned with the first rising edge of DQS and the successive data-out elements are edge aligned to successive edges of DQS. This is shown in following figure with a CAS latency of 2 and 3. Upon completion of a read burst, assuming no other READ command has been initiated, the DQs will go to High-Z. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 29 - W94AD6KB / W94AD2KB 8.5.3 Read Burst Showing CAS Latency CK CK Command Address READ NOP NOP NOP NOP NOP BA Col n CL=2 DQS DO n DQ CL=3 DQS DO n DQ = Don't Care 1) DO n = Data Out from column n 2) BA, Col n = Bank A, Column n 3) Burst Length = 4; 3 subsequent elements of Data Out appear in the programmed order following DO n 4) Shown with nominal tAC, tDQSCK and tDQSQ 8.5.4 Read to Read Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being truncated. The new READ command should be issued X cycles after the first READ command, where X equals the number of desired data-out element pairs (pairs are required by the 2n-prefetch architecture). This is shown in following figure. 8.5.5 Consecutive Read Bursts CK CK Command Address READ NOP BA,Col n READ NOP NOP NOP BA,Col b CL=2 DQS DQ DO n DO b CL=3 DQS DO n DQ DO b 1) DO n (or b) = Data Out from column n (or column b) 2) Burst Length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first) 3) Read bursts are to an active row in the bank 4) Shown with nominal tAC, tDQSCK and tDQSQ = Don't Care Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 30 - W94AD6KB / W94AD2KB 8.5.6 Non-Consecutive Read Bursts A READ command can be initiated on any clock cycle following a previous READ command. Nonconsecutive Reads are shown in following figure. CK CK Command Address READ NOP NOP BA,Col n READ NOP NOP BA,Col b CL=2 DQS DQ DO n DO b CL=3 DQS DO n DQ = Don't Care 1) DO n (or b) = Data Out from column n (or column b) 2) BA, Col n (b) = Bank A, Column n (b) 3) Burst Length = 4; 3 subsequent elements of Data Out appear in the programmed order following DO n (b) 4) Shown with nominal tAC, tDQSCK and tDQSQ Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 31 - W94AD6KB / W94AD2KB 8.5.7 Random Read Bursts Full-speed random read accesses within a page or pages can be performed as shown in following figure. CK CK Command Address READ READ READ READ NOP BA,Col n BA,Col x BA,Col b BA,Col g NOP CL=2 DQS DO n DQ DO n' DO x DO x' DO n DO n' DO b DO b' DO g DO g' DO b DO b' CL=3 DQS DQ DO x DO x' = Don't Care 1) DO n ,etc. = Data Out from column n, etc. n', x', etc. = Data Out elements, according to the programmed burst order 2) BA, Col n = Bank A, Column n 3) Burst Length = 2, 4, 8 or 16 in cases shown (if burst of 4, 8 or 16 the burst is interrupted) 4) Reads are to active rows in any banks 8.5.8 Read Burst Terminate Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in following figure. The BURST TERMINATE latency is equal to the read (CAS) latency, i.e., the BURST TERMINATE command should be issued X cycles after the READ command where X equals the desired data-out element pairs. CK CK Command Address READ BST NOP NOP NOP NOP BA,Col n CL=2 DQS DQ CL=3 DQS DQ = Don't Care 1) DO n = Data Out from column n 2) BA, Col n = Bank A, Column n 3) Cases shown are bursts of 4, 8 or 16 terminated after 2 data elements. 4) Shown with nominal tAC, tDQSCK and tDQSQ Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 32 - W94AD6KB / W94AD2KB 8.5.9 Read to Write Data from READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in following figure for the case of nominal tDQSS. CK CK Command Address READ BST NOP BA,Col n WRITE NOP NOP WRITE NOP BA,Col b tDQSS CL=2 DQS DO n DQ DM Command Address READ BST NOP NOP BA,Col n BA,Col b CL=3 DQS DO n DQ DM = Don't Care 1) DO n = Data Out from column n; DI b= Data In to column b 2) Burst length = 4, 8 or 16 in the cases shown; If the burst length is 2, the BST command can be omitted 3) Shown with nominal tAC, tDQSCK and tDQSQ Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 33 - W94AD6KB / W94AD2KB 8.5.10 Read to Precharge A Read burst may be followed by or truncated with a PRECHARGE command to the same bank (provided Auto Precharge was not activated). The PRECHARGE command should be issued X cycles after the READ command, where X equal the number of desired data-out element pairs. This is shown in following figure. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data-out elements. In the case of a Read being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from Read burst with Auto Precharge enabled. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to truncate bursts. CK CK Command Address READ NOP PRE NOP NOP Bank (a or all) BA,Col n ACT BA,Row tRP CL=2 DQS DQ DO n CL=3 DQS DQ DO n = Don't Care 1) DO n = Data Out from column n 2) Cases shown are either uninterrupted of 4, or interrupted bursts of 8 or 16 3) Shown with nominal tAC,tDQSCK and tDQSQ 4) Precharge may be applied at (BL/2) tCK after the READ command. 5) Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks. 6) The ACTIVE command may be applied if tRC has been met. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 34 - W94AD6KB / W94AD2KB 8.5.11 Burst Terminate of Read The BURST TERMINATE command is used to truncate read bursts (with Auto Precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated. Note that the BURST TERMINATE command is not bank specific. This command should not be used to terminate write bursts. CK CK CKE (High) CS RAS CAS WE A0-An BA0,BA1 = Don't Care 8.6 Write The WRITE command is used to initiate a burst write access to an active row, with a burst length as set in the Mode Register. BA0 and BA1 select the bank, and the address inputs select the starting column location. The value of A10 determines whether or not Auto Precharge is used. If Auto Precharge is selected, the row being accessed will be precharged at the end of the write burst; if Auto Precharge is not selected, the row will remain open for subsequent accesses. 8.6.1 Write Command CK CK CKE (High) CS RAS CAS WE Address CA Enable AP A10 AP Disable AP BA0,BA1 BA = Don't Care BA = Bank Address CA = Column Address AP = Auto Precharge Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 35 - W94AD6KB / W94AD2KB 8.6.2 Basic Write Timing Parameters Basic Write timing parameters for DQs are shown in below figure; they apply to all Write operations. Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered Low, the corresponding data will be written to the memory; if the DM signal is registered High, the corresponding data inputs will be ignored, and a write will not be executed to that byte / column location. tCK tCH tCL CK CK tDQSS Case 1: tDQSS = min tDSH tDQSH tDSH tWPST DQS tWPRES tWPRE tDH tDS DQ, DM Case 2: tDQSS = max tDQSL DI n tDQSH tDQSS tDSS tWPST DQS tWPRES DQ, DM tDSS tWPRE tDS tDH tDQSL DI n = Don't Care 1) DI n = Data In for column n 2) 3 subsequent elements of Data In are applied in the programmed order following DI n. 3) tDQSS: each rising edge of DQS must fall within the +/-25% window of the corresponding positive clock edge. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 36 - W94AD6KB / W94AD2KB 8.6.3 Write Burst (min. and max. tDQSS) During Write bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and the subsequent data elements will be registered on successive edges of DQS. The Low state of DQS between the WRITE command and the first rising edge is called the write preamble, and the Low state on DQS following the last data-in element is called the write postamble. The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range - from 75% to 125% of a clock cycle. Following figure shows the two extremes of tDQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQs will remain high-Z and any additional input data will be ignored. CK CK Command WRITE Address BA,Col b NOP NOP NOP NOP NOP tDQSSmin DQS DQ DI b DM tDQSSmax DQS DQ DI b DM = Don't Care 1) DI b = Data In to column b. 2) 3 subsequent elements of Data In are applied in the programmed order following DI b. 3) A non-interrupted burst of 4 is shown. 4) A10 is LOW with the WRITE command (Auto Precharge is disabled) 8.6.4 Write to Write Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data, can be maintained. The new WRITE command can be issued on any positive edge of the clock following the previous WRITE command. The first data-in element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new WRITE command should be issued X cycles after the first WRITE command, where X equals the number of desired data-in element pairs. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 37 - W94AD6KB / W94AD2KB 8.6.5 Concatenated Write Bursts An example of concatenated write bursts is shown in below figure. CK CK Command Address WRITE NOP WRITE BA,Col b NOP NOP NOP BA,Col n tDQSSmin DQS DI b DQ DI n DM tDQSSmax DQS DI b DQ DI n DM = Don't Care 1) DI b (n) = Data in to column b (column n) 2) 3 subsequent elements of Data In are applied in the programmed order following DI b. 3 subsequent elements of Data In are applied in the programmed order following DI n. 3) Non-interrupted bursts of 4 are shown. 4) Each WRITE command may be to any active bank 8.6.6 Non-Concatenated Write Bursts An example of non-concatenated write bursts is shown in below figure. CK CK Command Address WRITE NOP NOP BA,Col b WRITE NOP NOP BA,Col n tDQSSmax DQS DQ DI b DI n DM = Don't Care 1) Dl b (n) = Data in to column b (or column n) 2) 3 subsequent elements of Data In are applied in the programmed order following DI b. 3 subsequent elements of Data In are applied in the programmed order following DI n. 3) Non-interrupted bursts of 4 are shown. 4) Each WRITE command may be to any active bank and may be to the same or different devices. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 38 - W94AD6KB / W94AD2KB 8.6.7 Random Write Cycles Full-speed random write accesses within a page or pages can be performed as shown in below figure. CK CK Command Address WRITE WRITE WRITE WRITE WRITE BA,Col b BA,Col x BA,Col n BA,Col a BA,Col g NOP tDQSSmax DQS DQ DI b DI b' DI x DI x' DI n DI n' DI a DI a' DM = Don't Care 1) Dl b etc. = Data in to column b, etc.; b', etc. = the next Data In following Dl b, etc. according to the programmed burst order 2) Programmed burst length = 2, 4, 8 or 16 in cases shown. If burst of 4, 8 or 16, burst would be truncated 3) Each WRITE command may be to any active bank and may be to the same or different devices. 8.6.8 Write to Read Data for any Write burst may be followed by a subsequent READ command. 8.6.9 Non-Interrupting Write to Read To follow a Write without truncating the write burst, tWTR should be met as shown in the figure below. CK CK Command WRITE Address BA,Col b NOP NOP NOP READ NOP NOP BA,Col n tDQSSmax tWTR CL=3 DQS DQ DI b DM = Don't Care 1) Dl b = Data in to column b 3 subsequent elements of Data In are applied in the programmed order following DI b. 2) A non-interrupted burst of 4 is shown. 3) tWTR is referenced from the positive clock edge after the last Data In pair. 4) A10 is LOW with the WRITE command (Auto Precharge is disabled) 5) The READ and WRITE commands are to the same device but not necessarily to the same bank. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 39 - W94AD6KB / W94AD2KB 8.6.10 Interrupting Write to Read Data for any Write burst may be truncated by a subsequent READ command as shown in the figure below. Note that the only data-in pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in must be masked with DM. CK CK Command WRITE NOP NOP READ BA,Col b Address NOP NOP NOP BA,Col n tDQSSmax tWTR CL=3 DQS DO n DI b DQ DM = Don't Care 1) Dl b = Data in to column b. DO n = Data out from column n. 2) An interrupted burst of 4 is shown, 2 data elements are written. 3 subsequent elements of Data In are applied in the programmed order following DI b. 3) tWTR is referenced from the positive clock edge after the last Data In pair. 4) A10 is LOW with the WRITE command (Auto Precharge is disabled) 5) The READ and WRITE commands are to the same device but not necessarily to the same bank. 8.6.11 Write to Precharge Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto Precharge was not activated). To follow a WRITE without truncating the WRITE burst, tWR should be met as shown in the figure below. 8.6.12 Non-Interrupting Write to Precharge CK CK Command Address WRITE NOP NOP NOP NOP BA,Col b PRE BA a (or all) tDQSSmax tWR DQS DQ DI b DM = Don't Care 1) Dl b = Data in to column b 3 subsequent elements of Data In are applied in the programmed order following DI b. 2) A non-interrupted burst of 4 is shown. 3) tWR is referenced from the positive clock edge after the last Data In pair. 4) A10 is LOW with the WRITE command (Auto Precharge is disabled) Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 40 - W94AD6KB / W94AD2KB 8.6.13 Interrupting Write to Precharge Data for any WRITE burst may be truncated by a subsequent PRECHARGE command as shown in below figure. Note that only data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data-in should be masked with DM, as shown in below figure. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. CK CK Command Address WRITE NOP NOP NOP PRE BA,Col b BA a (or all) tWR tDQSSmax *2 DQS DQ NOP DI b DM *1 *1 *1 *1 = Don't Care 1) Dl b = Data in to column b. 2) An interrupted burst of 4, 8 or 16 is shown, 2 data elements are written. 3) tWR is referenced from the positive clock edge after the last desired Data In pair. 4) A10 is LOW with the WRITE command (Auto Precharge is disabled) 5) *1 = can be Don't Care for programmed burst length of 4 6) *2 = for programmed burst length of 4, DQS becomes Don't Care at this point 8.7 Precharge The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged. In case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care”. Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE command being issued. A PRECHARGE command will be treated as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 41 - W94AD6KB / W94AD2KB 8.7.1 Precharge Command CK CK CKE (High) CS RAS CAS WE Address All Banks A10 One Bank BA0,BA1 BA = Don't Care BA = Bank Address (if A10 = L, otherwise Don't Care) 8.8 Auto Precharge Auto Precharge is a feature which performs the same individual bank precharge function as described above, but without requiring an explicit command. This is accomplished by using A10 (A10 = High), to enable Auto Precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the read or write burst. Auto Precharge is non persistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto Precharge ensures that a precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharing time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation section of this specification. 8.9 Refresh Requirements LPDDR SDRAM devices require a refresh of all rows in any rolling 64mS interval. Each refresh is generated in one of two ways: by an explicit AUTO REFRESH command, or by an internally timed event in SELF REFRESH mode. Dividing the number of device rows into the rolling 64mS interval defines the average refresh interval (tREFI), which is a guideline to controllers for distributed refresh timing. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 42 - W94AD6KB / W94AD2KB 8.10 Auto Refresh AUTO REFRESH command is used during normal operation of the LPDDR SDRAM. This command is non persistent, so it must be issued each time a refresh is required. The refresh addressing is generated by the internal refresh controller. The LPDDR SDRAM requires AUTO REFRESH commands at an average periodic interval of tREFI. 8.10.1 Auto Refresh Command CK CK CKE (High) CS RAS CAS WE A0-An BA0,BA1 = Don't Care 8.10.2 Auto Refresh Cycles Back-to-Back An Auto Refresh cycle timing diagram is shown in below. CK CK tRP Command PRE NOP tRFC ARF NOP NOP DQ ARF NOP NOP ACT Ba,A Row n Address A10 (AP) tRFC Pre All Row n High-z = Don't Care Ba A, Row n = Bank A, Row n Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 43 - W94AD6KB / W94AD2KB 8.11 Self Refresh The SELF REFRESH command can be used to retain data in the LPDDR SDRAM, even if the rest of the system is powered down. When in the Self Refresh mode, the LPDDR SDRAM retains data without external clocking. The LPDDR SDRAM device has a built-in timer to accommodate Self Refresh operation. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is LOW. Input signals except CKE are “Don’t Care” during Self Refresh. The user may halt the external clock one clock after the SELF REFRESH command is registered. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. The clock is internally disabled during Self Refresh operation to save power. The minimum time that the device must remain in Self Refresh mode is tRFC. The procedure for exiting Self Refresh requires a sequence of commands. First, the clock must be stable prior to CKE going back High. Once Self Refresh Exit is registered, a delay of at least t XSR must be satisfied before a valid command can be issued to the device to allow for completion of any internal refresh in progress. The use of Self Refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from Self Refresh mode. Upon exit from Self Refresh an extra AUTO REFRESH command is recommended. In the Self Refresh mode, Partial Array Self Refresh (PASR) function is described in the Extended Mode Register section. 8.11.1 Self Refresh Command CK CK CKE CS RAS CAS WE A0-An BA0,BA1 = Don't Care Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 44 - W94AD6KB / W94AD2KB 8.11.2 Self Refresh Entry and Exit A Self Refresh entry and exit timing diagram is shown in below. CK CK tXSR >tRFC tRP tRFC CKE Command NOP PRE ARF NOP NOP ARF DQ ACT Ba A, Row n Address A10 (AP) NOP Row n Pre All High-z = Don't Care Enter Self Refresh Mode Exit from Self Refresh Mode Any Command (Auto Refresh Recommened) Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 45 - W94AD6KB / W94AD2KB 8.12 Power Down Power-down is entered when CKE is registered Low (no accesses can be in progress). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE. In power-down mode, CKE Low must be maintained, and all other input signals are “Don’t Care”. The minimum power-down duration is specified by tCKE. However, power-down duration is limited by the refresh requirements of the device. The power-down state is synchronously exited when CKE is registered High (along with a NOP or DESELECT command). A valid command may be applied tXP after exit from power-down. For Clock Stop during Power-Down mode, please refer to the Clock Stop subsection in this specification. 8.12.1 Power-Down Entry and Exit CK CK tRP tXP tCKE CKE Command PRE NOP NOP NOP Address A10 (AP) DQ NOP NOP Valid Valid Valid Pre All High-z Power Down Entry Exit from Power Down Precharge Power-Down mode shown; all banks are idle and tRP is met when Power-down Entry command is issued Any Command = Don't Care Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 46 - W94AD6KB / W94AD2KB 8.13 Deep Power Down The Deep Power-Down (DPD) mode enables very low standby currents. All internal voltage generators inside the LPDDR SDRAM are stopped and all memory data is lost in this mode. All the information in the Mode Register and the Extended Mode Register is lost. Deep Power-Down is entered using the BURST TERMINATE command except that CKE is registered Low. All banks must be in idle state with no activity on the data bus prior to entering the DPD mode. While in this state, CKE must be held in a constant Low state. To exit the DPD mode, CKE is taken high after the clock is stable and NOP commands must be maintained for at least 200μs. After 200μs a complete re-initialization is required following steps 4 through 11 as defined for the initialization sequence. 8.13.1 Deep Power-Down Entry and Exit T0 T1 Ta0 NOP DPD Ta1 Ta2 NOP Valid CK CK CKE Command Address Valid DQS DQ DM tRP T = 200 µs Enter DPD Mode Exit DPD Mode = Don't Care 1) Clock must be stable before exiting Deep Power-Down mode. That is, the clock must be cycling within specifications by Ta0 2) Device must be in the all banks idle state prior to entering Deep Power-Down mode 3) 200µs is required before any command can be applied upon exiting Deep Power-Down mode 4) Upon exiting Deep Power-Down mode a PRECHARGE ALL command must be issued, followed by two AUTO REFRESH commands and a load mode register sequence Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 47 - W94AD6KB / W94AD2KB 8.14 Clock Stop Stopping a clock during idle periods is an effective method of reducing power consumption. The LPDDR SDRAM supports clock stop under the following conditions:  the last command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has executed to completion, including any data-out during read bursts; the number of clock pulses per access command depends on the device’s AC timing parameters and the clock frequency;  the related timing conditions (tRCD, tWR, tRP, tRFC, tMRD) has been met;  CKE is held High When all conditions have been met, the device is either in “idle state” or “row active state” and clock stop mode may be entered with CK held Low and CK held High. Clock stop mode is exited by restarting the clock. At least one NOP command has to be issued before the next access command may be applied. Additional clock pulses might be required depending on the system characteristics. The following Figure shows clock stop mode entry and exit  Initially the device is in clock stop mode  The clock is restarted with the rising edge of T0 and a NOP on the command inputs  With T1 a valid access command is latched; this command is followed by NOP commands in order to allow for clock stop as soon as this access command is completed  Tn is the last clock pulse required by the access command latched with T1  The clock can be stopped after Tn 8.14.1 Clock Stop Mode Entry and Exit T0 T1 T2 Tn CK CK CKE Timing Condition NOP Command CMD NOP NOP NOP Valid Address (High-Z) DQ, DQS Clock Stopped Exit Clock Stop Mode Valid Command Enter Clock Stop Mode = Don't Care Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 48 - W94AD6KB / W94AD2KB 9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETER SYMBOL VALUES UNITS MIN. MAX. VDD -0.5 2.3 V VDDQ -0.5 2.3 V VIN, VOUT -0.5 2.3 V Operating Temperature (for 5E/6E grades) TCASE -25 85 °C Operating Temperature (for 5I/6I grades) TCASE -40 85 °C Storage Temperature TSTG -55 150 °C Short Circuit Output Current IOUT ±50 mA PD 1.0 W Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Voltage on any pin relative to VSS Power Dissipation Note: Stresses greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 9.2 Input / Output Capacitance PARAMETER SYMBOL MIN. MAX. UNITS Input Capacitance CK, CK CCK 1.5 3.0 pF Input Capacitance delta CK, CK CDCK 0.25 pF 3.0 pF 0.5 pF 5.0 pF 3 0.5 pF 3 Input capacitance, all other input-only pins CI Input capacitance delta, all other input-only pins CDI Input/ output capacitance, DQ,DM,DQS CIO Input/output capacitance delta, DQ, DM, DQS CDIO 1.5 3.0 NOTES Notes 1. These values are guaranteed by design and are tested on a sample base only. 2. These capacitance values are for single monolithic devices only. Multiple die packages will have parallel capacitive loads. 3. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is required to match signal propagation times of DQ, DQS and DM in the system. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 49 - W94AD6KB / W94AD2KB 9.3 Electrical Characteristics and AC/DC Operating Conditions All values are recommended operating conditions unless otherwise noted. 9.3.1 Electrical Characteristics and AC/DC Operating Conditions PARAMETER/CONDITION Supply Voltage I/O Supply Voltage SYMBOL MIN. MAX. UNIT NOTES VDD 1.70 1.95 V - VDDQ 1.70 1.95 V - Address and Command Inputs (A0~An, BA0, BA1, CKE, CS , RAS , CAS , WE ) Input High Voltage VIH 0.8 * VDDQ VDDQ + 0.3 V - Input Low Voltage VIL -0.3 0.2 * VDDQ V - VIN -0.3 VDDQ + 0.3 V - DC Input Differential Voltage VID(DC) 0.4 * VDDQ VDDQ + 0.6 V 2 AC Input Differential Voltage VID(AC) 0.6 * VDDQ VDDQ + 0.6 V 2 VIX 0.4 * VDDQ 0.6 x VDDQ V 3 DC Input High Voltage VIHD(DC) 0.7 * VDDQ VDDQ + 0.3 V - DC Input Low Voltage VILD(DC) -0.3 0.3 x VDDQ V - AC Input High Voltage VIHD(AC) 0.8 * VDDQ VDDQ + 0.3 V - AC Input Low Voltage VILD(AC) -0.3 0.2 * VDDQ V - DC Output High Voltage (IOH = -0.1mA) VOH 0.9 * VDDQ - V - DC Output Low Voltage (IOL = 0.1mA) VOL - 0.1 * VDDQ V - Input Leakage Current IiL -1 1 µA 4 Output Leakage Current IoL -5 5 µA 5 Clock Inputs (CK, CK ) DC Input Voltage AC Differential Cross Point Voltage Data Inputs (DQ, DM, DQS) Data Outputs (DQ, DQS) Leakage Current Notes 1. All voltages referenced to VSS and VSSQ must be same potential. 2. VID(DC) and VID(AC) are the magnitude of the difference between the input level on CK and the input level on CK . 3. The value of VIX is expected to be 0.5 * VDDQ and must track variations in the DC level of the same. 4. Any input 0V ≤ VIN ≤ VDD. All other pins are not tested under VIN = 0V. 5. Any output 0V ≤ VOUT ≤ VDDQ. DOUT is disabled. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 50 - W94AD6KB / W94AD2KB 9.4 DC Characteristics 9.4.1 IDD Specification and Test Conditions (x16) [Recommended Operating Conditions; Note 1-4] PARAMETER SYMBOL TEST CONDITION -5 -6 UNIT Operating one bank active-precharge current IDD0 tRC = tRCmin; tCK = tCKmin; CKE is HIGH; CS is HIGH between valid commands; address inputs are SWITCHING; data bus inputs are STABLE 70 60 mA Precharge power-down standby current IDD2P all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE 0.6 0.6 mA Precharge power-down standby current with clock stop IDD2PS 0.6 0.6 mA Precharge non powerdown standby current IDD2N 15 15 mA 8 8 mA 3.6 3.6 mA 3.6 3.6 mA 15 15 mA 8 8 mA 115 105 mA 115 105 mA 95 95 mA 10 10 µA all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE all banks idle, CKE is HIGH; CS is HIGH, CK Precharge non powerdown standby current with clock stop IDD2NS Active power-down standby current IDD3P Active power-down standby current with clock stop IDD3PS Active non power-down standby current IDD3N = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active, CKE is HIGH; CS is HIGH, Active non power-down standby current with clock stop IDD3NS Operating burst read current IDD4R Operating burst write current IDD4W Auto-Refresh Current IDD5 Deep Power-Down current IDD8*4 CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active; BL = 4; CL = 3; tCK = tCKmin; continuous read bursts; IOUT = 0 mA; address inputs are SWITCHING; 50% data change each burst transfer one bank active; BL = 4; tCK = tCKmin; continuous write bursts; address inputs are SWITCHING; 50% data change each burst transfer tRC = tRFCmin; tCK = tCKmin ; burst refresh; CKE is HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE Address and control inputs are STABLE; data bus inputs are STABLE Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 51 - W94AD6KB / W94AD2KB 9.4.2 IDD Specification and Test Conditions (x32) [Recommended Operating Conditions; Note 1-4] PARAMETER SYMBOL TEST CONDITION -5 -6 UNIT Operating one bank active-precharge current IDD0 tRC = tRCmin; tCK = tCKmin; CKE is HIGH; CS is HIGH between valid commands; address inputs are SWITCHING; data bus inputs are STABLE 70 60 mA Precharge power-down standby current IDD2P all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE 0.6 0.6 mA Precharge power-down standby current with clock stop IDD2PS 0.6 0.6 mA Precharge non powerdown standby current IDD2N 15 15 mA 8 8 mA 3.6 3.6 mA 3.6 3.6 mA 15 15 mA 8 8 mA 115 105 mA 115 105 mA 95 95 mA 10 10 µA all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE all banks idle, CKE is HIGH; CS is HIGH, CK Precharge non powerdown standby current with clock stop IDD2NS Active power-down standby current IDD3P Active power-down standby current with clock stop IDD3PS Active non power-down standby current IDD3N = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active, CKE is HIGH; CS is HIGH, Active non power-down standby current with clock stop IDD3NS Operating burst read current IDD4R Operating burst write current IDD4W Auto-Refresh Current IDD5 Deep Power-Down current IDD8*4 CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE one bank active; BL = 4; CL = 3; tCK = tCKmin; continuous read bursts; IOUT = 0 mA; address inputs are SWITCHING; 50% data change each burst transfer one bank active; BL = 4; tCK = tCKmin; continuous write bursts; address inputs are SWITCHING; 50% data change each burst transfer tRC = tRFCmin; tCK = tCKmin ; burst refresh; CKE is HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE Address and control inputs are STABLE; data bus inputs are STABLE Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 52 - W94AD6KB / W94AD2KB IDD6 Conditions: PARAMETER Self Refresh Current SYM. IDD6 TEST CONDITION CKE is LOW; CK = LOW, CK = HIGH; Extended Mode Register set to all 0’s; Address and control inputs are STABLE; Data bus inputs are STABLE PASR RANGE 45°C 85°C UNIT Full array 750 1300 µA 1/2 array 600 1050 µA 1/4 array 500 900 µA Notes: 1. IDD specifications are tested after the device is properly initialized. 2. Input slew rate is 1V/ns. 3. Definitions for IDD: LOW is defined as VIN ≤ 0.1 * VDDQ; HIGH is defined as VIN ≥ 0.9 * VDDQ; STABLE is defined as inputs stable at a HIGH or LOW level; SWITCHING is defined as: - Address and command: inputs changing between HIGH and LOW once per two clock cycles; - Data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE. 4. IDD8 is typical values at 25°C. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 53 - W94AD6KB / W94AD2KB 9.5 AC Characteristics and Operating Condition [Recommended Operating Conditions: Notes 1-9] PARAMETER CL = 3 DQ Output Access Time from CK, CK CL = 2 CL = 3 DQS Output Access Time from CK, CK -5 SYM. CL = 2 tAC tDQSCK -6 MIN. MAX. MIN. MAX. 2.0 5.0 2.0 5.0 2.0 6.5 2.0 6.5 2.0 5.0 2.0 5.0 2.0 6.5 2.0 6.5 UNIT nS nS Clock high-level width tCH 0.45 0.55 0.45 0.55 tCK Clock low-level width tCL 0.45 0.55 0.45 0.55 tCK tHP Min. (tCL,tCH) Clock half period Clock cycle time DQ and DM input setup time DQ and DM input hold time CL = 3 Address and control input hold time Min. (tCL,tCH) nS 10,11 5 6 nS 12 12 12 nS 12 0.48 0.6 nS 13,14,15 slow 0.58 0.7 nS 13,14,16 fast 0.48 0.6 nS 13,14,15 0.58 0.7 nS 13,14,16 1.4 1.6 nS 17 0.9 1.1 nS 15,18 1.1 1.3 nS 16,18 0.9 1.1 nS 15,18 1.1 1.3 nS 16,18 tIPW 2.3 2.6 nS 17 tLZ 1.0 1.0 nS 19 CL = 2 fast slow DQ and DM input pulse width Address and control input setup time tCK tDS tDH tDIPW fast slow fast slow Address and control input pulse width Data-out Low-impedance Time from CK, CK Data-out High-impedance Time from CK, CL = 3 CK CL = 2 DQS-DQ skew tIS tIH tHZ tDQSQ DQ/DQS output hold time from DQS tQH 5.0 5.0 6.5 6.5 0.4 tHP tQHS 0.5 tHP tQHS 20 nS 11 11 tQHS 065 nS tDQSS 0.75 1.25 0.75 1.25 tCK DQS input high-level width tDQSH 0.4 0.6 0.4 0.6 tCK DQS input low-level width tDQSL 0.4 0.6 0.4 0.6 tCK DQS falling edge to CK setup time tDSS 0.2 0.2 tCK DQS falling edge hold time from CK tDSH 0.2 0.2 tCK tCK tMRD 2 2 tWPRES 0 0 Write postamble tWPST 0.4 Write preamble tWPRE 0.25 Write preamble setup time CL = 3 CL = 2 tRPRE 0.6 0.4 0.6 0.25 19 nS Write command to 1st DQS latching transition MODE REGISTER SET command period 0.5 nS Data hold skew factor Read preamble NOTES nS 21 tCK 22 tCK 0.9 1.1 0.9 1.1 tCK 23 0.5 1.1 0.5 1.1 tCK 23 0.4 0.6 0.4 0.6 tCK 70,000 42 70,000 nS Read postamble tRPST ACTIVE to PRECHARGE command period tRAS 40 ACTIVE to ACTIVE command period tRC tRAS + tRP tRAS + tRP nS AUTO REFRESH to ACTIVE/AUTO REFRESH command period tRFC 72 72 nS Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 54 - W94AD6KB / W94AD2KB -5 -6 PARAMETER SYM. ACTIVE to READ or WRITE delay tRCD 15 18 nS tRP 3 3 tCK ACTIVE bank A to ACTIVE bank B delay tRRD 10 12 nS WRITE recovery time tWR 15 15 nS 24 Auto precharge write recovery + precharge time tDAL - - tCK 25 Internal write to Read command delay tWTR 1 1 tCK Self Refresh exit to next valid command delay tXSR 120 120 nS 26 Exit power down to next valid command delay tXP 2 1 tCK 27 tCKE 1 1 tCK PRECHARGE command period CKE min. pulse width (high and low pulse width) MIN. MAX. MIN. MAX. UNIT Refresh Period tREF 64 64 mS Average periodic refresh interval tREFI 7.8 7.8 μS MRS for SRR to READ tSRR 2 2 tCK READ of SRR to next valid command tSRC CL+1 CL+1 tCK NOTES 28,29 Notes: 1. All voltages referenced to VSS. 2. All parameters assume proper device initialization. 3. Tests for AC timing may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage and temperature range specified. 4. The circuit shown below represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). For the half strength driver with a nominal 10pF load parameters t AC and tQH are expected to be in the same range. However, these parameters are not subject to production test but are estimated by design / characterization. Use of IBIS or other simulation tools for system design validation is suggested. Full Drive Strength Half Drive Strength I/O I/O Z0 = 50 Ohms 20 pF Z0 = 50 Ohms 10 pF Time Reference Load 5. The CK/ CK input reference voltage level (for timing referenced to CK/ CK ) is the point at which CK and CK cross; the input reference voltage level for signals other than CK/ CK is VDDQ/2. 6. The timing reference voltage level is VDDQ/2. 7. AC and DC input and output voltage levels are defined in the section for Electrical Characteristics and AC/DC operating conditions. 8. A CK/ CK differential slew rate of 2.0 V/nS is assumed for all parameters. 9. CAS Latency definition: with CL = 3 the first data element is valid at (2 * tCK + tAC) after the clock at which the READ command was registered; with CL = 2 the first data element is valid at (tCK + tAC) after the clock at which the READ command was registered. 10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits of tCL and tCH) 11. tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH). tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 55 - W94AD6KB / W94AD2KB 12. The only time that the clock frequency is allowed to change is during clock stop, power-down or self-refresh modes. 13. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input signals, and VIH(DC) to VIL(AC) for falling input signals. 14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. 15. Input slew rate ≥ 1.0 V/nS. 16. Input slew rate ≥ 0.5 V/nS and < 1.0 V/nS. 17. These parameters guarantee device timing but they are not necessarily tested on each device. 18. The transition time for address and command inputs is measured between VIH and VIL. 19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 20. tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 21. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before the corresponding CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t DQSS. 22. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 23. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the system. It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled). 24. At least one clock cycle is required during tWR time when in auto precharge mode. 25. tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms, if not already an integer, round to the next higher integer. 26. There must be at least two clock pulses during the tXSR period. 27. There must be at least one clock pulse during the tXP period. 28. tREFI values are dependent on density and bus width. 29. A maximum of 8 Refresh commands can be posted to any given LPDDR, meaning that the maximum absolute interval between any Refresh command and the next Refresh command is 8*tREFI. 9.5.1 CAS Latency Definition (With CL = 3) T0 T1 T2 READ NOP NOP T2n T3 T3n T4 T4n T5 T5n T6 CK CK Command NOP NOP NOP NOP CL=3 tRPST tDQSCKmin tDQSCKmin tRPRE DQS tLZmin All DQ, collectively T2 T2n T3 T3n T4 T4n T5 T5n tLZmin 1) DQ transitioning after DQS transition define tDQSQ window. 2) ALL DQ must transition by tDQSQ after DQS transitions, regardless of tAC 3) tAC is the DQ output window relative to CK,and is the long term component of DQ skew. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 56 - W94AD6KB / W94AD2KB 9.5.2 Output Slew Rate Characteristics PARAMETER MIN MAX UNIT NOTES Pull-up and Pull-Down Slew Rate for Full Strength Driver 0.7 2.5 V/nS 1,2 Pull-up and Pull-Down Slew Rate for Three-Quarter Strength Driver 0.5 1.75 V/nS 1,2 Pull-up and Pull-Down Slew Rate for Half Strength Driver 0.3 1.0 V/nS 1,2 Output Slew rate Matching ratio (Pull-up to Pull-down) 0.7 1.4 - 3 Notes: 1. Measured with a test load of 20 pF connected to VSSQ. 2. Output slew rate for rising edge is measured between VILD(DC) to VIHD(AC) and for falling edge between VIHD(DC) to VILD(AC). 3. The ratio of pull-up slew rate to pull-down slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 9.5.3 AC Overshoot/Undershoot Specification PARAMETER SPECIFICATION Maximum peak amplitude allowed for overshoot 0.5 V Maximum peak amplitude allowed for undershoot 0.5 V The area between overshoot signal and VDD must be less than or equal to 3 V-nS The area between undershoot signal and GND must be less than or equal to 3 V-nS AC Overshoot and Undershoot Definition 2.5 Overshoot Area 2.0 VDD 1.5 Voltage (V) 9.5.4 1.0 Max Amplitude = 0.5V Max Area = 3V-nS 0.5 VSS 0 -0.5 Undershoot Area Time (nS) Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 57 - W94AD6KB / W94AD2KB 10. PACKAGE DIMENSIONS 10.1 LPDDR x16 Package Outline VFBGA 60 Balls (8x9 mm2, Ball pitch: 0.8mm, Ø =0.42mm) –A– D1 aaa D PIN #1 e –B– K J H G E E1 F E D C Φb B A 2 1 2 3 4 5 6 7 8 aaa 9 CAVITY MIN NOM MAX MIN NOM MAX A --- --- 1.025 --- --- 0.040 A1 0.270 0.320 0.370 0.011 0.013 0.015 D 7.90 8.00 8.10 0.311 0.315 0.319 E 8.90 9.00 9.10 0.350 0.354 0.358 D1 --- 6.40 --- --- 0.252 ----- E1 --- 7.20 --- --- 0.283 e --- 0.80 --- --- 0.031 --- b 0.40 0.45 0.50 0.016 0.018 0.020 aaa 0.15 0.006 bbb 0.20 0.008 ccc 0.12 0.005 A1 Symbol Dimension in inch A // Dimension in mm bbb C –C– SOLDER BALL ccc SEATING PLANE C BALL LAND 1 BALL OPENING Note: 1. Ball land : 0.5mm. Ball opening : 0.4mm. PCB Ball land suggested ≤ 0.4mm 2. Dimensions apply to Solder Balls Post-Reflow. The Pre-Reflow diameter is 0.42 on a 0.4 SMD Ball Pad Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 58 - W94AD6KB / W94AD2KB 10.2 LPDDR x32 Package Outline VFBGA 90 Balls (8x13 mm2, Ball pitch: 0.8mm, Ø =0.42mm) –A– D1 aaa D PIN #1 e –B– R P N M L K E E1 J H G F E D C Φb B A 2 1 2 3 4 5 6 7 8 aaa 9 CAVITY MIN NOM MAX MIN NOM MAX A --- --- 1.025 --- --- 0.040 A1 0.270 0.320 0.370 0.011 0.013 0.015 D 7.90 8.00 8.10 0.311 0.315 0.319 E 12.90 13.00 13.10 0.508 0.512 0.516 D1 --- 6.40 --- --- 0.252 --- E1 --- 11.20 --- --- 0.441 --- e --- 0.80 --- --- 0.031 --- b 0.40 0.45 0.50 0.016 0.018 0.020 aaa 0.15 0.006 bbb 0.20 0.008 ccc 0.12 0.005 bbb C A1 Symbol Dimension in inch A // Dimension in mm –C– SOLDER BALL SEATING PLANE ccc C BALL LAND 1 BALL OPENING Note: 1. Ball land : 0.5mm. Ball opening : 0.4mm. PCB Ball land suggested ≤ 0.4mm 2. Dimensions apply to Solder Balls Post-Reflow. The Pre-Reflow diameter is 0.42 on a 0.4 SMD Ball Pad Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 59 - W94AD6KB / W94AD2KB 11. REVISION HISTORY VERSION DATE PAGE DESCRIPTION P01-001 Dec. 19, 2012 All P01-002 Mar. 25, 2013 50, 51 A01-001 Jul. 01, 2013 All 52 Remove text "Preliminary" & release to active version Add PASR value A01-002 Jul. 30, 2013 2 Add 166MHz ordering information A01-003 Nov. 27, 2013 8 Remove Reduce page A01-004 Jul. 21, 2014 All 6 58 59 Refine format Update section 4.2 LPDDR x32 ball assignment figure Update symbol A1 spec of VFBGA 60 balls package Update symbol A1 spec of VFBGA 90 balls package A01-005 Oct. 02, 2014 58 Revise symbol E1 spec typo of VFBGA 60 balls package First preliminary release Update IDD3P & IDD3PS value Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. Publication Release Date: Oct. 02, 2014 Revision: A01-005 - 60 -