W9864G2GH-6C

W9864G2GH 512K X 4 BANKS X 32BITS SDRAM Table of Contents1. 2. 3. 4. 5. 6. 7. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 AVAILABLE PART NUMBER...................................................................................................... 4 PIN CONFIGURATION ............................................................................................................... 5 PIN DESCRIPTION..................................................................................................................... 6 BLOCK DIAGRAM ...................................................................................................................... 7 FUNCTIONAL DESCRIPTION.................................................................................................... 8 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 8. 9. 8.1 9.1 Power Up and Initialization ............................................................................................. 8 Programming Mode Register.......................................................................................... 8 Bank Activate Command ................................................................................................ 8 Read and Write Access Modes ...................................................................................... 8 Burst Read Command .................................................................................................... 9 Burst Command .............................................................................................................. 9 Read Interrupted by a Read ........................................................................................... 9 Read Interrupted by a Write............................................................................................ 9 Write Interrupted by a Write............................................................................................ 9 Write Interrupted by a Read............................................................................................ 9 Burst Stop Command ................................................................................................... 10 Addressing Sequence of Sequential Mode .................................................................. 10 Addressing Sequence of Interleave Mode.................................................................... 10 Auto-precharge Command ........................................................................................... 11 Precharge Command.................................................................................................... 11 Self Refresh Command ................................................................................................ 11 Power Down Mode ....................................................................................................... 12 No Operation Command............................................................................................... 12 Deselect Command ...................................................................................................... 12 Clock Suspend Mode.................................................................................................... 12 Simplified Stated Diagram ............................................................................................ 14 Absolute Maximum Ratings .......................................................................................... 15 OPERATION MODE ................................................................................................................. 13 ELECTRICAL CHARACTERISTICS......................................................................................... 15 -1- Publication Release Date:Aug. 13, 2007 Revision A09 W9864G2GH 9.2 9.3 9.4 9.5 10. 10.1 10.2 10.3 10.4 10.5 11. 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15 11.16 11.17 11.18 11.19 11.20 11.21 11.22 12. 13. 12.1 Recommended DC Operating Conditions .................................................................... 15 Capacitance .................................................................................................................. 16 DC Characteristics ........................................................................................................ 16 AC Characteristics and Operating Condition................................................................ 17 Command Input Timing ................................................................................................ 20 Read Timing.................................................................................................................. 21 Control Timing of Input Data......................................................................................... 22 Control Timing of Output Data ...................................................................................... 23 Mode Register Set Cycle .............................................................................................. 24 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 25 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)........... 26 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 27 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)........... 28 Interleaved Bank Write (Burst Length = 8) ................................................................... 29 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 30 Page Mode Read (Burst Length = 4, CAS Latency = 3)............................................... 31 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) ..................................... 32 Auto-precharge Read (Burst Length = 4, CAS Latency = 3) ........................................ 33 Auto-precharge Write (Burst Length = 4) .................................................................... 34 Auto Refresh Cycle ..................................................................................................... 35 Self Refresh Cycle....................................................................................................... 36 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)............................. 37 Power Down Mode ...................................................................................................... 38 Auto-precharge Timing (Write Cycle).......................................................................... 39 Auto-precharge Timing (Read Cycle).......................................................................... 40 Timing Chart of Read to Write Cycle........................................................................... 41 Timing Chart of Write to Read Cycle........................................................................... 41 Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 42 Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 42 CKE/DQM Input Timing (Write Cycle) ......................................................................... 43 CKE/DQM Input Timing (Read Cycle)......................................................................... 44 86L TSOP (II)-400 mil................................................................................................... 45 TIMING WAVEFORMS ............................................................................................................. 20 OPERATING TIMING EXAMPLE ............................................................................................. 25 PACKAGE SPECIFICATION .................................................................................................... 45 REVISION HISTORY ................................................................................................................ 46 Publication Release Date:Aug. 13, 2007 Revision A09 -2- W9864G2GH 512K X 4 BANKS X 32BITS SDRAM 1. GENERAL DESCRIPTION W9864G2GH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 512K words × 4 banks × 32 bits. Using pipelined architecture and 0.11 µm process technology, W9864G2GH delivers a data bandwidth of up to 800M bytes per second. For different application, W9864G2GH is sorted into the following speed grades:-5,-6/-6C/-6I,-7.The -5 parts can run up to 200MHz/CL3.The -6/-6C/-6I parts can run up to 166 MHz/CL3. And the grade of –6C with tCK=7.5nS on CL=2, tIH=0.8nS on CL=2/3.And the -6I grade which is guaranteed to support -40°C ~ 85°C.The -7 parts can run up to 143 MHz/CL3. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9864G2GH is ideal for main memory in high performance applications. 2. FEATURES • • • • • • • • • • • • • 3.3V± 0.3V for -5/-6/-6C/-6I grade power supply 2.7V～3.6V for -7 grade power supply 524,288 words × 4 banks × 32 bits organization Self Refresh Current: Standard and Low Power CAS Latency: 2 & 3 Burst Length: 1, 2, 4, 8 and full page Sequential and Interleave Burst Byte data controlled by DQM0-3 Auto-precharge and controlled precharge Burst read, single write operation 4K refresh cycles/64 mS Interface: LVTTL Packaged in TSOP II 86-pin, 400 mil W9864G2GH is using Lead free materials -3- Publication Release Date:Aug. 13, 2007 Revision A09 W9864G2GH 3. AVAILABLE PART NUMBER PART NUMBER SPEED (CL=3) SELF REFRESH CURRENT (MAX.) OPERATING TEMPERATURE W9864G2GH-5 W9864G2GH-6/-6C W9864G2GH-6I W9864G2GH-7 200 MHz 166 MHz 166 MHz 143 MHz 2mA 2mA 2mA 2mA 0°C ~ 70°C 0°C ~ 70°C -40°C ~ 85°C 0°C ~ 70°C -4- Publication Release Date:Aug. 13, 2007 Revision A09 W9864G2GH 4. PIN CONFIGURATION VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 NC VCC DQM0 WE CAS RAS CS NC BS0 BS1 A10/AP A0 A1 A2 DQM2 VCC NC DQ16 VSSQ DQ17 DQ18 VCCQ DQ19 DQ20 VSSQ DQ21 DQ22 VCCQ DQ23 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 Vss DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC DQ31 VCCQ DQ30 DQ29 VSSQ DQ28 DQ27 VCCQ DQ26 DQ25 VSSQ DQ24 VSS -5- Publication Release Date:Aug. 13, 2007 Revision A09 W9864G2GH 5. PIN DESCRIPTION PIN NUMBER 24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66 PIN NAME FUNCTION DESCRIPTION Multiplexed pins for row and column address. Row address: A0−A10. Column address: A0−A7. A10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by BS0, BS1. Select bank to activate during row address latch time, or bank to read/write during address latch time. A0−A10 Address 22, 23 2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 74, 76, 77, 79, 80, 82, 83, 85 20 BS0, BS1 Bank Select DQ0−DQ31 Data Input/ Output Multiplexed pins for data output and input. CS Chip Select Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command input. When sampled at the rising edge of the clock RAS , CAS and WE define the operation to be executed. 19 RAS Row Address Strobe 18 17 CAS Column Address Referred to RAS Strobe Write Enable Referred to RAS The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. System clock used to sample inputs on the rising edge of clock. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM. Separated power from VCC, to improve DQ noise immunity. Separated ground from VSS, to improve DQ noise immunity. No connection.(The NC pin must connect to ground or floating.) WE 16, 28, 59, 71 Input/Output DQM0−DQM3 Mask CLK Clock Inputs 68 67 CKE Clock Enable 1, 15, 29, 43 44, 58, 72, 86 3, 9, 35, 41, 49, 55, 75, 81 6, 12, 32, 38, 46, 52, 78, 84 14, 21, 30, 57, 69, 70, 73 VCC VSS VCCQ VSSQ NC Power Ground Power for I/O Buffer Ground for I/O Buffer No Connection -6- Publication Release Date:Aug. 13, 2007 Revision A09 W9864G2GH 6. BLOCK DIAGRAM CLK CLOCK BUFFER CKE CS RAS CAS WE CONTROL SIGNAL COMMAND DECODER GENERATOR COLUMN DECODER COLUMN DECODER ROW DECODER ROW DECODER A10 CELL ARRAY BANK #0 CELL ARRAY BANK #1 A0 ADDRESS BUFFER MODE REGISTER SENSE AMPLIFIER SENSE AMPLIFIER A9 BS0 BS1 DATA CONTROL CIRCUIT COLUMN COUNTER DQ BUFFER DQ0 DQ31 DQM0~3 REFRESH COUNTER COLUMN DECODER ROW DECODER ROW DECODER COLUMN DECODER CELL ARRAY BANK #2 CELL ARRAY BANK #3 SENSE AMPLIFIER SENSE AMPLIFIER NOTE: The cell array configuration is 2048 * 256 * 32 -7- Publication Release Date:Aug. 13, 2007 Revision A09 W9864G2GH 7. FUNCTIONAL DESCRIPTION 7.1 Power Up and Initialization The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. During power up, all VCC and VCCQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power up voltage must not exceed VCC + 0.3V on any of the input pins or VCC supplies. After power up, an initial pause of 200 µS is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation. 7.2 Programming Mode Register After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table. 7.3 Bank Activate Command The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is specified as TRAS (max.). 7.4 Read and Write Access Modes After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The address inputs determine the starting column address. Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle. -8- Publication Release Date:Aug. 13, 2007 Revision A09 W9864G2GH 7.5 Burst Read Command The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8 and full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode. 7.6 Burst Command The Burst Write command is initiated by applying logic low level to CS , CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored. 7.7 Read Interrupted by a Read A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS Latency from the interrupting Read Command the is satisfied. 7.8 Read Interrupted by a Write To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed. 7.9 Write Interrupted by a Write A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. 7.10 Write Interrupted by a Read A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored. -9- Publication Release Date:Aug. 13, 2007 Revision A09 W9864G2GH 7.11 Burst Stop Command A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS Latency in a burst read cycle, interrupted by Burst Stop. 7.12 Addressing Sequence of Sequential Mode A column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2. Table 2 Address Sequence of Sequential Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 BL = 2 (disturb address is A0) No address carry from A0 to A1 BL = 4 (disturb addresses are A0 and A1) No address carry from A1 to A2 BL = 8 (disturb addresses are A0, A1 and A2) No address carry from A2 to A3 7.13 Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3. Table 3 Address Sequence of Interleave Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2 BL = 4 BL = 8 - 10 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G2GH 7.14 Auto-precharge Command If A10 is set to high when the Read or Write Command is issued, then the Auto-precharge function is entered. During Auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS Latency. A Read or Write Command with Auto-precharge cannot be interrupted before the entire burst operation is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with Auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Autoprecharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-precharge function is initiated. The SDRAM automatically enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred to as write tWR. The bank undergoing Auto-precharge cannot be reactivated until tWR and tRP are satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Autoprecharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS (min). 7.15 Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BS0 and BS1 are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP). 7.16 Self Refresh Command The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the tAC cycle time plus the Self Refresh exit time. If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode. - 11 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G2GH 7.17 Power Down Mode The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on tCK. The input buffers need to be enabled with CKE held high for a period equal to tCES (min.) + tCK (min.). 7.18 No Operation Command The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS , CAS and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 7.19 Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS , CAS and WE signals become don’t cares. 7.20 Clock Suspend Mode During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. - 12 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G2GH 8. OPERATION MODE Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. TABLE 1 TRUTH TABLE (NOTE (1), (2)) COMMAND Bank Active Bank Precharge Precharge All Write Write with Auto-precharge Read Read with Auto-precharge Mode Register Set No-Operation Burst Stop Device Deselect Auto-Refresh Self-Refresh Entry Self Refresh Exit Clock suspend Mode Entry Power Down Mode Entry Clock Suspend Mode Exit Power Down Mode Exit Data write/Output Enable Data Write/Output Disable Notes: Device State CKEn-1 CKEn DQM BS0, 1 A10 A0-A9 CS RAS L L L H H H H L H H x L L x H x x H x x H x x CAS H H H L L L L L H H x L L x H x x H x x H x x WE Idle Any Any Active (3) Active (3) Active (3) Active (3) Idle Any Active (4) Any Idle Idle idle (S.R) Active Idle Active (5) Active Any (power down) Active Active H H H H H H H H H H H H H L L H H H L L L H H x x x x x x x x x x x H L H H L L L H H H x x x x x x x x x x x x x x x x x x x x x x x L H v v x v v v v v x x x x x x x x x x x x x x x v L H L H L H v x x x x x x x x x x x x x x x V x x v v v v v x x x x x x x x x x x x x x x L L L L L L L L L L H L L H L x H L x H L x x H L L L L H H L H L x H H x x x X H X X H x x (1) v = valid, x = Don’t care, L = Low Level, H = High Level (2) CKEn signal is input leve l when commands are provided. (3) These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode. - 13 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G2GH 8.1 Simplified Stated Diagram Self Refresh LF SE it ex F EL S REF Mode Register Set MRS IDLE CBR Refresh CK E CK E Power Down ROW ACTIVE BS T ACT CKE CKE T BS ea R Active Power Down Writ ew Aut o pr ith ech arg e o Aut rit e d W ith dw Rea arge ch p re Write CKE CKE Read CKE CKE READ SUSPEND WRITE SUSPEND WRITE Read READ Write PR E( p rec har ge term inat ion ) PR WRITEA SUSPEND CKE WRITEA CKE READA CKE CKE READA SUSPEND PRE ) tion ina term ge har rec E(p POWER ON Precharge Precharge Automatic sequence Manual input MRS = Mode Register Set REF = Refresh ACT = Active PRE = Precharge WRITEA = Write with Auto-precharge READA = Read with Auto-precharge - 14 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G2GH 9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETER SYMBOL RATING UNIT NOTES Input, Column Output Voltage Power Supply Voltage Operating Temperature Operating Temperature (-6I) Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current VIN, VOUT VCC, VCCQ -0.3~VCC+ 0.3V -0.3~4.6V 0 ~ 70 -40 ~ 85 -55 ~ 150 260 1 50 V V °C °C °C °C W mA 1 1 1 1 1 1 1 1 TOPR TOPR TSTG TSOLDER PD IOUT Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 9.2 Recommended DC Operating Conditions PARAMETER SYM. VCC VCCQ VCC VCCQ (TA = 0 to 70°C for -5/-6/-6C/-7, TA = -40 to 85°C for -6I ) MIN. TYP. MAX. UNIT NOTES Power Supply Voltage Power Supply Voltage (for I/O Buffer) Power Supply Voltage(-7) Power Supply Voltage (for I/O Buffer)(-7) Input High Voltage Input Low Voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current 3.0 3.0 2.7 2.7 2 -0.3 2.4V -10 -10 3.3 3.3 3.3 3.3 - 3.6 3.6 3.6 3.6 VCC +0.3 +0.8 0.4 10 10 V V V V V V V V µA µA 1 2 IOH= -2mA IOL= 2mA VIH VIL VOH VOL II(L) Io(L) 3 4 Note: 1. VIH (max.) = VCC/VCCQ+1.2V for pulse width < 5 nS 2. VIL (min.) = VSS/VSSQ-1.2V for pulse width < 5 nS 3. Any input 0V