W9864G6GH-6I

W9864G6GH 1M × 4 BANKS × 16 BITS SDRAM Table of Contents1. 2. 3. 4. 5. 6. 7. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 AVAILABLE PART NUMBER ..................................................................................................... 4 PIN CONFIGURATION ............................................................................................................... 4 PIN DESCRIPTION..................................................................................................................... 5 BLOCK DIAGRAM ...................................................................................................................... 6 FUNCTIONAL DESCRIPTION ................................................................................................... 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 8. 9. Power Up and Initialization ............................................................................................. 7 Programming Mode Register Set command .................................................................. 7 Bank Activate Command ................................................................................................ 7 Read and Write Access Modes ...................................................................................... 7 Burst Read Command .................................................................................................... 8 Burst Command.............................................................................................................. 8 Read Interrupted by a Read ........................................................................................... 8 Read Interrupted by a Write............................................................................................ 8 Write Interrupted by a Write............................................................................................ 8 Write Interrupted by a Read............................................................................................ 8 Burst Stop Command ..................................................................................................... 9 Addressing Sequence of Sequential Mode .................................................................... 9 Addressing Sequence of Interleave Mode ..................................................................... 9 Auto-precharge Command ........................................................................................... 10 Precharge Command.................................................................................................... 10 Self Refresh Command ................................................................................................ 10 Power Down Mode ....................................................................................................... 11 No Operation Command............................................................................................... 11 Deselect Command ...................................................................................................... 11 Clock Suspend Mode.................................................................................................... 11 OPERATION MODE ................................................................................................................. 12 ELECTRICAL CHARACTERISTICS......................................................................................... 13 9.1 9.2 Absolute Maximum Ratings .......................................................................................... 13 Recommended DC Operating Conditions .................................................................... 13 Publication Release Date:Aug. 13, 2007 Revision A09 -1- W9864G6GH 9.3 9.4 9.5 10. 10.1 10.2 10.3 10.4 11. 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15 11.16 11.17 11.18 11.19 11.20 11.21 11.22 12. 13. 12.1 Capacitance .................................................................................................................. 13 DC Characteristics........................................................................................................ 14 AC Characteristics and Operating Condition................................................................ 15 Command Input Timing ................................................................................................ 18 Read Timing.................................................................................................................. 19 Control Timing of Input/Output Data............................................................................. 20 Mode Register Set Cycle .............................................................................................. 21 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 22 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)........... 23 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 24 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)........... 25 Interleaved Bank Write (Burst Length = 8) ................................................................... 26 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 27 Page Mode Read (Burst Length = 4, CAS Latency = 3) .............................................. 28 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) ..................................... 29 Auto-precharge Read (Burst Length = 4, CAS Latency = 3)........................................ 30 Auto-precharge Write (Burst Length = 4) .................................................................... 31 Auto Refresh Cycle ..................................................................................................... 32 Self Refresh Cycle....................................................................................................... 33 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)............................. 34 Power-down Mode ...................................................................................................... 35 Auto-precharge Timing (Write Cycle).......................................................................... 36 Auto-precharge Timing (Read Cycle) ......................................................................... 37 Timing Chart of Read to Write Cycle........................................................................... 38 Timing Chart of Write to Read Cycle........................................................................... 38 Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 39 Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 39 CKE/DQM Input Timing (Write Cycle)......................................................................... 40 CKE/DQM Input Timing (Read Cycle)......................................................................... 41 54L TSOP (II)-400 mil................................................................................................... 42 TIMING WAVEFORMS ............................................................................................................. 18 OPERATINOPERATING TIMING EXAMPLE........................................................................... 22 PACKAGE SPECIFICATION .................................................................................................... 42 REVISION HISTORY ................................................................................................................ 43 -2- Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 1. GENERAL DESCRIPTION W9864G6GH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 1M words × 4 banks × 16 bits. Using pipelined architecture and 0.11 µm process technology, W9864G6GH delivers a data bandwidth of up to 400M bytes per second. For different application, W9864G6GH is sorted into the following speed grades: -5, -6/-6I, -7/-7S. The -5 parts can run up to 200MHz/CL3. The -6/-6I parts can run up to 166MHz/CL3. The -7/-7S parts can run up to 143MHz/CL3. And the grade of –7S with tRP=18nS. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9864G6GH is ideal for main memory in high performance applications. 2. FEATURES • • • • • • • • • • • • • 3.3V± 0.3V for -5/-6/-6I grade power supply 2.7V～3.6V for -7/-7S grade power supply 1,048,576 words × 4 banks × 16 bits organization Self Refresh Current: Standard and Low Power CAS Latency: 2 & 3 Burst Length: 1, 2, 4, 8 and full page Sequential and Interleave Burst Byte data controlled by LDQM, UDQM Auto-precharge and controlled precharge Burst read, single write operation 4K refresh cycles/64 mS Interface: LVTTL Packaged in TSOP II 54-pin, 400 mil W9864G6GH is using Lead free materials -3- Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 3. AVAILABLE PART NUMBER PART NUMBER SPEED (CL=3) SELF REFRESH CURRENT (MAX.) OPERATING TEMPERATURE W9864G6GH-5 W9864G6GH-6 W9864G6GH-7/-7S W9864G6GH-6I 200 MHz 166 MHz 143 MHz 166 MHz 2mA 2mA 2mA 2mA 0°C ~ 70°C 0°C ~ 70°C 0°C ~ 70°C -40°C ~ 85°C 4. PIN CONFIGURATION VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BS0 BS1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS -4- Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 5. PIN DESCRIPTION PIN NUMBER PIN NAME FUNCTION DESCRIPTION Multiplexed pins for row and column address. 23 ~ 26, 22, 29 ~35 A0−A11 Row address: A0−A11. Column address: A0−A7. Address A10 is sampled during a precharge command to determine if all banks are to be precharged or bank selected by BS0, BS1. Select bank to activate during row address latch time, or bank to read/write during address latch time. Multiplexed pins for data output and input. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command input. When sampled at the rising edge of the clock RAS , CAS and WE define the operation to be executed. Referred to RAS Referred to RAS The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. System clock used to sample inputs on the rising edge of clock. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM. for I/O Separated power from VDD, to improve DQ noise immunity. Separated ground from VSS, to improve DQ noise immunity. No connection.(The NC pin must connect to 20, 21 BS0, BS1 Bank Select 2, 4, 5, 7, 8, 10, Data 11, 13, 42, 44, DQ0−DQ15 45, 47, 48, 50, Input/ Output 51, 53 19 CS Chip Select 18 RAS Row Address Strobe Column Address Strobe Write Enable Input/output mask 17 16 CAS WE UDQM LDQM CLK 39, 15 38 Clock Inputs 37 1, 14, 27 28, 41, 54 3, 9, 43, 49 6, 12, 46, 52 36, 40 CKE VDD VSS VDDQ VSSQ NC Clock Enable Power Ground Power buffer Ground for I/O buffer No Connection ground or floating.) -5- Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 6. BLOCK DIAGRAM CLK CLOCK BUFFER CKE CONTROL CS SIGNAL RAS CAS GENERATOR COMMAND DECODER WE ROW DECODER COLUMN DECODER COLUMN DECODER ROW DECODER A10 CELL ARRAY BANK #0 CELL ARRAY BANK #1 A0 A9 A11 BS0 BS1 ADDRESS BUFFER MODE REGISTER SENSE AMPLIFIER SENSE AMPLIFIER DATA CONTROL CIRCUIT COLUMN COUNTER DQ BUFFER DQ0 DQ15 REFRESH COUNTER UDQM LDQM COLUMN DECODER ROW DECODER ROW DECODER COLUMN DECODER CELL ARRAY BANK #2 CELL ARRAY BANK #3 SENSE AMPLIFIER SENSE AMPLIFIER NOTE: The cell array configuration is 4096 * 256 * 16 -6- Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 7. FUNCTIONAL DESCRIPTION 7.1 Power Up and Initialization The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. During power up, all VDD and VDDQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed VDD +0.3V on any of the input pins or VDD supplies. After power up, an initial pause of 200 µS is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation. 7.2 Programming Mode Register Set command After initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table. 7.3 Bank Activate Command The Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS (max.). 7.4 Read and Write Access Modes After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The address inputs determine the starting column address. Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle. Publication Release Date:Aug. 13, 2007 Revision A09 -7- W9864G6GH 7.5 Burst Read Command The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequence mode. 7.6 Burst Command The Burst Write command is initiated by applying logic low level to CS , CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored. 7.7 Read Interrupted by a Read A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS Latency from the interrupting Read Command the is satisfied. 7.8 Read Interrupted by a Write To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed. 7.9 Write Interrupted by a Write A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. 7.10 Write Interrupted by a Read A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored. -8- Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 7.11 Burst Stop Command A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS Latency in a burst read cycle, interrupted by Burst Stop. 7.12 Addressing Sequence of Sequential Mode A column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2. Table 2 Address Sequence of Sequential Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 n n+1 n+2 n+3 n+4 n+5 n+6 n+7 BL = 2 (disturb address is A0) No address carry from A0 to A1 BL = 4 (disturb addresses are A0 and A1) No address carry from A1 to A2 BL = 8 (disturb addresses are A0, A1 and A2) No address carry from A2 to A3 7.13 Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3. Table 3 Address Sequence of Interleave Mode DATA ACCESS ADDRESS BURST LENGTH Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2 BL = 4 BL = 8 -9- Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 7.14 Auto-precharge Command If A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS Latency. A Read or Write Command with auto-precharge cannot be interrupted before the entire burst operation is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of AutoPrecharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred to as write tWR. The bank undergoing auto-precharge cannot be reactivated until tWR and tRP are satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Autoprecharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS (min). 7.15 Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BS0, and BS1 are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP). 7.16 Self Refresh Command The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the tAC cycle time plus the Self Refresh exit time. If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode. - 10 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 7.17 Power Down Mode The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on tCK. The input buffers need to be enabled with CKE held high for a period equal to tCKS (min.) + tCK (min.). 7.18 No Operation Command The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS , CAS , and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 7.19 Deselect Command The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS , CAS , and WE signals become don't Care. 7.20 Clock Suspend Mode During normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited. - 11 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 8. OPERATION MODE Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. Table 1 Truth Table (note (1), (2)) Command Bank Active Bank Precharge Precharge All Write Write with Auto-precharge Read Read with Auto-precharge Mode Register Set No-Operation Burst Stop Device Deselect Auto-Refresh Self-Refresh Entry Self Refresh Exit Clock suspend Mode Entry Power Down Mode Entry Clock Suspend Mode Exit Power Down Mode Exit Data write/Output Enable Data write/Output Disable Notes: Device State Idle Any Any Active (3) Active (3) Active (3) Active (3) Idle Any Active (4) Any Idle Idle idle (S.R) Active Idle Active (5) Active Any (power down) Active Active CKEn-1 CKEn DQM BS0, 1 H H H H H H H H H H H H H L L H H H L L L H H x x x x x x x x x x x H L H H L L L H H H x x x x x x x x x x x x x x x x x x x x x x x L H v v x v v v v v x x x x x x x x x x x x x x x A10 v L H L H L H v x x x x x x x x x x x x x x x A0-A9, A11 V x x v v v v v x x x x x x x x x x x x x x x CS RAS L L L H H H H L H H x L L x H x x H x x H x x CAS H H H L L L L L H H x L L x H x x H x x H x x WE L L L L L L L L L L H L L H L x H L x H L x x H L L L L H H L H L x H H x x x X H X X H x x (1) v = valid, x = Don't care, L = Low Level, H = High Level (2) CKEn signal is input leve l when commands are provided. (3) These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation. (5) Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode. - 12 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 9. ELECTRICAL CHARACTERISTICS 9.1 Absolute Maximum Ratings PARAMETER SYMBOL RATING UNIT NOTES Input, Column Output Voltage Power Supply Voltage Operating Temperature (-5/-6/-7/-7S) Operating Temperature (-6I) Storage Temperature Soldering Temperature (10s) Power Dissipation Short Circuit Output Current VIN, VOUT VDD, VDDQ TOPR TOPR TSTG TSOLDER PD IOUT -0.3 ~ VDD +0.3 -0.3 ~ 4.6 0 ~ 70 -40 ~ 85 -55 ~ 150 260 1 50 V V °C °C °C °C W mA 1 1 1 1 1 1 1 1 Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliabilityof the device. 9.2 Recommended DC Operating Conditions PARAMETER SYM. MIN. TYP. MAX. UNIT NOTES (TA = 0 to 70°C for -5/-6/-7/-7S, TA = -40 to 85°C for -6I) Supply Voltage (Normal operation) Supply voltage (for –7/-7S) Supply Voltage for I/O Buffer Supply Voltage for I/O Buffer (for -7/-7S) Input High Voltage Input Low Voltage VDD VDD VDDQ VDDQ VIH VIL 3.0 2.7 3.0 2.7 2.0 -0.3 3.3 3.3 - 3.6 3.6 3.6 3.6 VDD+0.3 0.8 V V V V V V 2 2 2 2 2 2 Note: VIH (max.) = VDD/VDDQ+1.2V for pulse width < 5 nS , VIL (min.) = VSS/VSSQ-1.2V for pulse width < 5 nS 9.3 Capacitance PARAMETER SYM. MIN. MAX. UNIT (VDD =3V±0.3V for-5/-6/-6I ,VDD=2.7V-3.6V for -7/-7S , TA = 25 °C, f = 1 MHz) Input Capacitance Ci1 (A0 to A11, BS0, BS1, CS , RAS , CAS , WE , CKE) Input Capacitance (CLK) Input/Output Capacitance (DQ0−DQ15) Input Capacitance DQM Note: These parameters are periodically sampled and not 100% tested 2.5 2.5 4 3.0 4 4 6.5 5.5 pf pf pf pf CCLK Co Ci2 - 13 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 9.4 DC Characteristics -5 MAX. Operating Current tCK = min., tRC = min. Active precharge command cycling without burst operation Standby Current tCK = min., CS = VIH VIH/L = VIH (min.)/VIL (max.) Bank: Inactive State Standby Current CLK = VIL, CS = VIH VIH/L=VIH (min.)/VIL (max.) Bank: Inactive State No Operating Current tCK = min., CS = VIH (min.) Bank: Active State (4 Banks) Burst Operating Current (tCK = min.) Read/Write command cycling Auto Refresh Current (tCK = min.) Auto refresh command cycling Self Refresh Current Self refresh mode (CKE = 0.2V) CKE = VIH CKE = VIL (Power Down mode) CKE = VIH CKE = VIL (Power Down mode) ICC2S 15 15 15 CKE = VIH CKE = VIL (Power Down mode) ICC2 40 35 30 3 ICC1 1 Bank Operation 100 (VDD =3V±0.3V for-5/-6 ,VDD=2.7V-3.6V for -7/-7S on TA = 0 to 70°C, VDD =3V±0.3V for -6I on TA = -40 to 85°C ) PARAMETER SYM. -6/6I MAX. 90 -7/-7S MAX. 80 UNIT NOTES 3 ICC2P 2 2 2 3 ICC2PS 2 2 2 mA ICC3 65 60 55 ICC3P 15 15 15 ICC4 180 165 145 3, 4 ICC5 160 140 120 3 ICC6 2 2 2 PARAMETER Input Leakage Current (0V ≤ VIN ≤ VDD, all other pins not under test = 0V) Output Leakage Current (Output disable, 0V ≤ VOUT ≤ VDDQ) LVTTL Output ″H″ Level Voltage (IOUT = -2 mA) LVTTL Output “L″ Level Voltage (IOUT = 2 mA) SYMBOL II(L) MIN. -5 MAX. 5 UNIT µA NOTE S lO(L) -5 5 µA VOH 2.4 - V VOL - 0.4 V - 14 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 9.5 AC Characteristics and Operating Condition (VDD =3V±0.3V for-5/-6, VDD=2.7V-3.6V for -7/-7S on TA = 0 to 70°C, VDD =3V±0.3V for -6I on TA = -40 to 85°C ) (Notes: 5, 6) PARAMETER SYM. -5 MIN. MAX. -6/-6I MIN. MAX. MIN. -7 MAX. MIN. -7S MAX. UNIT NOTES Ref/Active to Ref/Active Command Period Active to precharge Command Period Active to Read/Write Command Delay Time Read/Write(a) to Read/ Write(b) Command Period Precharge to Active(b) Command Period Active(a) to Active(b) Command Period Write Recovery Time CL* = 2 CL* = 3 CLK Cycle Time CL* = 2 CL* = 3 CLK High Level CLK Low Level Access Time from CLK CL* = 2 CL* = 3 Output Data Hold Time Output Data High Impedance Time Output Data Low Impedance Time Power Down Mode Entry Time Transition Time of CLK (Rise and Fall) Data-in-Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time Command Hold Time tRC tRAS tRCD tCCD tRP tRRD tWR 55 40 15 1 15 10 2 100000 60 42 18 1 18 12 2 10000 0 65 45 20 1 20 14 2 100000 65 45 20 1 18 nS 14 2 tCK tCK 100000 nS tCK tCH tCL tAC tOH tHZ tLZ tSB tT tDS tDH tAS tAH tCKS tCKH tCMS tCMH 10 5 2 2 1000 1000 7.5 6 2 2 1000 1000 10 7 2 2 1000 1000 10 7 2 2 1000 1000 9 9 6 5.5 11 11 7 8 11 nS 7 1 7 10 10 10 10 10 10 10 10 － 5.5 5 2 2 6 2 0 6 1 1.5 1 1.5 1 1.5 1 1.5 1 1.5 1 1.5 1 1.5 1 1.5 1 0 6 5.5 2 7 2 0 7 1 1.5 1 1.5 1 1.5 1 1.5 1 0 4.5 2 2 0 0 5 1 1.5 1 1.5 1 1.5 1 1.5 1 5 2 0 0 - 15 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH AC Characteristics and Operating Condition, continued PARAMETER SYM. -5 MIN. MAX. -6/-6I MIN. MAX. MIN. -7 MAX. MIN. -7S MAX. UNIT NOTES Refresh Time Mode Register Set Cycle Time Exit self refresh to ACTIVE Command tREF tRSC tXSR 10 70 64 14 72 64 14 75 64 14 75 64 mS nS nS Notes: 1.Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices. 2. All voltages are referenced to VSS 3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC. 4. These parameters depend on the output loading conditions. Specified values are obtained with output open. 5. Power up sequence please refer to "Functional Description" section described before. 6. AC Testing Conditions PARAMETER CONDITIONS 　 Output Reference Level Output Load Input Signal Levels Transition Time (tT: tr/tf) of Input Signal Input Reference Level 1.4V See diagram below 2.4V/0.4V 1/1 nS 1.4V 1.4 V 50 ohms output Z = 50 ohms 30pF AC TEST LOAD 7. Transition times are measured between VIH and VIL. 8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. - 16 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 9. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows the number of clock cycles = specified value of timing/ clock period (count fractions as whole number) (1)tCH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min.). tCL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max.). (2)A.C Latency Characteristics CKE to clock disable (CKE Latency) DQM to output to HI-Z (Read DQM Latency) DQM to output to HI-Z (Write DQM Latency) Write command to input data (Write Data Latency) 1 2 0 0 0 CL = 2 CL = 3 Precharge to Last Valid data out CL = 2 CL = 3 Bust Stop Command to DQ Hi-Z Lead time CL = 2 CL = 3 Bust Stop Command to Last Valid Data out CL = 2 CL = 3 Read with Auto-precharge Command to Active/Ref Command CL = 2 CL = 3 Write with Auto-precharge Command to Active/Ref Command CL = 2 CL = 3 2 3 1 2 2 3 1 2 BL + tRP BL + tRP (BL+1) + tRP (BL+1) + tRP tCK + nS tCK CS to Command input ( CS Latency) Precharge to DQ Hi-Z Lead time 10. Assumed input rise and fall time (tT ) = 1nS. If tr & tf is longer than 1nS, transient time compensation should be considered, i.e., [(tr + tf)/2-1]nS should be added to the parameter ( The tT maximum can’t be more than 10nS for low frequency application. ) 11. If clock rising time (tT) is longer than 1nS, (tT/2-0.5)nS should be added to the parameter. - 17 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 10. TIMING WAVEFORMS 10.1 Command Input Timing tCK tCL tCH VIH CLK VIL tT tCMS tCMH tCMH tT tCMS CS tCMS tCMH RAS tCMS tCMH CAS tCMS tCMH WE tAS tAH A0-A11 BS0, 1 tCKS tCKH tCKS tCKH tCKS tCKH CKE - 18 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 10.2 Read Timing Read CAS Latency CLK CS RAS CAS WE A0-A11 BS0, 1 tAC tLZ tOH Valid Data-Out tAC tHZ tOH Valid Data-Out DQ Read Command Burst Length - 19 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 10.3 Control Timing of Input/Output Data Control Timing of Input Data (Word Mask) CLK tCMH tCMS tCMH tCMS DQM tDS tDH Valid Data-in tDS tDH Valid Data-in tDS tDH Valid Data-in tDS tDH Valid Data-in DQ0 -15 (Clock Mask) CLK tCKH tCKS tCKH tCKS CKE tDS tDH Valid Data-in tDS tDH Valid Data-in tDS tDH Valid Data-in tDS tDH Valid Data-in DQ0 -15 Control Timing of Output Data (Output Enable) CLK tCMH tCMS tCMH tCMS DQM tAC tOH tOH Valid Data-Out tAC tOH Valid Data-Out tHZ tLZ tAC tOH Valid Data-Out tAC DQ0 -15 OPEN (Clock Mask) CLK tCKH tCKS tCKH tCKS CKE tAC tOH tAC tOH Valid Data-Out Valid Data-Out tAC tOH tOH Valid Data-Out tAC DQ0 -15 - 20 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 10.4 Mode Register Set Cycle tRSC CLK tCMS tCMH CS tCMS tCMH RAS tCMS tCMH CAS tCMS tCMH WE tAS tAH Register set data A0-A11 BS0,1 A0 A1 A2 A3 A4 A5 A6 A0 A7 A8 A9 A0 A10 A11 A0 BS0 BS1 "0" "0" "0" "0" A0 Reserved "0" "0" (Test Mode) Reserved A0 Write Mode CAS Latency Addressing Mode Burst Length A2 0 0 0 0 1 1 1 1 A0 A1 A0 A0 A0 0 0 A0 1 0 A0 0 1 A0 1 1 A0 0 0 A0 1 0 A0 0 1 A0 1 1 A0 A3 A0 0 A0 1 next command BurstA0 Length Sequential A0 Interleave A0 1 A0 1 A0 A0 2 2 A0 4 A0 4 A0 8 A0 8 A0 Reserved FullA0 Page A0 Addressing Mode Sequential A0 Interleave A0 CAS Latency A0 Reserved A0 Reserved A0 2 A0 3 Reserved Single Write Mode Burst read and Burst write A0 Burst read and single write A0 A0 Reserved A6 0 0 0 0 1 A5 A4 A0 A0 0 0 A0 1 0 A0 0 1 A0 1 1 A0 0 0 A9 A0 A0 0 A0 1 - 21 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11. OPERATINOPERATING TIMING EXAMPLE 11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC tRAS tRP tRP tRAS RAS tRAS tRP tRAS CAS WE BS0 BS1 tRCD tRCD RBb RAc tRCD RBd tRCD RAe A10 A0-A9, A11 DQM RAa RAa CAw RBb CBx RAc CAy RBd CBz RAe CKE tAC tAC aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 tAC cy0 cy1 cy2 cy3 tAC DQ tRRD tRRD tRRD tRRD Bank #0 Active Bank #1 Bank #2 Idle Bank #3 Read Active Precharge Read Active Read Precharge Active Precharge Read Active - 22 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC tRAS tRP tRP tRAS RAS tRAS tRP tRAS CAS WE BS0 BS1 tRCD tRCD RBb RAc tRCD tRCD RBd RAe A10 RAa A0-A9, A11 DQM CKE RAa CAw RBb CBx RAc CAy RBd CBz RAe tAC tAC aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 tAC cy0 cy1 cy2 cy3 tAC dz0 DQ tRRD tRRD tRRD tRRD Bank #0 Bank #1 Bank #2 Idle Bank #3 Active Read Active AP* Read Active Read AP* Active AP* Read Active * AP is the internal precharge start timing - 23 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC RAS tRAS tRP tRP tRAS tRAS tRP CAS WE BS0 BS1 tRCD tRCD RBb RAc tRCD A10 RAa A0-A9, A11 DQM RAa CAx RBb CBy RAc CAz CKE tAC tAC ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 tAC by7 CZ0 DQ tRRD tRRD Bank #0 Bank #1 Bank #2 Active Read Precharge Active Read Precharge Active Read Precharge Idle Bank #3 - 24 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) 0 1 2 3 4 5 6 7 8 tRC 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS tRAS tRP tRAS tRAS tRP CAS WE BS0 BS1 tRCD tRCD tRCD RBb RAc A10 RAa A0-A9, A11 DQM RAa CAx RBb CBy RAc CAz CKE tCAC tCAC ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 tCAC by6 CZ0 DQ tRRD tRRD Bank #0 Bank #1 Bank #2 Active Read Active AP* Read Active Read AP* Idle Bank #3 * AP is the internal precharge start timing - 25 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.5 Interleaved Bank Write (Burst Length = 8) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS tRAS tRP CAS tRCD tRCD tRCD WE BS0 BS1 A10 RAa RBb RAc A0-A9, A11 DQM RAa CAx RBb CBy RAc CAz CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD tRRD Bank #0 Bank #1 Bank #2 Bank #3 Active Write Active Write Precharge Active Write Precharge Idle - 26 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRP tRAS CAS WE BS0 BS1 tRCD tRCD RBb RAb tRCD A10 RAa A0-A9 A11 DQM CKE DQ RAa CAx RBb CBy RAc CAz ax0 ax1 ax4 ax5 ax6 ax7 by0 by1 by2 by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD tRRD Bank #0 Active Bank #1 Bank #2 Idle Bank #3 Write Active Write AP* Active Write AP* * AP is the internal precharge start timing - 27 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tCCD tCCD tCCD CS tRAS tRAS tRP tRP RAS CAS WE BS0 BS1 tRCD tRCD RBb A10 A0-A9, A11 DQM CKE RAa RAa CAI RBb CBx CAy CAm CBz tAC tAC a0 a1 a3 bx0 tAC tAC tAC am0 am1 am2 bz0 bz1 bz2 bz3 DQ tRRD a2 bx1 Ay0 Ay1 Ay2 Bank #0 Active Bank #1 Bank #2 Idle Bank #3 Read Active Read Read Read Read Precharge AP* * AP is the internal precharge start timing - 28 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.8 Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRAS tRP RAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11 RAa CAx CAy DQM CKE tAC tWR ax0 ax1 ax2 ax3 ax4 ax5 ay0 ay1 ay2 ay3 ay4 DQ QQ Q Q Q Q D D D D D Bank #0 Bank #1 Bank #2 Bank #3 Active Read Write Precharge Idle - 29 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC RAS tRAS tRP tRAS tRP CAS WE BS0 BS1 tRCD tRCD RAb A10 RAa A0-A9, A11 DQM CKE RAa CAw RAb CAx tAC tAC aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 DQ Bank #0 Bank #1 Bank #2 Active Read AP* Active Read AP* Idle Bank #3 * AP is the internal precharge start timing - 30 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.10 Auto-precharge Write (Burst Length = 4) CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS tRC tRC RAS tRAS tRP tRAS tRP CAS WE BS0 BS1 tRCD tRCD RAb RAc A10 A0-A9, A11 DQM CKE DQ RAa RAa CAw RAb CAx RAc aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3 Bank #0 Bank #1 Bank #2 Active Write AP* Active Write AP* Active Idle Bank #3 * AP is the internal precharge start timing - 31 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.11 Auto Refresh Cycle (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRP tRC tRC CS RAS CAS WE BS0,1 A10 A0-A9, A11 DQM CKE DQ All Banks Prechage Auto Refresh Auto Refresh (Arbitrary Cycle) - 32 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.12 Self Refresh Cycle (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRP RAS CAS WE BS0,1 A10 A0-A9, A11 DQM tSB tCKS tCKS CKE tCKS DQ tXSR Self Refresh Cycle Self Refresh Exit No Operation / Command Inhibit All Banks Precharge Self Refresh Entry Arbitrary Cycle - 33 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.13 Bust Read and Single Write (Burst Length = 4, CAS Latency = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS tRCD WE BS0 BS1 A10 RBa A0-A9, A11 DQM CKE RBa CBv CBw CBx CBy CBz tAC tAC av0 Q av1 Q av2 Q av3 Q aw0 D ax0 D ay0 D az0 Q az1 Q az2 Q az3 Q DQ Bank #0 Active Bank #1 Bank #2 Bank #3 Idle Read Single Write Read - 34 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.14 Power-down Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS WE BS A10 RAa RAa A0-A9 A11 DQM RAa CAa RAa CAx tSB tSB CKE tCKS tCKS ax0 ax1 ax2 tCKS ax3 tCKS DQ Active NOP Read Precharge NOP Active Precharge Standby Power Down mode Active Standby Power Down mode Note: The PowerDown Mode is entered by asserting CKE "low". All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode. When CKE goes high, command input must be No operation at next CLK rising edge. Violating refresh requirements during power-down may result in a loss of data. - 35 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.15 Auto-precharge Timing (Write Cycle) 0 1 2 3 4 5 6 7 8 9 10 11 12 CLK (1) CAS Latency = 2 (a) burst length = 1 Command Write tWR AP tRP Act DQ (b) burst length = 2 Command D0 Write tWR AP tRP Act DQ (c) burst length = 4 Command D0 Write D1 AP tWR tRP Act DQ (d) burst length = 8 Command D0 Write D1 D2 D3 AP tWR tRP Act DQ (2) CAS Latency = 3 (a) burst length = 1 Command D0 D1 D2 D3 D4 D5 D6 D7 Write tWR AP tRP Act DQ (b) burst length = 2 Command D0 Write tWR AP tRP Act DQ (c) burst length = 4 Command D0 Write D1 AP tWR tRP Act DQ (d) burst length = 8 Command D0 Write D1 D2 D3 AP tWR tRP Act Act DQ D0 D1 D2 D3 D4 D5 D6 D7 Note ) Write AP Act represents the Write with Auto precharge command. represents the start of internal precharing. represents the Bank Active command. When the /auto precharge command is asserted,the period from Bank Activate command to the start of intermal precgarging must be at least tRAS (min). - 36 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.16 Auto-precharge Timing (Read Cycle) 0 (1) CAS Latency=2 ( a ) burst length = 1 Command 1 AP 2 3 Act 4 5 6 7 8 9 10 11 Read tRP DQ ( b ) burst length = 2 Command Q0 Read AP tRP Act Q1 AP tRP DQ ( c ) burst length = 4 Command Q0 Read Q0 Read Q0 Act Q3 AP tRP DQ ( d ) burst length = 8 Command Q1 Q1 Q2 Q2 Act DQ (2) CAS Latency=3 ( a ) burst length = 1 Command Q3 Q4 Q5 Q6 Q7 Read AP tRP Act Q0 DQ ( b ) burst length = 2 Command Read AP tRP Act Q0 Q1 AP tRP DQ ( c ) burst length = 4 Command Read Q0 Read Q0 Act Q2 Q3 AP tRP DQ ( d ) burst length = 8 Command Q1 Act Q6 Q7 DQ Q1 Q2 Q3 Q4 Q5 Note ) Read AP Act represents the Read with Auto precharge command. represents the start of internal precharging. represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS (min). - 37 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.17 Timing Chart of Read to Write Cycle In the case of Burst Length = 4 0 (1) CAS Latency=2 ( a ) Command 1 Read 2 Write 3 4 5 6 7 8 9 10 11 DQM DQ D0 Read D1 Write D2 D3 ( b ) Command DQM DQ D0 Read Write D0 Read D1 Write D1 D2 D3 (2) CAS Latency=3 ( a ) Command DQM DQ ( b ) Command DQM D2 D3 DQ D0 D1 D2 D3 Note: The Output data must be masked by DQM to avoid I/O conflict. 11.18 Timing Chart of Write to Read Cycle In the case of Burst Length = 4 0 (1) CAS Latency = 2 ( a ) Command DQM DQ ( b ) Command DQM DQ 1 Write D0 Write D0 2 Read 3 4 5 6 7 8 9 10 11 Q0 Read D1 Q1 Q2 Q3 Q0 Q1 Q2 Q3 (2) CAS Latency = 3 ( a ) Command DQM DQ ( b ) Command DQM Write D0 Write D0 Read Q0 Read D1 Q0 Q1 Q2 Q3 Q1 Q2 Q3 DQ - 38 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) 0 (1) Read cycle ( a ) CAS latency =2 Command 1 2 3 4 5 BST 6 7 8 9 10 11 Read Q0 Read Q0 Q1 Q1 Q2 DQ Q3 BST Q2 Q4 ( b )CAS latency = 3 Command DQ Q3 Q4 (2) Write cycle Command Write Q0 Q1 Q2 Q3 Q4 BST DQ Note: BST represents the Burst stop command 11.20 Timing Chart of Burst Stop Cycle (Precharge Command) 0 (1) Read cycle (a) CAS latency =2 Command DQ 1 2 3 4 5 6 7 8 9 10 11 Read Q0 Read Q0 Q1 Q1 Q2 PRCG Q3 PRCG Q2 Q3 Q4 Q4 (b) CAS latency =3 Command DQ (2) Write cycle (a) CAS latency =2 Command DQM DQ Write tWR PRCG Q0 Write Q1 Q2 Q3 Q4 PRCG tWR (b) CAS latency =3 Command DQM DQ Q0 Q1 Q2 Q3 Q4 - 39 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.21 CKE/DQM Input Timing (Write Cycle) CLK cycle No. 1 2 3 4 5 6 7 External CLK Internal CKE DQM DQ D1 D2 D3 DQM MASK (1) D5 CKE MASK D6 CLK cycle No. 1 2 3 4 5 6 7 External CLK Internal CKE DQM DQ D1 D2 D3 DQM MASK (2) D5 CKE MASK D6 CLK cycle No. External CLK Internal CKE DQM DQ 1 2 3 4 5 6 7 D1 D2 D3 CKE MASK (3) D4 D5 D6 - 40 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 11.22 CKE/DQM Input Timing (Read Cycle) CLK cycle No. 1 2 3 4 5 6 7 External CLK Internal CKE DQM DQ Q1 Q2 Q3 Q4 Open Open Q6 (1) CLK cycle No. 1 2 3 4 5 6 7 External CLK Internal CKE DQM DQ Q1 Q2 Q3 Q4 Open Q6 (2) CLK cycle No. 1 2 3 4 5 6 7 External CLK Internal CKE DQM DQ Q1 Q2 Q3 Q4 Q5 Q6 (3) - 41 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 12. PACKAGE SPECIFICATION 12.1 54L TSOP (II)-400 mil - 42 - Publication Release Date:Aug. 13, 2007 Revision A09 W9864G6GH 13. REVISION HISTORY VERSION DATE PAGE DESCRIPTION A01 A02 A03 A04 A05 A06 A07 A08 Jul. 05, 2006 Aug. 03, 2006 Aug. 07, 2006 Oct. 03, 2006 Nov. 01, 2006 Nov. 02, 2006 Apr. 10, 2007 May 04, 2007 All 3,13,14,15 15,16 14 15 20 3,13,14,15 3,13,14,15 Create new datasheet Add -6C grade Modify Transition Time of CLK Add tXSR timing specification Remove tT(min) timing specification Control timing of Input/Output Data waveform correction (x 32 DQ I/O change to x 16 DQ I/O) Add -6I grade for Ta= -40 to 85°C Modify -6 grade AC specification with tCK=7.5nS, tAC=5.5nS on CL=2, remove -6C grade Revise transient time tT AC test condition and calculate formula for compensation consideration in Notes 6, 10 of AC Characteristics and Operating Condition A09 Aug. 13, 2007 16,17 Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 43 - Publication Release Date:Aug. 13, 2007 Revision A09