WM8974_07

w Mono CODEC with Speaker Driver DESCRIPTION The WM8974 is a low power, high quality mono CODEC designed for portable applications such as Digital Still Camera or Digital Voice Recorder. The device integrates support for a differential or single ended mic, and includes drivers for speakers or headphone, and mono line output. External component requirements are reduced as no separate microphone or headphone amplifiers are required. Advanced Sigma Delta Converters are used along with digital decimation and interpolation filters to give high quality audio at sample rates from 8 to 48ks/s. Additional digital filtering options are available in the ADC path, to cater for application filtering such as ‘wind noise reduction’, plus an advanced mixed signal ALC function with noise gate is provided. The digital audio interface supports A-law and µ-law companding. An on-chip PLL is provided to generate the required Master Clock from an external reference clock. The PLL clock can also be output if required elsewhere in the system. The WM8974 operates at supply voltages from 2.5 to 3.6V, although the digital supplies can operate at voltages down to 1.71V to save power. The speaker and mono outputs use a separate supply of up to 5V which enables increased output power if required. Different sections of the chip can also be powered down under software control by way of the selectable two or three wire control interface. WM8974 is supplied in a very small 4x4mm QFN package, offering high levels of functionality in minimum board area, with high thermal performance. WM8974 FEATURES • • • • • • • • • Mono CODEC: Audio sample rates:8, 11.025, 16, 22.05, 24, 32, 44.1, 48kHz DAC SNR 98dB, THD -84dB (‘A’-weighted @ 8 – 48ks/s) ADC SNR 94dB, THD -83dB (‘A’-weighted @ 8 – 48ks/s) On-chip Headphone/Speaker Driver with ‘cap-less’ connect - 40mW output power into 16Ω / 3.3V SPKVDD - BTL speaker drive 0.9W into 8Ω / 5V SPKVDD Additional MONO Line output Multiple analog or ‘Aux’ inputs, plus analog bypass path Mic Preamps: Differential or single end Microphone Interface - Programmable preamp gain - Psuedo differential inputs with common mode rejection - Programmable ALC / Noise Gate in ADC path Low-noise bias supplied for electret microphones • OTHER FEATURES • 5 band EQ (record or playback path) • Digital Playback Limiter • Programmable ADC High Pass Filter (wind noise reduction) • Programmable ADC Notch Filter • On-chip PLL • Low power, low voltage - 2.5V to 3.6V (digital: 1.71V to 3.6V) - power consumption 2.6, x128 (ADCOSR=1)=>4.9 0.2 1mA from SPKVDD + 0.2mA from AVDD in 5V mode 1mA from SPKVDD + 0.2mA from AVDD in 5V mode 0.2 0.2 x64 (DACOSR=0)=>1.8, x128(DACOSR=1)=>1.9 AVDD CURRENT (MILLIAMPS) Table 62 AVDD Supply Current w PD Rev 4.2 March 2007 64 Production Data WM8974 REGISTER MAP ADDR B[15:9] DEC HEX REGISTER NAME Software Reset Power manage’t 1 Power manage’t 2 Power manage’t 3 Audio Interface Companding ctrl Clock Gen ctrl Additional ctrl GPIO DAC Control DAC digital Vol ADC Control ADC Digital Vol EQ1 – low shelf EQ2 – peak 1 EQ3 – peak 2 EQ4 – peak 3 EQ5 – high shelf DAC Limiter 1 DAC Limiter 2 Notch Filter 1 Notch Filter 2 Notch Filter 3 Notch Filter 4 ALC control 1 ALC control 2 ALC control 3 Noise Gate PLL N PLL K 1 PLL K 2 PLL K 3 Attenuation ctrl Input ctrl INP PGA gain ctrl ADC Boost ctrl Output ctrl SPK mixer ctrl B8 B7 B6 B5 B4 B3 B2 B1 B0 DEF’T VAL (HEX) 0 1 2 3 4 5 6 7 8 10 11 14 15 18 19 20 21 22 24 25 27 28 29 30 32 33 34 35 36 37 38 39 40 44 45 47 49 50 00 01 02 03 04 05 06 07 08 0A 0B 0E 0F 12 13 14 15 16 18 19 1B 1C 1D 1E 20 21 22 23 24 25 26 27 28 2C 2D 2F 31 32 Software reset BUFDCOP EN 0 0 BCP 0 CLKSEL 0 0 0 0 HPFEN 0 EQMODE EQ2BW EQ3BW EQ4BW 0 LIMEN 0 NFU NFU NFU NFU ALCSEL ALCZC ALCMODE 0 0 0 0 0 0 0 0 0 PLLK[17:9] PLLK[8:0] 0 MBVSEL 0 PGABOOST 0 0 0 0 INPPGAZC 0 0 0 0 0 0 0 INPPGA MUTE MICP2BOOSTVOL 0 AUX2SPK 0 0 0 0 0 0 0 AUXMODE MONOATT SPKATTN N AUX2 INPPGA MICN2 INPPGA 0 MICP2 INPPGA 0 NFEN 0 0 0 0 0 ALCHLD ALCDCY 0 0 0 PLLPRE SCALE PLLK[23:18] NGEN ALCMAX 0 0 0 0 0 EQ1C EQ2C EQ3C EQ4C EQ5C LIMDCY LIMLVL NFA0[13:7] NFA0[6:0] NFA1[13:7] NFA1[6:0] ALCMIN ALCLVL ALCATK NGTH PLLN[3:0] HPFAPP HPFCUT 0 0 0 0 0 MONOEN FRAMEP 0 0 MCLKDIV 0 0 DACMU 0 OPCLKDIV DEEMPH 0 GPIOPOL DACOSR 128 DACVOL ADCOSR 128 ADCVOL EQ1G EQ2G EQ3G EQ4G EQ5G LIMATK LIMBOOST 0 0 ADCPOL AMUTE AUXEN 0 SPKNEN WL 0 PLLEN 0 SPKPEN MICBEN BOOSTEN 0 FMT DAC_COMP BCLKDIV SR GPIOSEL 0 DACPOL BIASEN 0 MONO MIXEN BUFIOEN INPPGAEN SPK MIXEN 0 0 VMIDSEL ADCEN DACEN 0 000 000 000 050 DACLRSW ADCLRSW AP AP ADC_COMP 0 LOOPBACK 000 MS 140 SLOWCLKE 000 N 000 000 0FF 100 0FF 12C 02C 02C 02C 02C 032 000 000 000 000 000 038 00B 032 000 008 00C 093 0E9 000 003 010 INPPGAVOL 0 MONO BOOST 0 SPK BOOST 0 AUX2BOOSTVOL TSDEN BYP2SPK VROI DAC2SPK 000 002 000 w PD Rev 4.2 March 2007 65 WM8974 ADDR B[15:9] DEC HEX Production Data REGISTER NAME B8 B7 B6 B5 B4 B3 B2 B1 B0 DEF’T VAL (HEX) 039 BYP2 MONO DAC2 MONO 000 54 56 36 38 SPK volume ctrl MONO mixer ctrl 0 0 SPKZC 0 SPKMUTE MONO MUTE 0 0 0 SPKVOL AUX2 MONO REGISTER BITS BY ADDRESS Notes: 1. Default values of N/A indicate non-latched data bits (e.g. software reset or volume update bits). 2. Register bits marked as "Reserved" should not be changed from the default. REGISTER ADDRESS 0 (00h) 1 (01h) 8 BIT [8:0] LABEL RESET BUFDCOPEN DEFAULT N/A 0 Software reset Dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration. 0=Buffer disabled 1=Buffer enabled (required for 1.5x gain boost) Reserved Auxilliary input buffer enable 0 = OFF 1 = ON PLL enable 0=PLL off 1=PLL on Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON Analogue amplifier bias control 0=Disabled 1=Enabled Unused input/output tie off buffer enable 0=Disabled 1=Enabled Reference string impedance to VMID pin: 00=off (open circuit) 01=75kΩ 10=300kΩ 11=2.5kΩ Reserved Input BOOST enable 0 = Boost stage OFF 1 = Boost stage ON Reserved Input microphone PGA enable 0 = disabled 1 = enabled Reserved ADC Enable Control 0 = ADC disabled 1 = ADC enabled Reserved Analogue to Digital Converter (ADC) Input Signal Path Input Boost Auxiliary Inputs DESCRIPTION REFER TO Resetting the Chip Analogue Outputs 7 6 AUXEN 0 0 5 PLLEN 0 Master Clock and Phase Locked Loop (PLL) Microphone Biasing Circuit Power Management Enabling the Outputs Power Management 4 MICBEN 0 3 BIASEN 0 2 BUFIOEN 0 1:0 VMIDSEL 00 2 (02h) 8:5 4 BOOSTEN 0000 0 3 2 INPPGAEN 0 0 1 0 ADCEN 0 0 3 (03h) 8 0 w PD Rev 4.2 March 2007 66 Production Data REGISTER ADDRESS 7 BIT LABEL MONOEN DEFAULT 0 MONOOUT enable 0 = disabled 1 = enabled SPKOUTN enable 0 = disabled 1 = enabled SPKOUTP enable 0 = disabled 1 = enabled Reserved Mono Mixer Enable 0 = disabled 1 = enabled Speaker Mixer Enable 0 = disabled 1 = enabled Reserved DAC enable 0 = DAC disabled 1 = DAC enabled BCLK polarity 0=normal 1=inverted Frame clock polarity 0=normal 1=inverted DSP Mode control 1 = Reserved 0 = Configures the interface so that MSB is available on 2nd BCLK rising edge after FRAME rising edge 6:5 WL 10 Word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits Audio interface Data Format Select: 00=Right Justified 01=Left Justified 10=I2S format 11= DSP/PCM mode DESCRIPTION WM8974 REFER TO Analogue Outputs 6 SPKNEN 0 Analogue Outputs 5 SPKPEN 0 Analogue Outputs 4 3 MONOMIXEN 0 0 Analogue Outputs 2 SPKMIXEN 0 Analogue Outputs 1 0 DACEN 0 0 Analogue Outputs 4 (04h) 8 BCP 0 Digital Audio Interfaces Digital Audio Interfaces 7 FRAMEP 0 Digital Audio Interfaces 4:3 FMT 10 Digital Audio Interfaces 2 DACLRSWAP 0 Controls whether DAC data appears in ‘right’ or ‘left’ phases of Digital Audio FRAME clock: Interfaces 0=DAC data appear in ‘left’ phase of FRAME 1=DAC data appears in ‘right’ phase of FRAME Controls whether ADC data appears in ‘right’ or ‘left’ phases of Digital Audio FRAME clock: Interfaces 0=ADC data appear in ‘left’ phase of FRAME 1=ADC data appears in ‘right’ phase of FRAME Reserved Reserved DAC companding 00=off 01=reserved 10=µ-law 11=A-law Digital Audio Interfaces 1 ADCLRSWAP 0 0 5 (05h) 8:5 4:3 DAC_COMP 0 0000 00 w PD Rev 4.2 March 2007 67 WM8974 REGISTER ADDRESS BIT 2:1 LABEL ADC_COMP DEFAULT 00 ADC companding 00=off 01=reserved 10=µ-law 11=A-law Digital loopback function 0=No loopback 1=Loopback enabled, ADC data output is fed directly into DAC data input. Controls the source of the clock for all internal operation: 0=MCLK 1=PLL output Sets the scaling for either the MCLK or PLL clock output (under control of CLKSEL) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 Configures the BCLK and FRAME output frequency, for use when the chip is master over BCLK. 000=divide by 1 (BCLK=MCLK) 001=divide by 2 (BCLK=MCLK/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved Reserved Sets the chip to be master over FRAME and BCLK 0=BCLK and FRAME clock are inputs 1=BCLK and FRAME clock are outputs generated by the WM8974 (MASTER) Reserved Approximate sample rate (configures the coefficients for the internal digital filters): 000=48kHz 001=32kHz 010=24kHz 011=16kHz 100=12kHz 101=8kHz 110-111=reserved Reserved Reserved PLL Output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4 DESCRIPTION Production Data REFER TO Digital Audio Interfaces 0 LOOPBACK 0 Digital Audio Interfaces 6 (06h) 8 CLKSEL 1 Digital Audio Interfaces Digital Audio Interfaces 7:5 MCLKDIV 010 4:2 BCLKDIV 000 Digital Audio Interfaces 1 0 MS 0 0 Digital Audio Interfaces 7 (07h) 8:4 3:1 SR 00000 000 Audio Sample Rates 0 8 (08h) 8:6 5:4 OPCLKDIV 0 000 00 General Purpose Input Output w PD Rev 4.2 March 2007 68 Production Data REGISTER ADDRESS 3 BIT LABEL GPIOPOL DEFAULT 0 GPIO Polarity invert 0=Non inverted 1=Inverted CSB/GPIO pin function select: 000=CSB input 001= Jack insert detect 010=Temp ok 011=Amute active 100=PLL clk o/p 101=PLL lock 110=Reserved 111=Reserved Reserved 00 DACMU 0 Reserved DAC soft mute enable 0 = DACMU disabled 1 = DACMU enabled De-Emphasis Control 00 = No de-emphasis 01 = 32kHz sample rate 10 = 44.1kHz sample rate 11 = 48kHz sample rate DAC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) DAC auto mute enable 0 = auto mute disabled 1 = auto mute enabled Reserved DAC Polarity Invert 0 = No inversion 1 = DAC output inverted Reserved DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Reserved Reserved HPFEN 1 High Pass Filter Enable 0=disabled 1=enabled Select audio mode or application mode 0=Audio mode (1st order, fc = ~3.7Hz) 1=Application mode (2nd order, fc = HPFCUT) Application mode cut-off frequency See Table 11 for details. ADC oversample rate select 0 = 64x (lowest power) 1 = 128x (best SNR) Reserved DESCRIPTION WM8974 REFER TO General Purpose Input Output General Purpose Input Output 2:0 GPIOSEL 000 9 (09h) 10 (0Ah) 8:0 8:7 6 Output Signal Path 5:4 DEEMPH 00 Output Signal Path 3 DACOSR128 0 Power Management Output Signal Path 2 AMUTE 0 1 0 DACPOL 0 0 Output Signal Path 11 (0Bh) 8 7:0 DACVOL 0 11111111 Output Signal Path 12 (0Ch) 13 (0Dh) 14 (0Eh) 8:0 8:0 8 Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) Power Management 7 HPFAPP 0 6:4 3 HPFCUT ADCOSR128 000 0 2:1 00 w PD Rev 4.2 March 2007 69 WM8974 REGISTER ADDRESS 0 BIT LABEL ADCPOL DEFAULT 0 ADC Polarity 0=normal 1=inverted Reserved ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Reserved Reserved EQMODE 1 0 EQ1C 01 0 = Equaliser applied to ADC path 1 = Equaliser applied to DAC path Reserved EQ Band 1 Cut-off Frequency: 00=80Hz 01=105Hz 10=135Hz 11=175Hz 4:0 19 (13h) 8 EQ1G EQ2BW 01100 0 EQ Band 1 Gain Control. See Table 35 for details. Band 2 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth Reserved Band 2 Centre Frequency: 00=230Hz 01=300Hz 10=385Hz 11=500Hz 4:0 20 (14h) 8 EQ2G EQ3BW 01100 0 Band 2 Gain Control. See Table 35 for details. Band 3 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth Reserved Band 3 Centre Frequency: 00=650Hz 01=850Hz 10=1.1kHz 11=1.4kHz 4:0 21 (15h) 8 EQ3G EQ4BW 01100 0 Band 3 Gain Control. See Table 35 for details. Band 4 Bandwidth Control 0=narrow bandwidth 1=wide bandwidth Reserved Band 4 Centre Frequency: 00=1.8kHz 01=2.4kHz 10=3.2kHz 11=4.1kHz 4:0 22 (16h) 8:7 EQ4G 01100 00 Band 4 Gain Control. See Table 35 for details. Reserved DESCRIPTION Production Data REFER TO Analogue to Digital Converter (ADC) 15 (0Fh) 8 7:0 ADCVOL 0 11111111 Analogue to Digital Converter (ADC) 16 (10h) 17 (11h) 18 (12h) 8:0 8:0 8 7 6:5 Output Signal Path Output Signal Path Output Signal Path Output Signal Path 7 6:5 EQ2C 0 01 Output Signal Path Output Signal Path Output Signal Path 7 6:5 EQ3C 0 01 Output Signal Path Output Signal Path Output Signal Path 7 6:5 EQ4C 0 01 Output Signal Path Output Signal Path w PD Rev 4.2 March 2007 70 Production Data REGISTER ADDRESS BIT 6:5 LABEL EQ5C DEFAULT 01 DESCRIPTION Band 5 Cut-off Frequency: 00=5.3kHz 01=6.9kHz 10=9kHz 11=11.7kHz 4:0 24 (18h) 8 EQ5G LIMEN 01100 0 Band 5 Gain Control. See Table 35 for details. Enable the DAC digital limiter: 0=disabled 1=enabled DAC Limiter Decay time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms 1011 to 1111=1.536s 3:0 LIMATK 0010 DAC Limiter Attack time (per 6dB gain change) for 44.1kHz sampling. Note that these will scale with sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms 25 (19h) 8:7 6:4 LIMLVL 00 000 Reserved DAC Limiter Programmable signal threshold level (determines level at which the limiter starts to operate) 000=-1dB 001=-2dB 010=-3dB 011=-4dB 100=-5dB 101 to 111=-6dB WM8974 REFER TO Output Signal Path Output Signal Path Output Signal Path 7:4 LIMDCY 0011 Output Signal Path Output Signal Path Output Signal Path w PD Rev 4.2 March 2007 71 WM8974 REGISTER ADDRESS BIT 3:0 LABEL LIMBOOST DEFAULT 0000 DESCRIPTION DAC Limiter volume boost (can be used as a stand alone volume boost when LIMEN=0): 0000=0dB 0001=+1dB 0010=+2dB … (1dB steps) 1011=+11dB 1100=+12dB 1101 to 1111=reserved 27 (1Bh) 8 7 NFU NFEN 0 0 Production Data REFER TO Output Signal Path Notch filter update. The notch filter values used internally only Analogue to Digital update when one of the NFU bits is set high. Converter (ADC) Notch filter enable: 0=Disabled 1=Enabled Notch Filter a0 coefficient, bits [13:7] Analogue to Digital Converter (ADC) Analogue to Digital Converter (ADC) 6:0 28 (1Ch) 8 7 6:0 29 (1Dh) 8 7 6:0 30 (1Eh) 8 7 6:0 32 (20h) 8 NFA0[13:7] NFU 0000000 0 0 Notch filter update. The notch filter values used internally only Analogue to Digital update when one of the NFU bits is set high. Converter (ADC) Reserved Notch Filter a0 coefficient, bits [6:0] Analogue to Digital Converter (ADC) NFA0[6:0] NFU 0000000 0 0 Notch filter update. The notch filter values used internally only Analogue to Digital update when one of the NFU bits is set high. Converter (ADC) Reserved Notch Filter a1 coefficient, bits [13:7] Analogue to Digital Converter (ADC) NFA1[13:7] NFU 0000000 0 0 Notch filter update. The notch filter values used internally only Analogue to Digital update when one of the NFU bits is set high. Converter (ADC) Reserved Notch Filter a1 coefficient, bits [6:0] ALC function select: 0=ALC off (PGA gain set by INPPGAVOL register bits) 1=ALC on (ALC controls PGA gain) Reserved Set Maximum Gain of PGA when using ALC: 111=+35.25dB 110=+29.25dB 101=+23.25dB 100=+17.25dB 011=+11.25dB 010=+5.25dB 001=-0.75dB 000=-6.75dB Set minimum gain of PGA when using ALC: 000=-12dB 001=-6dB 010=0dB 011=+6dB 100=+12dB 101=+18dB 110=+24dB 111=+30dB Analogue to Digital Converter (ADC) Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC) NFA1[6:0] ALCSEL 0000000 0 7:6 5:3 ALCMAX 111 2:0 ALCMIN 000 Input Limiter / Automatic Level Control (ALC) w PD Rev 4.2 March 2007 72 Production Data REGISTER ADDRESS 33 (21h) 8 BIT LABEL ALCZC DEFAULT 0 DESCRIPTION ALC zero cross detection. 0 = disabled 1 = enabled ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms … (time doubles with every step) 1111 = 43.691s ALC target – sets signal level at ADC input 0000 = -28.5dB FS 0001 = -27.0dB FS … (1.5dB steps) 1110 = -7.5dB FS 1111 = -6dB FS Determines the ALC mode of operation: 0=ALC mode 1=Limiter mode. Decay (gain ramp-up) time (ALCMODE =0) Per step 0000 0001 0010 1010 or higher 0011 410us 820us 1.64ms 420ms Per 6dB 3.3ms 6.6ms 13.1ms 3.36s 90% of range 24ms 48ms 192ms 24.576s WM8974 REFER TO Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC) 7:4 ALCHLD 000 3:0 ALCLVL 1011 Input Limiter / Automatic Level Control (ALC) 34 (22h) 8 ALCMODE 0 Input Limiter / Automatic Level Control (ALC) Input Limiter / Automatic Level Control (ALC) 7:4 ALCDCY 0011 … (time doubles with every step) Decay (gain ramp-up) time (ALCMODE =1) Per step 0000 0001 0010 1010 90.8us 181.6us 363.2us 93ms Per 6dB 726.4us 1.453ms 2.905ms 744ms 90% of range 5.26ms 10.53ms 21.06ms 5.39s Input Limiter / Automatic Level Control (ALC) … (time doubles with every step) 3:0 ALCATK 0010 ALC attack (gain ramp-down) time (ALCMODE = 0) Per step 0000 0001 0010 1010 or higher 0010 104us 208us 416us 106ms Per 6dB 832us 1.664ms 3.328ms 852ms 90% of range 6ms 12ms 24.1ms 6.18s … (time doubles with every step) ALC attack (gain ramp-down) time (ALCMODE = 1) Per step 0000 0001 0010 1010 22.7us 45.4us 90.8us 23.2ms Per 6dB 182.4us 363.2us 726.4us 186ms 90% of range 1.31ms 2.62ms 5.26ms 1.348s Input Limiter / Automatic Level Control (ALC) PD Rev 4.2 March 2007 73 … (time doubles with every step) 35 (23h) 8:4 3 NGEN 00000 0 Reserved ALC Noise gate function enable 1 = enable 0 = disable w WM8974 REGISTER ADDRESS BIT 2:0 LABEL NGTH DEFAULT 000 DESCRIPTION ALC Noise gate threshold: 000=-39dB 001=-45dB 010=-51db … (6dB steps) 111=-81dB Reserved 0 = MCLK input not divided (default) 1 = Divide MCLK by 2 before input PLL Integer (N) part of PLL input/output frequency ratio. Use values greater than 5 and less than 13. Reserved Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Fractional (K) part of PLL1 input/output frequency ratio (treat as one 24-digit binary number). Reserved Attenuation control for bypass path (output of input boost stage) to mono mixer input 0 = 0dB 1 = -10dB Attenuation control for bypass path (output of input boost stage) to speaker mixer input 0 = 0dB 1 = -10dB Reserved Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.65 * AVDD Reserved Auxiliary Input Mode 0 = inverting buffer 1 = mixer (on-chip input resistor bypassed) Select AUX amplifier output as input PGA signal source. 0=AUX not connected to input PGA 1=AUX connected to input PGA amplifier negative terminal. Connect MICN to input PGA negative terminal. 0=MICN not connected to input PGA 1=MICN connected to input PGA amplifier negative terminal. Connect input PGA amplifier positive terminal to MICP or VMID. 0 = input PGA amplifier positive terminal connected to VMID 1 = input PGA amplifier positive terminal connected to MICP through variable resistor string Reserved Input PGA zero cross enable: 0=Update gain when gain register changes 1=Update gain on 1st zero cross after gain register write. Production Data REFER TO Input Limiter / Automatic Level Control (ALC) 36 (24h) 8:5 4 PLLPRESCALE 0000 0 Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Master Clock and Phase Locked Loop (PLL) Analogue Outputs 3:0 PLLN[3:0] 1000 37 (25h) 8:6 5:0 PLLK[23:18] 000 001100 38 (26h) 8:0 PLLK[17:9] 010010011 39 (27h) 8:0 PLLK[8:0] 011101001 40 (28h) 8:3 2 MONOATTN 000000 0 1 SPKATTN 0 Analogue Outputs 0 44 (2Ch) 8 MBVSEL 0 0 Input Signal Path 7:4 3 AUXMODE 0000 0 Input Signal Path 2 AUX2INPPGA 0 Input Signal Path 1 MICN2INPPGA 1 Input Signal Path 0 MICP2INPPGA 1 Input Signal Path 45 (2Dh) 8 7 INPPGAZC 0 0 Input Signal Path w PD Rev 4.2 March 2007 74 Production Data REGISTER ADDRESS 6 BIT LABEL INPPGAMUTE DEFAULT 0 DESCRIPTION Mute control for input PGA: 0=Input PGA not muted, normal operation 1=Input PGA muted (and disconnected from the following input BOOST stage). Input PGA volume 000000 = -12dB 000001 = -11.25db . 010000 = 0dB . 111111 = 35.25dB WM8974 REFER TO Input Signal Path 5:0 INPPGAVOL 010000 Input Signal Path 47 (2Fh) 8 PGABOOST 0 Input Boost Input Signal Path 0 = PGA output has +0dB gain through input BOOST stage. 1 = PGA output has +20dB gain through input BOOST stage. Reserved Controls the MICP pin to the input boost stage (NB, when using this path set MICP2INPPGA=0): 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage … 111=+6dB gain through boost stage Reserved Controls the auxilliary amplifier to the input boost stage: 000=Path disabled (disconnected) 001=-12dB gain through boost stage 010=-9dB gain through boost stage … 111=+6dB gain through boost stage Reserved Mono output boost stage control (see Table 37 for details) 0=No boost (output is inverting buffer) 1=1.5x gain boost Speaker output boost stage control (see Table 37 for details) 0=No boost (outputs are inverting buffers) 1 = 1.5x gain boost Thermal Shutdown Enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled VREF (AVDD/2 or 1.5xAVDD/2) to analogue output resistance 0: approx 1kΩ 1: approx 30 kΩ Reserved Output of auxiliary amplifier to speaker mixer input 0 = not selected 1 = selected Reserved Bypass path (output of input boost stage) to speaker mixer input 0 = not selected 1 = selected Output of DAC to speaker mixer input 0 = not selected 1 = selected Analogue Outputs Analogue Outputs Analogue Outputs Input Signal Path Input Signal Path 7 6:4 0 MICP2BOOSTVOL 000 3 2:0 0 AUX2BOOSTVOL 000 49 (31h) 8:4 3 MONOBOOST 00000 0 2 SPKBOOST 0 Analogue Outputs 1 TSDEN 1 Output Switch 0 VROI 0 Analogue Outputs 50 (32h) 8:6 5 AUX2SPK 000 0 4:2 1 BYP2SPK 000 0 0 DAC2SPK 0 Analogue Outputs w PD Rev 4.2 March 2007 75 WM8974 REGISTER ADDRESS 54 (36h) 8 7 SPKZC 0 Speaker Volume control zero cross enable: 1 = Change gain on zero cross only 0 = Change gain immediately Speaker output mute enable 0=Speaker output enabled 1=Speaker output muted (VMIDOP) Speaker Volume Adjust 111111 = +6dB 111110 = +5dB … (1.0 dB steps) 111001=0dB … 000000=-57dB Reserved MONOOUT Mute Control 0=No mute 1=Output muted. During mute the mono output will output VMID which can be used as a DC reference for a headphone out. Reserved Output of Auxilliary amplifier to mono mixer input: 0 = not selected 1 = selected BIT LABEL DEFAULT DESCRIPTION Production Data REFER TO Analogue Outputs 6 SPKMUTE 0 Analogue Outputs 5:0 SPKVOL 111001 Analogue Outputs 56 (38h) 8:7 6 MONOMUTE 0 0 Analogue Outputs 5:3 2 AUX2MONO 0 0 Analogue Outputs 1 BYP2MONO 0 Bypass path (output of input boost stage) to mono mixer input Analogue Outputs 0 = non selected 1 = selected Output of DAC to mono mixer input 0 = not selected 1 = selected Analogue Outputs 0 DAC2MONO 0 w PD Rev 4.2 March 2007 76 Production Data WM8974 DIGITAL FILTER CHARACTERISTICS PARAMETER ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay ADC High Pass Filter High Pass Filter Corner Frequency -3dB -0.5dB -0.1dB DAC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay Table 63 Digital Filter Characteristics f > 0.546fs 0.546fs -80 29/fs dB +/- 0.035dB -6dB 0 0.5fs +/-0.035 dB 0.454fs 3.7 10.4 21.6 Hz f > 0.546fs 0.546fs -60 21/fs dB +/- 0.025dB -6dB 0 0.5fs +/- 0.025 dB 0.454fs TEST CONDITIONS MIN TYP MAX UNIT TERMINOLOGY 1. 2. 3. Stop Band Attenuation (dB) – the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple – any variation of the frequency response in the pass-band region Note that this delay applies only to the filters and does not include additional delays through other digital circuits. See Table 64 for the total delay. PARAMETER ADC Path Group Delay Total Delay (ADC analogue input to digital audio interface output) DAC Path Group Delay Total Delay (Audio interface input to DAC analogue output) Table 64 Total Group Delay Notes: 1. Wind noise filter is disabled. EQ disabled EQ enabled 34/fs 35/fs 36/fs 37/fs 38/fs 39/fs EQ disabled EQ enabled 26/fs 27/fs 28/fs 29/fs 30/fs 31/fs TEST CONDITIONS MIN TYP MAX UNIT w PD Rev 4.2 March 2007 77 WM8974 DAC FILTER RESPONSES 0.2 0 -20 Response (dB) -40 -60 -80 -100 - 120 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 Production Data 0.15 0.1 Response (dB) 0.05 0 -0.05 -0.1 -0.15 -0.2 0 0.1 0.2 Frequency (Fs) 0.3 0.4 0.5 Figure 36 DAC Digital Filter Frequency Response Figure 37 DAC Digital Filter Ripple ADC FILTER RESPONSES 0.2 0 -20 Response (dB) Response (dB) 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0.2 -40 -60 -80 -100 - 120 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.1 0.2 Frequency (Fs) 0.3 0.4 0.5 Figure 38 ADC Digital Filter Frequency Response Figure 39 ADC Digital Filter Ripple w PD Rev 4.2 March 2007 78 Production Data WM8974 DE-EMPHASIS FILTER RESPONSES 0 -1 -2 -3 R esponse (dB) -4 -5 -6 -7 -8 -9 - 10 0 2000 4000 6000 8000 10000 12000 14000 16000 Frequency (Hz) 0.30 0.25 0.20 R esponse (dB) 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 0 2000 4000 6000 8000 10000 12000 14000 16000 Frequency (Hz) Figure 40 De-emphasis Frequency Response (32kHz) Figure 41 De-emphasis Error (32kHz) 0 -1 -2 -3 R esponse (dB) -4 -5 -6 -7 -8 -9 - 10 0 5000 10000 Frequency (Hz) 15000 20000 0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 0 5000 10000 Frequency (Hz) 15000 20000 Figure 42 De-emphasis Frequency Response (44.1kHz) 0 -1 -2 -3 R esponse (dB) -4 -5 -6 -7 -8 -9 - 10 0 5000 10000 Frequency (Hz) 15000 20000 R esponse (dB) Figure 43 De-emphasis Error (44.1kHz) 0.10 0.08 0.06 0.04 R esponse (dB) 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0 5000 10000 Frequency (Hz) 15000 20000 Figure 44 De-emphasis Frequency Response (48kHz) Figure 45 De-emphasis Error (48kHz) w PD Rev 4.2 March 2007 79 WM8974 HIGHPASS FILTER Production Data The WM8974 has a selectable digital highpass filter in the ADC filter path. This filter has two modes, audio and applications. In audio mode the filter is a 1st order IIR with a cutoff of around 3.7Hz. In applications mode the filter is a 2nd order high pass filter with a selectable cutoff frequency. 5 0 -5 -10 Response (dB) 10 0 -10 Response (dB) 0 5 10 15 20 25 30 35 40 45 Frequency (Hz) -15 -20 -25 -30 -35 -40 -20 -30 -40 -50 - 60 0 200 400 600 Frequency (Hz) 800 1000 1200 Figure 46 ADC Highpass Filter Response, HPFAPP=0 Figure 47 ADC Highpass Filter Responses (48kHz), HPFAPP=1, all cutoff settings shown. 10 0 -10 Response (dB) 10 0 -10 -20 -30 -40 -50 -60 -20 Response (dB) -30 -40 -50 -60 -70 -80 0 200 400 600 Frequency (Hz) 800 1000 1200 -70 -80 -90 0 200 400 600 Frequency (Hz) 800 1000 1200 Figure 48 ADC Highpass Filter Responses (24kHz), HPFAPP=1, all cutoff settings shown. Figure 49 ADC Highpass Filter Responses (12kHz), HPFAPP=1, all cutoff settings shown. w PD Rev 4.2 March 2007 80 Production Data WM8974 The WM8974 has a 5-band equaliser which can be applied to either the ADC path or the DAC path. The plots from Figure 50 to Figure 63 show the frequency responses of each filter with a sampling frequency of 48kHz, firstly showing the different cut-off/centre frequencies with a gain of ±12dB, and secondly a sweep of the gain from -12dB to +12dB for the lowest cut-off/centre frequency of each filter. 5-BAND EQUALISER 15 15 10 10 5 Magnitude (dB) 5 Magnitude (dB) 10 0 0 0 -5 -5 -10 -10 -15 -1 10 10 1 10 Frequency (Hz) 2 10 3 10 4 10 5 -15 -1 10 10 0 10 1 10 Frequency (Hz) 2 10 3 10 4 10 5 Figure 50 EQ Band 1 – Low Frequency Shelf Filter Cut-offs Figure 51 EQ Band 1 – Gains for Lowest Cut-off Frequency 15 15 10 10 5 Magnitude (dB) 5 Magnitude (dB) 10 0 0 0 -5 -5 -10 -10 -15 -1 10 10 1 10 Frequency (Hz) 2 10 3 10 4 10 5 -15 -1 10 10 0 10 1 10 Frequency (Hz) 2 10 3 10 4 10 5 Figure 52 EQ Band 2 – Peak Filter Centre Frequencies, EQ2BW=0 15 Figure 53 EQ Band 2 – Peak Filter Gains for Lowest Cut-off Frequency, EQ2BW=0 10 5 Magnitude (dB) 0 -5 -10 -15 -2 10 10 -1 10 0 10 Frequency (Hz) 1 10 2 10 3 10 4 Figure 54 EQ Band 2 – EQ2BW=0, EQ2BW=1 w PD Rev 4.2 March 2007 81 WM8974 Production Data 15 15 10 10 5 Magnitude (dB) Magnitude (dB) 0 1 2 3 4 5 5 0 0 -5 -5 -10 -10 -15 -1 10 10 10 10 Frequency (Hz) 10 10 10 -15 -1 10 10 0 10 1 10 Frequency (Hz) 2 10 3 10 4 10 5 Figure 55 EQ Band 3 – Peak Filter Centre Frequencies, EQ3BW=0 15 Figure 56 EQ Band 3 – Peak Filter Gains for Lowest Cut-off Frequency, EQ3BW=0 10 5 Magnitude (dB) 0 -5 -10 -15 -2 10 10 -1 10 0 10 Frequency (Hz) 1 10 2 10 3 10 4 Figure 57 EQ Band 3 – EQ3BW=0, EQ3BW=1 w PD Rev 4.2 March 2007 82 Production Data WM8974 15 15 10 10 5 Magnitude (dB) Magnitude (dB) 0 1 2 3 4 5 5 0 0 -5 -5 -10 -10 -15 -1 10 10 10 10 Frequency (Hz) 10 10 10 -15 -1 10 10 0 10 1 10 Frequency (Hz) 2 10 3 10 4 10 5 Figure 58 EQ Band 4 – Peak Filter Centre Frequencies, EQ3BW=0 15 Figure 59 EQ Band 4 – Peak Filter Gains for Lowest Cut-off Frequency, EQ4BW=0 10 5 Magnitude (dB) 0 -5 -10 -15 -2 10 10 -1 10 0 10 Frequency (Hz) 1 10 2 10 3 10 4 Figure 60 15 EQ Band 4 – EQ3BW=0, EQ3BW=1 15 10 10 5 Magnitude (dB) Magnitude (dB) 0 1 2 3 4 5 5 0 0 -5 -5 -10 -10 -15 -1 10 10 10 10 Frequency (Hz) 10 10 10 -15 -1 10 10 0 10 1 10 Frequency (Hz) 2 10 3 10 4 10 5 Figure 61 EQ Band 5 – High Frequency Shelf Filter Cut-offsFigure 62 EQ Band 5 – Gains for Lowest Cut-off Frequency w PD Rev 4.2 March 2007 83 WM8974 Production Data Figure 63 shows the result of having the gain set on more than one channel simultaneously. The blue traces show each band (lowest cut-off/centre frequency) with ±12dB gain. The red traces show the cumulative effect of all bands with +12dB gain and all bands -12dB gain, with EQxBW=0 for the peak filters. 20 15 10 Magnitude (dB) 5 0 -5 -10 -15 -1 10 10 0 10 1 10 Frequency (Hz) 2 10 3 10 4 10 5 Figure 63 Cumulative Frequency Boost/Cut w PD Rev 4.2 March 2007 84 Production Data WM8974 APPLICATIONS INFORMATION RECOMMENDED EXTERNAL COMPONENTS Figure 64 Recommended External Components w PD Rev 4.2 March 2007 85 WM8974 PACKAGE DIAGRAM FL: 24 PIN QFN PLASTIC PACKAGE 4 X 4 X 0.9 mm BODY, 0.50 mm LEAD PITCH DETAIL 1 D2 19 24 D Production Data DM045.A 18 EXPOSED GROUND 6 PADDLE 1 4 E2 INDEX AREA (D/2 X E/2) E A SEE DETAIL 2 13 12 e 6 2X 7 b 1 bbb M C A B 2X aaa C aaa C TOP VIEW BOTTOM VIEW ccc C A3 A 0.08 C 5 DETAIL 1 DETAIL 2 45 degrees Datum L 1 e R L1 Terminal tip e/2 C SEATING PLANE SIDE VIEW A1 DETAIL 2 0.32mm EXPOSED GROUND PADDLE W T A3 H b Exposed lead G Half etch tie bar DETAIL 2 Symbols A A1 A3 b D D2 E E2 e G H L L1 T W aaa bbb ccc REF: MIN 0.80 0 0.18 2.55 2.55 Dimensions (mm) NOM MAX NOTE 0.90 1.00 0.02 0.05 0.20 REF 1 0.25 0.30 4.00 2.70 4.00 2.70 0.50 BSC 0.213 0.1 0.40 0.1 0.2 2.80 2.80 2 2 0.30 0.03 0.50 0.15 7 Tolerances of Form and Position 0.15 0.10 0.10 JEDEC, MO-220, VARIATION VGGD-2. NOTES: 1. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. FALLS WITHIN JEDEC, MO-220, VARIATION VGGD-2. 3. ALL DIMENSIONS ARE IN MILLIMETRES. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JEDEC 95-1 SPP-002. 5. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 6. REFER TO APPLICATIONS NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING. 7. DEPENDING ON THE METHOD OF LEAD TERMINATION AT THE EDGE OF THE PACKAGE, PULL BACK (L1) MAY BE PRESENT. 8. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. w PD Rev 4.2 March 2007 86 Production Data WM8974 IMPORTANT NOTICE W olfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current. Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty. Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product. Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. Any use of products by the customer for such purposes is at the customer’s own risk. Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner. Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. ADDRESS: W olfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com w PD Rev 4.2 March 2007 87