X20C05J-35

APPLICATION NOTE AVAILABLE X20C05 4K AN56 X20C05 High Speed AUTOSTORE™ NOVRAM 512 x 8 FEATURES DESCRIPTION The Xicor X20C05 is a 512 x 8 NOVRAM featuring a high-speed static RAM overlaid bit-for-bit with a nonvolatile electrically erasable PROM (E2PROM). The X20C05 is fabricated with advanced CMOS floating gate technology to achieve high speed with low power and wide power-supply margin. The X20C05 features the JEDEC approved pinout for byte-wide memories, compatible with industry standard RAMs, ROMs, EPROMs, and E2PROMs. The NOVRAM design allows data to be easily transferred from RAM to E2PROM (store) and E2PROM to RAM (recall). The store operation is completed in 5ms or less and the recall operation is completed in 5µs or less. Xicor NOVRAMS are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM, and a minimum 1,000,000 store operations to the E2PROM. Data retention is specified to be greater than 100 years. • • • • • • • • Fast Access Time: 35ns, 45ns, 55ns High Reliability —Endurance: 1,000,000 Nonvolatile Store Operations —Retention: 100 Years Minimum Power-on Recall —E2PROM Data Automatically Recalled Into SRAM Upon Power-up AUTOSTORE™ NOVRAM —User Enabled Option —Automatically Stores SRAM Data Into the E2PROM Array When VCC Low Threshold is Detected —Open Drain AUTOSTORE Status Output Pin Software Data Protection —Locks Out Inadvertent Store Operations Low Power CMOS —Standby: 250µA Infinite E2PROM Array Recall, and RAM Read and Write Cycles Upward compatible with X20C16 (16K) PIN CONFIGURATION PLASTIC CERDIP NC A7 LCC PLCC VCC WE NC NE AS NE NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 X20C05 21 20 19 18 17 16 15 VCC WE AS A8 NC NC OE NC CE I/O7 I/O6 I/O5 I/O4 I/O3 A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 4 3 2 1 32 31 30 29 28 27 26 A8 NC NC NC OE NC CE I/O7 I/O6 7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 V X20C05 (TOP VIEW) 25 24 23 22 10 11 12 13 21 14 15 16 17 18 19 20 I/O1 I/O2 NC I/O3 I/O4 VSS I/O5 3827 FHD F02 3827 FHD F03 AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc. ©Xicor, Inc. 1991 - 1997 Patents Pending 3827-2.7 7/31/97 T4/C0/D0 SH 1 Characteristics subject to change without notice X20C05 PIN DESCRIPTIONS Addresses (A0–A8) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read and recall operations. Output Enable LOW disables a store operation regardless of the state of CE, WE, or NE. Data In/Data Out (I/O0–I/O7) Data is written to or read from the X20C05 through the I/O pins. The I/O pins are placed in the high impedance state when either CE or OE is HIGH or when NE is LOW. Write Enable (WE) The Write Enable input controls the writing of data to the RAM. FUNCTIONAL DIAGRAM AS VCC SENSE EEPROM ARRAY Nonvolatile Enable (NE) The Nonvolatile Enable input controls the recall function to the E2PROM array. AUTOSTORE Output (AS) AS is an open drain output which, when asserted indicates VCC has fallen below the AUTOSTORE threshold (VASTH). AS may be wire-ORed with multiple open drain outputs and used as an interrupt input to a microcontroller. PIN NAMES Symbol A0–A8 I/O0–I/O7 WE CE OE NE AS VCC VSS NC Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable Nonvolatile Enable AUTOSTORE Output +5V Ground No Connect 3827 PGM T01 A3–A6 ROW SELECT CE OE WE NE A0–A2 A7–A8 COLUMN SELECT & I/OS CONTROL LOGIC I/O0–I/O7 ST O HIGH SPEED 512 x 8 SRAM ARRAY R R E EC AL L 3827 FHD F01 2 X20C05 DEVICE OPERATION The CE, OE, WE and NE inputs control the X20C05 operation. The X20C05 byte-wide NOVRAM uses a 2-line control architecture to eliminate bus contention in a system environment. The I/O bus will be in a high impedance state when either OE or CE is HIGH, or when NE is LOW. RAM Operations RAM read and write operations are performed as they would be with any static RAM. A read operation requires CE and OE to be LOW with WE and NE HIGH. A write operation requires CE and WE to be LOW with NE HIGH. There is no limit to the number of read or write operations performed to the RAM portion of the X20C05. MEMORY TRANSFER OPERATIONS There are two memory transfer operations: a recall operation whereby the data stored in the E2PROM array is transferred to the RAM array; and a store operation which causes the entire contents of the RAM array to be stored in the E2PROM array. Recall operations are performed automatically upon power-up and under host system control when NE, OE and CE are LOW and WE is HIGH. The recall operation takes a maximum of 5µs. There are two methods of initiating a store operation. The first is the software store command. This command takes the place of the hardware store employed on the X20C04. This command is issued by entering into the special command mode: NE, CE, and WE strobe LOW while at the same time a specific address and data combination is sent to the device. This is a three step operation: the first address/data combination is 155[H]/AA[H]; the second combination is 0AA[H]/55[H]; and the final command combination is 155[H]/33[H]. This sequence of pseudo write operations will immediately initiate a store operation. Refer to the software command timing diagrams for details on set and hold times for the various signals. The second method of storing data is through the AUTOSTORE command. When enabled, data is automatically stored from the RAM into the E2PROM array whenever VCC falls below the preset AUTOSTORE threshold. This feature is enabled by performing the first two steps for the software store with the command combination being 155[H]/CC[H]. The AUTOSTORE feature is disabled by issuing the three step command sequence with the command combination being 155[H]/CD[H]. The AUTOSTORE feature will also be reset if VCC falls below the power-up reset threshold (approximately 3.5V) and is then raised back into the operating range. DATA PROTECTION The X20C05 supports two methods of protecting the nonvolatile data. —If after power-up the AUTOSTORE feature is not enabled, no AUTOSTORE can occur. —If after power-up no RAM write operations have occurred no store operation can be initiated. The software store and AUTOSTORE commands will be ignored. SYMBOL TABLE WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance 3 X20C05 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................. –65°C to +135°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS ....................................... –1V to +7V D.C. Output Current ........................................... 10mA Lead Temperature (Soldering, 10 seconds)...... 300°C RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Military Min. 0°C –40°C –55°C Max. +70°C +85°C +125°C 3827 PGM T02.1 *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Supply Voltage X20C05 Limits 5V ± 10% 3827 PGM T03.1 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol lCC1 Parameter VCC Current (Active) Min. Max. 100 Units mA Test Conditions NE = WE = VIH, CE = OE = VIL Address Inputs = 0.4V/2.4V Levels @ f = 20MHz. All I/Os = Open All Inputs = VIH All I/Os = Open CE = VIH All Other Inputs = VIH, All I/Os = Open All Inputs = VCC – 0.3V All I/Os = Open VIN = VSS to VCC VOUT = VSS to VCC, CE = VIH ICC2 ICC3 ISB1 ISB2 ILI ILO VIL(1) VIH(1) VOL VOLAS VOH VCC Current During Store VCC Current During AUTOSTORE VCC Standby Current (TTL Input) VCC Standby Current (CMOS Input) Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage AUTOSTORE Output Output HIGH Voltage 5 2.5 10 250 10 10 0.8 VCC + 0.5 0.4 0.4 mA mA mA µA µA µA V V V V V –1 2 2.4 IOL = 4mA IOLAS = 1mA IOH = –4mA 3827 PGM T04.3 POWER-UP TIMING Symbol tPUR(2) tPUW(2) Parameter Power-Up to RAM Operation Power-Up to Nonvolatile Operation Max. 100 5 Units µs ms 3827 PGM T05 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V. Symbol CI/O(2) CIN(2) Test Input/Output Capacitance Input Capacitance Max. 10 6 Units pF pF Conditions VI/O = 0V VIN = 0V 3827 PGM T06.2 Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. 4 X20C05 ENDURANCE AND DATA RETENTION Parameter Endurance Store Cycles Data Retention MODE SELECTION CE H L L L L L L L L WE X H L L H L H L H NE X H H H L L H L L OE X L H H L H H L H Mode Not Selected Read RAM Write “1” RAM Write “0” RAM Array Recall Software Command Output Disabled Not Allowed No Operation I/O Output High Z Output Data Input Data High Input Data Low Output High Z Input Data Output High Z Output High Z Output High Z A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels 30pF Min. 100,000 1,000,000 100 Units Data Changes Per Bit Store Cycles Years 3827 PGM T07.1 Power Standby Active Active Active Active Active Active Active Active 3827 PGM T09 EQUIVALENT A.C. LOAD CIRCUIT 5V 735Ω OUTPUT 318Ω 0V to 3V 5ns 1.5V 3827 PGM T08.2 3827 FHD F04 5 X20C05 A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Read Cycle Limits X20C05-35 Symbol tRC tCE tAA tOE tLZ(3) tOLZ(3) tHZ(3) tOHZ(3) tOH Read Cycle tRC ADDRESS tCE CE tOE OE VIH WE tOLZ tLZ DATA I/O DATA VALID tAA 3827 FHD F05 X20C05-45 Min. 45 Max. 45 45 25 0 0 X20C05-55 Min. 55 55 55 30 0 0 Max. Units ns ns ns ns ns ns ns ns ns 3827 PGM T10 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold From Address Change Min. 35 Max. 35 35 20 0 0 15 15 0 20 20 0 0 25 25 tOHZ tOH tHZ DATA VALID Note: (3) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ and tOHZ are measured, with CL = 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the outptus are no longer driven. 6 X20C05 Write Cycle Limits X20C05-25 X20C05-35 X20C05-45 X20C05-55 Symbol tWC tCW tAS tWP tWR tDW tDH tWZ(4) tOW(4) tOZ(4) Parameter Write Cycle Time Chip Enable to End of Write Input Address Setup Time Write Pulse Width Write Recovery Time Data Setup to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write Output Enable to Output in High Z Min. 25 25 0 30 0 15 0 5 Max. Min. Max. Min. Max. Min. Max. Units 35 30 0 30 0 15 0 15 5 15 5 20 45 35 0 35 0 20 3 20 5 25 55 40 0 40 0 25 3 25 ns ns ns ns ns ns ns ns ns ns 3827 PGM T11 WE Controlled Write Cycle tWC ADDRESS OE tCW CE tAS WE tOZ DATA OUT tDW DATA IN DATA VALID 3827 FHD F06 tWP tWR tOW tDH Note: (4) tWZ, tOW and tOZ are periodically sampled and not 100% tested. 7 X20C05 CE Controlled Write Cycle tWC ADDRESS OE VIH tCW CE tAS WE tWZ DATA OUT tDW DATA IN DATA VALID tDH tOW tWP tWR 3827 FHD F07.1 8 X20C05 Array Recall Cycle Limits X20C05-35 Symbol tRCC tRCP(5) tRWE Parameter Array Recall Cycle Time Recall Pulse Width to Initiate Recall WE Setup Time to NE Min. 30 0 Max. 5 1000 X20C05-45 Min. 40 0 Max. 5 1000 X20C05-55 Min. 50 0 Max. 5 1000 Units µs ns ns 3827 PGM T13.1 Array Recall Cycle tRCC ADDRESS tRCP NE OE tRWE WE CE DATA I/O 3827 FHD F10 Note: (5) The Recall Pulse Width (tRCP) is a minimum time that NE, OE and CE must be LOW simultaneously to insure data integrity, NE and CE. 9 X20C05 Software Command Timing Limits X20C05-35 Symbol tSTO tSP(6) tSPH tWC tAS tAH tDS tDH tSOE(7) tOEST(7) tNHZ(7) tNES tNEH Parameter Store Cycle Time Store Pulse Width Store Pulse Hold Time Write Cycle Time Address Setup Time Address Hold time Data Setup Time Data Hold Time OE Disable to Store Function Output Enable from End of Store Nonvolatile Enable to Output in High Z NE Setup Time NE Hold Time Min. 30 35 35 0 0 15 0 20 10 15 5 5 5 5 Max. 5 40 45 45 0 0 20 3 20 10 20 5 5 X20C05-45 Min. Max. 5 50 55 55 0 0 25 3 20 10 25 X20C05-55 Min. Max. 5 Units ms ns ns ns ns ns ns ns ns ns ns ns ns 3827 PGM T12.1 CE Controlled Software Command Sequence tWC ADDRESS 155 0AA 155 tSTO OE tAS CE tAH WE tNES NE tSOE DATA OUT tDS DATA IN AA tDH 55 CMD tNHZ tNEH tSP tSPH tOEST 3827 FHD F08.2 Notes: (6) The Store Pulse Width (tSP) is a minimum time that NE, WE and CE must be LOW simultaneously. (7) tSOE, tOEST and tNHZ are periodically sampled and not 100% tested. 10 X20C05 WE Controlled Software Command Sequence tWC ADDRESS 155 0AA 155 tSTO OE tOEST CE tAS WE tNES NE tSOE DATA OUT tDS DATA IN AA tDH 55 CMD tNHZ tNEH tSP tAH tSPH 3827 FHD F09.2 11 X20C05 AUTOSTORE Feature The AUTOSTORE feature automatically saves the contents of the X20C05’s RAM to the on-board bit-for-bit shadow E2PROM at power-down. This circuitry insures that no data is lost during accidental power-downs or general system crashes, and is ideal for microprocessor caching systems, embedded software systems, and general system back-up memory. The AUTOSTORE instruction (EAS) to the SDP register sets the AUTOSTORE enable latch, allowing the X20C05 AUTOSTORE CYCLE Timing Diagrams 5 VOLTS (V) to automatically perform a store operation whenever VCC falls below the AUTOSTORE threshold (VASTH). VCC must remain above the AUTOSTORE Cycle End Voltage (VASEND) for the duration of the store cycle (tASTO). The detailed timing for this feature is illustrated in the AUTOSTORE timing diagram, below. Once the AUTOSTORE cycle is initiated, all other device functions are inhibited. VCC V AUTOSTORE CYCLE IN PROGRESS ASTH VASEND tASTO STORE TIME 4 3 2 1 TIME (ms) VCC VASTH 0V tPUR tASTO tPUR AS 3827 FHD F14 AUTOSTORE CYCLE LIMITS X20C05 Symbol tASTO VASTH VASEND Parameter AUTOSTORE Cycle Time AUTOSTORE Threshold Voltage AUTOSTORE Cycle End Voltage Min. 4.0 3.5 Max. 2.5 4.3 Units ms V V 3827 PGM T15 12 X20C05 SDP (Software Data Protection) Store State Diagram POWER UP POWER UP NO STORE RAM Write or Recall S0 ADDR 155, DATA AA Power Down Power On Recall ADDR 155, DATA AA S1 Software Store Enabled SS NO STORE RAS ADDR 155, DATA AA EAS ADDR 0AA, DATA 55 S2 NO STORE Software Store & AUTOSTORE Power Down Enabled (AUTOSTORE) WRITE: ADDR 555, DATA=COMMAND STORE ON SS OR ENABLE / RESET AUTOSTORE EAS SS 3827 FHD F13.1 3827 FHD F12.1 SOFTWARE DATA PROTECTION COMMANDS Command EAS RAS SS Enable AUTOSTORE Reset AUTOSTORE Software Store Data CC[H] CD[H] 33[H] 3827 PGM T14.1 13 X20C05 NOTES 14 X20C05 PACKAGING INFORMATION 28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D 1.490 (37.85) 1.435 (36.45) 0.610 (15.49) 0.500 (12.70) PIN 1 1.30 (33.02) REF. 0.100 (2.54) 0.035 (0.89) SEATING PLANE 0.200 (5.08) 0.125 (3.18) 0.225 (5.72) 0.140 (3.56) 0.060 (1.52) 0.015 (0.38) 0.110 (2.79) 0.090 (2.29) TYP. 0.100 (2.54) 0.070 (1.78) 0.030 (0.76) TYP. 0.055 (1.40) 0.026 (0.66) 0.014 (0.36) TYP. 0.018 (0.46) 0.620 (15.75) 0.590 (14.99) TYP. 0.614 (15.60) TYP. 0.010 (0.25) 0° 15° NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 15 X20C05 PACKAGING INFORMATION 28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 1.460 (37.08) 1.400 (35.56) 0.550 (13.97) 0.510 (12.95) PIN 1 INDEX PIN 1 1.300 (33.02) REF. 0.085 (2.16) 0.040 (1.02) SEATING PLANE 0.150 (3.81) 0.125 (3.17) 0.160 (4.06) 0.125 (3.17) 0.030 (0.76) 0.015 (0.38) 0.110 (2.79) 0.090 (2.29) 0.062 (1.57) 0.050 (1.27) 0.020 (0.51) 0.016 (0.41) 0.610 (15.49) 0.590 (14.99) TYP. 0.010 (0.25) 0° 15° NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 16 X20C05 PACKAGING INFORMATION 32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E 0.015 (0.38) 0.003 (0.08) 0.150 (3.81) BSC 0.020 (0.51) x 45° REF. PIN 1 0.095 (2.41) 0.075 (1.91) 0.022 (0.56) 0.006 (0.15) 0.200 (5.08) BSC 0.055 (1.39) 0.045 (1.14) TYP. (4) PLCS. 0.028 (0.71) 0.022 (0.56) (32) PLCS. 0.050 (1.27) BSC 0.040 (1.02) x 45° REF. TYP. (3) PLCS. 0.458 (11.63) 0.442 (11.22) 0.458 (11.63) –– 0.300 (7.62) BSC 0.120 (3.05) 0.060 (1.52) 0.088 (2.24) 0.050 (1.27) 0.560 (14.22) 0.540 (13.71) 0.400 (10.16) BSC 0.558 (14.17) –– 32 1 PIN 1 INDEX CORDER NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. TOLERANCE: ±1% NTL ±0.005 (0.127) 17 X20C05 PACKAGING INFORMATION 32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J 0.420 (10.67) 0.050 (1.27) TYP. 0.045 (1.14) x 45° 0.021 (0.53) 0.013 (0.33) TYP. 0.017 (0.43) 0.495 (12.57) 0.485 (12.32) TYP. 0.490 (12.45) 0.453 (11.51) 0.447 (11.35) TYP. 0.450 (11.43) 0.300 (7.62) REF. PIN 1 SEATING PLANE ±0.004 LEAD CO – PLANARITY — 0.015 (0.38) 0.095 (2.41) 0.060 (1.52) 0.140 (3.56) 0.100 (2.45) TYP. 0.136 (3.45) 0.048 (1.22) 0.042 (1.07) 0.595 (15.11) 0.585 (14.86) TYP. 0.590 (14.99) 0.553 (14.05) 0.547 (13.89) TYP. 0.550 (13.97) 0.400 (10.16)REF. 3° TYP. NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY 18 X20C05 ORDERING INFORMATION X20C05 Device X X -X Access Time –35 = 35ns –45 = 45ns –55 = 55ns Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C Package D = 28-Lead Cerdip P = 28 Lead Plastic DIP E = 32-Pad Ceramic LCC J = 32-Lead PLCC LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. 19