X20C17P-35

APPLICATION NOTE AVAILABL E X20C17 16K AN56 X20C17 High Speed AUTOSTORE™ NOVRAM 2K x 8 Bit FEATURES DESCRIPTION The Xicor X20C17 is a 2K x 8 NOVRAM featuring a highspeed static RAM overlaid bit-for-bit with a nonvolatile electrically erasable PROM (E 2 PROM) and the AUTOSTORE feature which automatically saves the RAM contents to E2PROM at power-down. The X20C17 is fabricated with advanced CMOS floating gate technology to achieve high speed with low power and wide power-supply margin. The X20C17 features a compatible JEDEC approved byte-wide memory pinout for industry standard SRAMs. The NOVRAM design allows data to be easily transferred from RAM to E2PROM (store) and E2PROM to RAM (recall). The store operation is completed in 2.5ms or less. An automatic array recall operation reloads the contents of the E2PROM into RAM upon power-up. Xicor NOVRAMS are designed for unlimited write operations to RAM, either from the host or recalls from E2PROM, and a minimum 1,000,000 store operations to the E2PROM. Data retention is specified to be greater than 100 years. • • • • • • 24-Pin Standard SRAM DIP Pinout Fast Access Time: 35ns, 45ns, 55ns High Reliability —Endurance: 1,000,000 Nonvolatile Store Operations —Retention: 100 Years Minimum AUTOSTORE™ NOVRAM —Automatically Stores SRAM Data Into the E2PROM Array When VCC Low Threshold is Detected —E2PROM Data Automatically Recalled Into RAM Upon Power-up Low Power CMOS —Standby: 250µA Infinite E2PROM Array Recall, and RAM Read and Write Cycles PIN CONFIGURATION PLASTIC A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 X20C17 24 23 22 21 20 19 18 17 16 15 14 13 VCC A8 A9 WE OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 2015 ILL F02.1 AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc. ©Xicor, Inc. 1992, 1995 Patents Pending 2015-2.5 8/1/97 T1/C0/D0 SH 1 Characteristics subject to change without notice X20C17 PIN DESCRIPTIONS Addresses (A0–A10) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read and recall operations. Output Enable LOW disables a store operation regardless of the state of CE, WE. Data In/Data Out (I/O0–I/O7) Data is written to or read from the X20C17 through the I/O pins. The I/O pins are placed in the high impedance state when either CE or OE is HIGH. Write Enable (WE) The Write Enable input controls the writing of data to the static RAM. FUNCTIONAL DIAGRAM PIN NAMES Symbol A0–A10 I/O0–I/O7 WE CE OE VCC VSS Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground 2015 PGM T01 VCC SENSE EEPROM ARRAY AL L A3–A8 ROW SELECT CE OE WE CONTROL LOGIC A0–A2 A9–A10 COLUMN SELECT & I/OS I/O0–I/O7 ST O HIGH SPEED 2K x 8 SRAM ARRAY R R E EC 2015 FHD F01.1 2 X20C17 DEVICE OPERATION The CE, OE, and WE inputs control the X20C17 operation. The X20C17 byte-wide NOVRAM uses a 2-line control architecture to eliminate bus contention in a system environment. The I/O bus will be in a high impedance state when either OE or CE is HIGH. RAM Operations RAM read and write operations are performed as they would be with any static RAM. A read operation requires CE and OE to be LOW. A write operation requires CE and WE to be LOW. There is no limit to the number of read or write operations performed to the RAM portion of the X20C17. Memory Transfer Operations There are two memory transfer operations: a recall operation whereby the data stored in the E2PROM array is transferred to the RAM array; and a store operation which causes the entire contents of the RAM array to be stored in the E2PROM array. Recall operations are performed automatically upon power-up. Store operations are performed automatically upon power-down. The store operation take a maximum of 2.5ms. Write Protection The X20C17 supports two methods of protecting the nonvolatile data. —If after power-up no RAM write operations have occured, no AUTOSTORE operation can be initiated. —VCC Sense – All functions are inhibited when VCC is ≤ 3V typical. WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance SYMBOL TABLE The following symbol table provides a key to understanding the conventions used in the device timing diagrams. The diagrams should be used in conjunction with the device timing specifications to determine actual device operation and performance, as well as device suitability for user’s application. 3 X20C17 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias .................. –65°C to +135°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS ....................................... –1V to +7V D.C. Output Current ........................................... 10mA Lead Temperature (Soldering, 10 seconds) ...... 300°C RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Military Min. 0°C –40°C –55°C Max. +70°C +85°C +125°C 2015 PGM T02.1 *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any conditions other than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Supply Voltage X20C17 Limits 4.5V to 5.25V 2015 PGM T03.1 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.) Limits Symbol lCC1 Parameter VCC Current (Active) Min. Max. 100 Units mA Test Conditions WE = VIH, CE = OE = VIL Address Inputs = 0.4V/2.4V Levels @ f = 20MHz, All I/Os = Open All I/Os = Open All Inputs = VIH, All I/Os = Open All Inputs = VCC – 0.3V All I/Os = Open VIN = VSS to VCC VOUT = VSS to VCC, CE = VIH ICC2(2) ISB1 ISB2 ILI ILO VIL(1) VIH(1) VOL VOH VCC Current During AUTOSTORE VCC Standby Current (TTL Input) VCC Standby Current (CMOS Input) Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage 2.5 10 250 10 10 0.8 VCC + 1 0.4 mA mA µA µA µA V V V V –1 2 2.4 IOL = 4mA IOH = –4mA 2015 PGM T04.3 POWER-UP TIMING Symbol tPUR(2) tPUW(2) Parameter Power-Up to RAM Operation Power-Up to Nonvolatile Operation Max. 100 5 Units µs ms 2015 PGM T05 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V. Symbol CI/O(2) CIN(2) Test Input/Output Capacitance Input Capacitance Max. 10 6 Units pF pF Conditions VI/O = 0V VIN = 0V 2015 PGM T06.2 Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. 4 X20C17 ENDURANCE AND DATA RETENTION Parameter Endurance Store Cycles Data Retention MODE SELECTION CE H L L L L L WE X H L L L H OE X L H H L H Mode Not Selected Read RAM Write “1” RAM Write “0” RAM Not Allowed No Operation I/O Output High Z Output Data Input Data High Input Data Low Output High Z Output High Z Power Standby Active Active Active Active Active 2015 PGM T09 Min. 100,000 1,000,000 100 Units Data Changes Per Bit Store Cycles Years 2015 PGM T07.1 EQUIVALENT A.C. LOAD CIRCUIT 5V 893Ω OUTPUT 347Ω 30pF A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels 0V to 3V 5ns 1.5V 2015 PGM T08.1 2015 FHD F04 5 X20C17 A.C. CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified) Read Cycle Limits X20C17-35 -40°C to +85°C Symbol tRC tCE tAA tOE tLZ(3) tOLZ(3) tHZ(3) tOHZ(3) tOH Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold From Address Change Min. 35 35 35 20 0 0 0 0 0 0 0 0 0 0 Max. X20C17-45 Min. 45 45 45 25 0 0 0 0 0 Max. X20C17-55 Min. 55 55 55 30 Max. Units ns ns ns ns ns ns ns ns ns 2015 PGM T10 15 15 20 20 25 25 Read Cycle tRC ADDRESS tCE CE tOE OE WE tOLZ tLZ DATA I/O DATA VALID tAA 2015 FHD F05 tOHZ tOH tHZ DATA VALID Note: (3) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF, from the point when CE or OE return HIGH (whichever occurs first) to the time when the Outputs are no longer driven. 6 X20C17 Write Cycle Limits X20C17-35 Symbol tWC tCW tAS tWP tWR tDW tDH tOEH tOES tOZ(4) Parameter Write Cycle Time Chip Enable to End of Write Input Address Setup Time Write Pulse Width Write Recovery Time Data Setup to End of Write Data Hold Time OE High Hold Time OE High Setup Time Output Enable to Output in High Z Min. 35 30 0 30 0 15 3 0 0 15 Max. X20C17-45 Min. 45 35 0 35 0 20 3 0 0 20 Max. X20C17-55 Min. 55 40 0 40 0 25 3 0 0 25 Max. Units ns ns ns ns ns ns ns ns ns ns 2015 PGM T11 Write Cycle tWC ADDRESS OE tCW CE tAS WE tOZ DATA OUT tDW DATA IN DATA VALID tDH tOEH tWP tWR 2015 FHD F06.1 Note: (4) tOW, tOZ are periodically sampled and not 100% tested. 7 X20C17 AUTOSTORE Feature The AUTOSTORE feature automatically saves the contents of the X20C17’s static RAM to the on-board bit-forbit shadow E2PROM at power-down. This circuitry insures that no data is lost during accidental power-downs or general system crashes, and is ideal for microprocessor caching systems, embedded software systems, and general system back-up memory. The X20C17 automatically initiates a nonvolatile store cycle whenever Vcc falls below the AUTOSTORE threshold voltage (VASTH). VCC must remain above the AUTOSTORE Cycle End Voltage (VASEND) for the duration of the store cycle (tASTO). The detailed timing for this feature is illustrated in the AUTOSTORE timing diagram, below. Once the AUTOSTORE cycle is initiated, all other device functions are inhibited. AUTOSTORE CYCLE Timing Diagram and Suggested AUTOSTORE Implementation Circuit V CC 5 VOLTS (V) VCC AUTOSTORE CYCLE IN PROGRESS VASTH VASEND 4 3 2 1 V CC tASTO STORE TIME X20C17 22µF TIME (ms) 2015 ILL F30.4 2015 FHD F14 AUTOSTORE CYCLE LIMITS X20C17 Symbol tASTO (5) VASTH VASEND (5) Note: Parameter AUTOSTORE Cycle Time AUTOSTORE Threshold Voltage AUTOSTORE Cycle End Voltage Min. 4.0 3.5 Max. 2.5 4.3 Units ms V V 2015 PGM T15 (5) tASTO and VASEND are periodically sampled and not 100% tested. 8 X20C17 Normalized ICC by Temperature over the VCC Range and Frequency 1.4 1.2 1.0 VCC = 5.5V VCC = 5.0V VCC = 4.5V ICC (NORMALIZED) 0.8 0.6 0.4 0.2 0.0 0 1.0 2.0 3.0 4.0 5.0 5.5 6.6 8.3 10.0 11.1 12.5 13.3 14.3 15.2 16.7 20.0 25.0 30.0 FREQUENCY (MHz) 2015 FHD F31.1 Normalized ICC by Temperature over Frequency 1.4 1.2 1.0 ICC (NORMALIZED) -55°C +25°C +125°C 0.8 0.6 0.4 0.2 0.0 0 1.0 2.0 3.0 4.0 5.0 5.5 6.6 8.3 10.0 11.1 12.5 13.3 14.3 15.2 16.7 20.0 25.0 30.0 FREQUENCY (MHz) 2015 FHD F33.2 9 X20C17 PACKAGING INFORMATION 24-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 1.265 (32.13) 1.230 (31.24) 0.557 (14.15) 0.530 (13.46) PIN 1 INDEX PIN 1 1.100 (27.94) REF. 0.080 (2.03) 0.065 (1.65) SEATING PLANE 0.150 (3.81) 0.125 (3.18) 0.162 (4.11) 0.140 (3.56) 0.030 (0.76) 0.015 (0.38) 0.110 (2.79) 0.090 (2.29) 0.065 (1.65) 0.040 (1.02) 0.022 (0.56) 0.014 (0.36) 0.625 (15.87) 0.600 (15.24) TYP. 0.010 (0.25) 0° 15° NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 3926 FHD F03 10 X20C17 ORDERING INFORMATION X20C17 Device X X -X Access Time –35 = 35ns –45 = 45ns –55 = 55ns Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C M = Military = –55°C to +125°C Package P = 24 Lead Plastic Dip LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. 11