X28LC512PI-15

X28LC512/X28LC513 512K X28LC512/X28LC513 3.3 Volt, Byte Alterable E2PROM 64K x 8 Bit FEATURES • • • • • • • • • Low VCC Operation: VCC = 3.3V ±10% Access Time: 150ns Simple Byte and Page Write —Self-Timed —No Erase Before Write —No Complex Programming Algorithms —No Overerase Problem Low Power CMOS: —Active: 25mA —Standby: 150µA Software Data Protection —Protects Data Against System Level Inadvertant Writes High Speed Page Write Capability Highly Reliable Direct Write™ Cell —Endurance: 10,000 Write Cycles —Data Retention: 100 Years Early End of Write Detection —DATA Polling —Toggle Bit Polling Two PLCC and LCC Pinouts —X28LC512 —X28LC010 E2PROM Pin Compatible —X28LC513 —Compatible with Lower Density E2PROMs DESCRIPTION The X28LC512/513 is a low-power 64K x 8 E2PROM, fabricated with Xicor’s proprietary, high performance, floating gate CMOS technology. The X28LC512/513 features the JEDEC approved pinout for bytewide memories, compatible with industry standard EPROMS. The X28LC512/513 supports a 128-byte page write operation, effectively providing a 39µs/byte write cycle and enabling the entire memory to be written in less than 2.5 seconds. The X28LC512/513 also features DATA Polling and Toggle Bit Polling, system software support schemes used to indicate the early completion of a write cycle. In addition, the X28LC512/513 supports the Software Data Protection option. PIN CONFIGURATIONS PLCC A12 A15 NC NC VCC WE NC PLASTIC DIP NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 X28LC512 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE NC A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/04 I/O3 A11 A9 A8 A13 A14 NC NC NC WE VCC NC NC NC NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TSOP 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 NC NC VSS NC NC I/O2 I/O1 I/O0 A0 A1 A2 A3 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 30 32 31 29 54 3 2 1 6 28 7 27 26 8 X28LC512 25 9 (TOP VIEW) 24 10 11 23 12 22 13 15 16 17 18 19 20 21 14 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 A14 A13 A8 A9 A11 OE A10 CE I/O7 X28LC512 3005 ILL F03 PLCC A7 A12 A14 A15 VCC WE A13 A6 A5 A4 A3 A2 A1 A0 NC I/O0 30 32 31 29 54 3 2 1 6 28 7 27 26 8 X28LC513 25 9 (TOP VIEW) 24 10 11 23 12 22 13 15 16 17 18 19 20 21 14 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 3005 ILL F04.1 A8 A9 A11 NC OE A10 CE I/O7 I/O6 Characteristics subject to change without notice 3005 ILL F22.2 3005 ILL F02.1 © Xicor, Inc. 1991, 1995, 1996 Patents Pending 3005-3.2 8/5/97 T2/C0/D0 EW 1 X28LC512/X28LC513 PIN DESCRIPTIONS Addresses (A0–A15) The Address inputs select an 8-bit memory location during a read or write operation. Chip Enable (CE) The Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, power consumption is reduced. Output Enable (OE) The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/Data Out (I/O0–I/O7) Data is written to or read from the X28LC512/513 through the I/O pins. Write Enable (WE) The Write Enable input controls the writing of data to the X28LC512/513. PIN NAMES Symbol A0–A15 I/O0–I/O7 WE CE OE VCC VSS NC Description Address Inputs Data Input/Output Write Enable Chip Enable Output Enable 3.3V ± 10% Ground No Connect 3005 PGM T01 FUNCTIONAL DIAGRAM A7–A15 X BUFFERS LATCHES AND DECODER 512K-BIT E2PROM ARRAY A0–A6 Y BUFFERS LATCHES AND DECODER I/O BUFFERS AND LATCHES I/O0–I/O7 DATA INPUTS/OUTPUTS CE OE WE VCC VSS 3005 ILL F01 CONTROL LOGIC AND TIMING 2 X28LC512/X28LC513 DEVICE OPERATION Read Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH. Write Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28LC512/513 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 5ms. Page Write Operation The page write feature of the X28LC512/513 allows the entire memory to be written in 2.5 seconds. Page write allows two to one hundred twenty-eight bytes of data to be consecutively written to the X28LC512/513 prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A15) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address. The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twentyseven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100µs of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100µs, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100µs. Write Operation Status Bits The X28LC512/513 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1. Figure 1. Status Bit Assignment I/O DP TB 5 4 3 2 1 0 RESERVED TOGGLE BIT DATA POLLING 3005 ILL F11 DATA Polling (I/O7) The X28LC512/513 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28LC512/ 513, eliminating additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e. write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data. Toggle Bit (I/O6) The X28LC512/513 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle, I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease and the device will be accessible for additional read or write operations. 3 X28LC512/X28LC513 DATA Polling I/O7 Figure 2a. DATA Polling Bus Sequence LAST WRITE WE CE OE VIH I/O7 HIGH Z VOL An An An An An An An 3005 ILL F12 VOH X28LC512 READY A0–A15 Figure 2b. DATA Polling Software Flow DATA Polling can effectively halve the time for writing to the X28LC512/513. The timing diagram in Figure 2a illustrates the sequence of events on the bus. The software flow diagram in Figure 2b illustrates one method of implementing the routine. WRITE DATA WRITES COMPLETE? YES SAVE LAST DATA AND ADDRESS NO READ LAST ADDRESS IO7 COMPARE? YES X28LC512 READY NO 3005 ILL F13 4 X28LC512/X28LC513 The Toggle Bit I/O6 Figure 3a. Toggle Bit Bus Sequence LAST WRITE WE CE OE I/O6 VOH * VOL HIGH Z * X28LC512 READY * Beginning and ending state of I/O6 will vary. 3005 ILL F14 Figure 3b. Toggle Bit Software Flow The Toggle Bit can eliminate the software housekeeping chore of saving and fetching the last address and data written to a device in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28LC512/513 memories that is frequently updated. Toggle Bit Polling can also provide a method for status checking in multiprocessor applications. The timing diagram in Figure 3a illustrates the sequence of events on the bus. The software flow diagram in Figure 3b illustrates a method for polling the Toggle Bit. LAST WRITE LOAD ACCUM FROM ADDR n COMPARE ACCUM WITH ADDR n COMPARE OK? YES X28LC512 READY NO 3005 ILL F15 5 X28LC512/X28LC513 HARDWARE DATA PROTECTION The X28LC512/513 provides three hardware features that protect nonvolatile data from inadvertent writes. • Noise Protection—A WE pulse typically less than 10ns will not initiate a write cycle. • Write Inhibit—Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. Write cycle timing specifications must be observed concurrently. SOFTWARE DATA PROTECTION The X28LC512/513 offers a software controlled data protection feature. The X28LC512/513 is shipped from Xicor with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/ -down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable. The X28LC512/513 can be automatically protected during power-up and power-down without the need for external circuits by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation utilizing the software algorithm. This circuit is nonvolatile and will remain set for the life of the device unless the reset command is issued. Once the software protection is enabled, the X28LC512/ 513 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device. Note: The data in the three-byte enable sequence is not written to the memory array. SOFTWARE ALGORITHM Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 4a and 4b for the sequence. The three byte sequence opens the page write window enabling the host to write from one to one hundred twenty-eight bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state. 6 X28LC512/X28LC513 Software Data Protection Figure 4a. Timing Sequence—Software Data Protect Enable Sequence followed by Byte or Page Write VCC 0V DATA ADDR CE ≤tBLC MAX WE BYTE OR PAGE AA 5555 55 2AAA A0 5555 WRITES OK tWC WRITE PROTECTED (VCC) NOTE: All other timings and control pins are per page write timing requirements. 3005 ILL F16 Figure 4b. Write Sequence for Software Data Protection Regardless of whether the device has previously been protected or not, once the software data protected algorithm is used and data has been written, the X28LC512/513 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28LC512/513 will be write protected during power-down and after any subsequent power-up. The state of A15 while executing the algorithm is don’t care. WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA A0 TO ADDRESS 5555 Note: Once initiated, the sequence of write operations should not be interrupted. WRITE DATA XX TO ANY ADDRESS OPTIONAL BYTE/PAGE LOAD OPERATION WRITE LAST BYTE TO LAST ADDRESS AFTER tWC RE-ENTERS DATA PROTECTED STATE 3005 FHD F17 7 X28LC512/X28LC513 Resetting Software Data Protection Figure 5a. Reset Software Data Protection Timing Sequence VCC STANDARD OPERATING MODE DATA ADDR CE AA 5555 55 2AAA 80 5555 AA 5555 55 2AAA 20 5555 ≥tWC WE NOTE: All other timings and control pins are per page write timing requirements. 3005 ILL F18 Figure 5b. Software Sequence to Deactivate Software Data Protection In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an E2PROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28LC512/513 will be in standard operating mode. WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA Note: Once initiated, the sequence of write operations should not be interrupted. WRITE DATA 80 TO ADDRESS 5555 WRITE DATA AA TO ADDRESS 5555 WRITE DATA 55 TO ADDRESS 2AAA WRITE DATA 20 TO ADDRESS 5555 3005 FHD F19 8 X28LC512/X28LC513 SYSTEM CONSIDERATIONS Because the X28LC512/513 is frequently used in large memory arrays it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation this assures that all deselected devices are in their standby mode and that only the selected device(s) is outputting data on the bus. Because the X28LC512/513 has two power modes, standby and active, proper decoupling of the memory Active Supply Current vs. Ambient Temperature 7.5 7 6.5 VCC = 3.3V 35 30 25 20 15 –55°C +25°C +125°C array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the I/ Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1µF high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. In addition, it is recommended that a 4.7µF electrolytic bulk capacitor be placed between VCC and VSS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces. ICC (RD) by Temperature over Frequency 40 3.3 VCC ICC (mA) 5.5 5 4.5 4 –55 –10 +35 +80 +125 AMBIENT TEMPERATURE (°C) 3005 ILL F25 ICC RD (mA) 6 10 0 5 10 15 3005 ILL F24 FREQUENCY (MHz) Standby Supply Current vs. Ambient Temperature 0.14 VCC = 3.3V 0.13 0.12 ISB (mA) 0.11 0.1 0.09 0.08 –55 –10 +35 +80 +125 3005 ILL F26 AMBIENT TEMPERATURE (°C) 9 X28LC512/X28LC513 ABSOLUTE MAXIMUM RATINGS* Temperature under Bias X28LC512/513 ............................. –10°C to +85°C X28LC512I/X28LC513I .............. –65°C to +135°C Storage Temperature ....................... –65°C to +150°C Voltage on any Pin with Respect to VSS ....................................... –1V to +7V D.C. Output Current ............................................. 5mA Lead Temperature (Soldering, 10 seconds) .............................. 300°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMEND OPERATING CONDITIONS Temperature Commercial Industrial Min. 0°C –40°C Max. +70°C +85°C 3005 PGM T02 Supply Voltage X28LC512/513 Limits 3.3V ± 10% 3005 PGM T03.1 D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified.) Limits Symbol ICC Parameter VCC Current (Active) (CMOS Inputs) Min. Max. 25 Units mA Test Conditions CE = OE = VIL, WE = VIH, All I/O’s = Open, Address Inputs = 0.1xVCC/0.9xVCC Levels @ f = 5MHz OE = VIL, CE = VCC – 0.3V All I/O’s = Open, Other Inputs = VIH VIN = VSS to VCC VOUT = VSS to VCC, CE = VCC ISB ILI ILO VlL(1) VIH(1) VOL VOH VCC Current (Standby) (CMOS Inputs) Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage 150 10 10 0.6 VCC + 0.5 0.4 µA µA µA V V V V –1 2 2.4 IOL = 1mA IOH = –200µA 3005 PGM T04.2 Notes: (1) VIL min. and VIH max. are for reference only and are not tested. 10 X28LC512/X28LC513 POWER-UP TIMING Symbol tPUR(2) tPUW(2) Parameter Power-up to Read Operation Power-up to Write Operation Max. 100 5 Units µs ms 3005 PGM T05 CAPACITANCE TA = +25°C, f = 1MHz, VCC = 3.3V Symbol CI/O(2) CIN(2) Parameter Input/Output Capacitance Input Capacitance Max. 10 10 Units pF pF Test Conditions VI/O = 0V VIN = 0V 3005 PGM T06.1 ENDURANCE AND DATA RETENTION Parameter Endurance Data Retention A.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels 0V to 3V 10ns 1.5V 3856 PGM T07.1 Min. 10,000 100 MODE SELECTION CE L L H X X OE L H X L X WE H L X X H Max. Units Cycles per Byte Years 3005 PGM T11 Mode Read Write Standby and Write Inhibit Write Inhibit Write Inhibit I/O DOUT DIN High Z — — Power Active Active Standby — — 3005 PGM T08 EQUIVALENT A.C. LOAD CIRCUIT 5V 2.66KΩ OUTPUT 4.46KΩ 30pF SYMBOL TABLE WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance 3005 ILL F21.3 Note: (2) This parameter is periodically sampled and not 100% tested. Don’t Care: Changes Allowed N/A 11 X28LC512/X28LC513 A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read Cycle Limits X28LC512-15 X28LC512-20 X28LC512-25 X28LC513-15 X28LC513-20 X28LC513-25 Symbol tRC tCE tAA tOE tLZ(3) tOLZ(3) tHZ(3) tOHZ(3) tOH Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE LOW to Active Output OE LOW to Active Output CE HIGH to High Z Output OE HIGH to High Z Output Output Hold from Address Change Min. 150 150 150 80 0 0 50 50 0 0 0 0 50 50 0 Max. Min. 200 200 200 80 0 0 50 50 Max. Min. 250 250 250 80 Max. Units ns ns ns ns ns ns ns ns ns 3005 PGM T09.2 Read Cycle tRC ADDRESS tCE CE tOE OE WE VIH tOLZ tLZ DATA I/O HIGH Z DATA VALID tAA tOH tHZ DATA VALID tOHZ 3005 FHD F05 Notes: (3) tLZ min., tHZ, tOLZ min., and tOHZ are periodically sampled and not 100% tested. tHZ max. and tOHZ max. are measured, with CL = 5pF from the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven. 12 X28LC512/X28LC513 WRITE CYCLE LIMITS Symbol tWC(4) tAS tAH tCS tCH tCW tOES tOEH tWP tWPH tDV tDS tDH tDW tBLC Parameter Write Cycle Time Address Setup Time Address Hold Time Write Setup Time Write Hold Time CE Pulse Width OE HIGH Setup Time OE HIGH Hold Time WE Pulse Width WE HIGH Recovery Data Valid Data Setup Data Hold Delay to Next Write Byte Load Cycle Min. 0 50 0 0 100 10 10 100 100 1 50 0 10 0.20 Max. 5 Units ms ns ns ns ns ns ns ns ns ns µs ns ns µs µs 3005 PGM T10.1 100 WE Controlled Write Cycle tWC ADDRESS tAS tCS CE tAH tCH OE tOES WE tDV DATA IN DATA VALID tDS DATA OUT HIGH Z 3005 ILL F06 tWP tOEH tDH Notes: (4) tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to complete the internal write operation. 13 X28LC512/X28LC513 CE Controlled Write Cycle tWC ADDRESS tAS CE tOES OE tOEH tCS WE tDV DATA IN DATA VALID tDS DATA OUT HIGH Z 3005 ILL F07 tAH tCW tWPH tCH tDH Page Write Cycle OE(5) CE tWP WE tWPH *ADDRESS(6) tBLC I/O BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 LAST BYTE BYTE n+2 tWC 3005 ILL F08.1 *For each successive write within the page write operation, A7–A15 should be the same or writes to an unknown address could occur. Notes: (5) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. (6) The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing. 14 X28LC512/X28LC513 DATA Polling Timing Diagram(7) An An An ADDRESS CE WE tOEH OE tDW I/O7 DIN=X DOUT=X tWC DOUT=X tOES 3005 ILL F09 Toggle Bit Timing Diagram CE WE tOEH OE tDW I/O6 HIGH Z * tWC * Starting and ending state of I/O6 will vary, depending upon actual tWC. 3005 ILL F10 tOES * Note: (7) Polling operations are by definition read cycles and are therefore subject to read cycle timings. 15 X28LC512/X28LC513 PACKAGING INFORMATION 32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J 0.420 (10.67) 0.050 (1.27) TYP. 0.045 (1.14) x 45° 0.021 (0.53) 0.013 (0.33) TYP. 0.017 (0.43) 0.495 (12.57) 0.485 (12.32) TYP. 0.490 (12.45) 0.453 (11.51) 0.447 (11.35) TYP. 0.450 (11.43) 0.300 (7.62) REF. PIN 1 SEATING PLANE ±0.004 LEAD CO – PLANARITY — 0.015 (0.38) 0.095 (2.41) 0.060 (1.52) 0.140 (3.56) 0.100 (2.45) TYP. 0.136 (3.45) 0.048 (1.22) 0.042 (1.07) 0.595 (15.11) 0.585 (14.86) TYP. 0.590 (14.99) 0.553 (14.05) 0.547 (13.89) TYP. 0.550 (13.97) 0.400 (10.16)REF. 3° TYP. NOTES: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY 3926 FHD F13 16 X28LC512/X28LC513 PACKAGING INFORMATION 32-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P 1.665 (42.29) 1.644 (41.76) 0.557 (14.15) 0.510 (12.95) PIN 1 INDEX PIN 1 1.500 (38.10) REF. 0.085 (2.16) 0.040 (1.02) SEATING PLANE 0.160 (4.06) 0.125 (3.17) 0.160 (4.06) 0.140 (3.56) 0.030 (0.76) 0.015 (0.38) 0.110 (2.79) 0.090 (2.29) 0.070 (17.78) 0.030 (7.62) 0.022 (0.56) 0.014 (0.36) 0.625 (15.88) 0.590 (14.99) TYP. 0.010 (0.25) 0° 15° NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH 3926 FHD F25 17 X28LC512/X28LC513 PACKAGING INFORMATION 40-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T 12.522 (0.493) 1.143 (0.045) 12.268 (0.483) 0.889 (0.035) PIN #1 IDENT. O 1.016 (0.040) 0.127 (0.005) DP. X O 0.762 (0.030) 0.076 (0.003) DP. 1 0.500 (0.0197) 0.965 (0.038) 1.219 (0.048) 10.058 (0.396) 9.957 (0.392) 0.178 (0.007) 15° TYP. SEATING PLANE 0.254 (0.010) 0.152 (0.006) 0.065 (0.0025) 1.016 (0.040) SEATING PLANE 14.148 (0.557) 13.894 (0.547) DETAIL A 0.813 (0.032) TYP. 0.432 (0.017) 0.152 (0.006) TYP. 4° TYP. A 0.432 (0.017) 0.508 (0.020) TYP. 14.80 ± 0.05 (0.583 ± 0.002) 0.30 ± 0.05 (0.012 ± 0.002) TYPICAL 40 PLACES 15 EQ. SPC. @ 0.50 ± 0.04 0.0197 ± 0.016 = 9.50 ± 0.06 (0.374 ± 0.0024) OVERALL TOL. NON-CUMULATIVE SOLDER PADS 0.17 (0.007) 0.03 (0.001) FOOTPRINT 1.30 ± 0.05 (0.051 ± 0.002) 0.50 ± 0.04 (0.0197 ± 0.0016) NOTE: 1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES). 3926 ILL F39.2 18 X28LC512/X28LC513 ORDERING INFORMATION X28LC512 Device X X -X Access Time –15 = 150ns –20 = 200ns –25 = 250ns Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package J = 32-Lead PLCC P = 32-Lead Plastic Dip T = 40-Lead TSOP X28LC513 Device X X -X Access Time –15 = 150ns –20 = 200ns –25 = 250ns Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package J = 32-Lead PLCC LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness tor any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. US. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use as critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. 19