XC2S50-6FGG256C

— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — 0 Spartan-IIE 1.8V FPGA Automotive XA Product Family: Introduction and Ordering R DS106-1 (v2.0) August 9, 2013 0 0 Introduction The Xilinx Automotive (XA) Spartan™-IIE 1.8V Field-Programmable Gate Array family is specifically designed to meet the needs of high-volume, cost-sensitive automotive electronic applications. The family gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The five-member family offers densities ranging from 50,000 to 300,000 system gates, as shown in Table 1. System performance is supported beyond 200 MHz. Product Specification • Guaranteed to meet full electrical specifications over TJ = –40°C to +125°C • Second generation ASIC replacement technology - Densities as high as 6,912 logic cells with up to 300,000 system gates - Very low cost System-level features - SelectRAM+™ hierarchical memory: · 16 bits/LUT distributed RAM · Configurable 4K-bit true dual-port block RAM · Fast interfaces to external RAM - Dedicated carry logic for high-speed arithmetic - Efficient multiplier support - Cascade chain for wide-input functions - Abundant registers/latches with enable, set, reset - Four dedicated DLLs for advanced clock control · Eliminate clock distribution delay · Multiply, divide, or phase shift - Four primary low-skew global clock distribution nets - IEEE 1149.1 compatible boundary scan logic Versatile I/O and packaging - Low-cost packages available in all densities - 19 high-performance interface standards · LVTTL, LVCMOS, HSTL, SSTL, AGP, CTT, GTL · LVDS and LVPECL differential I/O - Up to 120 differential I/O pairs that can be input, output, or bidirectional Fully supported by powerful Xilinx ISE development system - Fully automatic mapping, placement, and routing - Integrated with design entry and verification tools - Extensive IP library including DSP functions • Spartan-IIE devices deliver more gates, I/Os, and features per dollar than other FPGAs by combining advanced process technology with a streamlined architecture based on the proven Virtex™-E platform. Features include block RAM (to 64K bits), distributed RAM (to 98,304 bits), 19 selectable I/O standards, and four DLLs (Delay-Locked Loops). Fast, predictable interconnect means that successive design iterations continue to meet timing requirements. XA devices are available in both the extended-temperature Q-grade (-40°C to +125°C) and industrial I-grade (-40°C to +100°C) and are qualified to the industry-recognized AEC-Q100 standard. The XA Spartan-IIE family is a superior alternative to mask-programmed ASICs. The FPGA avoids the initial cost, lengthy development cycles, and inherent risk of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary (impossible with ASICs). • • Features • AEC-Q100 device qualification and full PPAP support available in both extended temperature Q-grade and I-grade Table 1: XA Spartan-IIE FPGA Family Members Device Logic Cells Typical System Gate Range (Logic and RAM) CLB Array (R x C) Total CLBs Maximum Available User I/O(1) Maximum Differential I/O Pairs Distributed RAM Bits Block RAM Bits XA2S50E 1,728 23,000 - 50,000 16 x 24 384 102 83 24,576 32K XA2S100E 2,700 37,000 - 100,000 20 x 30 600 102 86 38,400 40K XA2S150E 3,888 52,000 - 150,000 24 x 36 864 182 114 55,296 48K XA2S200E 5,292 71,000 - 200,000 28 x 42 1,176 182 120 75,264 56K XA2S300E 6,912 93,000 - 300,000 32 x 48 1,536 182 120 98,304 64K Notes: 1. User I/O counts include the four global clock/user input pins. See details in Table 3, page 5 © 2002–2013 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS106-1 (v2.0) August 9, 2013 Product Specification www.xilinx.com 1 — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — R Spartan-IIE 1.8V FPGA Automotive XA Product Family: Introduction and Ordering General Overview The Spartan-IIE family of FPGAs have a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks (IOBs). There are four Delay-Locked Loops (DLLs), one at each corner of the die. Two columns of block RAM lie on opposite sides of the die, between the CLBs and the IOB columns. The XC2S400E has four columns of block RAM. These functional elements are interconnected by a powerful hierarchy of versatile routing channels (see Figure 1). Spartan-IIE FPGAs are customized by loading configuration data into internal static memory cells. Unlimited reprogramming cycles are possible with this approach. Stored values in these cells determine logic functions and interconnections implemented in the FPGA. Configuration data can be read from an external serial PROM (master serial mode), or written into the FPGA in slave serial, slave parallel, or Boundary Scan modes. Spartan-IIE FPGAs are typically used in high-volume applications where the versatility of a fast programmable solution adds benefits. Spartan-IIE FPGAs are ideal for shortening product development cycles while offering a cost-effective solution for high volume production. Spartan-IIE FPGAs achieve high-performance, low-cost operation through advanced architecture and semiconduc- 2 tor technology. Spartan-IIE devices provide system clock rates beyond 200 MHz. Spartan-IIE FPGAs offer the most cost-effective solution while maintaining leading edge performance. In addition to the conventional benefits of high-volume programmable logic solutions, Spartan-IIE FPGAs also offer on-chip synchronous single-port and dual-port RAM (block and distributed form), DLL clock drivers, programmable set and reset on all flip-flops, fast carry logic, and many other features. Spartan-IIE Family Compared to Spartan-II Family • • • • • • • Higher density and more I/O Higher performance Unique pinouts in cost-effective packages Differential signaling - LVDS, Bus LVDS, LVPECL VCCINT = 1.8V - Lower power - 5V tolerance with external resistor - 3V tolerance directly LVTTL and LVCMOS2 input buffers powered by VCCO instead of VCCINT Unique larger bitstream www.xilinx.com DS106-1 (v2.0) August 9, 2013 Product Specification — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — R Spartan-IIE 1.8V FPGA Automotive XA Product Family: Introduction and Ordering DLL BLOCK RAM BLOCK RAM BLOCK RAM BLOCK RAM DLL DLL DLL I/O LOGIC DS077_01_052102 Figure 1: Basic Spartan-IIE Family FPGA Block Diagram DC Specifications Absolute Maximum Ratings (1) Symbol Description Min Max Units VCCINT Supply voltage relative to GND –0.5 2.0 V VCCO Supply voltage relative to GND –0.5 4.0 V VREF Input reference voltage –0.5 4.0 V –0.5 4.05 V GND (2,3) VIN Input voltage relative to VTS Voltage applied to 3-state output (3) –0.5 4.0 V TSTG Storage temperature (ambient) –65 +150 °C - +135 °C TJ Junction temperature Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 2. VIN should not exceed VCCO by more than 3.6V over extended periods of time (e.g., longer than a day). 3. Maximum DC overshoot must be limited to either VCCO + 0.5V or 10 mA, and undershoot must be limited to –0.5V or 10 mA, whichever is easier to achieve. The Maximum AC conditions are as follows: The device pins may undershoot to –2.0V or overshoot to VCCO + 2.0V, provided this over/undershoot lasts no more than 11 ns with a forcing current no greater than 100 mA. 4. For soldering guidelines, see the Packaging Information on the Xilinx Web site. DS106-1 (v2.0) August 9, 2013 Product Specification www.xilinx.com 3 — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — R Spartan-IIE 1.8V FPGA Automotive XA Product Family: Introduction and Ordering Recommended Operating Conditions Symbol TJ Description Junction temperature Min Max Units –40 125 °C VCCINT Supply voltage relative to GND (1) 1.8 – 5% 1.8 + 5% V VCCO Supply voltage relative to GND (2) 1.2 3.6 V - 250 ns TIN Input signal transition time (3) Notes: 1. Functional operation is guaranteed down to a minimum VCCINT of 1.62V (Nominal VCCINT –10%). For every 50 mV reduction in VCCINT below 1.71V (nominal VCCINT –5%), all delay parameters increase by 3%. 2. Minimum and maximum values for VCCO vary according to the I/O standard selected. 3. Input and output measurement threshold is ~50% of VCCO. DC Characteristics Over Operating Conditions Symbol Description Quiescent V CCINT supply current(1) ICCINTQ Min Max Units XA2S50E - 200 mA XA2S100E - 350 mA XA2S150E - 450 mA XA2S200E - 550 mA XA2S300E - 650 mA Notes: 1. With no output current loads, no active pull-up resistors, and all I/O pins 3-stated and floating. Spartan-IIE Product Availability Table 2 shows the package and speed grades available for Spartan-IIE family devices. Table 3 shows the maximum user I/Os available on the device and the number of user I/Os available for each device/package combination. Table 2: Spartan-IIE Package and Speed Grade Availability Pins 144 256 Type Plastic TQFP Fine Pitch BGA Device Code TQ144 FT256 XA2S50E -6 I,Q XA2S100E -6 I,Q XA2S150E -6 - I,Q XA2S200E -6 - I,Q XA2S300E -6 - I,Q Notes: 1. Q = –40°C to +125°C (TJ) 2. I = –40°C to +100°C (TJ) 4 www.xilinx.com DS106-1 (v2.0) August 9, 2013 Product Specification — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — R Spartan-IIE 1.8V FPGA Automotive XA Product Family: Introduction and Ordering Table 3: Spartan-IIE User I/O Chart Device Maximum User I/O XA2S50E Available User I/O According to Package Type TQ144 FT256 102 102 - XA2S100E 102 102 - XA2S150E 182 - 182 XA2S200E 182 - 182 XA2S300E 182 - 182 Ordering Information Example: XA2S50E -6 TQ 144 Q Device Type Temperature Range Number of Pins Speed Grade Package Type Device Ordering Options Device XA2S50E Speed Grade -6 Standard Performance XA2S100E Package Type / Number of Pins Temperature Range (TJ ) TQ144 144-pin Plastic Thin QFP Q = Automotive Extended –40°C to +125°C FT256 I = Automotive Industrial –40°C to +100°C 256-ball Fine Pitch BGA XA2S150E XA2S200E XA2S300E DS106-1 (v2.0) August 9, 2013 Product Specification www.xilinx.com 5 — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — R Spartan-IIE 1.8V FPGA Automotive XA Product Family: Introduction and Ordering Revision History 6 Version Date Description 1.0 07/17/2002 Initial Xilinx release. 1.1 11/18/2002 Added XC2S400-E and XC2S600-E devices. Added FG676 to package list. 1.2 11/26/2002 Updated Max User I/O and Differential I/O Pairs in Table 1 and Max User I/O in Table 3. Updated notes for Recommended Operating Conditions. 1.3 06/04/2003 Changed five-member family to seven-member family in first paragraph. 1.4 06/16/2003 Updated features list. Added DC Characteristics Over Operating Conditions table. Deleted “FG676” from Table 2, Table 3, and the Device Ordering Options section. 1.5 07/16/2003 Updated features list, Table 1, DC Characteristics Over Operating Conditions table, and Table 3. 1.6 09/24/2003 Updated title to read "Product Specification" (removed "Advance") 1.7 10/18/2004 Extensive edits to update family from IQ to XA 2.0 08/09/2013 This product is obsolete/discontinued per XCN12026. www.xilinx.com DS106-1 (v2.0) August 9, 2013 Product Specification