PDSP16116

PDSP16330 MC Pythagoras Processor DS3240 ISSUE 3.1 November 1998 The PDSP16330 is a high speed digital CMOS IC that converts Cartesian data (Real and Imaginary) into Polar form (Magnitude and Phase), at rates up to 10MHz. Cartesian 16+16 bit 2's complement or Sign-Magnitude data is converted into 16 bit Phase format. The Magnitude output may be scaled in amplitude by powers of 2. The Phase output represents a full 2 x π field to eliminate phase ambiguities. Polyimide is used as an inter-layer dielectric and as glassivation. GC100 FEATURES 10MHz Cartesian to Polar Conversion 16-Bit Cartesian Inputs 16-Bit Magnitude Output 12-Bit Phase Output 2’s Complement or Sign-Magnitude Input Formats Three-state Outputs and Independent Data Enables Simplify System Interfacing Magnitude Scaling Facility with Overflow Flag Less than 400 mW Power Dissipation at 10MHz 100 pin CQFP Package Fig.1 Pin connections - QFP Package Rev Date A B C D FEB 1992 MAR 1993 OCT 1995 NOV 1998 ASSOCIATED PRODUCTS PDSP16112 PDSP16116 PDSP16318 PDSP16350 PDSP16510A 16 X 12 Complex Multiplier 16 X 16 Complex Multiplier Complex Accumulator I/Q Splitter and NCO Stand Alone FFT Processor APPLICATIONS Digital Signal Processing Digital Radio Radar Processing Sonar Processing Robotics ORDERING INFORMATION PDSP16330/MC/GC1R (10MHz - QFP Package, MIL-STD-883 Screening) X15:0 Y15:0 CEX CEY 16 16 SIGN SIGN 16 π Y/X 9 FORM MAGNITUDE 15 X 2 30 MAGNITUDE 15 Y 2 30 SIGN X SIGN Y X>Y /4 ARCTAN ROM 9 + 32 2 2 X +Y 16 S0 ROTATE 12 SHIFT S1 2 OEM OEP M15:0 OVR P11:0 Fig.2 Block diagram PDSP16330 MC FUNCTIONAL DESCRIPTION The PDSP16330 converts incoming Cartesian Data into the equivalent Polar Values. The device accepts new 16 + 16 bit complex data every cycle, and delivers a 16 bit + 12 bit Polar equivalent after 24 clock cycles.The input data can be in 2s’ Complement or Sign Magnitude format selected via the FORM input. The output is in a magnitude format for both the Magnitude output and the Phase. Phase data is zero for data with a zero Y input and positive X, and is 400 hex for zero X data and positive Y, is 800 hex for zero Y data and negative X, and is C00 hex for zero X and negative Y. The LSB weighting (bit 0) is 2 x π/4096 radians. The 16 bit Magnitude result may be scaled by shifting one, two, or three places in the more significant direction, effectively multiplying the Magnitude result by 2,4 or 8 respectively. Any of these shifts can under certain conditions cause an invalid result to be output from the device. Under these circumstances the OVR output will become active. The PDSP16330 has independent clock enables and three state output controls for all ports. S1-0 These inputs select the scaling factor to be applied to the Magnitude output. They are latched by the rising edge of CLK and determine the scaling of the output in the cycle after they are loaded into the device. The scale factor applied is determined by the table. Should the scaling factor applied cause an invalid Magnitude result to be output on the M Port, then the OVR Flag will become active for the period that the M Port output is invalid. S1 0 0 1 1 S0 0 1 0 1 Scaling Factor x1 x2 x4 x8 FORM This input selects the format of the X and Y input data. A low level on FORM indlcates that the Input data is twos’ complement format (Note: input data 8000 hex is not valid in 2s’ complement mode). This input refers to the format of the current Input data and may be changed on a per cycle basis if desired. The level of FORM is latched at the same time as the data to which it refers. The output number range is from 0 to 2 when the scaling factor is set at x1. 2 PDSP16330 MC PIN DESCRIPTIONS Symbol CLK CEX CEY X15-X0 Y15-Y0 M15-M0 Pin Name and Description Clock: Common Clock to device Registers. Register contents change on the rising edge of clock. Both pins must be connected. Clock Enable: Clock Enable for X Port. The clock to the X port is enabled by a low level. Clock Enable: Clock Enable for Y Port The clock to the Y port is enabled by a low level. X Data Input Data presented to this input is loaded into the device by the rising edge of CLK. X15 is the MSB Y Data Input Data presented to this input is loaded into the device by the rising edge of CLK. Y15 is the MSB M Data Output: Magnitude data generated by the device is output on this port. Data changes on the rising edge of CLK, M15 is the MSB. The weighting of M15 is determined by the Scale factor selected . P Data Output: Phase data generated by the device is output on this port. Data changes on the rising edge of CLK, P11 is the MSB. The weighting of P11 is π radians. Output Enable: Output Enable for M Port. The M Port is in a high impedance state when this input is high. Output Enable: Output Enable for P Port. The P Port is in a high impedance state when this input is high. Format Select This input selects the format of the Cartesian Data input on the X and Y ports. This input is latched by the rising edge of CLK, and is applied at the same time as the data to which it refers. A low !evel indicates that two’s complement data is applied, a high indicates Sign-Magnitude Scaling Control: Control input for scaling of Magnitude Data. This input is latched by the rising edge of CLK, and determines the scaling to be applied to the Magnitude result. The Scaling is applied to the output data in the cycle following the cycle in which the control was latched. Overflow: Overflow flag. This signal becomes active if the scaling currently selected causes an invalid value to be presented to the Magnitude output. +5V supply. All Vcc pins must be connected. 0V supply. All GND pins must be connected. P11-P0 OEM OEP FORM S1-S0 OVR Vcc GND INPUT DATA RANGE 2's Complement 7FFF . . . 0001 0000 FFFF . . . 8001 Sign Magnitude 7FFF . . . 0001 0000 8000 . . . FFF 3 PDSP16330 MC PIN FUNCTION Pin No. GC 91 92 93 94 95 96 97 98 99 100 1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function Pin No. GC 23 24 25 26 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 57 58 Function Pin No. GC 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 81 82 83 84 85 86 87 88 89 90 Function M7 M6 M5 M4 M3 M2 M1 M0 S0 S1 GND Vcc FORM Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 YO CEY CLK Vcc GND GND GND GND GND GND GND OEP P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 GND Vcc CEX X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 CLK OVR Vcc GND OEM M15 M14 M13 M12 M11 M10 M9 M8 ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise stated): Tamb (Military) =-55° C to + 125°C Vcc (Military) = 5.0V + 10%, GND = 0V STATIC CHARACTERISTICS Value Characteristic Symbol Min. * Output high voltage * Output low voltage * Input high voltage (CMOS) * Input low voltage (CMOS) * Input high voltage (TTL) * Input low voltage (TTL) * Input leakage current (Note 1 ) † Input capacitance * Output leakage current † Output SC current VOH VOL VIH VIL VIH VIL IIL CIN loz IOS 2.4 0.6 3.0 1.0 2.2 -10 10 -50 -50 + 50 230 0.8 + 120 Typ. Max. V V V V V V µA pF µA mA 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 IOH = 3.2mA lOL=-3.2mA Inputs CEX, CEY and CLK only Inputs CEX, CEY and CLK only All other inputs All other inputs GND < VIN