SP5511NADP

SP5511 Bidirectional I2C Bus 4-Address Synthesiser DS3090 - 4.0 January 1997 The SP5511 is a single-chip frequency synthesiser designed for TV tuning systems. Control data is entered in the standard I2C BUS format. In 18-lead plastic DIL package, the SP5511 has three addressable current-limited output ports (P0-P3) and four bi-directional output ports (P0-P2) and four addressable bi-directional open-collector ports (P4-P7) of which P6 is also a 3-bit 5-level ADC input. The information on these ports can be read via the I2C BUS. The SP5511S is a variant in a 16-lead miniature plastic package, without P0-P2 but functionally identical in other respects to the SP5511. The device has four programmable I2C BUS addresses, allowing two or more synthesisers to be used in a system. CHARGE PUMP CRYSTAL Q1 CRYSTAL Q2 SDA SCL 1 2 3 4 18 17 16 15 DRIVE OUTPUT VEE RF INPUT RF INPUT VCC P0 OUTPUT PORT P1 OUTPUT PORT P2 OUTPUT PORT P3 ADD SELECT PORT 5 SP5511 14 6 7 8 9 13 12 11 10 † I/O PORT P7 FEATURES s Complete 1·3GHz Single Chip System * I/O PORT P6 † I/O PORT P5 † I/O PORT P4 s s s s s s s s s s Programmable via the I C BUS Low Power Consumption (240mW Typ.) Low Radiation Phase Lock Detector Varactor Drive Amp Disable 7 Controllable Outputs, 4 Bi-directional (SP5511) 4 Bi-directional Controllable Outputs (SP5511S) 5-Level ADC Variable I C BUS Address for Picture in Picture TV ESD Protection * 2 2 DP18 CHARGE PUMP CRYSTAL Q1 CRYSTAL Q2 SDA SCL 1 16 DRIVE OUTPUT VEE RF INPUT RF INPUT VCC NC P3 ADD SELECT PORT I/O PORT P4 SP5511S † I/O PORT P7 * I/O PORT P6 † I/O PORT P5 8 9 † * Normal ESD handling precautions should be observed. APPLICATIONS † = Logic level I/O port * = 3-bit ADC input MP16 s Cable Tuning Systems s VCRs ORDERING INFORMATION SP5511 NA DP (18-lead plastic package) SP5511S NA MP (16-lead miniature plastic package) Fig. 1 Pin connections – top view SP5511 ELECTRICAL CHARACTERISTICS TAMB = 210°C to 180°C, VCC = 14·5V to 15·5V. All pin references are to the SP5511 (DP18 package). These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Reference frequency 4MHz unless otherwise stated. Value Characteristic Supply current Prescaler input voltage Prescaler input impedance Prescaler input capacitance SDA, SCL Input high voltage Input low voltage Input high current Input low current Leakage current SDA Output voltage Charge pump current low Charge pump current high Charge pump output leakage current Charge pump drive output current Charge pump amplifier gain Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator negative resistance Output Ports P0-P2 sink current (see note 1) P0-P2 leakage current (see note 1) P4-P7 sink current P4-P7 leakage current Input Ports P3 input current high P3 input current low P4, P5, P7 input voltage low P4, P5, P7 input voltage high P6 input current high P6 input current low Pin Min. 14 15,16 15,16 Typ. 48 12·5 30 50 2 3 0 5·5 1·5 10 210 10 0·4 650 6170 65 500 6400 10 40 2 11-13 11-13 6-9 6-9 10 10 6,8,9 6,8,9 7 7 750 0·7 10 10 1 20·5 0·8 2·7 110 210 1 1·5 10 200 Ω Parallel resonant crystal (note 2) mV p-p Ω mA µA mA µA mA mA V V µA µA VOUT = 12V VOUT = 13·2V VOUT = 0·7V VOUT = 13·2V V pin 10 = 13·2V V pin 10 = 0V Max. 60 300 300 VCC = 5V mA mVrms 80MHz to 1GHz mVrms 1·3GHz, see Fig. 5 Ω pF V V µA µA µA V µA µA nA Units Conditions 4,5 4,5 4,5 4,5 4,5 4 1 1 1 18 Input voltage = VCC Input voltage = 0V When VCC = 0V Sink current = 3mA Byte 4, bit 2 = 0, pin 1 = 2V Byte 4, bit 2 = 1, pin 1 = 2V Byte 4, bit 4 = 1, pin 1 = 2V V pin 18 = 0·7V See Table 3 for ADC levels NOTES 1. Ports P0-P2 not present on the SP5511S 2. The maximum resistance quoted refers to all conditions, including start-up. 2 SP5511 ABSOLUTE MAXIMUM RATINGS All voltages are referred to VEE and pin 3 at 0V Parameter SP5511 Supply voltage RF input voltage Port voltage 14 15,16 6-9,11-13 6-9 11-13 10 6-9,11-13 15-16 1 18 2 4,5 Pin SP5511S 12 13,14 6-9 6-9 10 6-9 13-14 1 16 2 4,5 20·3 20·3 20·3 20·3 20·3 20·3 255 20·3 20·3 20·3 20·3 Min. 20·3 Value Max. 7 2·5 14 6 14 VCC10·3 50 VCC10·3 VCC10·3 VCC10·3 VCC10·3 VCC10·3 5·5 1150 1150 78 24 111 41 363 V V p-p V V V V mA V V V V V V °C °C °C/W °C/W °C/W °C/W mW With VCC applied VCC not applied Port in off state Port in on state Port in on state Units Conditions Total port output current RF input DC offset Charge pump DC offset Drive output DC offset Crystal oscillator DC offset SDA, SCL input voltage Storage temperature Junction temperature DP18 thermal resistance, chip-to-ambient DP18 thermal resistance, chip-to-case MP16 thermal resistance, chip-to-ambient MP16 thermal resistance, chip-to-case Power consumption at 5·5V VCC RF IN RF IN POWER ON DETECTOR LOCK DETECTOR 15 BIT DIVIDER RATIO LATCH I2C BUS TRANSCEIVER SDA 8-BIT LATCH PORT INFORMATION ADDRESS SELECT 3-BIT ADC 3 TTL LEVEL COMP CHARGE PUMP T0 CP CONTROL DATA LATCH T1 VEE OS PRE AMP 48 PRESCALER 15 BIT PROGRAMMABLE DIVIDER FDIV PHASE COMP F FCOMP DIVIDER 4512 OSC 4MHz Q1 CRYSTAL Q2 CHARGE PUMP DRIVE OUTPUT SCL LOGIC P3 P0 P1 P2 P4 P5 P6 P7 Fig. 2 Block diagram. (Ports P0-P2 not present on SP5511S) 3 SP5511 The SP5511 is programmed from an I2C BUS. Data and Clock are fed in on the SDA and SCL lines respectively as defined by the I2C Bus format. The synthesiser can either accept new data (write mode) or send data (read mode). The Tables in Fig. 3 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an I2C BUS system. Table 4 shows how the address is selected by applying a voltage to P3. The address input circuit is shown in Fig.6.The LSB of the address Byte (R/W) sets the device into read mode if it is high and write mode if it is low. When the SP5511 receives a correct address Byte it pulls the SDA line low during the acknowledge period and during following acknowledge periods after further data Bytes are programmed. When the SP5511 is programmed into the read mode the controlling device accepting the data must pull down the SDA line during the following acknowledge period to read another status Byte. FUNCTIONAL DESCRIPTION WRITE MODE (FREQUENCY SYNTHESIS) When the device is in the write mode Bytes 213 select the synthesised frequency while Bytes 415 select the output port states and charge pump information. Once the correct address is received and acknowledged, the first Bit of the next Byte determines whether that Byte is interpreted as Byte 2 or 4, a logic 0 for frequency information and a logic 1 for charge pump and output port information. Additional data Bytes can be entered without the need to readdress the device until an I2C stop condition is recognised. This allows a smooth frequency sweep for fine tuning or AFC purposes. If the transmission of data is stopped mid-byte (i.e., by another device on the bus) then the previously programmed byte is maintained. Frequency data from Bytes 2 and 3 is stored in a 15-bit shift register and is used to control the division ratio of the 15-bit programmable divider which is preceded by a divide-by-8 prescaler and amplifier to give excellent sensitivity at the local oscillator input; see Fig 5. The input impedance is shown in Figs. 7 and 8. The programmed frequency can be calculated by multiplying the programmed division ratio by 8 times the comparison frequency FCOMP. When frequency data is entered, the phase comparator, via the charge pump and varactor drive amplifier, adjusts the local oscillator control voltage until the output of the programmable divider is frequency and phase locked to the comparison frequency. The reference frequency may be generated by an external source capacitively coupled into pin 2 or provided by an onchip 4MHz crystal controlled oscillator. Note that the comparison frequency is 7·8125kHz when a 4MHz reference is used. Bit 2 of Byte 4 of the programming data (CP) controls the current in the charge pump circuit, a logic 1 for 6170µA and a logic 0 for 650µA, allowing compensation for the variable tuning slope of the tuner and also to enable fast channel changes over the full band. Bit 4 of Byte 4 (T0) disables the charge pump if set to a logic 1. Bit 8 of Byte 4 (OS) switches the charge pump drive amplifier’s output off when it is set to a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the phase comparator inputs are available on P6 and P7, a logic 1 connects FCOMP to P6 and FDIV to P7. Byte 5 programs the output ports P0-P7, a logic 0 for a high impedance output, logic 1 for low impedance (on). READ MODE When the device is in the read mode the status data read from the device on the SDA line takes the form shown in Table 2. Bit 1 (POR) is the power on reset indicator and is set to a logic 1 if the power supply to the device has dropped below a nominal 3V and the programmed information lost (e.g., when the device is initially turned on). The POR is set to 0 when the read sequence is terminated by a stop command. The outputs are all set to high impedance when the device is initially powered up. Bit 2 (FL) indicates whether the device is phase locked, a logic 1 is present if the device is locked and a logic 0 if the device is unlocked. Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports P7, P5 and P4 respectively. A logic 0 indicates a low level and a logic 1 a high level. If the ports are to be used as inputs they should be programmed to a high impedance state (logic1). These inputs will then respond to data complying with standard TTL voltage levels. Bits 6, 7 and 8 (A2,A1,A0) combine to give the output of the 5-level ADC. The 5-level ADC can be used to feed AFC information to the microprocessor from the IF section of the television, as illustrated in Fig. 4. 4 SP5511 MSB Address Programmable divider Programmable divider Charge pump and test bits I/O port control bits 1 0 2 7 LSB 1 2 14 0 2 13 0 2 12 0 2 11 MA1 MA0 2 10 0 2 2 8 0 A A A A A Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 2 9 26 CP P6 25 T1 P5 24 T0 P4 23 1 P3 22 1 21 1 1 P7 OS P2* P1* P0* Table 1 Write data format (MSB transmitted first) Address Status byte 1 1 0 I2 0 I1 0 I0 MA1 MA0 A2 A1 1 A0 A A Byte 1 Byte 2 POR FL Table 2 Read data format A2 1 0 0 0 0 A1 0 1 1 0 0 A0 0 1 0 1 0 Voltage input to P6 0·6VCC to 13·2V 0·45VCC to 0·6VCC 0·3VCC to 0·45VCC 0·15VCC to 0·3VCC 0V to 0·15VCC MA1 MA0 Voltage input to P3 0 0 1 1 0 1 0 1 0V to 0·1VCC Open circuit 0·4VCC to 0·6VCC† 0·9VCC to VCC Table 3 ADC levels A MA1, MA0 CP T1 T0 OS P7, P6, P5, P4, P3, P2*, P1*, P0* POR FL I2, I1, I0 A2, A1, A0 NOTE : : : : : : : : : : : Table 4 Address selection Acknowledge bit Variable address bits (see Table 4) Charge Pump current select Test mode selection Charge pump disable Varactor drive Output disable Switch Control output port states Power On Reset indicator Phase lock detect flag Digital information from ports P7, P5 and P4 respectively 5-level ADC data from P6 (see Table 3) † Programmed by connecting a 15kΩ resistor between pin 10 and VCC * Don’t care condition on SP5511S. Fig. 3 Data formats 5 SP5511 APPLICATION A typical application is shown in Fig. 4. All input/output interface circuits are shown in Fig. 6. 130V 112V 22k 39n 180n 0·1µ 10k 22k 1 2 4MHz SDA 3 4 18 17 1n 16 15 22k P0 P1 P2 2N3906 2N3906 2N3906 22k 22k 1n OSCILLATOR OUTPUT 2N3904 47k 10n VT VARACTOR DRIVE 15V 15V 18p CONTROL MICRO I2C BUS SCL P7 P6 P5 P4 5 SP5511 14 6 7 8 9 13 12 11 10 TUNER    BAND INPUTS   112V P3 AFC OUT IF SECTION IF SIGNAL Fig. 4 Typical application 300 VIN (mV RMS INTO 50 Ω ) 37·5 OPERATING WINDOW 25 12·5 80 500 1000 FREQUENCY (MHz) 1300 1500 Fig. 5 Typical input sensitivity 6 SP5511 VREF VCC 550 550 CHARGE PUMP RF INPUTS 170 DRIVE OUTPUT RF input Loop amplifier VCC VCC 30k P3 10k 3k SCL/SDA * * ON SDA ONLY ACK Address programming port SCL and SDA inputs NOT ON P0-P2 PORT 12k* CRYSTAL Q1 *NO RESISTOR ON P4-P7 CRYSTAL Q2 Reference oscillator Ports P0-P2 and P4-P7 (SP5511). P4- P7 only on SP5511S Fig. 6 SP5511 input/output interface circuits 7 SP5511 j1 j 0.5 j2 j 0.2 j5 0 0.2 0.5 1 2 5 1·25GHz 2j 5 2j 0.2 S11:ZO = 50Ω NORMALISED TO 50Ω 2j 0.5 2j 1 2j 2 FREQUENCY MARKER STEP = 250MHz Fig. 7 Typical input impedance, SP5511 j1 j 0.5 j2 j 0.2 j5 0 0.2 0.5 1 2 5 2j 5 2j 0.2 1·25GHz S11:ZO = 50Ω NORMALISED TO 50Ω 2j 0.5 2j 1 2j 2 FREQUENCY MARKER STEP = 250MHz Fig. 8 Typical input impedance, SP5511S 8 SP5511 PACKAGE DETAILS Dimensions are shown thus: mm (in). 1 7·11 (0·28) MAX 18 0·23/0·41 (0·009/0·016) PIN 1 REF NOTCH 7·62 (0·3) NOM CTRS 1·14/1·65 (0·045/0·107) 25·40 (1·000) MAX 5·08/(0·20) MAX 0·51 (0·02) 3·05 (0·120) MIN MIN 0·38/0·61 (0·015/0·24) 18 LEADS AT 2·54 (0·10) NOM. SPACING 18-LEAD PLASTIC DIL – DP18 This package outline diagram is for guidance only. Please contact your GPS Customer Service Centre for further information. 9·80/10·01 (0·386/0·394) 0·19/0·25 (0·007/0·010) 0·37 (0·015) 345° 16 SPOT REF. CHAMFER REF. PIN 1 0·35/0·49 (0·014/0·019) 5·80/6·20 3·80/4·00 (0·150/0·157) (0·228/0·244) 0-8° 0·41/1·27 (0·016/0·050) 0·69 (0·027) MAX 16 LEADS AT 1·27 (0·050) NOM SPACING 0·10/0·25 1·35/1·75 (0·004/0·010) (0·053/0·069) 16-LEAD MINIATURE PLASTIC DIL - MP16 This package outline diagram is for guidance only. Please contact your GPS Customer Service Centre for further information. 9 SP5511 NOTES 10 SP5511 NOTES 11 For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. 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