SP5524SKG

Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ SP5524 Bidirectional I2C Bus Controlled Synthesiser DS3900 - 2.1 March 1995 The SP5524 is a single-chip frequency synthesiser designed for TV tuning systems. Control data is entered in the standard I2C BUS format. The device has six controllable open-collector output ports (P0-P3, P6 and P7), each capable of sinking 10mA. In addition, P1 is a 3-bit 5-level ADC input. The information on these ports can be read via the I2C BUS. The device has one fixed I2C BUS address and three programmable addresses, allowing two or more synthesisers to be used in a system. CHARGE PUMP CRYSTAL Q1 CRYSTAL Q2 SDA SCL 1 16 DRIVE OUTPUT VEE RF INPUT RF INPUT VCC P6 OUTPUT PORT P7 OUTPUT PORT/ADD SELECT I/O PORT P3 SP5524S ¦ I/O PORT P0 * I/O PORT P1 ¦ I/O PORT P2 8 9 FEATURES s Complete 1·3GHz Single Chip System ¦ MP16 Fig. 1 Pin connections – top view s s s s s s s s s Programmable via the I C BUS Low Power Consumption (215mW Typ.) Low Radiation Phase Lock Detector Varactor Drive Amp Disable 6 Controllable Outputs, 4 Bi-directional 5-Level ADC Variable I2C BUS Address for Picture in Picture TV ESD Protection * APPLICATIONS s Satellite TV when Combined with SP4902 2·5GHz Prescaler 2 s Cable Tuning Systems s VCRs ORDERING INFORMATION SP5524S KG MPAS (Tubes) SP5524S KG MPAD (Tape and Reel) * Normal ESD handling precautions should be observed. SP5524 ELECTRICAL CHARACTERISTICS TAMB = -10°C to +80°C, VCC = +4·5V to +5·5V. These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Reference frequency 4MHz unless otherwise stated. Value Characteristic Supply current Prescaler input voltage Prescaler input impedance Prescaler input capacitance SDA, SCL Input high voltage Input low voltage Input high current Input low current Leakage current SDA Output voltage Charge pump current low Charge pump current high Charge pump output leakage current Charge pump drive output current Charge pump amplifier gain Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator negative resistance Output Ports P0-P3, P6, P7 sink current (see note 1) P0-P3, P6, P7 leakage current (see note 1) Input Ports P7 input current high P7 input current low P0, P2, P3 input voltage low P0, P2, P3 input voltage high P1 input current high P1 input current low Pin Min. 12 13,14 13,14 Typ. 43 12·5 30 50 2 3 0 5·5 1·5 10 -10 10 0·4 ± 50 ± 170 ±5 500 6400 10 40 2 6-11 6-11 10 10 6,8,9 6,8,9 7 7 750 10 10 +10 -10 0·8 2·7 +10 -10 200 Ω Parallel resonant crystal (note 2) mV p-p Ω mA µA µA µA V V µA µA VOUT = 0·7V, see note 1 VOUT = 13·2V V pin 10 = 13·2V V pin 10 = 0V Max. 53 300 300 VCC = 5V mA mVrms 100MHz to 1GHz mVrms 50MHz and 1·3GHz, see Fig. 5 Ω pF V V µA µA µA V µA µA nA µA Units Conditions 4,5 4,5 4,5 4,5 4,5 4 1 1 1 16 Input voltage = VCC Input voltage = 0V When VCC = 0V Sink current = 3mA Byte 4, bit 2 = 0, pin 1 = 2V Byte 4, bit 2 = 1, pin 1 = 2V Byte 4, bit 4 = 1, pin 1 = 2V V pin 16 = 0·7V See Table 3 for ADC levels NOTES 1. Source impedance between all output ports and ground is approximately 5Ω. This should be taken into account when calculating output port saturation voltages. 2. The recommended crystal series resistance quoted refers to all conditions including start-up. 2 SP5524 ABSOLUTE MAXIMUM RATINGS All voltages are referred to VEE and pin 3 at 0V. Parameter Supply voltage RF input voltage Port voltage Total port output current RF input DC offset Charge pump DC offset Drive output DC offset Crystal oscillator DC offset SDA, SCL input voltage Pin Min. 12 13,14 6-11 6-11 6-11 13-14 1 16 2 4,5 -0·3 -0·3 -0·3 -0·3 -0·3 -0·3 -55 -0·3 -0·3 -0·3 Value Max. 6 2·5 14 6 50 VCC+0·3 VCC+0·3 VCC+0·3 VCC+0·3 VCC+0·3 5·5 +150 +150 111 41 321 V V p-p V V mA V V V V V V °C °C °C/W °C/W mW With VCC applied VCC not applied Port in off state Port in on state Units Conditions Storage temperature Junction temperature MP16 thermal resistance, chip-to-ambient MP16 thermal resistance, chip-to-case Power consumption at 5·5V VCC RF IN RF IN PRE AMP 48 PRESCALER LOCK DETECTOR 15 BIT PROGRAMMABLE DIVIDER FDIV PHASE COMP F FCOMP DIVIDER 4512 OSC 4MHz Q1 CRYSTAL Q2 POWER ON DETECTOR CHARGE PUMP SCL I2C BUS TRANSCEIVER 15 BIT DIVIDER RATIO LATCH CHARGE PUMP T0 CP DRIVE OUTPUT SDA 6-BIT LATCH PORT INFORMATION ADDRESS SELECT 3-BIT ADC CONTROL DATA LATCH T1 OS LOGIC 3 TTL LEVEL COMP VEE P6 P7 P3 P2 P1 P0 Fig. 2 Block diagram 3 SP5524 The SP5524 is programmed from an I2C BUS. Data and Clock are fed in on the SDA and SCL lines respectively as defined by the I2C Bus format. The synthesiser can either accept new data (write mode) or send data (read mode). The Tables in Fig. 3 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an I2C BUS system. Table 4 shows how the address is selected by applying a voltage to P7. The LSB of the address byte (R/W) sets the device into read mode if it is high and write mode if it is low. When the SP5524 receives a correct address byte it pulls the SDA line low during the acknowledge period and during following acknowledge periods after further data bytes are programmed. When the SP5524 is programmed into the read mode the controlling device accepting the data must pull down the SDA line during the following acknowledge period to read another status byte. FUNCTIONAL DESCRIPTION WRITE MODE (FREQUENCY SYNTHESIS) When the device is in the write mode Bytes 2+3 select the synthesised frequency while Bytes 4+5 select the output port states and charge pump information. Once the correct address is received and acknowledged, the first bit of the next byte determines whether that byte is interpreted as Byte 2 or 4, a logic 0 for frequency information and a logic 1 for charge pump and output port information. Additional data bytes can be entered without the need to readdress the device until an I2C stop condition is recognised. This allows a smooth frequency sweep for fine tuning or AFC purposes. If the transmission of data is stopped mid-byte (e.g., by another device on the bus) then the previously programmed byte is maintained. Frequency data from Bytes 2 and 3 is stored in a 15-bit shift register and is used to control the division ratio of the 15-bit programmable divider which is preceded by a divide-by-8 prescaler and amplifier to give excellent sensitivity at the local oscillator input; see Fig 5. The input impedance is shown in Fig. 7. The programmed frequency can be calculated by multiplying the programmed division ratio by 8 times the comparison frequency FCOMP. When frequency data is entered, the phase comparator, via the charge pump and varactor drive amplifier, adjusts the local oscillator control voltage until the output of the programmable divider is frequency and phase locked to the comparison frequency. The reference frequency may be generated by an external source capacitively coupled into pin 2 or provided by an onchip 4MHz crystal controlled oscillator. Note that the comparison frequency is 7·8125kHz when a 4MHz reference is used. Bit 2 of Byte 4 of the programming data (CP) controls the current in the charge pump circuit, a logic 1 for ±170µA and a logic 0 for ±50µA, allowing compensation for the variable tuning slope of the tuner and also to enable fast channel changes over the full band. Bit 4 of Byte 4 (T0) disables the charge pump if set to a logic 1. Bit 8 of Byte 4 (OS) switches the charge pump drive amplifier’s output off when it is set to a logic 1. Bit 3 of Byte 4 (T1) selects a test mode where the phase comparator inputs are available on P6 and P7, a logic 1 connects F COMP to P6 and FDIV to P7. Byte 5 programs the output ports P0-P3, P6 and P7, a logic 0 for a high impedance output, logic 1 for low impedance (on). READ MODE When the device is in the read mode the status data read from the device on the SDA line takes the form shown in Table 2. Bit 1 (POR) is the power on reset indicator and is set to a logic 1 if the power supply to the device has dropped below a nominal 3V and the programmed information lost (e.g., when the device is initially turned on). The POR is set to 0 when the read sequence is terminated by a stop command. The outputs are all set to high impedance when the device is initially powered up. Bit 2 (FL) indicates whether the device is phase locked, a logic 1 is present if the device is locked and a logic 0 if the device is unlocked. Bits 3, 4 and 5 (I2, I1, I0) show the status of the I/O Ports P0, P2 and P3 respectively. A logic 0 indicates a low level and a logic 1 a high level. If the ports are to be used as inputs they should be programmed to a high impedance state (logic1). These inputs will then respond to data complying with standard TTL voltage levels. Bits 6, 7 and 8 (A2,A1,A0) combine to give the output of the 5-level ADC. The 5-level ADC can be used to feed AFC information to the microprocessor from the IF section of the television, as illustrated in Fig. 4. 4 SP5524 MSB Address Programmable divider Programmable divider Charge pump and test bits I/O port control bits 1 0 2 7 LSB 1 2 14 6 0 2 13 5 0 2 12 4 0 2 11 3 MA1 MA0 2 10 2 0 2 2 8 0 A A A A A Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 2 2 9 1 2 2 2 2 2 1 P7 CP P6 T1 X T0 X 1 P3 1 P2 1 P1 OS P0 Table 1 Write data format (MSB transmitted first) Address Status byte 1 1 0 I2 0 I1 0 I0 MA1 MA0 A2 A1 1 A0 A A Byte 1 Byte 2 POR FL Table 2 Read data format A2 1 0 0 0 0 A1 0 1 1 0 0 A0 0 1 0 1 0 Voltage input to P1 0·6VCC to 13·2V 0·45VCC to 0·6VCC 0·3VCC to 0·45VCC 0·15VCC to 0·3VCC 0V to 0·15VCC MA1 MA0 Voltage input to P7 0 0 1 1 0 1 0 1 0V to 0·2VCC Always valid 0·3VCC to 0·7VCC 0·8VCC to 13·2V Table 3 ADC levels A MA1, MA0 CP T1 T0 OS P7, P6 P3, P2, P1, P0 POR FL I2, I1, I0 A2, A1, A0 X : : : : : : : : : : : : Table 4 Address selection Acknowledge bit Variable address bits (see Table 4) Charge Pump current select Test mode selection Charge pump disable Varactor drive Output disable Switch Control output port states Power On Reset indicator Phase lock detect flag Digital information from ports P0, P2 and P3 respectively 5-level ADC data from P1 (see Table 3) Don't care Fig. 3 Data formats 5 SP5524 APPLICATION A typical application is shown in Fig. 4. All input/output interface circuits are shown in Fig. 6. 130V 112V 22k 39n 180n 0·1µ 10k 22k 2N3904 47k 10n VT VARACTOR DRIVE 15V 15V 4MHz SDA 18p 1 16 1n 1n OSCILLATOR OUTPUT CONTROL MICRO I2C BUS SCL SP5524S TUNER P1 22k 22k 22k 8 112V 9 P3 P2 P0 12k 12k 2N3906 12k 2N3906 2N3906    BAND INPUTS   AFC OUT IF SECTION IF SIGNAL Fig. 4 Typical application 300 VIN (mV RMS INTO 50 Ω 37·5 OPERATING WINDOW 30 25 12·5 50 100 500 1000 FREQUENCY (MHz) 1300 1500 Fig. 5 Typical input sensitivity 6 SP5524 VREF VCC 550 13 RF INPUTS 550 1 CHARGE PUMP 170 14 16 DRIVE OUTPUT RF input Loop amplifier VCC VCC NOT ON P6 PORT 3k SCL/SDA * * ON SDA ONLY Ports P0 - P3, P6 and P7 SCL and SDA inputs ACK 2 CRYSTAL Q1 3 CRYSTAL Q2 Reference oscillator Fig. 6 Input/output interface circuits 7 SP5524 j1 j 0.5 j2 j 0.2 j5 0 0.2 0.5 1 2 5 2j 5 2j 0.2 1·25GHz S11:ZO = 50Ω NORMALISED TO 50Ω 2j 0.5 2j 1 2j 2 FREQUENCY MARKER STEP = 250MHz Fig. 7 Typical input impedance 8 For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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