VP215

VP215 Dual 90MHz 6-Bit Analog to Digital Converter Preliminary Information DS4068 - 1.4 May 1996 The VP215 is a dual 90MHz 6-bit Analog to Digital Converter designed for use in consumer satellite receivers and decoders, video systems, multimedia and communications applications. Operating from a single +5V supply, the VP215 includes an on-chip high bandwidth ADC driver amplifier, a 6-bit ADC and digital I/O that can be interfaced to either +5V or +3V. The VP215 also has the necessary bias voltages for the reference resistor chain in the 'flash' architecture of the ADC. CLKIN VCCD DGND VRT COMPA VINA AGND VCCA VRM COMPB VINB VRB N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 DA5 DA4 DA3 DA2 DA1 DA0 OGND VCCO DB5 DB4 DB3 DB2 DB1 DB0 FEATURES s 90MHz Conversion Rate s TTL Clock/Data Interface s 0.5 Volt Analog Input Range s Internal ADC Reference s Digital I/O’s compatible with +5V or +3V logic s Single 5 Volt Supply s Dual ADC System for good channel matching APPLICATIONS s Satellite Decoders s Multimedia s Communications ORDERING INFORMATION VP215A CG MP1S (Commercial - 28 pin plastic SO) VP215 21 20 19 18 17 16 15 MP28 Fig.1 Pin connections - top view (wide body) ------------------------------------------------2 8 21 COMPA VINA VRM 5 6 9 VRB VRM VRT VCCD VCCA VCCO ADC DRIVER + 6-BIT ADC 6 LATCHES DATA OUTPUTS 23 24 25 26 27 28 DA0 DA1 DA2 DA3 DA4 DA5 VRB 12 VREF OP AMPS CLOCK DRIVER 1 CLKIN VRT VINB COMPB VRB VRM VRT 4 11 10 3 7 + ADC DRIVER 6-BIT ADC 6 LATCHES DATA OUTPUTS 15 16 17 18 19 20 DB0 DB1 DB2 DB3 DB4 DB5 ------------------------------------------------DGND AGND OGND 22 Fig.2 System block diagram VP215 ABSOLUTE MAXIMUM RATINGS DC supply voltage (VCCA, VCCD, VCCO) -0.3 to+7V Analog input voltage (VIN) -0.3 to VCC+0.3V Digital inputs (CLKIN) VCC Digital output current (Ioh, Iol, Isc) -20 to +20mA Ambient operating temperature (Tamb) 0°C to +70°C Storage temperature (Tstorage) -55°C to +125°C THERMAL CHARACTERISTICS THERMAL RESISTANCES Junction to case(Θjc) Junction to ambient(Θja) 32°C/W 84°C/W ELECTRICAL CHARACTERISTICS Test conditions (unless otherwise stated) Tamb = 25°C, VCCA/D/O = +5V, full temperature range = 0°C to +70°C DC CHARACTERISTICS All specifications apply to either of the two ADCs Characteristic Resolution Static performance Differential non-linearity Integral non-linearity No missing codes Power supply Analog supply voltage Digital supply voltage Output supply voltage Analog supply current Digital supply current Output supply current Power dissipation Analog input Input range Input resistance Input capacitance Gain variation Gain matching Input -3dB bandwidth Ain input voltage Comp output CLKIN Input voltage high Input voltage low Input current high Input current low TTL digital outputs Output voltage high Output voltage low Output current high Output current low VCCA VCCD VCCO AICC DICC OICC PD Vin Rin Cin GV Gm F3dB Aindc Vcomp Vih Vil Iih Iil Symbol DNL INL Temp. +25°C Full +25°C Full Full Full Full Full +25°C Full +25°C Full +25°C Full +25°C Full +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full +25°C Full Test Level 4 4 4 4 4 4 4 4 1 4 1 4 1 4 1 5 1 5 4 1 4 1 1 1 4 1 4 1 4 1 4 1 4 1 4 1 4 1 4 4.75 4.75 4.75 14 34 3 260 20k 3.35 1.8 2.0 –0.2 2.4 Min. 6 Value Typ. Guaranteed 5.0 5.0 5.0 19 42 11 360 0.5 25k 4.0 200 3.6 2.0 –0.35 5.25 5.25 5.25 26 51 15 460 30k 0.25 0.25 3.85 2.2 0.8 1 –0.5 3.0 0.4 -400 1 V V V mA mA mA mA mA mA mW V Ω pF dB dB MHz V V V V V V µA mA Pk to Pk Max. ±0.5 ±0.5 ±0.5 ±0.5 Units Bits LSB LSB LSB LSB Conditions Fin=300Hz to 20MHz Fin=15.36MHz VCCD = 5.25V Vin = 2.7V VCCD = 5.25V Vin = 0.4V VCCO = 4.75V Ioh = 400µA VCCO = 4.75V Iol = 1mA VCCO = 4.75V VCCO = 4.75V Voh Vol Ioh Iol V V V V µA mA - 2 VP215 DC CHARACTERISTICS (cont.) Characteristic Reference voltage Vref ladder bottom Vref ladder middle Vref ladder top AC CHARACTERISTICS Characteristic Switching performance Clock high pulse width Clock low pulse width Max. conversion rate Data output setup time Data output hold time Aperture delay Aperture delay matching Aperture jitter Dynamic performance Differential non-linearity Integral non-linearity Signal to noise ratio Total harmonic distortion Effective No. of bits Crosstalk rejection Input offset Error rate Symbol Temp. Test Level 4 4 1 4 4 4 4 4 4 4 1 4 1 5 1 5 Min. 5.7 5.7 90 4 3 2 10 –0.95 31.8 40 5.0 Value Typ. 6 6 3 0.25 25 5.6 50 ±0.5 10e-8 Max. 8 8 4 0.5 50 +1.2 ±1 ±1 Units Conditions Symbol Temp. Test Level 1 1 1 Min. 2.367 2.848 3.337 Value Typ. 2.525 3.04 3.55 Max. 2.671 3.212 3.763 Units Conditions VRB VRM VRT +25°C +25°C +25°C V V V Tpw1 Tpw0 Fmax Tsetup Thold Tad Tadδ Taj DNL INL SNR THD ENOB CTR Vos BER +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C ns ns MHz ns ns ns ns ps rms LSB LSB dB dBc bits dBc LSB Cload=10pF Cload=10pF FCLK = 90.11MHz FIN = 11.26MHz NOTES 1. An input voltage of 0.0 volts ±0.5 LSB should nominally correspond to the ‘011111’ to ‘100000’B transition edge. TEST LEVELS Level 1 - 100% production tested. Level 2 - 100% production tested at 25°C and sample tested at specified temperatures. Level 3 - Sample tested only. Level 4 - Parameter is guaranteed by design and characterisation testing. Level 5 - Parameter is typical value only. Input Voltage Code 0.5 Volt Full Scale 00 01 q 31 32 33 q 62 63 Least positive valid input q 0 q Most positive valid input Digital Output Binary 000000 000001 q 011111 100000 100001 q 111110 111111 Table 1: Output coding 3 VP215 PIN DESCRIPTIONS - 28 Pin Plastic SO Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name CLKIN VCCD DGND VRT COMPA VINA AGND VCCA VRM COMPB VINB VRB N.C. N.C. DB0 DB1 DB2 DB3 DB4 DB5 VCCO OGND DA0 DA1 DA2 DA3 DA4 DA5 Description TTL clock input Digital voltage supply for ADC’s and input clock Digital ground Reference voltage- ladder top Capacitor compensation - A channel Analog signal input - A channel Analog ground Analog voltage supply for drivers and references Reference voltage- ladder middle Capacitor compensation - B channel Analog signal input - B channel Reference voltage- ladder bottom Not connected Not connected TTL digital output - channel B - LSB TTL digital output - channel B - MSB Output voltage supply for TTL data outputs Output ground TTL digital output - channel A - LSB TTL digital output - channel A - MSB Table 2: Pin descriptions ELECTRICAL CHARACTERISTICS DEFINITIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency, as determined by FFT analysis is reduced by 3dB. Aperture Delay The delay between the rising edge of the 90MHz clock signal and the instant the analog input signal is sampled. Aperture Jitter The sample to sample variation in aperture delay. Bit Error Rate (BER) The number of spurious code errors produced for any given input sinewave frequency at a given clock frequency. In this case it is the number of codes occurring outside the histogram cusp for a 1/2 FS sinewave. Data Outputs, Set-up and Hold Time Data output timings are measured from the 50% threshold to the 50% threshold on the rising edge of the output clock. Differential Non-linearity The deviation in any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) This is a measure of a device's dynamic performance and may be obtained from the SNR or from a sine wave curve test fit according to the following expressions: ENOB = SNR-1.76/6.02 or ENOB = N-log2[rms error (actual)/rms error (ideal)] where N is the conversion resolution and the actual rms error is the deviation from an ideal sine wave, calculated from the converter outputs with a sine wave input. Integral Non-linearity (INL) The deviation of the centre of each code from a reference line which has been determined by a least squares curve fit. Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude to the rms value of ‘noise’ which is defined as the sum of all other spectral components, including the harmonics, but excluding D.C. with a full-scale analog input signal. 4 VP215 Device Description The VP215 is a dual 90MHz 6-bit ADC system, (see Fig.2). Included on chip is a high bandwidth ADC driver amplifier, a 6-bit analog to digital converter, latches and TTL compatible data outputs. The VP215 also has the necessary bias voltages for the reference resistor chain in the ‘flash’ architecture of the ADC. VRM Analog Input The analog inputs, (VIN A,B) are A.C. coupled into the non-inverting input of the ADC driver amplifiers, which provide the necessary bandwidth, gain, offset and low impedance required to drive the ADC. The amplifier has been designed so that an input of 0 volts will produce an output level equal to the voltage present at the middle of the ADC resistor chain, VRM (3.00V typ.). This is achieved by an internal feedback loop within each amplifier which compares the amplifier output with VRM, (see Fig.3). This voltage will produce a transition binary code of 011111 to 100000 at the output of the ADC. INPUT SIGNAL CC ADC DRIVER AMP TO ADC DC SHIFT COMP_(Q,I) CCOMP Reference Voltage An on chip band gap voltage reference circuit combined with two op-amps provides all the necessary bias voltages for the ADC reference resistor chain, bottom (VRB), middle (VRM) and top(VRT). VRB, VRM and VRT have been brought out to pins 12, 9 and 4 respectively and should be decoupled with 100nF capacitors close to the package pins. Fig.3 DC offset internal feedback loop Digital Interface The TTL data output pins, (DA0-DA5) and (DB0-DB5), have been optimized to interface with devices in close proximity to the VP215 and are designed to provide satisfactory logic levels at speeds up to 90MHz into a fanout of one and a total load capacitance of 10pF. All data outputs should have approximately equivalent loading to ensure proper setup and hold times. For capacitive loads in excess of 10pF, output buffers are recommended. ADC Circuit The VP215 employs a ‘flash’ architecture consisting of a reference resistor chain, an array of 64 comparators, encoding logic and a 6-bit latch. The 63 reference levels generated by the resistor chain are compared with the analog output signal from the ADC driver amplifier using the comparator array. This produces a thermometer code which the encoding logic converts into a 6-bit word. Clock Interface The clock signal to the ADC synchronizes the sampling, conversion and output stages of the device as shown in the timing diagram (see Fig.4). The output of the ADC driver amp is sampled when the comparator array is latched on the rising edge of the input clock. Data is then presented to the TTL data outputs and latched on the falling edge of the input clock. V ref. VIN(A,B) Comparator Latch C L τ1 Data Out Clock to ADC N-1 N N+1 VIN(A,B) Tpw 1 CLKIN Tpw 0 Data Outputs N-1 N Tsu Fig.4 System timing diagram N+1 THold TTL Threshold 5 VP215 Layout And Grounding As with all high speed A to D converters, careful consideration must be given to the PCB layout. High performance can be obtained from the VP215 by tying all grounds to a solid low impedance ground plane. Separate analog and digital ground planes with a single common link under the device can also be used to help reduce the amount of digital noise fed back into the analog section of the converter. The VP215 should be decoupled with low impedance 100nF ceramic capacitors close to the package pins to avoid lead inductance effects and the decoupling on supply lines should further be improved by using a 47µF tantalum capacitor in parallel with a 100nF ceramic capacitor. If VCCA is derived from VCCD, a small inductor should be used to reduce digital noise on the analog power supply. Jitter and noise on clock input pins must be minimised. Long clock lines should therefore be avoided and all clock lines correctly terminated. Cross talk of digital signals to the analog inputs must also be prevented as sampling cross talk produces DC offsets on the sampled data, for this reason analog inputs should not be run next to clock or data lines. Device connections to the ground plane should be as short as possible. CLKIN 50R 1 1.2µH 100n 28 27 26 25 A Channel Data 2 3 4 100n 5 6 7 8 Cc Ccomp VP215 24 23 22 21 100n 47µ 100n VINA 50R VCCA 47µ 100n 100n VCCD 9 100n Cc Ccomp 20 19 18 17 16 15 Analog Ground Digital Ground B Channel Data 10 11 VINB 50R 100n 12 13 14 Fig.5 Applications diagram Application Circuit Fig.5 shows a typical applications circuit for the VP215. The supply connections are made using separate low noise digital and analog power supplies and VCCD is further isolated from VCCO using a 1.2µH inductor. The COMPA and COMPB pins must be decoupled to reduce any ripple at low frequencies which may distort the ADC driver amplifier output, (see Fig.2.) The decoupling capacitor value is determined by the required low frequency performance of the system and can be obtained from the following equation. A ripple voltage ≤ 10mV is recommended for good system performance, e.g. If the analog input frequency Fin= 10KHz a value of 0.75µF is required for CComp. To ensure effective A.C. coupling at low input frequencies, the coupling capacitors on pins 6 and 11 can be calculated from the high pass filter corner frequency equation, Fc = 1 2 x π x RC CComp = 75x10- 6 Fin x VRipple where Fc = Lower -3dB corner frequency (R = Input Resistance, 25K typ. - 20K min) 6 For more information about all Zarlink products visit our Web Site at w ww.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. 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