EZ80F91AZ050SK

eZ80Acclaim!® Flash Microcontrollers eZ80F91 MCU Product Brief PB013507-0412 Product Block Diagram • eZ80F91 MCU • 256 KB Flash + 512 B Flash 32-Bit GPIO 8 KB SRAM 10/100 Mbps Ethernet MAC 8 KB Frame Buffer Infrared Encoder/ 2 UART Decoder 4 PRT 4 CS + WSG I2C • SPI • Real Time Clock WDT JTAG • ZDI PLL • • • Key Features The eZ80F91 MCU is a member of Zilog’s eZ80Acclaim! product family, which offers onchip Flash versions of Zilog’s eZ80® processor core. The eZ80F91 MCU offers the following features: • 50 MHz high-performance eZ80 CPU • 256 KB Flash Program Memory and extra 512 B device configuration Flash Memory • 32 bits of General-Purpose Input/Output (GPIO) • 16 KB total on-chip high-speed SRAM: – 8 KB for general-purpose use – 8 KB for 10/100 BaseT Ethernet Media Access Controller (EMAC) high-speed frame buffer • IrDA-compatible infrared encoder/decoder • Two universal asynchronous receiver/ transmitter (UARTs) with independent baud rate generators • • • • • Inter-integrated circuit (I2C) and serial peripheral interface (SPI) with independent clock rate generator Four counter/timers with prescalers supporting event counting, input capture, output compare, and Pulse Width Modulator (PWM) modes Watchdog Timer (WDT) with internal RC clocking option Real time clock (RTC) with on-chip 32 KHz oscillator, selectable 50/60 Hz input, and separate RTC_VDD pin for battery backup Glueless external memory interface with 4 Chip-Selects/Wait-State Generators and external WAIT input pin. It also supports Intel and Motorola buses JTAG and Zilog Debug Interface (ZDI) supporting emulation features Low-power PLL and on-chip oscillator Programmable-priority vectored interrupts, non-maskable interrupts, and interrupt controller New DMA-like eZ80 CPU instructions Power management features supporting HALT/SLEEP modes and selective peripheral power-down controls 144-pin BGA package or 144-pin LQFP package 3.0 V to 3.6 V supply voltage with 5 V-tolerant inputs Operating temperature ranges: – Standard, 0ºC to +70ºC – Extended, –40ºC to +105ºC General Description The eZ80F91 MCU is industry’s first MCU featuring a high-performance 8-bit microcontroller with an integrated 10/100 BaseT EMAC. It is a power-efficient, optimized pipeline architecture Copyright ©2010 by ZiLOG, Inc. All rights reserved. www.zilog.com eZ80F91 MCU Product Brief 2 microcontroller with a maximum operating speed of 50 MHz. Offering on-chip Flash Memory, SRAM, Ethernet MAC, and rich peripherals, the eZ80F91 is well-suited for industrial, communication, automation, security, and embedded Internet applications. eZ80 CPU Core The eZ80 CPU operates either in Z80-compatible (64 KB) mode or full 24-bit (16 MB) addressing mode. Considering both the increased clock speed and processor efficiency, the processing power of the eZ80 CPU competes with the performance of 16-bit microprocessors. The eZ80 improves on the world-famous Z80 architecture. Like the Z80, the , eZ80 CPU features dual bank registers for fast context switching. eZ80F91 MCU Peripherals Description The eZ80F91 MCU includes the following peripheral elements: On-Chip Memory The eZ80F91 device offers 256 KB of Flash Program Memory. A separate page of 512 bytes Flash memory is available for general device configuration data. Other on-chip memory features include: • Single power supply operation • Page erase feature: 2048 bytes/page • Fast page erase and byte program operation • 78 ns minimum read cycle • Endurance: 10,000 write cycles (typical) • Data can be retained for more than 100 years at room temperature In addition, 16 KB of high-speed, relocatable SRAM is available, of which 8 KB is for generalpurpose use. Another 8 KB of SRAM is used by the EMAC for Ethernet operation, but is also useraccessible when Ethernet functionality is not required. General-Purpose Input/Output There are 32 bits of GPIO. All GPIO pins are individually programmable and support the PB013507-0412 following I/O modes: input, output, open drain, open source, level-triggered interrupts (High or Low), edge-triggered interrupts (High or Low), dual edge-triggered interrupts, and alternate function. Eight of the output pins can drive 10 mA each (Port A), while 16 other pins feature Schmitt-trigger input buffers (Port B and Port C). 10/100 BaseT Ethernet MAC The eZ80F91 MCU features an integrated IEEE 802.3 Ethernet controller with 8 KB of dynamically-configurable Tx/Rx frame buffer. It supports speed of 10 Mbps and 100 Mbps, full duplex operation, and an industry-standard Media Independent Interface (MII) for simple connection to an external Physical Layer interface (PHY) device. The eZ80F91 MCU delivers high performance and overall cost effectiveness as an embedded network microcontroller. High performance is achieved by optimizing the internal bus design of the eZ80 CPU with shared memories, dedicated Ethernet Tx/Rx DMAs, and Tx/Rx FIFOs. This bus design provides the highest data throughput over the Ethernet interface, yet requires minimum eZ80 CPU intervention and minimizes system loading. Infrared Encoder/Decoder • • • • Supports IrDA SIR format Operates seamlessly with on-chip UART Interfaces with IrDA-compliant transceivers Supports transmit/receive to 115 Kbps Universal Asynchronous Receiver/ Transmitter Each of the two UART channels contains a transmitter, a receiver, control logic/registers, and a Baud Rate Generator (BRG). • The BRG produces a lower-frequency bit clock from the system clock. All standard baud rates up to 115 Kbps (and higher) are supported. • The UART module implements the logic required to support asynchronous communications, hardware flow control, and 9-bit character format. The module also contains separate 16-byte-deep transmit and receive FIFOs. eZ80Acclaim! Flash Microcontrollers eZ80F91 MCU Product Brief 3 Inter-Integrated Circuit I2 C The channel contains control registers and a clock rate generator. The I2C interface operates in four modes: Master Transmit or Receive and Slave Transmit or Receive. A standard and fast I2C speed of 100 kbps and 400 kbps are supported. Serial Peripheral Interface The SPI channel contains control registers and a clock rate generator. The SPI is a synchronous serial interface allowing multiple SPI devices to be interconnected. The SPI interface is configured to function either as a master or a slave. Programmable Reload Timers The eZ80F91 MCU provides four independent Programmable Reloadable Counter Timers (PRT) to handle complex timing functions. Each timer is a 16-bit downcounter and offers a 4-bit clock prescaler with four selectable taps for CLK ÷ 4, CLK ÷ 16, CLK ÷ 64 and CLK ÷ 256. The timers operates in basic mode supporting SINGLE-PASS or CONTINUOUS count. Additional features include 4 input captures, 4 output compares, 2 external event counters, and 4 PWMs that can operate independently or in unison. Any one of the input capture pins can be programmed as master PWM power-trip inputs. Watchdog Timer The WDT features four programmable time-out periods. It operates either from the main system clock, the on-chip 32 KHz oscillator (from the RTC), or the internal RC oscillator. The time-out action of the WDT is user-programmable for either a hardware reset or a non-maskable interrupt to the eZ80 CPU. The source of action taken after a WDT time-out is indicated by a WDT status bit. Real Time Clock The RTC allows counting of seconds, minutes, hours, day-of-the-week, day-of-the-month, month, year, and century. Alarms and interrupts can be set for seconds, minutes, hours, and day-of-the-week. The RTC input is taken either from the on-chip 32 KHz oscillator or from a 50/60 Hz input. The PB013507-0412 RTC operates from an isolated RTC_V DD pin to allow constant operation from a battery. Chip-Select/Wait State Generator and WAIT Pin Four independent chip selects facilitate glueless interface to system memory and external devices. Each chip-select can be configured for up to 7 wait states and supports either memory or I/O space. Memory chip selects can be individually programmed on a 64 KB boundary. I/O chip selects can choose a 256-byte section of I/O space. The WAIT input pin allows interface with slow peripherals. It also supports Z80, Intel, and Motorola bus modes. JTAG Interface An IEEE 1149.1-compatible five-pin test access port (TAP) is provided to interface with on-chip test logic defined by IEEE standard. The TAP also includes Boundary Scan functions and is used to control on-chip emulation/debugging capabilities. Some features include software break points, 64word trace buffer, complex break points using address and data masks, and cascadable triggers. PLL and On-Chip Crystal Oscillator The eZ80F91 MCU features a low-power, programmable PLL that can be selected to generate the system clock. Taking the input from the on-chip crystal oscillator, the PLL generates system clock speed up to 50 MHz from low-cost, low-frequency external crystals in the range of 1 MHz to 10 MHz. Zilog Debug Interface The Zilog Debug Interface (ZDI) incorporates the functions of an in-circuit emulator. ZDI allows you to single-step code, change registers, edit programs, and view status of the internal registers. Block Transfer Instructions Block transfer instructions with expanded repeat capability are added to the eZ80 CPU. They provide high-performance data transfer similar to hardware DMAs. eZ80Acclaim! Flash Microcontrollers eZ80F91 MCU Product Brief 4 Power Management The eZ80F91 MCU supports several power management features. Two peripheral Power-Down Registers allow independent clock gating of on-chip peripherals under software control while operating under normal conditions. The eZ80 CPU writes to the control registers to disable the clock from driving any one of the peripherals while they are inactive. In addition, execution of the HALT instruction suspends eZ80 CPU operation and eliminates clock power associated with the eZ80 CPU core. Normal operation is restored via external and peripheral interrupts or hardware reset. • • • • Extended temperature, –40ºC to +105ºC Supply current at 50 MHz; 50 mA (typical) Supply current in HALT mode with peripherals powered down;