Z51F3220FNX

Z8051 Series 8-Bit Microcontrollers Z51F3220 Product Specification PS029902-0212 PRELIMINARY Copyright ©2012 Zilog®, Inc. All rights reserved. www.zilog.com Z51F3220 Product Specification ii Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2012 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8051 is a trademark or registered trademark of Zilog, Inc. All other product or service names are the property of their respective owners. PS029902-0212 PRELIMINARY Z51F3220 Product Specification iii Revision History Each instance in this document’s revision history reflects a change from its previous edition. For more details, refer to the corresponding page(s) or appropriate links furnished in the table below. Revision Level Description Page Feb 2012 02 Removed references to 28-pin SOP package. All Jan 2012 01 Original Zilog issue. All Date PS029902-0212 PRELIMINARY Revision History Z51F3220 Product Specification Table of Contents 1. Overview ............................................................................................................................................................... 10 1.1 Description ..................................................................................................................................................... 10 1.2 Features ......................................................................................................................................................... 11 1.3 Ordering Information ...................................................................................................................................... 12 1.4 Development Tools ........................................................................................................................................ 13 2. Block Diagram ...................................................................................................................................................... 16 3. Pin Assignment ..................................................................................................................................................... 17 4. Package Diagram ................................................................................................................................................. 19 5. Pin Description...................................................................................................................................................... 21 6. Port Structures ...................................................................................................................................................... 26 6.1 General Purpose I/O Port .............................................................................................................................. 26 6.2 External Interrupt I/O Port.............................................................................................................................. 27 7. Electrical Characteristics ...................................................................................................................................... 28 7.1 Absolute Maximum Ratings ........................................................................................................................... 28 7.2 Recommended Operating Conditions ........................................................................................................... 28 7.3 A/D Converter Characteristics ....................................................................................................................... 29 7.4 Power-On Reset Characteristics ................................................................................................................... 29 7.5 Low Voltage Reset and Low Voltage Indicator Characteristics .................................................................... 30 7.6 High Internal RC Oscillator Characteristics ................................................................................................... 31 7.7 Internal Watch-Dog Timer RC Oscillator Characteristics .............................................................................. 31 7.8 LCD Voltage Characteristics ......................................................................................................................... 32 7.9 DC Characteristics ......................................................................................................................................... 33 7.10 AC Characteristics ....................................................................................................................................... 35 7.11 SPI0/1/2 Characteristics .............................................................................................................................. 36 7.12 UART0/1 Characteristics ............................................................................................................................. 37 7.13 I2C0/1 Characteristics ................................................................................................................................. 38 7.14 Data Retention Voltage in Stop Mode ......................................................................................................... 39 7.15 Internal Flash Rom Characteristics ............................................................................................................. 40 7.16 Input/Output Capacitance ............................................................................................................................ 40 7.17 Main Clock Oscillator Characteristics .......................................................................................................... 41 7.18 Sub Clock Oscillator Characteristics ........................................................................................................... 42 7.19 Main Oscillation Stabilization Characteristics ............................................................................................. 43 7.20 Sub Oscillation Characteristics .................................................................................................................... 43 7.21 Operating Voltage Range ............................................................................................................................ 44 7.22 Recommended Circuit and Layout .............................................................................................................. 45 7.23 Typical Characteristics ................................................................................................................................ 46 8. Memory ................................................................................................................................................................. 49 8.1 Program Memory ........................................................................................................................................... 49 8.2 Data Memory ................................................................................................................................................. 51 8.3 XRAM Memory .............................................................................................................................................. 53 8.4 SFR Map ........................................................................................................................................................ 54 9. I/O Ports ................................................................................................................................................................ 63 9.1 I/O Ports ......................................................................................................................................................... 63 9.2 Port Register .................................................................................................................................................. 63 9.3 P0 Port ........................................................................................................................................................... 65 9.4 P1 Port ........................................................................................................................................................... 67 9.5 P2 Port ........................................................................................................................................................... 69 PS029902-0212 PRELIMINARY 1 Z51F3220 Product Specification 9.6 P3 Port ........................................................................................................................................................... 70 9.7 P4 Port ........................................................................................................................................................... 71 9.8 P5 Port ........................................................................................................................................................... 72 9.9 Port Function.................................................................................................................................................. 73 10. Interrupt Controller .............................................................................................................................................. 82 10.1 Overview ...................................................................................................................................................... 82 10.2 External Interrupt ......................................................................................................................................... 83 10.3 Block Diagram ............................................................................................................................................. 84 10.4 Interrupt Vector Table .................................................................................................................................. 85 10.5 Interrupt Sequence ...................................................................................................................................... 85 10.6 Effective Timing after Controlling Interrupt Bit ............................................................................................ 87 10.7 Multi Interrupt ............................................................................................................................................... 88 10.8 Interrupt Enable Accept Timing ................................................................................................................... 89 10.9 Interrupt Service Routine Address .............................................................................................................. 89 10.10 Saving/Restore General-Purpose Registers ............................................................................................. 89 10.11 Interrupt Timing.......................................................................................................................................... 90 10.12 Interrupt Register Overview ....................................................................................................................... 90 10.13 Interrupt Register Description .................................................................................................................... 92 11. Peripheral Hardware........................................................................................................................................... 99 11.1 Clock Generator........................................................................................................................................... 99 11.2 Basic Interval Timer ................................................................................................................................... 102 11.3 Watch Dog Timer ....................................................................................................................................... 105 11.4 Watch Timer............................................................................................................................................... 108 11.5 Timer 0 ....................................................................................................................................................... 111 11.6 Timer 1 ....................................................................................................................................................... 120 11.7 Timer 2 ....................................................................................................................................................... 130 11.8 Timer 3, 4 ................................................................................................................................................... 141 11.9 Buzzer Driver ............................................................................................................................................. 170 11.10 SPI 2 ........................................................................................................................................................ 172 11.11 12-Bit A/D Converter ............................................................................................................................... 178 11.12 USI0 (UART + SPI + I2C) ........................................................................................................................ 185 11.13 USI1 (UART + SPI + I2C) ........................................................................................................................ 222 11.15 LCD Driver ............................................................................................................................................... 260 12. Power Down Operation .................................................................................................................................... 272 12.1 Overview .................................................................................................................................................... 272 12.2 Peripheral Operation in IDLE/STOP Mode ............................................................................................... 272 12.3 IDLE Mode ................................................................................................................................................. 273 12.4 STOP Mode ............................................................................................................................................... 274 12.5 Release Operation of STOP Mode............................................................................................................ 275 13. RESET .............................................................................................................................................................. 277 13.1 Overview .................................................................................................................................................... 277 13.2 Reset Source ............................................................................................................................................. 277 13.3 RESET Block Diagram .............................................................................................................................. 277 13.4 RESET Noise Canceller ............................................................................................................................ 278 13.5 Power on RESET....................................................................................................................................... 278 13.6 External RESETB Input ............................................................................................................................. 281 13.7 Brown Out Detector Processor .................................................................................................................. 282 13.8 LVI Block Diagram ..................................................................................................................................... 283 14. On-chip Debug System .................................................................................................................................... 287 14.1 Overview .................................................................................................................................................... 287 14.2 Two-Pin External Interface ........................................................................................................................ 288 15. Flash Memory ................................................................................................................................................... 293 PS029902-0212 PRELIMINARY 2 Z51F3220 Product Specification 15.1 Overview .................................................................................................................................................... 293 16. Configure Option .............................................................................................................................................. 304 16.1 Configure Option Control ........................................................................................................................... 304 17. APPENDIX ........................................................................................................................................................ 305 PS029902-0212 PRELIMINARY 3 Z51F3220 Product Specification List of Figures Figure 1.4 StandAlone Gang8 (for Mass Production) ............................................................................... 15 Figure 2.1 Block Diagram .......................................................................................................................... 16 Figure 3.1 Z51F3220 44MQFP-1010 Pin Assignment .............................................................................. 17 Figure 3.2 Z51F3220 32SOP Pin Assignment .......................................................................................... 18 Figure 4.1 44-Pin MQFP Package ............................................................................................................. 19 Figure 4.2 32-Pin SOP Package................................................................................................................ 20 Figure 6.1 General Purpose I/O Port ......................................................................................................... 26 Figure 6.2 External Interrupt I/O Port ........................................................................................................ 27 Figure 7.1 AC Timing ................................................................................................................................. 35 Figure 7.2 SPI0/1/2 Timing ........................................................................................................................ 36 Figure 7.3 Waveform for UART0/1 Timing Characteristics ....................................................................... 37 Figure 7.4 Timing Waveform for the UART0/1 Module ............................................................................. 37 Figure 7.5 I2C0/1 Timing ........................................................................................................................... 38 Figure 7.6 Stop Mode Release Timing when Initiated by an Interrupt ...................................................... 39 Figure 7.7 Stop Mode Release Timing when Initiated by RESETB .......................................................... 39 Figure 7.8 Crystal/Ceramic Oscillator ........................................................................................................ 41 Figure 7.9 External Clock........................................................................................................................... 41 Figure 7.10 Crystal Oscillator .................................................................................................................... 42 Figure 7.11 External Clock......................................................................................................................... 42 Figure 7.12 Clock Timing Measurement at XIN ........................................................................................ 43 Figure 7.13 Clock Timing Measurement at SXIN ...................................................................................... 43 Figure 7.14 Operating Voltage Range ....................................................................................................... 44 Figure 7.15 Recommended Circuit and Layout ......................................................................................... 45 Figure 7.16 RUN (IDD1 ) Current .............................................................................................................. 46 Figure 7.17 IDLE (IDD2) Current ............................................................................................................... 46 Figure 7.18 SUB RUN (IDD3) Current....................................................................................................... 47 Figure 7.19 SUB IDLE (IDD4) Current ...................................................................................................... 47 Figure 7.20 STOP (IDD5) Current ............................................................................................................. 48 Figure 8.1 Program Memory ...................................................................................................................... 50 Figure 8.2 Data Memory Map .................................................................................................................... 51 Figure 8.3 Lower 128 Bytes RAM .............................................................................................................. 52 Figure 8.4 XDATA Memory Area ............................................................................................................... 53 Figure 10.1 External Interrupt Description ................................................................................................. 83 Figure 10.2 Block Diagram of Interrupt...................................................................................................... 84 Figure 10.3 Interrupt Vector Address Table .............................................................................................. 86 Figure 10.4 Effective Timing of Interrupt Enable Register ....................................................................... 87 Figure 10.5 Effective Timing of Interrupt Flag Register............................................................................. 87 Figure 10.6 Effective Timing of Interrupt ................................................................................................... 88 Figure 10.7 Interrupt Response Timing Diagram ...................................................................................... 89 Figure 10.8 Correspondence between Vector Table Address and the Entry Address of ISP .................. 89 Figure 10.9 Saving/Restore Process Diagram and Sample Source ......................................................... 89 Figure 10.10 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction ............................... 90 Figure 11.1 Clock Generator Block Diagram ............................................................................................. 99 Figure 11.2 Basic Interval Timer Block Diagram ..................................................................................... 102 PS029902-0212 PRELIMINARY 4 Z51F3220 Product Specification Figure 11.3 Watch Dog Timer Interrupt Timing Waveform ..................................................................... 105 Figure 11.4 Watch Dog Timer Block Diagram ......................................................................................... 106 Figure 11.5 Watch Timer Block Diagram................................................................................................. 108 Figure 11.6 8-Bit Timer/Counter Mode for Timer 0 ................................................................................. 112 Figure 11.7 8-Bit Timer/Counter 0 Example ............................................................................................ 112 Figure 11.8 8-Bit PWM Mode for Timer 0 ................................................................................................ 113 Figure 11.9 PWM Output Waveforms in PWM Mode for Timer 0 ........................................................... 114 Figure 11.10 8-Bit Capture Mode for Timer 0 .......................................................................................... 115 Figure 11.11 Input Capture Mode Operation for Timer 0 ........................................................................ 116 Figure 11.12 Express Timer Overflow in Capture Mode ......................................................................... 116 Figure 11.13 8-Bit Timer 0 Block Diagram .............................................................................................. 117 Figure 11.14 16-Bit Timer/Counter Mode for Timer 1 ............................................................................. 121 Figure 11.15 16-Bit Timer/Counter 1 Example ........................................................................................ 121 Figure 11.16 16-Bit Capture Mode for Timer 1........................................................................................ 122 Figure 11.17 Input Capture Mode Operation for Timer 1 ........................................................................ 123 Figure 11.18 Express Timer Overflow in Capture Mode ......................................................................... 123 Figure 11.19 16-Bit PPG Mode for Timer 1 ............................................................................................. 124 Figure 11.20 16-Bit PPG Mode Timming chart for Timer 1 ..................................................................... 125 Figure 11.21 16-Bit Timer/Counter Mode for Timer 1 and Block Diagram ............................................. 126 Figure 11.22 16-Bit Timer/Counter Mode for Timer 2 ............................................................................. 131 Figure 11.23 16-Bit Timer/Counter 2 Example ........................................................................................ 132 Figure 11.24 16-Bit Capture Mode for Timer 2........................................................................................ 133 Figure 11.25 Input Capture Mode Operation for Timer 2 ........................................................................ 134 Figure 11.26 Express Timer Overflow in Capture Mode ......................................................................... 134 Figure 11.27 16-Bit PPG Mode for Timer 2 ............................................................................................. 135 Figure 11.28 16-Bit PPG Mode Timming chart for Timer 2 ..................................................................... 136 Figure 11.29 16-Bit Timer/Counter Mode for Timer 2 and Block Diagram ............................................. 137 Figure 11.30 8-Bit Timer/Counter Mode for Timer 3, 4 ........................................................................... 142 Figure 11.31 16-Bit Timer/Counter Mode for Timer 3 ............................................................................. 143 Figure 11.32 8-Bit Capture Mode for Timer 3, 4..................................................................................... 145 Figure 11.33 16-Bit Capture Mode for Timer 3....................................................................................... 146 Figure 11.34 10-Bit PWM Mode (Force 6-ch) ........................................................................................ 148 Figure 11.35 10-Bit PWM Mode (Force All-ch) ...................................................................................... 149 Figure 11.36 Example of PWM at 4 MHz ............................................................................................... 150 Figure 11.37 Example of Changing the Period in Absolute Duty Cycle at 4 MHz .................................. 150 Figure 11.38 Example of PWM Output Waveform .................................................................................. 151 Figure 11.39 Example of PWM waveform in Back-to-Back mode at 4 MHz .......................................... 151 Figure 11.40 Example of Phase Correction and Frequency correction of PWM .................................... 152 Figure 11.41 Example of PWM External Synchronization with BLNK Input ........................................... 152 Figure 11.42 Example of Force Drive All Channel with A-ch .................................................................. 153 Figure 11.43 Example of Force Drive 6-ch Mode.................................................................................... 154 Figure 11.44 Example of PWM Delay ..................................................................................................... 157 Figure 11.45 Two 8-Bit Timer 3, 4 Block Diagram .................................................................................. 157 Figure 11.46 16-Bit Timer 3 Block Diagram ............................................................................................ 158 Figure 11.47 10-Bit PWM Timer 4 Block Diagram ................................................................................. 158 Figure 11.48 Buzzer Driver Block Diagram ............................................................................................. 170 Figure 11.49 SPI 2 Block Diagram .......................................................................................................... 172 Figure 11.50 SPI 2 Transmit/Receive Timing Diagram at CPHA = 0 ..................................................... 174 Figure 11.51 SPI 2 Transmit/Receive Timing Diagram at CPHA = 1 ..................................................... 174 PS029902-0212 PRELIMINARY 5 Z51F3220 Product Specification Figure 11.52 12-bit ADC Block Diagram ................................................................................................. 179 Figure 11.53 A/D Analog Input Pin with Capacitor .................................................................................. 179 Figure 11.54 A/D Power (AVREF) Pin with Capacitor ............................................................................ 179 Figure 11.55 ADC Operation for Align Bit................................................................................................ 180 Figure 11.56 A/D Converter Operation Flow ........................................................................................... 182 Figure 11.57 USI0 UART Block Diagram ................................................................................................ 187 Figure 11.58 Clock Generation Block Diagram (USI0) ........................................................................... 188 Figure 11.59 Synchronous Mode SCK0 Timing (USI0) .......................................................................... 189 Figure 11.60 Frame Format (USI0) ......................................................................................................... 190 Figure 11.61 Asynchronous Start Bit Sampling (USI0) ........................................................................... 194 Figure 11.62 Asynchronous Sampling of Data and Parity Bit (USI0) ..................................................... 194 Figure 11.63 Stop Bit Sampling and Next Start Bit Sampling (USI0) ..................................................... 195 Figure 11.64 USI0 SPI Clock Formats when CPHA0=0 ......................................................................... 197 Figure 11.65 USI0 SPI Clock Formats when CPHA0=1 ......................................................................... 198 Figure 11.66 USI0 SPI Block Diagram .................................................................................................... 199 Figure 11.67 Bit Transfer on the I2C-Bus (USI0) .................................................................................... 200 Figure 11.68 START and STOP Condition (USI0) .................................................................................. 201 Figure 11.69 Data Transfer on the I2C-Bus (USI0) ................................................................................. 201 Figure 11.70 Acknowledge on the I2C-Bus (USI0) ................................................................................. 202 Figure 11.71 Clock Synchronization during Arbitration Procedure (USI0).............................................. 203 Figure 11.72 Arbitration Procedure of Two Masters (USI0) .................................................................... 203 Figure 11.73 Formats and States in the Master Transmitter Mode (USI0) ............................................. 205 Figure 11.74 Formats and States in the Master Receiver Mode (USI0) ................................................. 207 Figure 11.75 Formats and States in the Slave Transmitter Mode (USI0) ............................................... 209 Figure 11.76 Formats and States in the Slave Receiver Mode (USI0) ................................................... 211 Figure 11.77 USI0 I2C Block Diagram .................................................................................................... 212 Figure 11.78 USI1 UART Block Diagram ................................................................................................ 224 Figure 11.79 Clock Generation Block Diagram (USI1) ........................................................................... 225 Figure 11.80 Synchronous Mode SCK1 Timing (USI1) .......................................................................... 226 Figure 11.81 Frame Format (USI1) ......................................................................................................... 227 Figure 11.82 Asynchronous Start Bit Sampling (USI1) ........................................................................... 231 Figure 11.83 Asynchronous Sampling of Data and Parity Bit (USI1) ..................................................... 231 Figure 11.84 Stop Bit Sampling and Next Start Bit Sampling (USI1) ..................................................... 232 Figure 11.85 USI1 SPI Clock Formats when CPHA1=0 ......................................................................... 234 Figure 11.86 USI1 SPI Clock Formats when CPHA1=1 ......................................................................... 235 Figure 11.87 USI1 SPI Block Diagram .................................................................................................... 236 Figure 11.88 Bit Transfer on the I2C-Bus (USI1) .................................................................................... 237 Figure 11.89 START and STOP Condition (USI1) .................................................................................. 238 Figure 11.90 Data Transfer on the I2C-Bus (USI1) ................................................................................. 238 Figure 11.91 Acknowledge on the I2C-Bus (USI1) ................................................................................. 239 Figure 11.92 Clock Synchronization during Arbitration Procedure (USI1).............................................. 240 Figure 11.93 Arbitration Procedure of Two Masters (USI1) .................................................................... 240 Figure 11.94 Formats and States in the Master Transmitter Mode (USI1) ............................................. 242 Figure 11.95 Formats and States in the Master Receiver Mode (USI1) ................................................. 244 Figure 11.96 Formats and States in the Slave Transmitter Mode (USI1) ............................................... 246 Figure 11.97 Formats and States in the Slave Receiver Mode (USI1) ................................................... 248 Figure 11.98 USI1 I2C Block Diagram .................................................................................................... 249 Figure 11.99 LCD Circuit Block Diagram................................................................................................. 261 Figure 11.100 LCD Signal Waveforms (1/2Duty, 1/2Bias) ...................................................................... 262 PS029902-0212 PRELIMINARY 6 Z51F3220 Product Specification Figure 11.101 LCD Signal Waveforms (1/3Duty, 1/3Bias) ...................................................................... 263 Figure 11.102 LCD Signal Waveforms (1/4Duty, 1/3Bias) ...................................................................... 264 Figure 11.103 LCD Signal Waveforms (1/8Duty, 1/4Bias) ...................................................................... 265 Figure 11.104 Internal Resistor Bias Connection .................................................................................... 266 Figure 11.105 External Resistor Bias Connection................................................................................... 267 Figure 11.106 LCD Circuit Block Diagram............................................................................................... 268 Figure 12.1 IDLE Mode Release Timing by External Interrupt ............................................................... 273 Figure 12.2 STOP Mode Release Timing by External Interrupt.............................................................. 274 Figure 12.3 STOP Mode Release Flow ................................................................................................... 275 Figure 13.1 RESET Block Diagram ......................................................................................................... 277 Figure 13.2 Reset noise canceller timer diagram .................................................................................... 278 Figure 13.3 Fast VDD Rising Time .......................................................................................................... 278 Figure 13.4 Internal RESET Release Timing On Power-Up ................................................................... 278 Figure 13.5 Configuration Timing when Power-on .................................................................................. 279 Figure 13.6 Boot Process WaveForm ..................................................................................................... 279 Figure 13.7 Timing Diagram after RESET ............................................................................................... 281 Figure 13.8 Oscillator generating waveform example ............................................................................. 281 Figure 13.9 Block Diagram of BOD ......................................................................................................... 282 Figure 13.10 Internal Reset at the power fail situation ............................................................................ 282 Figure 13.11 Configuration timing when BOD RESET ............................................................................ 283 Figure 13.12 LVI Diagram ........................................................................................................................ 283 Figure 14.1 Block Diagram of On-Chip Debug System........................................................................... 288 Figure 14.2 10-bit Transmission Packet .................................................................................................. 288 Figure 14.3 Data Transfer on the Twin Bus ............................................................................................ 289 Figure 14.4 Bit Transfer on the Serial Bus .............................................................................................. 289 Figure 14.5 Start and Stop Condition ...................................................................................................... 290 Figure 14.6 Acknowledge on the Serial Bus ........................................................................................... 290 Figure 14.7 Clock Synchronization during Wait Procedure .................................................................... 291 Figure 14.8 Connection of Transmission ................................................................................................. 292 Figure 15.1 Flash Program ROM Structure ............................................................................................. 294 PS029902-0212 PRELIMINARY 7 Z51F3220 Product Specification List of Tables Table 1-1 Ordering Information of Z51F3220 ............................................................................................ 12 Table 5-1 Normal Pin Description .............................................................................................................. 21 Table 7-1 Absolute Maximum Ratings....................................................................................................... 28 Table 7-2 Recommended Operating Conditions ....................................................................................... 28 Table 7-3 A/D Converter Characteristics ................................................................................................... 29 Table 7-4 Power-on Reset Characteristics ................................................................................................ 29 Table 7-5 LVR and LVI Characteristics ..................................................................................................... 30 Table 7-6 High Internal RC Oscillator Characteristics ............................................................................... 31 Table 7-7 Internal WDTRC Oscillator Characteristics ............................................................................... 31 Table 7-8 LCD Voltage Characteristics ..................................................................................................... 32 Table 7-9 DC Characteristics ..................................................................................................................... 33 Table 7-10 AC Characteristics ................................................................................................................... 35 Table 7-11 SPI0/1/2 Characteristics .......................................................................................................... 36 Table 7-12 UART0/1 Characteristics ......................................................................................................... 37 Table 7-13 I2C0/1 Characteristics ............................................................................................................. 38 Table 7-14 Data Retention Voltage in Stop Mode ..................................................................................... 39 Table 7-15 Internal Flash Rom Characteristics ......................................................................................... 40 Table 7-16 Input/Output Capacitance ........................................................................................................ 40 Table 7-17 Main Clock Oscillator Characteristics...................................................................................... 41 Table 7-18 Sub Clock Oscillator Characteristics ....................................................................................... 42 Table 7-19 Main Oscillation Stabilization Characteristics ......................................................................... 43 Table 7-20 Sub Oscillation Stabilization Characteristics ........................................................................... 43 Table 8-1 SFR Map Summary ................................................................................................................... 54 Table 8-2 SFR Map Summary ................................................................................................................... 55 Table 8-3 SFR Map .................................................................................................................................... 56 Table 9-1 Port Register Map ...................................................................................................................... 64 Table 10-1 Interrupt Group Priority Level .................................................................................................. 82 Table 10-2 Interrupt Vector Address Table ............................................................................................... 85 Table 10-3 Interrupt Register Map ............................................................................................................. 92 Table 11-1 Clock Generator Register Map .............................................................................................. 100 Table 11-2 Basic Interval Timer Register Map ........................................................................................ 103 Table 11-3 Watch Dog Timer Register Map ............................................................................................ 106 Table 11-4 Watch Timer Register Map .................................................................................................... 109 Table 11-5 Timer 0 Operating Modes ...................................................................................................... 111 Table 11-6 Timer 0 Register Map ............................................................................................................ 118 Table 11-7 Timer 1 Operating Modes ...................................................................................................... 120 Table 11-8 Timer 2 Register Map ............................................................................................................ 126 Table 11-9 Timer 2 Operating Modes ...................................................................................................... 130 Table 11-10 Timer 3 Register Map .......................................................................................................... 137 Table 11-11 Timer 3, 4 Operating Modes................................................................................................ 141 Table 11-12 PWM Frequency vs. Resolution at 8 MHz .......................................................................... 147 Table 11-13 PWM Channel Polarity ........................................................................................................ 147 Table 11-14 Timer 3, 4 Register Map ...................................................................................................... 159 PS029902-0212 PRELIMINARY 8 Z51F3220 Product Specification Table 11-15 Buzzer Frequency at 8 MHz ................................................................................................ 170 Table 11-16 Buzzer Driver Register Map ................................................................................................ 171 Table 11-17 SPI 2 Register Map ............................................................................................................. 175 Table 11-18 ADC Register Map............................................................................................................... 182 Table 11-19 Equations for Calculating USI0 Baud Rate Register Setting .............................................. 188 Table 11-20 CPOL0 Functionality............................................................................................................ 196 Table 11-21 USI0 Register Map .............................................................................................................. 213 Table 11-22 Equations for Calculating USI1 Baud Rate Register Setting .............................................. 225 Table 11-23 CPOL1 Functionality............................................................................................................ 233 Table 11-24 USI1 Register Map .............................................................................................................. 250 Table 11-25 Examples of USI0BD and USI1BD Settings for Commonly Used Oscillator Frequencies 259 Table 11-26 LCD Register Map ............................................................................................................... 268 Table 12-1 Peripheral Operation during Power Down Mode .................................................................. 272 Table 12-2 Power Down Operation Register Map ................................................................................. 276 Table 13-1 Reset State ............................................................................................................................ 277 Table 13-2 Boot Process Description ...................................................................................................... 280 Table 13-3 Reset Operation Register Map .............................................................................................. 284 Table 15-1Flash Memory Register Map .................................................................................................. 295 PS029902-0212 PRELIMINARY 9 Z51F3220 Product Specification Z51F3220 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 12-BIT A/D CONVERTER 1. Overview 1.1 Description The Z51F3220 is advanced CMOS 8-bit microcontroller with 32k bytes of Flash. This is powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. This provides the following features : 32k bytes of Flash, 256 bytes of IRAM, 768 bytes of XRAM , general purpose I/O, basic interval timer, watchdog timer, 8/16-bit timer/counter, 16-bit PPG output, 8-bit PWM output, 10-bit PWM output, watch timer, buzzer driving port, SPI, USI, 12-bit A/D converter, LCD driver, on-chip POR, LVR, LVI, on-chip oscillator and clock circuitry. The Z51F3220 also supports power saving modes to reduce power consumption. Device Name Flash XRAM IRAM 32k bytes 768 bytes 256 bytes Z51F3220FNX Z51F3220SKX PS029902-0212 ADC I/O PORT Package 16 channel 42 44-pin MQFP 12 channel 30 32-pin SOP PRELIMINARY 10 Z51F3220 Product Specification 1.2 Features • Low Voltage Reset • CPU - 14 level detect (1.60V/ 2.00V/ 2.10V/ 2.20V/ 2.32V/ 2.44V/ 2.59V/ 2.75V/ 2.93V/ 3.14V/ 3.38V/ 3.67V/ 4.00V/ 4.40V) - 8 Bit CISC Core (8051 Compatible) • ROM (Flash) Capacity - 32k Bytes • Low Voltage Indicator - Flash with self read/write capability - On chip debug and In-system programming (ISP) - Endurance : 100,000 times - 13 level detect (2.00V/ 2.10V/ 2.20V/ 2.32V/ 2.44V/ 2.59V/ 2.75V/ 2.93V/ 3.14V/ 3.38V/ 3.67V/ 4.00V/ 4.40V) • 256 Bytes IRAM • Interrupt Sources • 768 Bytes XRAM - External Interrupts (EXINT0~7, EINT8, EINT10, EINT11, EINT12) (12) - (27 Bytes including LCD display RAM) • General Purpose I/O (GPIO) - Timer(0/1/2/3/4) (5) - Normal I/O : 9 Ports - WDT (1) (P0[ 2:0], P5[5:0]) - BIT (1) - LCD shared I/O : 33 Ports - WT (1) (P0[7:3], P1, P2, P3, P4) - SPI 2 (1) • Basic Interval Timer (BIT) - USI0/1 (6) - 8Bit × 1ch - ADC (1) - Watch Dog Timer (WDT) • Internal RC Oscillator - 8Bit × 1ch - Inernal RC frequency: 16MHz ±0.5% (TA= 25°C) - 5kHz internal RC oscillator • Power Down Mode • Timer/ Counter - STOP, IDLE mode - 8Bit × 1ch (T0), 16Bit × 2ch (T1/T2) • Operating Voltage and Frequency - 8Bit × 2ch (T3/T4) or 16 Bit × 1ch (T3) - 1.8V ~ 5.5V (@32 ~ 38kHz with X-tal) • Programmable Pulse Generation - 1.8V ~ 5.5V (@0.4 ~ 4.2MHz with X-tal) - Pulse generation (by T1/T2) - 2.7V ~ 5.5V (@0.4 ~ 10.0MHz with X-tal) - 8Bit PWM (by T0) - 3.0V ~ 5.5V (@0.4 ~ 12.0MHz with X-tal) - 6-ch 10Bit PWM for Motor (by T4) - 1.8V ~ 5.5V (@0.5 ~ 8.0MHz with Internal RC) • Watch Timer (WT) - 3.91mS/0.25S/0.5S/1S/1M interval at 32.768kHz • Buzzer - 2.0V ~ 5.5V (@0.5 ~ 16.0MHz with Internal RC) - Voltage dropout converter included for core • Minimum Instruction Execution Time - 8Bit × 1ch - 125nS (@ 16MHz main clock) • SPI 2 - 61μS (@t 32.768kHz sub clock) - 8Bit × 1ch • Operating Temperature: – 40 ~ + 85℃ • USI0/1 (UART + SPI + I2C) - 8Bit UART × 2ch, 8Bit SPI × 2ch and I2C × 2ch • 12 Bit A/D Converter • Oscillator Type - 0.4-12MHz Crystal or Ceramic for main clock - 32.768kHz Crystal for sub clock - 16 Input channels • Package Type • LCD Driver - 44 MQFP-1010 - 21 Segments and 8 Common terminals - 32 SOP - Internal or external resistor bias - 1/2, 1/3, 1/4, 1/5, 1/6 and 1/8 duty selectable - Pb-free package - Resistor Bias and 16-step contrast control • Power On Reset - Reset release level (1.4V) PS029902-0212 PRELIMINARY 11 Z51F3220 Product Specification 1.3 Ordering Information Table 1-1 Ordering Information of Z51F3220 Device Name Z51F3220FNX Z51F3220SKX PS029902-0212 ROM Size IRAM Size XRAM Size 32k bytes Flash 256 bytes 768 bytes PRELIMINARY Package 44-pin MQFP 32-pin SOP 12 Z51F3220 Product Specification 1.3.1 Part Number Suffix Designation Zilog part numbers consist of a number of components, as indicated in the following example. Example: Part number Z51F3220FNX is an 8-bit MCU with 32 KB of Flash memory and 1 KB of RAM in a 44-pin MQFP package and operating within a –40°C to +85°C temperature range. In accordance with RoHS standards, this device has been built using lead-free solder. Z51 F 32 20 F N X Temperature Range X = –40°C to +85°C Pin Count N = 44 pins S = 32 pins Package F = MQFP J = SOP Device Type Flash Memory Size 32 = 32 KB Flash Flash Memory F = General-Purpose Flash Device Family Z51 = Z8051 8-Bit Core MCU 1.4 Development Tools 1.4.1 Compiler We do not provide the compiler. Please contact the third parties. The core of Z51F3220 is Mentor 8051. And, device ROM size is smaller than 32k bytes. Developer can use all kinds of third party’s standard 8051 compiler. 1.4.2 OCD Emulator and Debugger The OCD (On Chip Debug) emulator supports Zilog’s 8051 series MCU emulation. The OCD interface uses two-wire interfacing between PC and MCU which is attached to user’s system. The OCD can read or change the value of MCU internal memory and I/O peripherals. And the OCD also controls MCU internal debugging logic, it means OCD controls emulation, step run, monitoring, etc. The OCD Debugger program works on Microsoft-Windows NT, 2000, XP, Vista (32bit) operating system. PS029902-0212 PRELIMINARY 13 Z51F3220 Product Specification If you want to see more details, please refer to OCD debugger manual. You can download debugger S/W and manual from our web-site. Connection: - SCLK (Z51F3220 P01 port) - SDATA (Z51F3220 P00 port) OCD connector diagram: Connect OCD with user system PS029902-0212 PRELIMINARY 14 Z51F3220 Product Specification 1.4.3 Programmer Single programmer: PGMplus USB: It programs MCU device directly. OCD emulator: It can write code in MCU device too, because OCD debugging supports ISP (In System Programming). It does not require additional H/W, except developer’s target system. Gang programmer: It programs 8 MCU devices at once. So, it is mainly used in mass production line. Gang programmer is standalone type, it means it does not require host PC, after a program is downloaded from host PC to Gang programmer. Figure 1.1 StandAlone Gang8 (for Mass Production) PS029902-0212 PRELIMINARY 15 Z51F3220 Product Specification 2. Block Diagram DSDA AN0 -AN5/P02-P07 AN6-AN13 /P17-P10 AN14-AN15 /P20-P21 AVREF/P02 12 – Bit A/D Converter T0O/PWM0O/P53 EINT10/P54 EC0/P52 8 – Bit Timer 0 T1O/PWM1O/P12 EINT11/P12 EC1/P13 16 – Bit T imer 1 T2O/PWM2O/P11 EINT12/P11 16 – Bit T imer 2 T3O/P01 EC3/P00 EINT0/P02 T4O/P02 EINT1/P03 PWM4AA/P02 PWM4AB/P03 PWM4BA/P04 PWM4BB/P05 PWM4CA/P06 PWM4CB/P07 EINT8/BLNK/P52 P00/EC3/DSDA P01 /T3O/DSCL P02/AN0/AVREF/EINT0/T4O/PWM4AA P03/SEG26/AN1/EINT1/PWM4AB P04/SEG25/AN2/EINT2/PWM4BA P05/SEG24/AN3/EINT3/PWM4BB P06 /SEG23/AN4 /EINT4/PWM4 CA P07 /SEG22/AN5 /EINT5/PWM4 CB DSCL Low Voltage Indicator On-Chip Debug Buzzer M8051 Core 8 – Bit Timer 3 8 – Bit Timer 4 16 – Bit Timer 3 6 -ch PWM UART0 USI0 XRAM (768 B ytes) IRAM (256 Bytes) UART1 USI1 Low Voltage Reset SPI0 I2 C0 Basic Interval Timer Power On R eset MOSI2/P14 MISO2/P15 SCK 2/P16 SS2/P17 SPI2 32k Bytes Flash SPI1 I2 C1 LCD Driver/ Controller P 0 Port Watchdog Timer 5 kHz INT-RC OSC P10/SEG14 /AN 13/RXD1/SCL1/MISO1 P11/SEG 15/AN12/EINT12/T2O/PWM2O P12/SEG 16/AN11/EINT11/T1O/PWM1O P13 /SEG17/AN10/EC 1/BUZO P 14/SEG18 /AN9/MOSI2 P 15/SEG19 /AN 8/MISO2 P16 /SEG20/AN7/EINT7 /SCK2 P17/SEG21/AN6/EINT6/SS2 P 1 Port P20/SEG13 /AN 14/TXD1/SDA1/MOSI1 P21/SEG12 /AN15 //SCK1 P22/SEG11/SS1 P23-P27/SEG10-SEG6 P 2 Port P30 -P33/COM7-COM4 /SEG5-SEG2 P34 -P35/COM3-COM2 /SEG1-SEG0 P36-P37 /COM1-COM0 P 3 Port INT-RC OSC 16MHz BUZO/P13/SEG17/AN10 /EC1 TXD0/P41 RX0 /P40 MOSI0/P41 MISO0/P40 SCK 0/P42 SS0/P43 SDA 0/P41 SCL 0/P40 TXD1/P20 RXD1/P10 MOSI1/P20 MISO1/P10 SCK 1/P21 SS1/P22 SDA 1/P20 SCL 1/P10 COM0-COM1/P37-P 36 COM2-COM7/SEG0 -SEG5/P35-P30 SEG6-SEG29/P27-P03 VLC 0-VLC3/P43-P40 P5 Port P 50/XOUT P 51/XIN P 52/EINT8/EC0/BLNK SXIN/P53 /T0O/PWM0O SXOUT /P54/EINT10 P 55/RESETB P4 Port P 40/VLC3/RXD0/SCL0/MISO0 P 41/VLC2/TXD0/SDA0/MOSI0 P 42/VLC1/SCK0 P 43/VLC0/SS0 Watch Timer Voltage Down Converter VDD CLOCK/ SYSTEM CONTROL RESETB /P55 SXOUT/P54/EINT10 SXIN/P53/T0 O/PWM0O XIN/P51 XOUT/P50 VSS Figure 2.1 Block Diagram NOTE) The P14–P17, P23–P25, P34–P37, and P43 are not in the 32-pin package. PS029902-0212 PRELIMINARY 16 Z51F3220 Product Specification 3. Pin Assignment P54/SX OUT/EINT1 0 P53/SXIN/T0O /P WM0 O P52 /EINT8/E C0 /B LNK P51 /XIN P 50/XOUT VS S VDD P00 /E C3 /DSDA P0 1/T3O /DSCL P02 /AN0/AV RE F/EINT0 /T4O /PWM4A A P03/SE G26/AN1/EINT1 /PWM4A B 44 43 42 41 40 39 38 37 36 35 34 P55 /RESETB 1 33 P04 /SEG 25 /AN2 /EINT2/PWM4 BA P40/VLC3/RXD0/SCL0/MISO0 2 32 P05 /SEG 24 /AN3 /EINT3/PWM4 BB P41/VLC2/TXD0/SDA0/MOSI0 3 31 P06 /SEG 23 /AN4 /EINT4/PWM4 CA P42 /VLC 1/SCK 0 4 30 P07 /SEG 22 /AN5 /EINT5/PWM4 CB P43 /VLC0 /SS 0 5 29 P17 /SEG 21 /AN6 /EINT6/SS 2 P37/COM0 6 28 P16 /SEG 20 /AN7 /EINT7/SCK 2 P36/COM1 7 27 P15 /SEG 19 /AN8 /MISO2 P35 /COM2/SEG 0 8 26 P14 /SEG 18 /AN9 /MOSI2 P34 /COM3/SEG 1 9 25 P13 /SEG 17 /AN10 /EC1 /BUZO P33 /COM4/SEG 2 10 24 P12 /SEG 16 /AN11 /EINT11/T1O/PWM1O P32 /COM5/SEG 3 11 23 P11 /SEG 15 /AN12 /EINT12/T2O/PWM2O MC96F6432Q (44MQFP-1010) 12 13 14 15 16 17 18 19 20 21 22 P31 /COM6/SEG 4 P30 /COM7/SEG 5 P27 /SE G6 P26 /SE G7 P25 /SE G8 P24 /SE G9 P23 /SE G10 P22 /SE G11/SS 1 P21 /SE G12/AN15 /SCK1 P20 /SE G13/AN14 /TXD1/SDA1/MOSI1 P10 /SE G14/AN13 /RXD1/SCL1/MIS O1 Figure 3.1 Z51F3220 44MQFP-1010 Pin Assignment NOTE) On On-Chip Debugging, ISP uses P0[1:0] pin as DSDA, DSCL. PS029902-0212 PRELIMINARY 17 Z51F3220 Product Specification VSS 1 32 VDD P50/XOUT 2 31 P00 /EC3 /DSDA 3 30 P01 /T3O /DSCL 4 29 P02 /AN0 /AVREF /EINT0/T4O /PWM4AA P53/SXIN/T0 O/PWM0 O 5 28 P03 /SEG 26 /AN1 /EINT1/PWM4 AB P54 /SXOUT /EINT10 6 27 P04 /SEG25 /AN2 /EINT2/PWM4 BA P55 /RESETB 7 26 P05 /SEG24 /AN3 /EINT3/PWM4 BB P40/VLC3/RXD0/SCL0/MISO0 8 25 P06 /SEG23 /AN4 /EINT4/PWM4 CA P41/VLC2/TXD0/SDA0/MOSI0 9 24 P07 /SEG22 /AN5 /EINT5/PWM4 CB 23 P13 /SEG17 /AN10 /EC1/BUZO 22 P12 /SEG16 /AN11 /EINT11/T1O/PWM1O 21 P11 /SEG15 /AN12 /EINT12/T2O/PWM2O MC96F6332D (32-SOP) P51 /XIN P52 /EINT8/EC0/BLNK P42 /VLC 1/SCK 0 10 P33 /COM4/SEG 2 11 P32 /COM5/SEG 3 12 P31 /COM6/SEG 4 13 20 P10 /SEG14 /AN13 /RXD1 /SCL1 /MISO1 P30 /COM7/SEG 5 14 19 P20 /SEG 13 /AN14 /TXD1/SDA1 /MOSI1 P27/SEG 6 15 18 P21 /SEG 12 /AN15 /SCK 1 P26/SEG 7 16 17 P22 /SEG 11 /SS 1 Figure 3.2 Z51F3220 32SOP Pin Assignment NOTES) 1. On On-Chip Debugging, ISP uses P0[1:0] pin as DSDA, DSCL. 2. The P14-P17, P23-P25, P34-P37 and P43 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 32-pin package is used. PS029902-0212 PRELIMINARY 18 Z51F3220 Product Specification 4. Package Diagram Figure 4.1 44-Pin MQFP Package PS029902-0212 PRELIMINARY 19 Z51F3220 Product Specification Figure 4.2 32-Pin SOP Package PS029902-0212 PRELIMINARY 20 Z51F3220 Product Specification 5. Pin Description Table 5-1 Normal Pin Description PIN Name P00 I/O Func I/O P01 P02 A tion @RESET Port 0 is a bit-programmable I/O port which can be configured as a schmitt-trigger input, a push-pull output, or an open-drain output. Input E C3/DSDA T3O/DSCL N0/AVREF/EINT0/T4O/PWM4AA A pull-up resistor can be specified in 1-bit unit. P03 Shared with SEG26/AN1/EINT1/PWM4AB P04 SEG25/AN2/EINT2/PWM4BA P05 SEG24/AN3/EINT3/PWM4BB P06 SEG23/AN4/EINT4/PWM4CA P07 P10 SEG22/AN5/EINT5/PWM4CB I/O Port 1 is a bit-programmable I/O port which can be configured as a schmitt-trigger input, a P11 SEG15/ push-pull output, or an open-drain output. P12 SEG16/ A pull-up resistor can be specified in 1-bit unit. P13 The P14 – P17 are not in the 32-pin package. P14 Input SE G14/AN13/RXD1/SCL1/MISO1 AN12/EINT12/T2O/PWM2O AN11/EINT11/T1O/PWM1O SEG17/AN10/EC1/BUZO SEG18/AN9/MOSI2 P15 SEG19/AN8/MISO2 P16 SEG20/AN7/EINT7/SCK2 P17 P20 SEG21/AN6/EINT6/SS2 I/O P21 P22 Port 2 is a bit-programmable I/O port which can be configured as an input, a push-pull output, or an open-drain output. Input SE SEG12/AN15/SCK1 SEG11/SS1 A pull-up resistor can be specified in 1-bit unit. P23 SEG10 The P23 – P25 are not in the 32-pin package. P24 G13/AN14/TXD1/SDA1/MOSI1 SEG9 P25 SEG8 P26 SEG7 P27 P30 SEG6 I/O P31 Port 3 is a bit-programmable I/O port which can be configured as an input, a push-pull output. Input C COM6/SEG4 A pull-up resistor can be specified in 1-bit unit. P32 COM5/SEG3 The P34 – P37 are only in the 44-pin package. P33 OM7/SEG5 COM4/SEG2 P34 COM3/SEG1 P35 COM2/SEG0 P36 COM1 P37 P40 P41 P42 P43 COM0 I/O Port 4 is a bit-programmable I/O port which can be configured as an input, a push-pull output, or an open-drain output. Input VLC3 A pull-up resistor can be specified in 1-bit unit. The P43 is only in the 44-pin package. PS029902-0212 PRELIMINARY /RXD0/SCL0/MISO0 VLC2/TXD0/SDA0/MOSI0 VLC1/SCK0 VLC0/SS0 21 Z51F3220 Product Specification Table 5-1 Normal Pin Description (Continued) PIN Name P50 I/O Function I/O P51 P52 @RESET Port 5 is a bit-programmable I/O port which can be configured as a schmitt-trigger input or a push-pull output. Shared with Input XO UT XIN EINT8/EC0/BLNK A pull-up resistor can be specified in 1-bit unit. P53 SXIN/T0O/PWM0O P54 SXOUT/EINT10 P55 RESETB EINT0 I/O External interrupt input and Timer 3 capture input Input P02/AN EINT1 I/O External interrupt input and Timer 4 capture input Input P0 EINT2 I/O External interrupt inputs Input 0/AVREF/T4O/PWM4AA 3/SEG26/AN1/PWM4AB P04/SEG25/AN2/PWM4BA EINT3 P05/SEG24/AN3/PWM4BB EINT4 P06/SEG23/AN4/PWM4CA EINT5 P07/SEG22/AN5/PWM4CB EINT6 P17/SEG21/AN6/SS2 EINT7 P16/SEG20/AN7/SCK2 EINT8 P52/EC0/BLNK EINT10 I/O External interrupt input and Timer 0 capture input Input P 54/SXOUT EINT11 I/O External interrupt input and Timer 1 capture input Input P1 2/SEG16/AN11/T1O/PWM1O EINT12 I/O External interrupt input and Timer 2 capture input Input P1 1/SEG15/AN12/T2O/PWM2O T0O I/O Timer 0 interval output Input P53/SXIN/PWM0O T1O I/O Timer 1 interval output Input P12/SEG16/AN11/EINT11/PWM1O T2O I/O Timer 2 interval output Input P11/SEG15/AN12/EINT12/PWM2O T3O I/O Timer 3 interval output Input P01/DSCL I/O Timer 4 interval output T4O PWM0O Input P02/AN0/AVREF/EINT0/PWM4AA I/O Ti mer 0 PWM output Input P53/SXIN/T0O PWM1O I/O Ti mer 1 PWM output Input P12/SEG16/AN11/EINT11/T1O PWM2O I/O Ti mer 2 PWM output Input P11/SEG15/AN12/EINT12/T2O PWM4AA I/O Ti mer 4 PWM outputs Input P02/AN0/AVREF/EINT0/T4O PWM4AB P03/SEG26/AN1/EINT1 PWM4BA P04/SEG25/AN2/EINT2 PWM4BB P05/SEG24/AN3/EINT3 PWM4CA P06/SEG23/AN4/EINT4 PWM4CB P07/SEG22/AN5/EINT5 BLNK I/O External sync signal input for 6-ch PWMs Input P52/EINT8/EC0 EC0 I/O Timer 0 event count input Input P52/EINT8/BLNK EC1 I/O Timer 1 event count input Input P13/SEG17/AN10 EC3 I/O Timer 3 event count input Input P00/DSDA PS029902-0212 PRELIMINARY 22 Z51F3220 Product Specification Table 5-1 Normal Pin Description (Continued) PIN Name I/O F BUZO I/O unction @RESET Shared with Buzzer signal output I nput P13/SEG17/AN10/EC1 SCK0 I/O Serial 0 clock input/output Input P42/VLC1 SCK1 I/O Serial 1 clock input/output Input P21/SEG12/AN15 P16/SEG20/AN7/EINT7 SCK2 I/O Serial 2 clock input/output Input MOSI0 I/O SPI 0 master output, slave input Input P41/VLC2/TXD0/SDA0 MOSI1 I/O SPI 1 master output, slave input Input P20/SEG13/AN14/TXD1/SDA1 MOSI2 I/O SPI 2 master output, slave input Input P14/SEG18/AN9 MISO0 I/O SPI 0 master input, slave output Input P40/VLC3/RXD0/SCL0 MISO1 I/O SPI 1 master input, slave output Input P10/SEG14/AN13/RXD1/SCL1 MISO2 I/O SPI 2 master input, slave output Input P15/SEG19/AN8 SS0 I/O SPI 0 slave select input Input P43/VLC0 SS1 I/O SPI 1 slave select input Input P22/SEG11 SS2 TXD0 I/O SPI 2 slave select input Input P17/SEG21/AN6/EINT6 I/O UART 0 data output Input P41/VLC2/SDA0/MOSI0 TXD1 I/O UART 1 data output Input P20/SEG13/AN14/SDA1/MOSI1 RXD0 I/O UART 0 data input Input P40/VLC3/SCL0/MISO0 RXD1 I/O UART 1 data input Input P10/SEG14/AN13/SCL1/MISO1 SCL0 I/O I 2C 0 clock input/output Input P40/VLC3/RXD0/MISO0 SCL1 I/O I 2C 1 clock input/output Input P10/SEG14/AN13/RXD1/MISO1 SDA0 I/O I2C 0 data input/output Input P41/VLC2/TXD0/MOSI0 SDA1 I/O I2C 1 data input/output Input P20/SEG13/AN14/TXD1/MOSI1 Input P02/AN0/EINT0/T4O/PWM4AA Input P02/AVREF/EINT0/T4O/PWM4AA AVREF I /O A/ D converter reference voltage AN0 I/O A/D converter analog input channels AN1 P03/SEG26/EINT1/PWM4AB AN2 P04/SEG25/EINT2/PWM4BA AN3 P05/SEG24/EINT3/PWM4BB AN4 P06/SEG23/EINT4/PWM4CA AN5 P07/SEG22/EINT5/PWM4CB AN6 P17/SEG21/EINT6/SS2 AN7 P16/SEG20/EINT7/SCK2 AN8 P15/SEG19/MISO2 AN9 P14/SEG18/MOSI2 AN10 P13/SEG17/EC1 AN11 P12 /SEG16/EINT11/T1O/PWM1O AN12 P11 /SEG15/EINT12/T2O/PWM2O AN13 P10/SEG14/RXD1/SCL1/MISO1 AN14 P20/SEG13/TXD1/SDA1/MOSI1 AN15 P21/SEG12/SCK1 PS029902-0212 PRELIMINARY 23 Z51F3220 Product Specification Table 5-1 Normal Pin Description (Continued) PIN Name I/O Func VLC0 I/O tion @RESET LCD bias voltage pins Input Shared with P43/SS0 VLC1 P42/SCK0 VLC2 P41/TXD0/SDA0/MOSI0 VLC3 P40/RXD0/SCL0/MISO0 COM0– COM1 I/O LCD common signal outputs Input P37–P36 COM2– COM3 P35–P34/SEG0–SEG1 COM4– COM7 SEG0– SEG1 P33–P30/SEG2–SEG5 I/O LCD segment signal outputs Input P35–P34/COM2–COM3 SEG2– SEG5 P33–P30/COM4–COM7 SEG6– SEG10 P27–P23 SEG11 P22/SS1 SEG12 P21/SCK1/AN15 SEG13 P20/AN14/TXD1/SDA1/MOSI1 SEG14 P10/AN13/RXD1/SCL1/MISO1 SEG15 P11/AN12/EINT12/T2O/PWM2O SEG16 P12/AN11/EINT11/T1O/PWM1O SEG17 P13/AN10/EC1 SEG18 P14/AN9/MOSI2 SEG19 P15/AN8/MISO2 SEG20 P16/AN7/EINT7/SCK2 SEG21 P17/AN6/EINT6/SS2 SEG22 P07/AN5/EINT5/PWM4CB SEG23 P06/AN4/EINT4/PWM4CA SEG24 P05/AN3/EINT3/PWM4BB SEG25 P04/AN2/EINT2/PWM4BA SEG26 P03/AN1/EINT1/PWM4AB PS029902-0212 PRELIMINARY 24 Z51F3220 Product Specification Table 5-1 Normal Pin Description (Continued) PIN Name RESETB DSDA DSCL XIN I/O Func tion @RESET Shared with I/O System reset pin with a pull-up resistor when it is selected as the RESETB by CONFIGURE OPTION Input P I/O On chip debugger data input/output (NOTE4,5) I nput P00/EC3 put P01/T3O P51 I/O On chip debugger clock input (NOTE4,5) In I/O Ma in oscillator pins Input XOUT SXIN P50 I/O Sub oscillator pins Input SXOUT VDD, VSS 55 P53/T0O/PWM0O P54/EINT10 – Power input pins –– NOTES) 1. The P14–P17, P23–P25, P34–P37, and P43 are not in the 32-pin package. 2. The P55/RESETB pin is configured as one of the P55 and RESETB pin by the “CONFIGURE OPTION.” 3. If the P00/EC3/DSDA and P01/T3O/DSCL pins are connected to an emulator during the resetor power-on reset, the pins are automatically configured as the debugger pins. 4. The P00/EC3/DSDA and P01/T3O/DSCL pins are configured as inputs with internal pull-up resistor only during the reset or power-on reset. 5. The P50/XOUT, P51/XIN, P53/SXINT/T0O/PWM0O, and P54/SXOUT/EINT10 pins are configured as a function pin by software control. PS029902-0212 PRELIMINARY 25 Z51F3220 Product Specification 6. Port Structures 6.1 General Purpose I/O Port Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V) VDD PULL-UP REGISTER VDD OPEN DRAIN REGISTER DATA REGISTER 0 MUX SUB-FUNC DATA OUTPUT VDD PAD 1 SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER 1 MUX 0 CMOS or Schmitt Level Input PORTx INPUT or SUB-FUNC DATA INPUT ANALOG CHANNEL ENABLE ANALOG INPUT Figure 6.1 General Purpose I/O Port PS029902-0212 PRELIMINARY 26 Z51F3220 Product Specification 6.2 External Interrupt I/O Port Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V) VDD PULL-UP REGISTER VDD OPEN DRAIN REGISTER DATA REGISTER 0 MUX SUB-FUNC DATA OUTPUT VDD PAD 1 SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER 1 MUX 0 VDD Q EXTERNAL INTERRUPT INTERRUPT ENABLE D POLARITY REG. CP r FLAG CLEAR PORTx INPUT or SUB-FUNC DATA INPUT CMOS or Schmitt Level Input 0 MUX 1 Q D CP r ANALOG CHANNEL ENABLE DEBOUNCE CLK DEBOUNCE ENABLE ANALOG INPUT Figure 6.2 External Interrupt I/O Port PS029902-0212 PRELIMINARY 27 Z51F3220 Product Specification 7. Electrical Characteristics 7.1 Absolute Maximum Ratings Table 7-1 Absolute Maximum Ratings Parameter S Supply Voltage Normal Voltage Pin Rating Unit Note VDD ymbol -0.3 ~ +6.5 V – VI -0.3 ~ VDD+0.3 V VO -0.3 ~ VDD+0.3 V IOH -10 mA Maximum current output sourced by (IOH per I/O pin) ∑IOH -80 mA Maximum current (∑IOH) IOL Total Power Dissipation Storage Temperature Voltage on any pin with respect to VSS mA Maximum current sunk by (IOL per I/O pin) ∑IOL 120 60 mA Maximum current (∑IOL) PT 600 mW – °C – TSTG -65 ~ +150 NOTE) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 7.2 Recommended Operating Conditions Table 7-2 Recommended Operating Conditions Parameter Symbol Con (TA= -40°C ~ +85°C) ditions fX= 32 ~ 38kHz SX-tal fX= 0.4 ~ 4.2MHz Operating Voltage VDD = fX 0.4 ~ 10.0MHz fX= 0.5 ~ 8.0MHz Operating Temperature PS029902-0212 TOPR V TYP MAX 1.8 – 5.5 Unit 1.8 – 5.5 X-tal = fX 0.4 ~ 12.0MHz = fX 0.5 ~ 16.0MHz MIN 2.7 – 5.5 V 3.0 – 5.5 Internal RC = DD 1.8 ~ 5.5V PRELIMINARY 1.8 – 5.5 2.0 – 5.5 -40 – 85 °C 28 Z51F3220 Product Specification 7.3 A/D Converter Characteristics Table 7-3 A/D Converter Characteristics Parameter Sy mbol (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Conditions MIN TYP MAX Unit – –- 12 – bit Resolution – Integral Linear Error ILE Differential Linearity Error DLE – Zero Offset Error ZOE Full Scale Error FSE Conversion Time tCON 12b Analog Input Voltage Analog Reference Voltage –– ±3 – ±1 – – ±3 – – ±3 20 – – VAN – VSS – AVREF AVREF – 1.8 – VDD – – 2 μA 2 mA 0.1 μA AVREF= 2.7V – 5.5V fx= 8MHz it resolution, 8MHz Analog Input Leakage Current IAN AVRE ADC Operating Current IADC = F 5.12V Enable Disable – VDD= 5.12V –1 – LSB μS V NOTES) 1. Zero offset error is the difference between 0000000000 and the converted output for zero input voltage (VSS). 2. Full scale error is the difference between 1111111111 and the converted output for full-scale input voltage (AVREF). 7.4 Power-On Reset Characteristics Table 7-4 Power-on Reset Characteristics Parameter S (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) ymbol RESET Release Level VPOR – VDD Voltage Rising Time POR Current tR IPOR – PS029902-0212 Conditions M – PRELIMINARY IN TYP MAX Unit – 1.4 – V 0.2 – – V/mS μA 0.05 – – 29 Z51F3220 Product Specification 7.5 Low Voltage Reset and Low Voltage Indicator Characteristics Table 7-5 LVR and LVI Characteristics Parameter S Detection Level ymbol VLVR VLVI (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Conditions MIN The LVR can select all levels but LVI can select other levels except 1.60V. TYP MAX – 1.60 1.75 1.85 2.00 2.15 1.95 2.10 2.25 2.05 2.20 2.35 2.17 2.32 2.47 2.29 2.44 2.59 2.39 2.59 2.79 2.55 2.75 2.95 2.73 2.93 3.13 2.94 3.14 3.34 3.18 3.38 3.58 3.37 3.67 3.97 3.70 4.00 4.30 4.10 4.40 4.70 Unit V Hysteresis △V – – 10 100 mV Minimum Pulse Width tLW – 100 – – μS LVR and LVI Current IBL Enable (Both) Enable (One of two) – 10 VDD= 3V Disable (Both) PS029902-0212 PRELIMINARY .0 15.0 – 8.0 12.0 – – 0.1 μA 30 Z51F3220 Product Specification 7.6 High Internal RC Oscillator Characteristics Table 7-6 High Internal RC Oscillator Characteristics Parameter S Frequency f ymbol (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Conditions VDD = 2.0 – 5.5 V IRC MIN TYP MAX Unit – 16 – MHz TA = 25°C ±0.5 TA = 0°C to +70°C Tolerance – ±1 –– TA = -20°C to +80°C ±2 TA = -40°C to +85°C Clock Duty Ratio TOD Stabilization Time THFS – IRC Current IIRC % ±3 – Enable 40 50 60 % – – 100 μS – 0. 2– Disable – – mA 0.1 μA 7.7 Internal Watch-Dog Timer RC Oscillator Characteristics Table 7-7 Internal WDTRC Oscillator Characteristics Parameter S ymbol Frequency f WDTRC Stabilization Time tWDTS – WDTRC Current PS029902-0212 IWDTRC (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Conditions MIN – 2 – TYP MAX Unit 5 10 kHz mS – 1 Enable – 1 – Disable – – 0.1 PRELIMINARY μA 31 Z51F3220 Product Specification 7.8 LCD Voltage Characteristics Table 7-8 LCD Voltage Characteristics Parameter S ymbol (TA= -40°C ~ +85°C, VDD= 2.0V ~ 5.5V, VSS= 0V) Conditions LCD contrast disabled, 1/4 bias LCDCCR=00H LCD Voltage VLC0 LCD contrast enabled, 1/4 bias, No panel load MIN TYP MAX Unit Typx0.95 VDD VDDx16/31 Typx1.05 V Typx1.1 V LCDCCR=01H VDDx16/30 LCDCCR=02H VDDx16/29 LCDCCR=03H VDDx16/28 LCDCCR=04H VDDx16/27 LCDCCR=05H VDDx16/26 LCDCCR=06H VDDx16/25 LCDCCR=07H LCDCCR=08H Typx0.9 LCD Mid Bias Voltage(note) VLC2 LCD Driver Output Impedance RLO VL LCD Bias Dividing Resistor RLCD VLC3 VDDx16/23 LCDCCR=09H VDDx16/22 LCDCCR=0AH VDDx16/21 LCDCCR=0BH VDDx16/20 LCDCCR=0CH VDDx16/19 LCDCCR=0DH VDDx16/18 LCDCCR=0EH VDDx16/17 LCDCCR=0FH VLC1 VDDx16/24 VDD=2.7V to 5.5V, LCD clock = 0Hz, 1/4 bias, No panel load VDDx16/16 /4xVLC0 T ypx1.1 Typx0.9 2/4xVLC0 T ypx1.1 Typx0.9 1/4xVLC0 T ypx1.1 Typx0.9 3 CD = 3V, ILOAD = ±10uA –5 V 10 kΩ 40 60 TA = 25C 80 NOTE) It is middle output voltage when the VDD and the VLC0 node are connected. PS029902-0212 PRELIMINARY 32 Z51F3220 Product Specification 7.9 DC Characteristics Table 7-9 DC Characteristics Parameter Input High Voltage Input Low Voltage Output High Voltage (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, fXIN= 12MHz) Symbol Co nditions MIN TYP MAX Unit 0.8VDD – VDD V – VDD V – – 0.2VDD V – 0.3VDD V VDD-1.0 – – V –– 1.0 VDD= 4.5V, IOL= 15mA ; P1 –– 1.0 V VIH1 P0, P1, P5, RESETB VIH2 All input pins except VIH1 0.7VDD VIL1 P0, P1, P5, RESETB VIL2 All input pins except VIL1 – VOH VDD= 4.5V, IOH= -2mA, All output ports; VOL1 Output Low Voltage VOL2 VDD=4.5V, IOL= 10mA; All output ports except VOL2 Input High Leakage Current IIH All input ports – – 1 μA Input Low Leakage Current IIL All input ports -1 – – μA = VDD 5.0V 25 50 100 = VDD 3.0V 50 100 200 Pull-Up Resistor OSC feedback resistor PS029902-0212 RPU VI=0V, TA= 25°C All Input ports VI=0V, TA= 25°C RESETB = VDD 5.0V 15 0 250 400 = VDD 3.0V 30 0 500 700 200 2000 0 10000 RX1 XIN= VDD, XOUT= VSS TA= 25°C, VDD= 5V 600 1 RX2 SXIN=VDD, SXOUT=VSS TA= 25 °C ,VDD=5V 2500 500 PRELIMINARY kΩ kΩ kΩ 33 Z51F3220 Product Specification Table 7-9 DC Characteristics (Continued) Parameter Symbol C IDD1 (RUN) IDD2 Supply Current (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, fXIN= 12MHz) (IDLE) ondition TYP MAX Unit fXIN= 12MHz, VDD= 5V±10% – 3.0 6.0 fXIN= 10MHz, VDD= 3V±10% – 2.2 4.4 fIRC= 16MHz, VDD= 5V±10% – 3.0 6.0 fXIN= 12MHz, VDD= 5V±10% – 2.0 4.0 fXIN= 10MHz, VDD= 3V±10% – 1.3 2.6 fIRC= 16MHz, VDD= 5V±10% – 1.5 3.0 Sub RUN – 50.0 80.0 μA IDLE – 8.0 16.0 μA STOP, VDD= 5V±10%, TA= 25°C – 0.5 3.0 μA IDD3 fXIN= 32.768kHz VDD= 3V±10% IDD4 Sub TA= 25°C IDD5 MIN mA mA NOTES) 1. Where the fXIN is an external main oscillator, fSUB is an external sub oscillator, the fIRC is an internal RC oscillator, and the fx is the selected system clock. 2. All supply current items don’t include the current of an internal Watch-dog timer RC (WDTRC) oscillator and a peripheral block. 3. All supply current items include the current of the power-on reset (POR) block. PS029902-0212 PRELIMINARY 34 Z51F3220 Product Specification 7.10 AC Characteristics Table 7-10 AC Characteristics (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Parameter S RESETB input low width Interrupt input high, low width ymbol tRSL tINTH, tINTL MIN TYP MAX Unit Input, VDD= 5V Conditions 10 – – μS All interrupt, VDD= 5V 200 – – External Counter Input High, Low Pulse Width tECWH, tECWL ECn, VDD = 5 V (n= 0, 1, 3) 200 – – External Counter Transition Time tREC, tFEC ECn, VDD = 5 V (n= 0, 1, 3) 20 – – t IWL nS tIWH External Interrupt 0.8VDD 0.2VDD tRST RESETB 0.2VDD tECWL tFEC t ECWH tREC ECn 0.8VDD 0.2VDD Figure 7.1 AC Timing PS029902-0212 PRELIMINARY 35 Z51F3220 Product Specification 7.11 SPI0/1/2 Characteristics Table 7-11 SPI0/1/2 Characteristics Parameter S (TA= -40°C – +85°C, VDD= 1.8V – 5.5V) ymbol Conditions Output Clock Pulse Period MIN TYP MAX Internal SCK source 200 – – External SCK source 200 – – Internal SCK source 70 – – External SCK source 70 – – Internal/External SCK source 100 – Unit tSCK Input Clock Pulse Period Output Clock High, Low Pulse Width Input Clock High, Low Pulse Width First Output Clock Delay Time Output Clock Delay Time tSCKH, tSCKL tFOD nS – tDS – – – 50 Input Setup Time tDIS – 100 – – Input Hold Time tDIH – 150 – – SSn (Output/Input ) tSCK t FOD 0.8VDD SCKn (CPOLn=0) (Output/Input ) tSCKL tSCKH 0.2VDD SCKn (CPOLn=1) (Output/Input ) t DIS t DIH MISOn/MOSIn (Data Input ) MSB LSB tDS MISOn/MOSIn (Data Output ) MSB LSB NOTE) n =0, 1 and 2 Figure 7.2 SPI0/1/2 Timing PS029902-0212 PRELIMINARY 36 Z51F3220 Product Specification 7.12 UART0/1 Characteristics Table 7-12 UART0/1 Characteristics (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, fXIN=11.1MHz) Parameter S ymbol MIN TYP MAX Unit Serial port clock cycle time tSCK 1 250 tCPU x 16 1650 nS Output data setup to clock rising edge tS1 590 tCPU x 13 – nS Clock rising edge to input data valid tS2 – – 590 nS Output data hold after clock rising edge tH1 tCPU - 50 Input data hold after clock rising edge tH2 0–– Serial port clock High, Low level width tHIGH, tLOW 470 tCPU – nS nS tCPU x 8 970 nS t SCK t HIGH t LOW Figure 7.3 Waveform for UART0/1 Timing Characteristics t SCK Shift Clock tS1 Data Out tH1 D0 D1 D2 tS2 Data In Valid D3 D4 D5 D6 D7 t H2 Valid Valid Valid Valid Valid Valid Valid Figure 7.4 Timing Waveform for the UART0/1 Module PS029902-0212 PRELIMINARY 37 Z51F3220 Product Specification 7.13 I2C0/1 Characteristics Table 7-13 I2C0/1 Characteristics (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Parameter S Standard Mode ymbol Clock frequency MIN M tSCL High-Speed Mode AX MI NM 0 100 0 400 Clock High Pulse Width tSCLH 4.0 – 0. 6– Clock Low Pulse Width tSCLL 4.7 – 1. 3– tBF 4.7 – 1. 3– Start Condition Setup Time tSTSU 4.7 – 0. 6– Start Condition Hold Time tSTHD 4.0 – 0. 6– Stop Condition Setup Time tSPSU 4.0 – 0. 6– Stop Condition Hold Time tSPHD 4.0 – 0. 6– Bus Free Time Output Valid from Clock tVD 0–0 Data Input Hold Time tDIH 0–0 Data Input Setup Time tDIS 250 – 10 AX Unit kHz μS – 1.0 0 – nS tSCL tSCLH t STSU t SCLL tDIH t SPSU SCLn tSPHD SDAn tSTHD SDAn Out tVD tDIS t BF t VD NOTE) n= 0, and 1 Figure 7.5 I2C0/1 Timing PS029902-0212 PRELIMINARY 38 Z51F3220 Product Specification 7.14 Data Retention Voltage in Stop Mode Table 7-14 Data Retention Voltage in Stop Mode Parameter S ymbol Data retention supply voltage VDDDR Data retention supply current IDDDR (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Conditions MIN – TYP MAX 1.8 – 5. 5 –– VDDR= 1.8V, (TA= 25°C), Stop mode 1 Unit V μA ~ ~ Idle Mode (Watchdog Timer Active) Stop Mode Normal Operating Mode Data Retention ~ V DD VDDDR Execution of STOP Instruction 0.8VDD INT Request t WAIT NOTE: tWAIT is the same as (the selected bit overflow of BIT) X 1/(BIT Clock) Figure 7.6 Stop Mode Release Timing when Initiated by an Interrupt RESET Occurs ~ Oscillation Stabillization Time Stop Mode Normal Operating Mode Data Retention ~ ~ VDD V DDDR RESETB Execution of STOP Instruction 0.2 VDD 0.8 VDD TWAIT NOTE : tWAIT is the same as (4096 X 4 X 1/fx) (16.4mS @ 1MHz) Figure 7.7 Stop Mode Release Timing when Initiated by RESETB PS029902-0212 PRELIMINARY 39 Z51F3220 Product Specification 7.15 Internal Flash Rom Characteristics Table 7-15 Internal Flash Rom Characteristics Parameter S ymbol (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Condition MIN TYP M AX Unit Sector Write Time tFSW – – 2.5 2.7 Sector Erase Time tFSE – – 2.5 2.7 Hard-Lock Time tFHL – – 2.7 Page Buffer Reset Time tFBR – – 2.5 – fPGM – 0.4 – – MHz NFWE – – – 100,000 Times Flash Programming Frequency Endurance of Write/Erase 5 mS μS NOTE) During a flash operation, SCLK[1:0] of SCCR must be set to “00” or “01” (INT-RC OSC or Main X-TAL for system clock). 7.16 Input/Output Capacitance Table 7-16 Input/Output Capacitance Parameter S Input Capacitance Output Capacitance I/O Capacitance PS029902-0212 ymbol CIN COUT CIO (TA= -40°C ~ +85°C, VDD= 0V) Condition fx= 1MHz Unmeasured pins are connected to VSS PRELIMINARY MIN –– TYP M AX 10 Unit pF 40 Z51F3220 Product Specification 7.17 Main Clock Oscillator Characteristics Table 7-17 Main Clock Oscillator Characteristics Oscillator Para Crystal Ceramic Oscillator External Clock meter (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Condition Main oscillation frequency Main oscillation frequency XIN input frequency XIN MIN TYP M AX 1.8V – 5.5V 0.4 – 4.2 2.7V – 5.5V 0.4 – 10.0 3.0V – 5.5V 0.4 – 12.0 1.8V – 5.5V 0.4 – 4.2 2.7V – 5.5V 0.4 – 10.0 3.0V – 5.5V 0.4 – 12.0 1.8V – 5.5V 0.4 – 4.2 2.7V – 5.5V 0.4 – 10.0 3.0V – 5.5V 0.4 – 12.0 Unit MHz MHz MHz XOUT C2 C1 Figure 7.8 Crystal/Ceramic Oscillator XIN XOUT External Clock Source Open Figure 7.9 External Clock PS029902-0212 PRELIMINARY 41 Z51F3220 Product Specification 7.18 Sub Clock Oscillator Characteristics Table 7-18 Sub Clock Oscillator Characteristics Oscillator Para Crystal meter Sub oscillation frequency External Clock SXIN input frequency SXIN (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Condition 1.8V – 5.5V MIN 32 3 32 TYP M AX 2.768 3 8 Unit kHz 100 kHz – SXOUT C2 C1 Figure 7.10 Crystal Oscillator SXIN SXOUT External Clock Source Open Figure 7.11 External Clock PS029902-0212 PRELIMINARY 42 Z51F3220 Product Specification 7.19 Main Oscillation Stabilization Characteristics Table 7-19 Main Oscillation Stabilization Characteristics Oscillator Para Crystal Ceramic – External Clock (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) meter MIN fx > 1MHz Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. –– fXIN = 0.4 to 12MHz XIN input high and low width (tXH, tXL) 42 – TYP M – AX Unit 60 mS 10 mS 1250 nS 1/f XIN tXL tXH 0.8VDD XIN 0.2VDD Figure 7.12 Clock Timing Measurement at XIN 7.20 Sub Oscillation Characteristics Table 7-20 Sub Oscillation Stabilization Characteristics Oscillator Para Crystal – External Clock meter SXIN input high and low width (tXH, tXL) (TA= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) MIN – 5– TYP M – AX 10 Unit S 15 μS Figure 7.13 Clock Timing Measurement at SXIN PS029902-0212 PRELIMINARY 43 Z51F3220 Product Specification 7.21 Operating Voltage Range (fXIN =0.4 to 12MHz) (fSUB =32 to 38KHz) 12.0MHz 32.768KHz 10.0MHz 4.2MHz 0.4MHz 1.8 2.7 3.0 5.5 1.8 5.5 Supply voltage (V) Supply voltage (V) Figure 7.14 Operating Voltage Range PS029902-0212 PRELIMINARY 44 Z51F3220 Product Specification 7.22 Recommended Circuit and Layout { } This 0.1uF capacitor should be within 1cm from the VDD pin of MCU on the PCB layout. VDD VCC High-Current Part MC96F6432 { I/O Infrared LED, FND(7-Segment), ,,,,, etc VCC + 0.1uF 0.1uF VSS VDD } { DC Power The MCU power line(VDD a nd VSS) should be separated from the high current part at a DC power node on the PCB layout. } 0.01uF { XIN X-tal C1 C2 SXOUT 32.768kHz } The main and sub crystal should be as close by the MCU as possible. XOUT SXIN This 0.01uF capacitor is alternatively for noise immunity. The load capacitors of the sub clock - C1, C2: CL x 2 ± 15% - CL = (C1 x C2)/(C1 + C2) - Cstray - CL: the specific capacitor value of crystal - Cstray: the parasitic capacitor of a PCB (1pF – 1.5pF) Figure 7.15 Recommended Circuit and Layout PS029902-0212 PRELIMINARY 45 Z51F3220 Product Specification 7.23 Typical Characteristics These graphs and tables provided in this section are only for design guidance and are not tested or guaranteed. In graphs or tables some data are out of specified operating range (e.g. out of specified VDD range). This is only for information and devices are guaranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean - 3σ) respectively where σ is standard deviation. mA 3.00 2.50 2.00 10MHz -40℃ 1.50 10MHz +25℃ 10MHz +85℃ 1.00 0.50 0.00 2.7V 3.0V 3.3V Figure 7.16 RUN (IDD1 ) Current mA 1.40 1.20 1.00 0.80 10MHz -40℃ 0.60 10MHz +25℃ 10MHz +85℃ 0.40 0.20 0.00 2.7V 3.0V 3.3V Figure 7.17 IDLE (IDD2) Current PS029902-0212 PRELIMINARY 46 Z51F3220 Product Specification uA 160.0 140.0 120.0 100.0 -40℃ 80.0 +25℃ 60.0 +85℃ 40.0 20.0 0.0 2.7V 3.0V 3.3V 4.5V 5.0V 5.5V Figure 7.18 SUB RUN (IDD3) Current uA 30.00 25.00 20.00 -40℃ 15.00 +25℃ +85℃ 10.00 5.00 0.00 2.7V 3.0V 3.3V 4.5V 5.0V 5.5V Figure 7.19 SUB IDLE (IDD4) Current PS029902-0212 PRELIMINARY 47 Z51F3220 Product Specification uA 5.00 4.00 3.00 -40℃ +25℃ 2.00 +85℃ 1.00 0.00 2.7V 3.0V 3.3V 4.5V 5.0V 5.5V Figure 7.20 STOP (IDD5) Current PS029902-0212 PRELIMINARY 48 Z51F3220 Product Specification 8. Memory The Z51F3220 addresses two separate address memory stores: Program memory and Data memory. The logical separation of Program and Data memory allows Data memory to be accessed by 8-bit addresses, which makes the 8-bit CPU access the data memory more rapidly. Nevertheless, 16-bit Data memory addresses can also be generated through the DPTR register. Z51F3220 provides on-chip 32k bytes of the ISP type flash program memory, which can be read and written to. Internal data memory (IRAM) is 256 bytes and it includes the stack area. External data memory (XRAM) is 768 bytes and it includes 27 bytes of LCD display RAM. 8.1 Program Memory A 16-bit program counter is capable of addressing up to 64k bytes, but this device has just 32k bytes program memory space. Figure 8-1 shows the map of the lower part of the program memory. After reset, the CPU begins execution from location 0000H. Each interrupt is assigned a fixed location in program memory. The interrupt causes the CPU to jump to that location, where it commences execution of the service routine. External interrupt 11, for example, is assigned to location 000BH. If external interrupt 11 is going to be used, its service routine must begin at location 000BH. If the interrupt is not going to be used, its service location is available as general purpose program memory. If an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8 byte interval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use. PS029902-0212 PRELIMINARY 49 Z51F3220 Product Specification FFFFH 7FFFH 32k Bytes 0000H - 32k Bytes Including Interrupt Vector Region Figure 8.1 Program Memory PS029902-0212 PRELIMINARY 50 Z51F3220 Product Specification 8.2 Data Memory Figure 8-2 shows the internal data memory space available. FFH FFH Upper 1 28 Bytes Internal RAM (Indirect Addressing ) 80H Special Function Registers 128 B ytes (Direct Addressing) 80H 7FH Lower 128 Bytes Internal RAM (Direct or Indirect Addressing ) 00H Figure 8.2 Data Memory Map The internal data memory space is divided into three blocks, which are generally referred to as the lower 128 bytes, upper 128 bytes, and SFR space. Internal data memory addresses are always one byte wide, which implies an address space of only 256 bytes. However, in fact the addressing modes for internal RAM can accommodate up to 384 bytes by using a simple trick. Direct addresses higher than 7FH access one memory space and indirect addresses higher than 7FH access a different memory space. Thus Figure 8-2 shows the upper 128 bytes and SFR space occupying the same block of addresses, 80H through FFH, although they are physically separate entities. The lower 128 bytes of RAM are present in all 8051 devices as mapped in Figure 8-3. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers as R0 through R7. Two bits in the Program Status Word select which register bank is in use. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing. The next 16 bytes above the register banks form a block of bit-addressable memory space. The 8051 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00H through 7FH. All of the bytes in the lower 128 bytes can be accessed by either direct or indirect addressing. The upper 128 bytes RAM can only be accessed by indirect addressing. These spaces are used for data RAM and stack. PS029902-0212 PRELIMINARY 51 Z51F3220 Product Specification 7FH General Purpose Register 80 B ytes 30H 2FH 16 Bytes (128 bits) Bit Addressable 20H 1FH 8 Bytes 18H 17H 8 Bytes 10H 0FH 8 Bytes 08H 07H 8 Bytes 00H Register Bank 3 (8 Bytes) 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 Register Bank 2 (8 Bytes) Register Bank 1 (8 Bytes) Register Bank 0 (8 Bytes) R7 R6 R5 R4 R3 R2 R1 R0 Figure 8.3 Lower 128 Bytes RAM PS029902-0212 PRELIMINARY 52 Z51F3220 Product Specification 8.3 XRAM Memory Z51F3220 has 768 bytes XRAM. This area has no relation with RAM/Flash. It can be read and written to through SFR with 8-bit unit. 107 FH Extended Special Function Registers 128 B ytes (Indirect Addressing ) 1000 H Not used 02FFH External RAM 768 B ytes (Indirect Addressing ) 001BH 001AH LCD Display RAM 0000 H Figure 8.4 XDATA Memory Area PS029902-0212 PRELIMINARY 53 Z51F3220 Product Specification 8.4 SFR Map 8.4.1 SFR Map Summary - Table 8-1 SFR Map Summary Reserved M8051 compatible 00 0F8H 0F0H H/8H(1) 01H/9 IP1 – B STFR 0E0H ACC U 0D8H LVRC R 0D0H PSW P5I 0C8H O SCCR 0C0H EIFLAG0 0B0H P 0A8H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH FSADRH FSADRM FSADRL FIDR FMCR P5FSR USI1BD USI1SDHR USI1DR USI1SCLR USI1SCHR USI1ST1 USI1ST2 0E8H R 0B8H H IP P2I 5 USI1CR1 USI1CR2 USI1CR3 USI1CR4 USI1SAR P3FSR P4FSR SI0ST1 USI0ST2 USI0BD USI0SDHR USI0DR USI0SCLR USI0SCHR USI0CR1 USI0CR2 USI0CR3 USI0CR4 USI0SAR P0DB P15DB P0FSRL P0FSRH P1FSRL P1FSRH P2FSRL P2FSRH P4IO – – – – – – P3IO T2CRL T2CRH T2ADRL T2ADRH T2BDRL T2BDRH O T1CRL T1CRH T1ADRL T1ADRH T1BDRL T1BDRH P1IO T0CR T0CNT T0DR/ T0CDR IE2 IE3 P0PU O IE IE1 R SPISR P1PU P2PU P3PU EIPOL0L EIPOL0H EIFLAG1 EIPOL1 0A0H P4 P0IO 98H P3 LCDCRL LCDCRH LCDCCR ADCCRH ADCCRH ADCDRL ADCDRH 90H P2 P0OD P1OD P2OD P4OD P5PU WTCR BUZCR BITCNT WDTCR WDTDR/ WDTCNT BUZDR 88H P1 80H P0 WTDR/ WTCNT SP EO P4PU SPICR SPID SCCR BIT DPL CR DPH DPL1 DPH1 LVI CR PCON NOTE) These registers are bit-addressable. PS029902-0212 PRELIMINARY 54 Z51F3220 Product Specification Table 8-2 SFR Map Summary - 00H /8H(1) 01H/9 H 02H/0AH 03H/0BH 04H/0CH Reserved 05H/0DH 06H/0EH 07H/0FH 1078H ––– –– – – – 1070H ––– –– – – – 1068H ––– –– – – – 1060H ––– –– – – – 1058H ––– –– – – – 1050H ––– –– – – – 1048H ––– –– – – – 1040H ––– –– – – – 1038H ––– –– – – – 1030H ––– –– – – – 1028H ––– –– – – – 1020H ––– –– – – – 1018H ––– –– – – – T4CNT – – 1010H T 4DLYA 1008H T 4PPRL 100H T 3CR T4DLYB T4PPRH T3CNT/ T3DR/ T3CAPR T4DLYC T4ADRL T4AD T4CR T4 T4DR T4CAPR RH T4BDRL T4BDRH T4C PCR1 T4PCR2 T4PCR3 T4ISR DRL T4CDRH T4IMSK NOTE) These registers are bit-addressable. PS029902-0212 PRELIMINARY 55 Z51F3220 Product Specification 8.4.2 SFR Map Table 8-3 SFR Map Address Func 80H tion P0 Data Register 81H Stack Pointer 82H Data Pointer Register Low Symbol R/W P0 R/W @Reset 765 000 4 0 3 0 2 0 1 0 0 0 SP R/W 000 0 0 1 1 1 DPL R/W 000 0 0 0 0 0 83H Data Pointer Register High DPH R/W 000 0 0 0 0 0 84H Data Pointer Register Low 1 DPL1 R/W 0 0 0 0 0 0 0 0 85H Data Pointer Register High 1 DPH1 R/W 0 0 0 0 0 0 0 0 86H Low Voltage Indicator Control Register LVICR R/W – – 0 0 0 0 0 0 87H Power Control Register PCON R/W 0–– – 0 0 0 0 88H P1 Data Register P1 R/W 000 0 0 0 0 0 WTDR W 011 1 1 1 1 1 89H Watch Timer Data Register WTCNT R – 0 0 0 0 0 0 0 8AH System and Clock Control Register SCCR R/W – – – – – – 0 0 8BH Basic Interval Timer Control Register BITCR R/W 0 0 0 – 0 0 0 1 8CH Basic Interval Timer Counter Register BITCNT R 0 0 0 0 0 0 0 0 8DH Watch Dog Timer Control Register WDTCR R/W 0 0 0 – – – 0 0 WDTDR W 1 1 1 1 1 1 1 1 WDTCNT R 0 0 0 0 0 0 0 0 8EH Watch Timer Counter Register Watch Dog Timer Data Register Watch Dog Timer Counter Register 8FH BUZZER Data Register 90H P2 Data Register BUZDR R/W 111 1 1 1 1 1 P2 R/W 000 0 0 0 0 0 91H 92H P0 Open-drain Selection Register P0OD R/W 0 0 0 0 0 0 0 0 P1 Open-drain Selection Register P1OD R/W 0 0 0 0 0 0 0 0 93H P2 Open-drain Selection Register P2OD R/W 0 0 0 0 0 0 0 0 94H P4 Open-drain Selection Register P4OD R/W – – – – 0 0 0 0 95H P5 Pull-up Resistor Selection Register P5PU R/W – – 0 0 0 0 0 0 – – 0 0 0 0 0 – – 0 0 0 96H Watch Timer Control Register WTCR R/W 0 97H BUZZER Control Register BUZCR R/W ––– 98H P3 Data Register P3 R/W 000 0 0 0 0 0 99H LCD Driver Control Low Register LCDCRL R/W – – 0 0 0 0 0 0 9AH LCD Driver Control High Register LCDCRH R/W – – – 0 – – 0 0 9BH LCD Contrast Control register LCDCCR R/W 0 – – – 0 0 0 0 9CH A/D Converter Control Low Register ADCCRL R/W 0 0 0 0 0 0 0 0 9DH A/D Converter Control High Register ADCCRH R/W 0 – 0 0 0 0 0 0 9EH A/D Converter Data Low Register ADCDRL R x x x x x x x x 9FH A/D Converter Data High Register ADCDRH R x x xxxxx PS029902-0212 PRELIMINARY x 56 Z51F3220 Product Specification Table 8-2 SFR Map (Continued) Address Func A0H tion P4 Data Register @Reset Symbol R/W P4 R/W 765 ––– P0IO R/W 0 EO R/W ––– 0 4 – 0 3 0 2 0 1 0 0 0 A1H P0 Direction Register A2H Extended Operation Register 0 0 0 0 0 0 – 0 0 0 A3H P4 Pull-up Resistor Selection Register P4PU R/W – – A4H External Interrupt Polarity 0 Low Register EIPOL0L R/W 0 0 – – 0 0 0 0 0 0 0 0 0 0 A5H External Interrupt Polarity 0 High Register EIPOL0H R/W 0 0 0 0 0 0 0 0 A6H External Interrupt Flag 1 Register EIFLAG1 R/W 0 0 0 0 0 0 0 0 A7H External Interrupt Polarity 1 Register EIPOL1 R/W 0 0 0 0 0 0 0 0 A8H Interrupt Enable Register IE R/W 0 – 0 0 0 0 0 0 A9H Interrupt Enable Register 1 IE1 R/W – – 0 0 0 0 – 0 AAH Interrupt Enable Register 2 IE2 R/W – – 0 0 0 0 0 0 ABH Interrupt Enable Register 3 IE3 R/W – – 0 0 0 0 0 0 ACH P0 Pull-up Resistor Selection Register P0PU R/W 0 0 0 0 0 0 0 0 ADH P1 Pull-up Resistor Selection Register P1PU R/W 0 0 0 0 0 0 0 0 AEH P2 Pull-up Resistor Selection Register P2PU R/W 0 0 0 0 0 0 0 0 AFH P3 Pull-up Resistor Selection Register P3PU R/W 0 0 0 0 0 0 0 0 B0H P5 Data Register P5 R/W ––0 0 0 0 0 0 B1H P1 Direction Register P1IO R/W 0 0 0 0 0 0 0 0 B2H Timer 0 Control Register T0CR R/W 0 – 0 0 0 0 0 0 B3H Timer 0 Counter Register T0CNT R 0 0 0 0 0 0 0 0 T0DR R/W 1 1 1 1 1 1 1 1 0 B4H Timer 0 Data Register Timer 0 Capture Data Register T0CDR R 0 0 0 0 0 0 0 B5H SPI 2 Control Register SPICR R/W 0 0 0 0 0 0 0 0 B6H SPI 2 Data Register SPIDR R/W 0 0 0 0 0 0 0 0 B7H SPI 2 Status Register SPISR R/W 0 0 0 – 0 0 – – B8H Interrupt Priority Register IP R/W ––0 0 0 0 0 0 B9H P2 Direction Register BAH Timer 1 Control Low Register P2IO R/W 0 0 0 0 0 0 0 0 T1CRL R/W 0 0 0 0 – 0 0 0 BBH Timer 1 Counter High Register T1CRH R/W 0 – 0 0 – – – 0 BCH Timer 1 A Data Low Register T1ADRL R/W 1 1 1 1 1 1 1 1 BDH Timer 1 A Data High Register T1ADRH R/W 1 1 1 1 1 1 1 1 BEH Timer 1 B Data Low Register T1BDRL R/W 1 1 1 1 1 1 1 1 BFH Timer 1 BData High Register T1BDRH R/W 1 1 1 1 1 1 1 1 PS029902-0212 PRELIMINARY 57 Z51F3220 Product Specification Table 8-2 SFR Map (Continued) Address Func tion C0H External Interrupt Flag 0 Register C1H P3 Direction Register C2H Timer 2 Control Low Register @Reset Symbol R/W EIFLAG0 R/W 765 0 0 0 4 0 3 0 2 0 1 0 0 0 P3IO R/W 0 0 0 0 0 0 0 0 T2CRL R/W 0 0 0 0 – 0 – 0 C3H Timer 2 Control High Register T2CRH R/W 0 – 0 0 – – – 0 C4H Timer 2 A Data Low Register T2ADRL R/W 1 1 1 1 1 1 1 1 C5H Timer 2 A Data High Register T2ADRH R/W 1 1 1 1 1 1 1 1 C6H Timer 2 B Data Low Register T2BDRL R/W 1 1 1 1 1 1 1 1 C7H Timer 2 BData High Register T2BDRH R/W 1 1 1 1 1 1 1 1 C8H Oscillator Control Register OSCCR R/W ––0 0 1 0 0 0 C9H P4 Direction Register P4IO R/W – – 0 0 0 0 – – CAH Res erved – – – CBH Res erved – – – CCH Res erved – – – CDH Res erved – – – CEH Res erved – – – CFH Res erved – – PSW R/W 0 0 0 0 0 0 0 0 D0H Program Status Word Register – D1H P5 Direction Register P5IO R/W – – 0 0 0 0 0 0 D2H P0 Function Selection Low Register P0FSRL R/W – 0 0 0 0 0 0 0 D3H P0 Function Selection High Register P0FSRH R/W – – 0 0 0 0 0 0 D4H P1 Function Selection Low Register P1FSRL R/W 0 0 0 0 0 0 0 0 D5H P1 Function Selection High Register P1FSRH R/W 0 0 0 0 0 0 0 0 D6H P2 Function Selection Low Register P2FSRL R/W – – 0 0 0 0 0 0 D7H P2 Function Selection High Register P2FSRH R/W – – – – 0 0 0 0 D8H Low Voltage Reset Control Register LVRCR R/W 0 – – 0 0 0 0 0 D9H USI0 Control Register 1 USI0CR1 R/W 0 0 0 0 0 0 0 0 DAH USI0 Control Register 2 USI0CR2 R/W 0 0 0 0 0 0 0 0 DBH USI0 Control Register 3 USI0CR3 R/W 0 0 0 0 0 0 0 0 DCH USI0 Control Register 4 USI0CR4 R/W 0 – – 0 0 – 0 0 DDH USI0 Slave Address Register USI0SAR R/W 0 0 0 0 0 0 0 0 DEH P0 Debounce Enable Register P0DB R/W 0 0 0 0 0 0 0 0 DFH P1/P5 Debounce Enable Register P15DB R/W – – 0 0 0 0 0 0 PS029902-0212 PRELIMINARY 58 Z51F3220 Product Specification Table 8-2 SFR Map (Continued) Address Func E0H tion Accumulator Register @Reset Symbol R/W ACC R/W 76 00 5 0 43 00 2 0 1 0 0 0 E1H USI0 Status Register 1 USI0ST1 R/W 0 0 0 0 – 0 0 0 E2H USI0 Status Register 2 USI0ST2 R 0 0 0 0 0 0 0 0 E3H USI0 Baud Rate Generation Register E4H USI0 SDA Hold Time Register USI0BD R/W 1 1 1 1 1 1 1 1 USI0SHDR R/W 0 0 0 0 0 0 0 1 E5H USI0 Data Register USI0DR R/W 00 0 00 0 0 0 E6H USI0 SCL Low Period Register USI0SCLR R/W 0 0 1 1 1 1 1 1 E7H USI0 SCL High Period Register USI0SCHR R/W 0 0 1 1 1 1 1 1 E8H Reset Flag Register RSTFR R/W 1 x 0 0 x – – – E9H USI1 Control Register 1 USI1CR1 R/W 0 0 0 0 0 0 0 0 EAH USI1 Control Register 2 USI1CR2 R/W 0 0 0 0 0 0 0 0 EBH USI1 Control Register 3 USI1CR3 R/W 0 0 0 0 0 0 0 0 ECH USI1 Control Register 4 USI1CR4 R/W 0 – – 0 0 – 0 0 EDH USI1 Slave Address Register USI1SAR R/W 0 0 0 0 0 0 0 0 EEH P3 Function Selection Register P3FSR R/W 0 0 0 0 0 0 0 0 EFH P4 Function Selection Register P4FSR R/W – 0 0 0 0 0 0 0 F0H B Register B R/W 00 0 00 0 0 0 F1H USI1 Status Register 1 USI1ST1 R/W 0 0 0 0 – 0 0 0 F2H USI1 Status Register 2 USI1ST2 R 0 0 0 0 0 0 0 0 F3H USI1 Baud Rate Generation Register F4H USI1 SDA Hold Time Register USI1BD R/W 1 1 1 1 1 1 1 1 USI1SHDR R/W 0 0 0 0 0 0 0 1 0 F5H USI1 Data Register USI1DR R/W 00 0 00 0 0 F6H USI1 SCL Low Period Register USI1SCLR R/W 0 0 1 1 1 1 1 1 F7H USI1 SCL High Period Register USI1SCHR R/W 0 0 1 1 1 1 1 1 F8H Interrupt Priority Register 1 IP1 R/W – – 0 0 0 0 0 0 – – F9H Res erved – FAH Flash Sector Address High Register FSADRH R/W – – – – 0 0 0 0 FBH Flash Sector Address Middle Register FSADRM R/W 0 0 0 0 0 0 0 0 FCH Flash Sector Address Low Register FSADRL R/W 0 0 0 0 0 0 0 0 FDH Flash Identification Register FIDR R/W 00 0 00 0 0 0 FEH Flash Mode Control Register FMCR R/W 0 – – – – 0 0 0 FFH P5 Function Selection Register P5FSR R/W – – 0 0 0 0 0 0 PS029902-0212 PRELIMINARY 59 Z51F3220 Product Specification Table 8-2 SFR Map (Continued) Address Func 1000H 1001H tion @Reset Symbol R/W Timer 3 Control Register T3CR R/W Timer 3 Counter Register T3CNT R 0 0 T3DR W 1 1 Timer 3 Data Register Timer 3 Capture Data Register 76 0 – 5 0 43 0 0 2 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 T3CAPR R 0 0 0 0 0 0 0 0 T4CR R/W 0 0 0 0 0 0 0 0 R/W 0 0 0 0 0 0 0 0 R/W 0 0 0 0 0 0 0 0 R/W – 0 0 0 – – – – R/W 0 0 0 0 0 – – – R/W 0 0 0 0 0 – – – 1002H Timer 4 Control Register 1003H Timer 4 PWM Control Register 1 T4PCR1 1004H Timer 4 PWM Control Register 2 T4PCR2 1005H Timer 4 PWM Control Register 3 T4PCR3 1006H Timer 4 Interrupt Status Register T4ISR 1007H Timer 4 Interrupt Mask Register T4MSK 1008H Timer 4 PWM Period Low Register T4PPRL R/W 1 1 1 1 1 1 1 1 1009H Timer 4 PWM Period High Register T4PPRH R/W – – – – – – 0 0 100AH Timer 4 PWM A Duty Low Register T4ADRL R/W 0 1 1 1 1 1 1 1 100BH Timer 4 PWM A Duty High Register T4ADRH R/W – – – – – – 0 0 100CH Timer 4 PWM B Duty Low Register T4BDRL R/W 0 1 1 1 1 1 1 1 100DH Timer 4 PWM B Duty High Register T4BDRH R/W – – – – – – 0 0 100EH Timer 4 PWM C Duty Low Register T4CDRL R/W 0 1 1 1 1 1 1 1 100FH Timer 4 PWM C Duty High Register T4CDRH R/W – – – – – – 0 0 1010H Timer 4 PWM A Delay Register T4DLYA R/W 0 0 0 0 0 0 0 0 1011H Timer 4 PWM B Delay Register T4DLYB R/W 0 0 0 0 0 0 0 0 1012H Timer 4 PWM C Delay Register T4DLYC R/W 0 0 0 0 0 0 0 0 1013H Timer 4 Data Register 1014H Timer 4 Capture Data Register 1015H Timer 4 Counter Register T4DR R/W 1 1 1 1 1 1 1 1 T4CAPR R 0 0 0 0 0 0 0 0 T4CNT R 0 0 0 0 0 0 0 0 ………………………………….. 107FH Res erved PS029902-0212 – PRELIMINARY – – 60 Z51F3220 Product Specification 8.4.3 Compiler Compatible SFR ACC (Accumulator Register) : E0H 7 6 5 4 R/W R/W R/W R/W 3 2 1 R/W R/W R/W 3 2 1 R/W R/W R/W 3 2 1 R/W R/W R/W 3 2 1 R/W R/W R/W 3 2 1 R/W R/W R/W 0 ACC R/W Initial value : 00H Accumulator ACC B (B Register) : F0H 7 6 5 4 R/W R/W R/W R/W 0 B R/W Initial value : 00H B Register B SP (Stack Pointer) : 81H 7 6 5 4 0 SP R/W R/W R/W R/W R/W Initial value : 07H Stack Pointer SP DPL (Data Pointer Register Low) : 82H 7 6 5 4 0 DPL R/W R/W R/W R/W R/W Initial value : 00H Data Pointer Low DPL DPH (Data Pointer Register High) : 83H 7 6 5 4 R/W R/W R/W R/W 0 DPH DPH PS029902-0212 R/W Initial value : 00H Data Pointer High PRELIMINARY 61 Z51F3220 Product Specification DPL1 (Data Pointer Register Low 1) : 84H 7 6 5 4 3 2 1 R/W R/W R/W 3 2 1 R/W R/W R/W 2 1 0 DPL1 R/W R/W R/W R/W R/W Initial value : 00H Data Pointer Low 1 DPL1 DPH1 (Data Pointer Register High 1) : 85H 7 6 5 4 0 DPH1 R/W R/W R/W R/W R/W Initial value : 00H Data Pointer High 1 DPH1 PSW (Program Status Word Register) : D0H 7 6 5 4 3 CY AC F0 RS1 RS0 OV F1 R/W R/W R/W R/W R/W R/W R/W 0 P R/W Initial value : 00H CY Carry Flag AC Auxiliary Carry Flag F0 General Purpose User-Definable Flag RS1 Register Bank Select bit 1 RS0 Register Bank Select bit 0 OV Overflow Flag F1 User-Definable Flag P Parity Flag. Set/Cleared b y har dware each i nstruction c ycle t o indicate an odd/even number of ‘1’ bits in the accumulator EO (Extended Operation Register) : A2H 7 6 5 4 3 2 1 0 – – – TRAP_EN – DPSEL2 DPSEL1 DPSEL0 – – – R/W – R/W R/W TRAP_EN DPSEL[2:0] R/W Initial value : 00H Select the Instruction (Keep always ‘0’). 0 Select Software TRAP Instruction 1 Select MOVC @(DPTR++), A Select Banked Data Pointer Register DPSEL2 DPSEL1 S PSEL0 Description 0 0 0 DPTR 0 0 0 1 DPTR 1 Reserved PS029902-0212 PRELIMINARY 62 Z51F3220 Product Specification 9. I/O Ports 9.1 I/O Ports The Z51F3220 has ten groups of I/O ports (P0 ~ P5). Each port can be easily configured by software as I/O pin, internal pull up and open-drain pin to meet various system configurations and design requirements. Also P0 includes function that can generate interrupt according to change of state of the pin. 9.2 Port Register 9.2.1 Data Register (Px) Data Register is a bidirectional I/O port. If ports are configured as output ports, data can be written to the corresponding bit of the Px. If ports are configured as input ports, the data can be read from the corresponding bit of the Px. 9.2.2 Direction Register (PxIO) Each I/O pin can be independently used as an input or an output through the PxIO register. Bits cleared in this register will make the corresponding pin of Px to input mode. Set bits of this register will make the pin to output mode. Almost bits are cleared by a system reset, but some bits are set by a system reset. 9.2.3 Pull-up Resistor Selection Register (PxPU) The on-chip pull-up resistor can be connected to I/O ports individually with a pull-up resistor selection register (PxPU). The pull-up register selection controls the pull-up resister enable/disable of each port. When the corresponding bit is 1, the pull-up resister of the pin is enabled. When 0, the pull-up resister is disabled. All bits are cleared by a system reset. 9.2.4 Open-drain Selection Register (PxOD) There are internally open-drain selection registers (PxOD) for P0 ~ P4 and a bit for P5. The open-drain selection register controls the open-drain enable/disable of each port. Almost ports become push-pull by a system reset, but some ports become open-drain by a system reset. 9.2.5 Debounce Enable Register (PxDB) P0[7:2], P1[2:1], P1[7:6], P52 and P54 support debounce function. Debounce clocks of each ports are fx/1, fx/4, and fx/4096. 9.2.6 Port Function Selection Register (PxFSR) These r egisters de fine alternative functions of p orts. P lease remember th at these r egisters should be s et properly for alternative port function. A reset clears the PxFSR register to ‘00H’, which makes all pins to normal I/O ports. PS029902-0212 PRELIMINARY 63 Z51F3220 Product Specification 9.2.7 Register Map Table 9-1 Port Register Map Name Address P0 80H Dir Default Description R/W 00H P0 Data Register P0IO A1H R/W 00H P0 Direction Register P0PU ACH R/W 00H P0 Pull-up Resistor Selection Register P0OD 91H R/W 00H P0 Open-drain Selection Register P0DB DEH R/W 00H P0 Debounce Enable Register P0FSRH D3H R/W 00H P0 Function Selection High Register P0FSRL D2H R/W 00H P0 Function Selection Low Register P1 88H R/W 00H P1 Data Register P1IO B1H R/W 00H P1 Direction Register P1PU ADH R/W 00H P1 Pull-up Resistor Selection Register P1OD 92H R/W 00H P1 Open-drain Selection Register P15DB DFH R/W 00H P1/P5 Debounce Enable Register P1FSRH D5H R/W 00H P1 Function Selection High Register P1FSRL D4H R/W 00H P1 Function Selection Low Register R/W 00H P2 Data Register P2 90H P2IO B9H R/W 00H P2 Direction Register P2PU AEH R/W 00H P2 Pull-up Resistor Selection Register P2OD 93H R/W 00H P2 Open-drain Selection Register P2FSRH D7H R/W 00H P2 Function Selection High Register P2FSRL D6H R/W 00H P2 Function Selection Low Register P3 98H R/W 00H P3 Data Register P3IO C1H R/W 00H P3 Direction Register P3PU AFH R/W 00H P3 Pull-up Resistor Selection Register P3FSR EEH R/W 00H P3 Function Selection Register R/W 00H P4 Data Register P4IO C9H R/W 00H P4 Direction Register P4PU A3H R/W 00H P4 Pull-up Resistor Selection Register P4OD 94H R/W 00H P4 Open-drain Selection Register P4FSR EFH R/W 00H P4 Function Selection Register P5 B0H R/W 00H P5 Data Register P5IO D1H R/W 00H P5 Direction Register P5PU 95H R/W 00H P5 Pull-up Resistor Selection Register P5FSR EFH R/W 00H P5 Function Selection Register P4 A0H PS029902-0212 PRELIMINARY 64 Z51F3220 Product Specification 9.3 P0 Port 9.3.1 P0 Port Description P0 is 8-bit I/O port. P0 control registers consist of P0 data register (P0), P0 direction register (P0IO), debounce enable register (P0DB), P0 pull-up resistor selection register (P0PU), and P0 open-drain selection register (P0OD). Refer to the port function selection registers for the P0 function selection. 9.3.2 Register description for P0 P0 (P0 Data Register) : 80H 7 6 5 4 3 2 1 0 P07 P06 P05 P04 P03 P02 P01 P00 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 00H I/O Data P0[7:0] P0IO (P0 Direction Register) : A1H 7 6 5 4 3 2 1 0 P07IO P06IO P05IO P04IO P03IO P02IO P01IO P00IO R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 00H P0 Data I/O Direction. P0IO[7:0] 0I nput 1O utput NOTE: EC3/EINT0 ~ EINT5 function possible when input P0PU (P0 Pull-up Resistor Selection Register) : ACH 7 6 5 4 3 2 1 0 P07PU P06PU P05PU P04PU P03PU P02PU P01PU P00PU R/W R/W R/W R/W R/W R/W R/W P0PU[7:0] R/W Initial value : 00H Configure Pull-up Resistor of P0 Port 0D isable 1 Enab le P0OD (P0 Open-drain Selection Register) : 91H 7 6 5 4 3 2 1 0 P07OD P06OD P05OD P04OD P03OD P02OD P01OD P00OD R/W R/W R/W R/W R/W R/W R/W P0OD[7:0] PS029902-0212 R/W Initial value : 00H Configure Open-drain of P0 Port 0 Pu sh-pull output 1O pen-drain output PRELIMINARY 65 Z51F3220 Product Specification P0DB (P0 Debounce Enable Register) : DEH 7 6 5 4 3 2 1 0 DBCLK1 DBCLK0 P07DB P06DB P05DB P04DB P03DB P02DB R/W R/W R/W R/W R/W R/W R/W DBCLK[1:0] R/W Initial value : 00H Configure Debounce Clock of Port DBCLK1 DBCLK 0 De scription 00f x/1 01f x/4 10f x/4096 1 1 Res P07DB P06DB P05DB P04DB P03DB P02DB erved Configure Debounce of P07 Port 0 Di sable 1 En able Configure Debounce of P06 Port 0 Di sable 1 En able Configure Debounce of P05 Port 0 Di sable 1 En able Configure Debounce of P04 Port 0 Di sable 1 En able Configure Debounce of P03Port 0 Di sable 1 En able Configure Debounce of P02 Port 0 Di sable 1 En able NOTES) 1. If the same level is not detected on enabled pin three or four times in a row at the sampling clock, the signal is eliminated as noise. 2. A pulse level should be input for the duration of 3 clock or more to be actually detected as a valid edge. 3. The port debounce is automatically disabled at stop mode and recovered after stop mode release. PS029902-0212 PRELIMINARY 66 Z51F3220 Product Specification 9.4 P1 Port 9.4.1 P1 Port Description P1 is 8-bit I/O port. P1 control registers consist of P1 data register (P1), P1 direction register (P1IO), debounce enable register (P15DB), P1 pull-up resistor selection register (P1PU), and P1 open-drain selection register (P1OD) . Refer to the port function selection registers for the P1 function selection. 9.4.2 Register description for P1 P1 (P1 Data Register) : 88H 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 00H I/O Data P1[7:0] P1IO (P1 Direction Register) : B1H 7 6 5 4 3 2 1 0 P17IO P16IO P15IO P14IO P13IO P12IO P11IO P10IO R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 00H P1 Data I/O Direction P1IO[7:0] 0I nput 1O utput NOTE: E INT6/ENINT7/EINT11/EINT12/SS2/EC1 f unction pos sibl when input P1PU (P1 Pull-up Resistor Selection Register) : ADH 7 6 5 4 3 2 1 0 P17PU P16PU P15PU P14PU P13PU P12PU P11PU P10PU R/W R/W R/W R/W R/W R/W R/W P1PU[7:0] R/W Initial value : 00H Configure Pull-up Resistor of P1 Port 0D isable 1 Enab le P1OD (P1 Open-drain Selection Register) : 92H 7 6 5 4 3 2 1 0 P17OD P16OD P15OD P14OD P13OD P12OD P11OD P10OD R/W R/W R/W R/W R/W R/W R/W P1OD[7:0] PS029902-0212 R/W Initial value : 08H Configure Open-drain of P1 Port 0 Pu sh-pull output 1O pen-drain output PRELIMINARY 67 Z51F3220 Product Specification P15DB (P1/P5 Debounce Enable Register) : DFH 7 6 5 4 3 2 1 0 – – P54DB P52DB P17DB P16DB P12DB P11DB – – R/W R/W R/W R/W R/W P54DB P52DB P17DB P16DB P12DB P11DB R/W Initial value : 00H Configure Debounce of P54 Port 0 Di sable 1 En able Configure Debounce of P52 Port 0 Di sable 1 En able Configure Debounce of P17 Port 0 Di sable 1 En able Configure Debounce of P16 Port 0 Di sable 1 En able Configure Debounce of P12 Port 0 Di sable 1 En able Configure Debounce of P11 Port 0 Di sable 1 En able NOTES) 1. If the same level is not detected on enabled pin three or four times in a row at the sampling clock, the signal is eliminated as noise. 2. A pulse level should be input for the duration of 3 clock or more to be actually detected as a valid edge. 3. The port debounce is automatically disabled at stop mode and recovered after stop mode release. 4. Refer to the port 0 debounce enable register (P0DB) for the debounce clock of port 1 and port 5. PS029902-0212 PRELIMINARY 68 Z51F3220 Product Specification 9.5 P2 Port 9.5.1 P2 Port Description P2 is 8-bit I/O port. P2 control registers consist of P2 data register (P2), P2 direction register (P2IO), P2 pull-up resistor selection register (P2PU) and P2 open-drain selection register (P2OD). Refer to the port function selection registers for the P2 function selection. 9.5.2 Register description for P2 P2 (P2 Data Register) : 90H 7 6 5 4 3 2 1 0 P27 P26 P25 P24 P23 P22 P21 P20 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 00H I/O Data P2[7:0] P2IO (P2 Direction Register) : B9H 7 6 5 4 3 2 1 0 P27IO P26IO P25IO P24IO P23IO P22IO P21IO P20IO R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 00H P2 Data I/O Direction P2IO[7:0] 0I nput 1O utput NOTE: SS1 function possible when input P2PU (P2 Pull-up Resistor Selection Register) : AEH 7 6 5 4 3 2 1 0 P27PU P26PU P25PU P24PU P23PU P22PU P21PU P20PU R/W R/W R/W R/W R/W R/W R/W P2PU[7:0] R/W Initial value : 00H Configure Pull-up Resistor of P2 Port 0D isable 1 Enab le P2OD (P2 Open-drain Selection Register) : 93H 7 6 5 4 3 2 1 0 P27OD P26OD P25OD P24OD P23OD P22OD P21OD P20OD R/W R/W R/W R/W R/W R/W R/W P2OD[7:0] PS029902-0212 R/W Initial value : 00H Configure Open-drain of P2 Port 0 Pu sh-pull output 1O pen-drain output PRELIMINARY 69 Z51F3220 Product Specification 9.6 P3 Port 9.6.1 P3 Port Description P3 is 8-bit I/O port. P3 control registers consist of P3 data register (P3), P3 direction register (P3IO) and P3 pull-up resistor selection register (P3PU). Refer to the port function selection registers for the P3 function selection. 9.6.2 Register description for P3 P3 (P3 Data Register) : 98H 7 6 5 4 3 2 1 0 P37 P36 P35 P34 P33 P32 P31 P30 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 00H I/O Data P3[7:0] P3IO (P3 Direction Register) : C1H 7 6 5 4 3 2 1 0 P37IO P36IO P35IO P34IO P33IO P32IO P31IO P30IO R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 00H P3 Data I/O Direction P3IO[7:0] 0I nput 1O utput P3PU (P3 Pull-up Resistor Selection Register) : AFH 7 6 5 4 3 2 1 0 P37PU P36PU P35PU P34PU P33PU P32PU P31PU P30PU R/W R/W R/W R/W R/W R/W R/W P3PU[7:0] Configure Pull-up Resistor of P3 Port 0D isable 1 Enab PS029902-0212 R/W Initial value : 00H le PRELIMINARY 70 Z51F3220 Product Specification 9.7 P4 Port 9.7.1 P4 Port Description P4 is 4-bit I/O port. P4 control registers consist of P4 data register (P4), P4 direction register (P4IO), P4 pull-up resistor selection register (P4PU) and P4 open-drain selection register (P4OD). Refer to the port function selection registers for the P4 function selection. 9.7.2 Register description for P4 P4 (P4 Data Register) : A0H 7 6 5 4 3 2 1 0 – – – – P43 P42 P41 P40 – – – – R/W R/W R/W R/W Initial value : 00H I/O Data P4[3:0] P4IO (P4 Direction Register) : C9H 7 6 5 4 3 2 1 0 – – – – P43IO P42IO P41IO P40IO – – – – R/W R/W R/W R/W Initial value : 00H P4 Data I/O Direction P4IO[3:0] 0I nput 1O utput NOTE: SS0 function possible when input P4PU (P4 Pull-up Resistor Selection Register) : A3H 7 6 5 4 3 2 1 0 – – – – P43PU P42PU P41PU P40PU – – – – R/W R/W R/W P4PU[3:0] R/W Initial value : 00H Configure Pull-up Resistor of P4 Port 0D isable 1 Enab le P4OD (P4 Open-drain Selection Register) : 94H 7 6 5 4 3 2 1 0 – – – – P43OD P42OD P41OD P40OD – – – – R/W R/W R/W P4OD[3:0] PS029902-0212 R/W Initial value : 00H Configure Open-drain of P4 Port 0 Pu sh-pull output 1O pen-drain output PRELIMINARY 71 Z51F3220 Product Specification 9.8 P5 Port 9.8.1 P5 Port Description P5 is 6-bit I/O port. P5 control registers consist of P5 data register (P5), P5 direction register (P5IO) and P5 pull-up resistor selection register (P5PU) . Refer to the port function selection registers for the P5 function selection. 9.8.2 Register description for P5 P5 (P5 Data Register) : B0H 7 6 5 4 3 2 1 0 – – P55 P54 P53 P52 P51 P50 – – R/W R/W R/W R/W R/W R/W Initial value : 00H I/O Data P5[5:0] P5IO (P5 Direction Register) : D1H 7 6 5 4 3 2 1 0 – – P55IO P54IO P53IO P52IO P51IO P50IO – – R/W R/W R/W R/W R/W R/W Initial value : 00H P5 Data I/O Direction P5IO[5:0] 0I nput 1O utput NOTE: EC0/EINT8/EINT10/BLNK function possible when input P5PU (P5 Pull-up Resistor Selection Register) : 95H 7 6 5 4 3 2 1 0 – – P55PU P54PU P53PU P52PU P51PU P50PU – – R/W R/W R/W R/W R/W P5PU[5:0] Configure Pull-up Resistor of P5 Port 0D isable 1 Enab PS029902-0212 R/W Initial value : 00H le PRELIMINARY 72 Z51F3220 Product Specification 9.9 Port Function 9.9.1 Port Function Description Port function control registers consist of Port function selection register 0 ~ 5. (P0FSRH/L ~ P5FSR). 9.9.2 Register description for P0FSRH/L ~ P5FSR P0FSRH (Port 0 Function Selection High Register) : D3H 7 6 5 4 3 2 1 0 – – P0FSRH5 P0FSRH4 P0FSRH3 P0FSRH2 P0FSRH1 P0FSRH0 – – R/W R/W R/W R/W R/W P0FSRH[5:4] R/W Initial value : 00H P07 Function Select P0FSRH5 P0 FSRH4 De scription I/OPort (EI NT5 function p ossible when input) 00 0 1 SE G22 Function 1 0 AN5 11 P0FSRH[3:2] Function PWM 4CB Function P06 Function Select P0FSRH3 P0 FSRH2 De scription I/OPort (EI NT4 function p ossible when input) 00 0 1 SE G23 Function 1 0 AN4 11 P0FSRH[1:0] Function PWM 4CA Function P05 Function Select P0FSRH1 P0 FSRH0 De scription I/OPort (EI NT3 function p ossible when input) 00 0 1 SE G24 Function 1 0 AN3 11 PS029902-0212 Function PWM PRELIMINARY 4BB Function 73 Z51F3220 Product Specification P0FSRL (Port 0 Function Selection Low Register) : D2H 7 6 5 4 3 2 1 0 – P0FSRL6 P0FSRL5 P0FSRL4 P0FSRL3 P0FSRL2 P0FSRL1 P0FSRL0 – R/W R/W R/W R/W R/W R/W P0FSRL[6:5] R/W Initial value : 00H P04 Function Select P0FSRL6 P0F SRL5 De scription I/OPort (EI NT2 function p ossible when input) 00 0 1 SE G25 Function 1 0 AN2 11 P0FSRL[4:3] Function PWM 4BA Function P03 Function Select P0FSRL4 P0F SRL3 De scription I/OPort (EI NT1 function p ossible when input) 00 0 1 SE G26 Function 1 0 AN1 11 P0FSRL[2:1] Function PWM 4AB Function P02 Function Select P0FSRL2 P0F SRL1 De scription I/OPort (EI NT0 function p ossible when input) 00 0 1 AV REF Function 1 0 AN0 Function 11T P0FSRL0 PS029902-0212 4O/PWM4A Function P01 Function Select 0 I/ OPort 1T 3O Function PRELIMINARY 74 Z51F3220 Product Specification P1FSRH (Port 1 Function Selection High Register) : D5H 7 6 5 4 3 2 1 0 P1FSRH7 P1FSRH6 P1FSRH5 P1FSRH4 P1FSRH3 P1FSRH2 P1FSRH1 P1FSRH0 R/W R/W R/W R/W R/W R/W R/W P1FSRH[7:6] R/W Initial value : 00H P17 Function Select P1FSRH7 P1F SRH6 De scription I/OPort (EINT6/SS2 function possible when input) 00 0 1 SE G21 Function 1 0 AN6 Function 1 1 Not P1FSRH[5:4] used P16 Function Select P1FSRH5 P1F SRH4 De scription I/OPort (EI NT7 function p ossible when input) 00 0 1 SE G20 Function 1 0 AN7 Function 1 1 SCK2 P1FSRH[3:2] Function P15 Function Select P1FSRH3 P1F SRH2 De scription 0 0 I/ OPort 0 1 SE G19 Function 1 0 AN8 Function 11M P1FSRH[1:0] ISO2 Function P14 Function Select P1FSRH1 P0F SRH0 De scription 0 0 I/ OPort 0 1 SE PS029902-0212 G18 Function 1 0 AN9 Function 1 1 MO SI2 Function PRELIMINARY 75 Z51F3220 Product Specification P1FSRL (Port 1 Function Selection Low Register) : D4H 7 6 5 4 3 2 1 0 P1FSRL7 P1FSRL6 P1FSRL5 P1FSRL4 P1FSRL3 P1FSRL2 P1FSRL1 P1FSRL0 R/W R/W R/W R/W R/W R/W R/W P1FSRL[7:6] R/W Initial value : 00H P13 Function Select P1FSRL7 P1 FSRL6 De scription 0 0 I/OPort (EC1 function possible when input) 0 1 SE P1FSRL[5:4] G17 Function 1 0 AN10 Function 1 1 BUZO Function P12Function Select P1FSRL5 P1 FSRL4 De scription I/OPort (EINT11 function possible when input) 00 0 1 SE G16 Function 1 0 AN11 Function 11T P1FSRL[3:2] 1O/PWM1O Function P11 Function Select P1FSRL3 P1 FSRL2 De scription I/OPort (EINT12 function possible when input) 00 0 1 SE G15 Function 1 0 AN12 Function 11T P1FSRL[1:0] 2O/PWM2O Function P10 Function Select P1FSRL1 P1F SRL0 De scription 0 0 I/ OPort 0 1 SE PS029902-0212 G14 Function 1 0 AN13 Function 1 1 RXD1 /SCL1/MISO1 Function PRELIMINARY 76 Z51F3220 Product Specification P2FSRH (Port 2 Function Selection High Register) : D7H 7 6 5 4 3 2 1 0 – – – – P2FSRH3 P2FSRH2 P2FSRH1 P2FSRH0 – – – – R/W R/W R/W P2FSRH3 P27 Function select 0 I/ OPort 1 SEG P2FSRH2 OPort 1 SEG7 Function P25 Function select 0 I/ OPort 1 SEG P2FSRH0 8 Function P24 Function Select 0 I/ 1 PS029902-0212 6 Function P26 Function Select 0 I/ P2FSRH1 R/W Initial value : 00H OPort SEG9 Function PRELIMINARY 77 Z51F3220 Product Specification P2FSRL (Port 2 Function Selection Low Register) : D6H 7 6 5 4 3 2 1 0 – – P2FSRL5 P2FSRL4 P2FSRL3 P2FSRL2 P2FSRL1 P2FSRL0 – – R/W R/W R/W R/W R/W P2FSRL5 P23 Function Select 0 I/ OPort 1 SE P2FSRL4 G10 Function P22Function Select 0 I/OPort (SS1 function possible when input) 1 SE P2FSRL[3:2] R/W Initial value : 00H G11 Function P21 Function Select P2FSRL3 P2F SRL2 De scription 0 0 I/ OPort 0 1 SE P2FSRL[1:0] G12 Function 1 0 AN15 Function 1 1 SCK1 Function P20 Function Select P2FSRL1 P1F SRL0 De scription 0 0 I/ OPort 0 1 SE 1 0 AN14 11T PS029902-0212 PRELIMINARY G13 Function Function XD1/SDA1/MOSI1 Function 78 Z51F3220 Product Specification P3FSR (Port 3 Function Selection Register) : EEH 7 6 5 4 3 2 1 0 P3FSR7 P3FSR6 P3FSR5 P3FSR4 P3FSR3 P3FSR2 P3FSR1 P3FSR0 R/W R/W R/W R/W R/W R/W R/W P3FSR7 P37 Function select 0 I/ OPort 1 CO P3FSR6 OPort 1 COM1 Function P35 Function select 0 I/ OPort 1 CO P3FSR4 1 1 1 OPort COM5/SEG3 or COM1 Function P31 Function select 0 I/ 1 P3FSR0 OPort COM4/SEG2 or COM0 Function P32 Function Select 0 I/ P3FSR1 OPort COM3/SEG1 Function P33 Function select 0 I/ P3FSR2 M2/SEG0 Function P34 Function Select 0 I/ P3FSR3 M0 Function P36 Function Select 0 I/ P3FSR5 R/W Initial value : 00H OPort COM6/SEG4 or COM2/SEG4 Function P30 Function Select 0 I/ 1 OPort COM7/SEG5 or COM3/SEG5 Function NOTES) 1. The P30-P35 is automatically configured as common or segment signal according to the duty in the LCDCRL register when the pin is selected as the sub-function for common/segment. 2. The COM0-COM3 signals can be outputted through the P33-P30 pins. Refer to the LCD drive control high register (LCDCRH). . PS029902-0212 PRELIMINARY 79 Z51F3220 Product Specification P4FSR (Port 4 Function Selection Register) : EFH 7 6 5 4 3 2 1 0 – P4FSR6 P4FSR5 P4FSR4 P4FSR3 P4FSR2 P4FSR1 P4FSR0 – R/W R/W R/W R/W R/W R/W P4FSR6 P43 Function Select 0 I/OPort (SS0 function possible when input) 1 VLC0 P4FSR[5:4] R/W Initial value : 00H Function P42 Function Select P4FSR5 P4FSR 4 Description 0 0 I/ 0 1 VL OPort C1 Function 1 0 SCK0 1 1 Not P4FSR[3:2] Function used P41 Function Select P4FSR3 P4FSR 2 Description 0 0 I/ 0 1 VL 10T 1 1 Not P4FSR6[1:0] OPort C2 Function XD0/SDA0/MOSI0 Function used P40 Function Select P4FSR1 P4FSR 0 Description 0 0 I/ 0 1 VL OPort C3 Function 1 0 RXD0 1 1 Not PS029902-0212 /SCL0/MISO0 Function used PRELIMINARY 80 Z51F3220 Product Specification P5FSR (Port 5 Function Selection Register) : FFH 7 6 5 4 3 2 1 0 – – P5FSR5 P5FSR4 P5FSR3 P5FSR2 P5FSR1 P5FSR0 – – R/W R/W R/W R/W R/W P5FSR5 P54 Function Select 0 I/OPort (EINT10 function possible when input) 1 SXO P5FSR[4:3] R/W Initial value : 00H UT Function P53 Function Select P5FSR4 P5FSR 3 Description 0 0 I/ 0 1 SX 10T 1 1 Not P5FSR2 IN Function 0O/PWM0O Function used P51 Function Select 1 0 I/ 1 1 XIN P5FSR[1:0] OPort OPort Function P50 Function Select P5FSR1 P5FSR 0 Description 0 0 I/ 0 1 XO OPort UT Function 1 0 Not used 1 1 Not used NOTE) Refer to the configure option for the P55/RESETB. PS029902-0212 PRELIMINARY 81 Z51F3220 Product Specification 10. Interrupt Controller 10.1 Overview The Z51F3220 supports up to 23 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. They can also have four levels of priority assigned to them. The nonmaskable interrupt source is always enabled with a higher priority than any other interrupt source, and is not controllable by software. The interrupt controller has following features: - Receive the request from 23 interrupt source - 6 group priority - 4 priority levels - Multi Interrupt possibility - If the requests of different priority levels are received simultaneously, the request of higher priority level is served first. - Each interrupt source can be controlled by EA bit and each IEx bit - Interrupt latency: 3~9 machine cycles in single interrupt system The non-maskable interrupt is always enabled. The maskable interrupts are enabled through four pair of interrupt enable registers (IE, IE1, IE2, IE3). Each bit of IE, IE1, IE2, IE3 register individually enables/disables the corresponding interrupt source. Overall control is provided by bit 7 of IE (EA). When EA is set to ‘0’, all interrupts are disabled: when EA is set to ‘1’, interrupts are individually enabled or disabled through the other bits of the interrupt enable registers. The EA bit is always cleared to ‘0’ jumping to an interrupt service vector and set to ‘1’ executing the [RETI] instruction. The Z51F3220 supports a four-level priority scheme. Each maskable interrupt is individually assigned to one of four priority levels according to IP and IP1. Default interrupt mode is level-trigger mode basically, but if needed, it is possible to change to edge-trigger mode. Table 10-1 shows the Interrupt Group Priority Level that is available for sharing interrupt priority. Priority of a group is set by two bits of interrupt priority registers (one bit from IP, another one from IP1). Interrupt service routine serves higher priority interrupt first. If two requests of different priority levels are received simultaneously, the request of higher priority level is served prior to the lower one. Table 10-1 Interrupt Group Priority Level Interrupt Group Highest 0 (Bit0) Interrupt 0 Interrupt 6 Interrupt 12 Interrupt 18 1 (Bit1) Interrupt 1 Interrupt 7 Interrupt 13 Interrupt 19 2 (Bit2) Interrupt 2 Interrupt 8 Interrupt 14 Interrupt 20 3 (Bit3) Interrupt 3 Interrupt 9 Interrupt 15 Interrupt 21 4 (Bit4) Interrupt 4 Interrupt 10 Interrupt 16 Interrupt 22 5 (Bit5) Interrupt 5 Interrupt 11 Interrupt 17 Interrupt 23 PS029902-0212 Lowest PRELIMINARY Highest Lowest 82 Z51F3220 Product Specification 10.2 External Interrupt The external interrupt on INT0, INT1, INT5, INT6 and INT11 pins receive various interrupt request depending on the external interrupt polarity 0 high/low register (EIPOL0H/L) and external interrupt polarity 1 register (EIPOL1) as shown in Figure 10.1. Also each external interrupt source has enable/disable bits. The External interrupt flag 0 register (EIFLAG0) and external interrupt flag 1 register 1 (EIFLAG1) provides the status of external interrupts. EINT8 Pin FLAG8 INT6 Interrupt FLAG10 INT0 Interrupt FLAG11 INT1 Interrupt FLAG12 INT11 Interrupt 2 EINT10 Pin 2 EINT11 Pin 2 EINT12 Pin 2 EIPOL1 FLAG0 EINT0 Pin EINT1 Pin EINT2 Pin EINT3 Pin EINT4 Pin EINT5 Pin EINT6 Pin 2 FLAG1 2 FLAG2 2 FLAG3 2 FLAG4 2 INT5 Interrupt FLAG5 2 FLAG6 FLAG7 EINT7 Pin EIPOL0H, EIPOL0L Figure 10.1 External Interrupt Description PS029902-0212 PRELIMINARY 83 Z51F3220 Product Specification 10.3 Block Diagram EIPOL1 IE EIFLAG1.1 EINT10 FLAG10 EINT11 FLAG11 IP 0 EIFLAG1.2 1 I2C1IFR USI1 I2C IP1 2 USI1 Rx 3 USI1 Tx 4 EIPOL0H/L FLAG0 EIFLAG0.0 EINT1 FLAG1 EIFLAG0.1 EINT2 FLAG2 EIFLAG0.2 EINT3 FLAG3 EIFLAG0.3 EINT4 FLAG4 EIFLAG0.4 EINT5 FLAG5 EIFLAG0.5 EINT6 FLAG6 EIFLAG0.6 FLAG7 EIFLAG0.7 EINT0 EINT7 5 6 7 EIPOL1 8 IE1 9 EIFLAG 1.0 FLAG8 EINT8 USI0 I2C 10 I2C0IFR 11 USI0 Rx 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 USI0 Tx 12 EIFLAG 1.3 FLAG12 EINT12 13 IE2 EIPOL1 Timer 0 overflow 14 T0OVIFR 15 Timer 0 T0IFR Timer 1 T1IFR 16 Timer 2 T2IFR 17 Timer 3 T3IFR Timer 4 18 IE3 ADC 19 ADCIFR 20 SPI2 SPIIFR WT WTIFR 21 WDTIFR 22 WDT BIT BITIFR 23 12 13 14 15 16 17 18 19 20 21 22 23 12 13 14 15 16 17 18 19 20 21 22 23 0 Priority High 1 2 3 4 5 6 7 8 9 10 11 Level 0 Level 1 Level 2 Level 3 Release Stop/Sleep 12 13 EA 14 15 16 17 18 19 20 21 22 23 Priority Low Figure 10.2 Block Diagram of Interrupt NOTES) 1. The release signal for stop/idle mode may be generated by all interrupt sources which are enabled without reference to the priority level. 2. An interrupt request is delayed while data are written to IE, IE1, IE2, IE3, IP, IP1, and PCON register. PS029902-0212 PRELIMINARY 84 Z51F3220 Product Specification 10.4 Interrupt Vector Table The interrupt controller supports 24 interrupt sources as shown in the Table 10-2. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their own priority order. Table 10-2 Interrupt Vector Address Table Interrupt Source Symbol Hardware Reset External Interrupt 10 External Interrupt 11 USI1 I2C Interrupt USI1 Rx Interrupt USI1 Tx Interrupt External Interrupt 0 - 7 External Interrupt 8 USI0 I2C Interrupt USI0 Rx Interrupt USI0 Tx Interrupt External Interrupt 12 T0 Overflow Interrupt T0 Match Interrupt T1 Match Interrupt T2 Match Interrupt T3 Match Interrupt T4 Interrupt ADC Interrupt SPI 2 Interrupt WT Interrupt WDT Interrupt BIT Interrupt - RESETB INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT8 INT9 INT10 INT11 INT12 INT13 INT14 INT15 INT16 INT17 INT18 INT19 INT20 INT21 INT22 INT23 Interrupt Enable Bit 0 0 IE.0 IE.1 IE.2 IE.3 IE.4 IE.5 IE1.0 IE1.1 IE1.2 IE1.3 IE1.4 IE1.5 IE2.0 IE2.1 IE2.2 IE2.3 IE2.4 IE2.5 IE3.0 IE3.1 IE3.2 IE3.3 IE3.4 IE3.5 Polarity Mask Vector Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Non-Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable Maskable 0000H 0003H 000BH 0013H 001BH 0023H 002BH 0033H 003BH 0043H 004BH 0053H 005BH 0063H 006BH 0073H 007BH 0083H 008BH 0093H 009BH 00A3H 00ABH 00B3H 00BBH For maskable interrupt execution, EA bit must set ‘1’ and specific interrupt must be enabled by writing ‘1’ to associated bit in the IEx. If an interrupt request is received, the specific interrupt request flag is set to ‘1’. And it remains ‘1’ until CPU accepts interrupt. If the interrupt is served, the interrupt request flag will be cleared automatically. 10.5 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the PC at stack. For the interrupt service routine, the interrupt controller gives the address of LJMP instruction to CPU. Since the end of the execution of current instruction, it needs 3~9 machine cycles to go to the interrupt service routine. The interrupt service task is terminated by the interrupt return instruction [RETI]. Once an interrupt request is generated, the following process is performed. PS029902-0212 PRELIMINARY 85 Z51F3220 Product Specification 1 IE.EA Flag  0 2 Program Counter low Byte SP  SP + 1 M(SP)  (PCL) Saves PC value in order to continue process again after executing ISR 3 Program Counter high Byte SP  SP + 1 M(SP)  (PCH) 4 Interrupt Vector Address occurrence (Interrupt Vector Address) 5 ISR(Interrupt Service Routine) move, execute 6 Return from ISR RETI 7 Program Counter high Byte recovery (PCH)  (SP-1) 8 Program Counter low Byte recovery (PCL)  (SP-1) 9 IE.EA Flag  1 10 Main Program execution Figure 10.3 Interrupt Vector Address Table PS029902-0212 PRELIMINARY 86 Z51F3220 Product Specification 10.6 Effective Timing after Controlling Interrupt Bit Case a) Control Interrupt Enable Register (IE, IE1, IE2, IE3) Interrupt Enable Register command After executing IE set/clear, enable register is effective. Next Instruction Next Instruction Figure 10.4 Effective Timing of Interrupt Enable Register Case b) Interrupt flag Register Interrupt Flag Register Command Next Instruction After executing next instruction, interrupt flag result is effective. Next Instruction Figure 10.5 Effective Timing of Interrupt Flag Register PS029902-0212 PRELIMINARY 87 Z51F3220 Product Specification 10.7 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is served first. If more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware. However, for special features, multi-interrupt processing can be executed by software. Main Program Service INT1 ISR INT0 ISR Occur INT1 Interrupt Occur INT0 Interrupt RETI RETI Figure 10.6 Effective Timing of Interrupt Figure 10.6 shows an example of multi-interrupt processing. While INT1 is served, INT0 which has higher priority than INT1 is occurred. Then INT0 is served immediately and then the remain part of INT1 service routine is executed. If the priority level of INT0 is same or lower than INT1, INT0 will be served after the INT1 service has completed. An interrupt service routine may be only interrupted by an interrupt of higher priority and, if two interrupts of different priority occur at the same time, the higher level interrupt will be served first. An interrupt cannot be interrupted by another interrupt of the same or a lower priority level. If two interrupts of the same priority level occur simultaneously, the service order for those interrupts is determined by the scan order. PS029902-0212 PRELIMINARY 88 Z51F3220 Product Specification 10.8 Interrupt Enable Accept Timing Max. 4 Machine Cycle 4 Machine Cycle System Clock Interrupt goes Active Interrupt Latched Interrupt Processing : LCALL & LJMP Interrupt Routine Figure 10.7 Interrupt Response Timing Diagram 10.9 Interrupt Service Routine Address Basic Interval Timer Vector Table Address Basic Interval Timer Service Routine Address 00B3H 01H 0125H 0EH 00B4H 25H 0126H 2EH Figure 10.8 Correspondence between Vector Table Address and the Entry Address of ISP 10.10 Saving/Restore General-Purpose Registers INTxx : PUSH PUSH PUSH PUSH PUSH · · PSW DPL DPH B ACC Main Task Interrupt Service Task Saving Register Interrupt_Processing: ∙ ∙ POP POP POP POP POP RETI Restoring Register ACC B DPH DPL PSW Figure 10.9 Saving/Restore Process Diagram and Sample Source PS029902-0212 PRELIMINARY 89 Z51F3220 Product Specification 10.11 Interrupt Timing Interrupt sampled here CLP2 CLP1 CLP2 C1P1 C1P2 C2P1 C2P2 SCLK INT_SRC INTR_ACK LAST_CYC INTR_LCALL 8-Bit interrupt Vector INT_VEC {8’h00, INT_VEC} PROGA Figure 10.10 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction Interrupt sources are sampled at the last cycle of a command. If an interrupt source is detected the lower 8-bit of interrupt vector (INT_VEC) is decided. M8051W core makes interrupt acknowledge at the first cycle of a command, and executes long call to jump to interrupt service routine. st st NOTE) command cycle CLPx: L=Last cycle, 1=1 cycle or 1 phase, 2=2 nd cycle or 2 nd phase 10.12 Interrupt Register Overview 10.12.1 Interrupt Enable Register (IE, IE1, IE2, IE3) Interrupt enable register consists of global interrupt control bit (EA) and peripheral interrupt control bits. Total 24 peripherals are able to control interrupt. 10.12.2 Interrupt Priority Register (IP, IP1) The 24 interrupts are divided into 6 groups which have each 4 interrupt sources. A group can be assigned 4 levels interrupt priority using interrupt priority register. Level 3 is the highest priority, while level 0 is the lowest priority. After a reset IP and IP1 are cleared to ‘00H’. If interrupts have the same priority level, lower number interrupt is served first. PS029902-0212 PRELIMINARY 90 Z51F3220 Product Specification 10.12.3 External Interrupt Flag Register (EIFLAG0, EIFLAG1) The external interrupt flag 0 register (EIFLAG0) and external interrupt flag 1 register (EIFLAG1) are set to ‘1’ when the external interrupt generating condition is satisfied. The flag is cleared when the interrupt service routine is executed. Alternatively, the flag can be cleared by writing ‘0’ to it. 10.12.4 External Interrupt Polarity Register (EIPOL0L, EIPOL0H, EIPOL1) The external interrupt polarity 0 high/low register (EIPOL0H/L) and external interrupt polarity 1 register (EIPOL1) determines which type of rising/falling/both edge interrupt. Initially, default value is no interrupt at any edge. PS029902-0212 PRELIMINARY 91 Z51F3220 Product Specification 10.12.5 Register Map Table 10-3 Interrupt Register Map Name IE Address Dir Default Description A8H R/W 00H Interrupt Enable Register IE1 A9H R/W 00H Interrupt Enable Register 1 IE2 AAH R/W 00H Interrupt Enable Register 2 IE3 ABH R/W 00H Interrupt Enable Register 3 R/W 00H Interrupt Polarity Register 8H R/W 00H Interrupt Polarity Register 1 C0H R/W 00H External Interrupt Flag 0 Register IP B8H IP1 F EIFLAG0 EIPOL0L A4H R/W 00H External Interrupt Polarity 0 Low Register EIPOL0H A5H R/W 00H External Interrupt Polarity 0 High Register EIFLAG1 A6H R/W 00H External Interrupt Flag 1 Register EIPOL1 A7H R/W 00H External Interrupt Polarity 1 Register 10.13 Interrupt Register Description The interrupt r egister is us ed for controlling interrupt functions. A lso i t has e xternal interrupt c ontrol r egisters. The interrupt register consists of interrupt enable register (IE), interrupt enable register 1 (IE1), interrupt enable register 2 (IE2) and interrupt enable register 3 (IE3). For external interrupt, it consists of external interrupt flag 0 register (E IFLAG0), external interrupt polarity 0 high/low register (E IPOL0H/L), e xternal interrupt fla g 1 register (EIFLAG1) and external interrupt polarity 1 register (EIPOL1). PS029902-0212 PRELIMINARY 92 Z51F3220 Product Specification 10.13.1 Register Description for Interrupt IE (Interrupt Enable Register) : A8H 7 6 5 4 3 2 1 0 EA – INT5E INT4E INT3E INT2E INT1E INT0E R/W – R/W R/W R/W R/W R/W EA INT5E Enable or Disable All Interrupt bits 0 All Interrupt disable 1 All Interrupt enable Enable or Disable External Interrupt 0 ~ 7 (EINT0 ~ EINT7) 0D isable 1 Enab INT4E isable 1 Enab isable 1 Enab isable 1 Enab isable 1 Enab le Enable or Disable External Interrupt 10 (EINT10) 0D isable 1 Enab PS029902-0212 le Enable or Disable External Interrupt 11(EINT11) 0D INT0E le Enable or Disable USI1 I2C Interrupt 0D INT1E le Enable or Disable USI1 Rx Interrupt 0D INT2E le Enable or Disable USI1 Tx Interrupt 0D INT3E R/W Initial value : 00H le PRELIMINARY 93 Z51F3220 Product Specification IE1 (Interrupt Enable Register 1): A9H 7 6 5 4 3 2 1 0 – – INT11E INT10E INT9E INT8E – INT6E – – R/W R/W R/W R/W – INT11E Enable or Disable External Interrupt 12 (EINT12) 0D isable 1 Enab INT10E isable 1 Enab isable 1 Enab isable 1 Enab le Enable or Disable External Interrupt 8 (EINT8) 0D isable 1 Enab PS029902-0212 le Enable or Disable USI0 I2C Interrupt 0D INT6E le Enable or Disable USI0 Rx Interrupt 0D INT8E le Enable or Disable USI0 Tx Interrupt 0D INT9E R/W Initial value: 00H le PRELIMINARY 94 Z51F3220 Product Specification IE2 (Interrupt Enable Register 2) : AAH 7 6 5 4 3 2 1 0 –- – INT17E INT16E INT15E INT14E INT13E INT12E – – R/W R/W R/W R/W R/W R/W Initial value : 00H Enable or Disable Timer 4 Interrupt INT17E 0D isable 1 Enab le Enable or Disable Timer 3 Match Interrupt INT16E 0D isable 1 Enab le Enable or Disable Timer 2 Match Interrupt INT15E 0D isable 1 Enab le Enable or Disable Timer 1 Match Interrupt INT14E 0D isable 1 Enab le Enable or Disable Timer 0 I Match nterrupt INT13E 0D isable 1 Enab le Enable or Disable Timer 0 Overflow Interrupt INT12E 0D isable 1 Enab le IE3 (Interrupt Enable Register 3) : ABH 7 6 5 4 3 2 1 0 – – – INT22E INT21E INT20E INT19E INT18E – – – R/W R/W R/W R/W INT22E Enable or Disable BIT Interrupt 0D isable 1 Enab INT21E isable 1 Enab isable 1 Enab isable 1 Enab le Enable or Disable ADC Interrupt 0D isable 1 Enab PS029902-0212 le Enable or Disable SPI 2 Interrupt 0D INT18E le Enable or Disable WT Interrupt 0D INT19E le Enable or Disable WDT Interrupt 0D INT20E R/W Initial value : 00H le PRELIMINARY 95 Z51F3220 Product Specification IP (Interrupt Priority Register) : B8H 7 6 5 4 3 2 1 0 – – IP5 IP4 IP3 IP2 IP1 IP0 – – R/W R/W R/W R/W R/W R/W Initial value : 00H IP1 (Interrupt Priority Register 1) : F8H 7 6 5 4 3 2 1 0 – – IP15 IP14 IP13 IP12 IP11 IP10 – – R/W R/W R/W R/W R/W IP[5:0], IP1[5:0] PS029902-0212 R/W Initial value : 00H Select Interrupt Group Priority IP1x I Px Description 00 level 0 (lowest) 01 level 1 10 level 2 11 level 3 (highest) PRELIMINARY 96 Z51F3220 Product Specification EIFLAG0 (External Interrupt Flag 0 Register) : C0H 7 6 5 4 3 2 1 0 FLAG7 FLAG6 FLAG5 FLAG4 FLAG3 FLAG2 FLAG1 FLAG0 R/W R/W R/W R/W R/W R/W R/W EIFLAG0[7:0] R/W Initial value : 00H When an E xternal Interrupt 0-7 is occ urred, the flag be comes ‘ 1’. The flag is cleared only by writing ‘0’ to the bit. So, the flag should be cleared by software. 0 External Interrupt 0 ~ 7 not occurred 1 External Interrupt 0 ~ 7 occurred EIPOL0H (External Interrupt Polarity 0 High Register): A5H 7 6 5 R/W R/W POL7 R/W 4 3 R/W R/W POL6 EIPOL0H[7:0] 2 1 R/W R/W POL5 0 POL4 R/W Initial value: 00H External interrupt (EINT7, EINT6, EINT5, EINT4) polarity selection POLn[1:0] De scription 0 0 No interrupt at any edge 0 1 Interrupt on rising edge 1 0 Interrupt on falling edge 1 1 Interrupt on both of rising and falling edge Where n =4, 5, 6 and 7 EIPOL0L (External Interrupt Polarity 0 Low Register): A4H 7 6 5 POL3 R/W 4 3 POL2 R/W R/W EIPOL0L[7:0] 2 1 POL1 R/W R/W 0 POL0 R/W R/W R/W Initial value: 00H External interrupt (EINT0, EINT1, EINT2, EINT3) polarity selection POLn[1:0] De scription 0 0 No interrupt at any edge 0 1 Interrupt on rising edge 1 0 Interrupt on falling edge 1 1 Interrupt on both of rising and falling edge Where n =0, 1, 2 and 3 PS029902-0212 PRELIMINARY 97 Z51F3220 Product Specification EIFLAG1 (External Interrupt Flag 1 Register) : A6H 7 6 5 4 3 2 1 0 T0OVIFR T0IFR T3IFR – FLAG12 FLAG11 FLAG10 FLAG8 R/W R/W R/W – R/W R/W R/W R/W Initial value : 00H When T0 overflow interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or automatically clear by INT_ACK signal. T0OVIFR 0 T0 overflow Interrupt no generation 1 T0 overflow Interrupt generation When T0 interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or automatically clear by INT_ACK signal. T0IFR 0 T0 Interrupt no generation 1 T0 Interrupt generation When T3 interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or automatically clear by INT_ACK signal. T3IFR EIFLAG1[3:0] 0 T3 Interrupt no generation 1 T3 Interrupt generation When a n E xternal Interrupt ( EINT8, E INT10-EINT12) is occurred, the f lag becomes ‘1’. The flag is cleared b y writing ‘0’ t o the bit or automatically cleared by INT_ACK signal. 0 External Interrupt not occurred 1 External Interrupt occurred EIPOL1 (External Interrupt Polarity 1 Register): A7H 7 6 5 POL12 R/W 4 3 POL11 R/W R/W EIPOL1[7:0] 2 1 POL10 R/W R/W 0 POL8 R/W R/W R/W Initial value: 00H External interrupt (EINT8,EINT10,EINT11,EINT12) polarity selection POLn[1:0] De scription 0 0 No interrupt at any edge 0 1 Interrupt on rising edge 1 0 Interrupt on falling edge 1 1 Interrupt on both of rising and falling edge Where n =8, 10, 11 and 12 PS029902-0212 PRELIMINARY 98 Z51F3220 Product Specification 11. Peripheral Hardware 11.1 Clock Generator 11.1.1 Overview As shown in Figure 11.1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains main/sub-frequency clock oscillator. The main/sub clock operation can be easily obtained by attaching a crystal between the XIN/SXIN and XOUT/SXOUT pin, respectively. The main/sub clock can be also obtained from the external oscillator. In this case, it is necessary to put the external clock signal into the XIN/SXIN pin and open the XOUT/SXOUT pin. The default system clock is 1MHz INT-RC Oscillator and the default division rate is eight. In order to stabilize system internally, it is used 1MHz INT-RC oscillator on POR. - Calibrated Internal RC Oscillator (16 MHz ) . INT-RC OSC/1 (16 MHz) . INT-RC OSC/2 (8 MHz) . INT-RC OSC/4 (4 MHz) . INT-RC OSC/8 (2 MHz) . INT-RC OSC/16 (1 MHz, Default system clock) . INT-RC OSC/32 (0.5 MHz) - Main Crystal Oscillator (0.4~12 MHz) - Sub Crystal Oscillator (32.768 kHz) - Internal WDTRC Oscillator (5 kHz) 11.1.2 Block Diagram XIN XOUT f XIN Main OSC STOP M ode XCLKE IRCS[2:0] DCLK 3 Internal RC OSC (16MHz) 1 /1 1 /2 1 /4 1 /8 1/16 1/32 M fIRC U X SXIN STOP M ode SCLKE Stabilization Time Generation BITCK[1:0 ] 2 fx/4096 fx/1024 fx/128 fx/16 f SUB Sub OSC SCLK (f x) (Core, System, Peripheral ) Clock Change STOP M ode IRCE SXOUT System Clock Gen. M BIT clock U X BIT overflow BIT M U X 2 WT SCLK[1:0] WDTRC OSC (5kHz) WDT clock WDT /256 WDTCK Figure 11.1 Clock Generator Block Diagram PS029902-0212 PRELIMINARY 99 Z51F3220 Product Specification 11.1.3 Register Map Table 11-1 Clock Generator Register Map Name SCCR OSCCR C8 Address Dir Default Description 8AH R/W 00H System and Clock Control Register H R/W 20H Oscillator Control Register 11.1.4 Clock Generator Register Description The clock generator register uses clock control for system operation. The clock generation consists of System and clock control register and oscillator control register. 11.1.5 Register Description for Clock Generator SCCR (System and Clock Control Register) : 8AH 7 6 5 4 3 2 1 0 – – – – – – SCLK1 SCLK0 – – – – – – R/W SCLK [1:0] R/W Initial value : 00H System Clock Selection Bit SCLK1 SC LK0 Description 00 1 External Main OSC (fXIN) for system clock 1 0 External Sub OSC (fSUB) for system clock 11 PS029902-0212 INT RC OSC (fIRC) for system clock 0 Not used PRELIMINARY 100 Z51F3220 Product Specification OSCCR (Oscillator Control Register) : C8H 7 6 5 4 3 2 1 0 – – IRCS2 IRCS1 IRCS0 IRCE XCLKE SCLKE – – R/W R/W R/W R/W R/W IRCS[2:0] Internal RC Oscillator Post-divider Selection IRCS2 I RCS1 IRCS0 Description 00 0 INT-RC/32 (0.5MHz) 00 1 INT-RC/16 (1MHz) 01 0 INT-RC/8 (2MHz) 01 1 INT-RC/4 (4MHz) 10 0 INT-RC/2 (8MHz) 10 1 Other values IRCE XCLKE SCLKE PS029902-0212 R/W Initial value : 08H INT-RC/1 (16MHz) Not used Control the Operation of the Internal RC Oscillator 0 Enable operation of INT-RC OSC 1 Disable operation of INT-RC OSC Control the Operation of the External Main Oscillator 0 Disable operation of X-TAL 1 Enable operation of X-TAL Control the Operation of the External Sub Oscillator 0 Disable operation of SX-TAL 1 Enable operation of SX-TAL PRELIMINARY 101 Z51F3220 Product Specification 11.2 Basic Interval Timer 11.2.1 Overview The Z51F3220 has one 8-bit basic interval timer that is free-run and can’t stop. Block diagram is shown in Figure 11.2. In addition, the basic interval timer generates the time base for watchdog timer counting. It also provides a basic interval timer interrupt (BITIFR). The Z51F3220 has these basic interval timer (BIT) features: - During Power On, BIT gives a stable clock generation time - On exiting Stop mode, BIT gives a stable clock generation time - As timer function, timer interrupt occurrence 11.2.2 Block Diagram BCK[2 :0] Start C PU BIT C lock selected bit overflow 8 -Bit U p C ounter BITCNT BCLR To interrupt block clear clear RESET STOP BITIFR WDT INT_ ACK Figure 11.2 Basic Interval Timer Block Diagram PS029902-0212 PRELIMINARY 102 Z51F3220 Product Specification 11.2.3 Register Map Table 11-2 Basic Interval Timer Register Map Name Address Dir BITCNT 8CH BITCR 8BH Default Description R 00H Basic Interval Timer Counter Register R/W 01H Basic Interval Timer Control Register 11.2.4 Basic Interval Timer Register Description The basic interval timer register consists of basic interval timer counter register (BITCNT) and basic interval timer control register (BITCR). If BCLR bit is set to ‘1’, BITCNT becomes ‘0’ and then counts up. After 1 machine cycle, BCLR bit is cleared to ‘0’ automatically. 11.2.5 Register Description for Basic Interval Timer BITCNT (Basic Interval Timer Counter Register) : 8CH 7 6 5 4 3 2 1 0 BITCNT7 BITCNT6 BITCNT5 BITCNT4 BITCNT3 BITCNT2 BITCNT1 BITCNT0 R R R R R R R BITCNT[7:0] PS029902-0212 R Initial value : 00H BIT Counter PRELIMINARY 103 Z51F3220 Product Specification BITCR (Basic Interval Timer Control Register) : 8BH 7 6 5 4 3 2 1 0 BITIFR BITCK1 BITCK0 – BCLR BCK2 BCK1 BCK0 R/W R/W R/W – R/W R/W R/W BITIFR BITCK[1:0] R/W Initial value : 01H When BIT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 BIT interrupt no generation 1 BIT interrupt generation Select BIT clock source BITCK1 BIT CK0 De scription BCLR 00 fx/4096 01 fx/1024 10 fx/128 11 fx/16 If this bit is written to ‘1’, BIT Counter is cleared to ‘0’ 0 Free Running 1 Clear BCK[2:0] PS029902-0212 Counter Select BIT overflow period BCK2 BCK1 BCK0 Description 0 0 0 Bit 0 overflow (BIT Clock * 2) 0 0 1 Bit 1 overflow (BIT Clock * 4) (default) 0 1 0 Bit 2 overflow (BIT Clock * 8) 0 1 1 Bit 3 overflow (BIT Clock * 16) 1 0 0 Bit 4 overflow (BIT Clock * 32) 1 0 1 Bit 5 overflow (BIT Clock * 64) 1 1 0 Bit 6 overflow (BIT Clock * 128) 1 1 1 Bit 7 overflow (BIT Clock * 256) PRELIMINARY 104 Z51F3220 Product Specification 11.3 Watch Dog Timer 11.3.1 Overview The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or something like that, and resumes the CPU to the normal state. The watchdog timer signal for malfunction detection can be used as either a CPU reset or an interrupt request. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. It is possible to use free running 8bit timer mode (WDTRSON=’0’) or watch dog timer mode (WDTRSON=’1’) as setting WDTCR[6] bit. If WDTCR[5] is written to ‘1’, WDT counter value is cleared and counts up. After 1 machine cycle, this bit is cleared to ‘0’ automatically. The watchdog timer consists of 8-bit binary counter and the watchdog timer data register. When the value of 8-bit binary counter is equal to the 8 bits of WDTCNT, the interrupt request flag is generated. This can be used as Watchdog timer interrupt or reset of CPU in accordance with the bit WDTRSON. The input clock source of watch dog timer is the BIT overflow. The interval of watchdog timer interrupt is decided by BIT overflow period and WDTDR set value. The equation can be described as WDT Interrupt Interval = (BIT Interrupt Interval) X (WDTDR Value+1) 11.3.2 WDT Interrupt Timing Waveform Source Clock BIT Overflow WDTCNT[7:0] 0 1 2 3 0 1 2 3 0 1 2 Counter Clear WDTDR[7:0] n 3 WDTCL Occur WDTIFR Interrupt WDTDR  0000_0011b WDTRESETB Match Detect RESET Figure 11.3 Watch Dog Timer Interrupt Timing Waveform PS029902-0212 PRELIMINARY 105 Z51F3220 Product Specification 11.3.3 Block Diagram WDT Clock WDTCNT clear To RESET Circuit WDTEN WDTIFR To interrupt block clear WDTDR WDTCL WDTRSON INT_ACK WDTCR Figure 11.4 Watch Dog Timer Block Diagram 11.3.4 Register Map Table 11-3 Watch Dog Timer Register Map Name Address WDTCNT 8EH Dir Default Description R 00H Watch Dog Timer Counter Register WDTDR 8EH W FFH Watch Dog Timer Data Register WDTCR 8DH R/W 00H Watch Dog Timer Control Register 11.3.5 Watch Dog Timer Register Description The watch dog timer register consists of watch dog timer counter register (WDTCNT), watch dog timer data register (WDTDR) and watch dog timer control register (WDTCR). PS029902-0212 PRELIMINARY 106 Z51F3220 Product Specification 11.3.6 Register Description for Watch Dog Timer WDTCNT (Watch Dog Timer Counter Register: Read Case) : 8EH 7 6 5 4 3 2 1 0 WDTCNT 7 WDTCNT 6 WDTCNT 5 WDTCNT 4 WDTCNT3 WDTCNT 2 WDTCNT 1 WDTCNT 0 R R R R R R R WDTCNT[7:0] R Initial value : 00H WDT Counter WDTDR (Watch Dog Timer Data Register: Write Case) : 8EH 7 6 5 4 3 2 1 0 WDTDR7 WDTDR 6 WDTDR 5 WDTDR 4 WDTDR 3 WDTDR 2 WDTDR 1 WDTDR 0 W W W W W W W W Initial value : FFH WDTDR[7:0] Set a period WDT Interrupt Interval=(BIT Interrupt Interval) x(WDTDR Value+1) NOTE) Do not write “0” in the WDTDR register. WDTCR (Watch Dog Timer Control Register) : 8DH 7 6 5 4 3 2 1 0 WDTEN WDTRSON WDTCL – – – WDTCK WDTIFR R/W R/W R/W – – – R/W WDTEN Control WDT Operation 0 Di sable 1 Enab WDTRSON WDTCL 0 Free Running 8-bit timer 1 Watch Dog Timer RESET ON Clear WDT Counter 1 WDTIFR PS029902-0212 le Control WDT RESET Operation 0 Free WDTCK R/W Initial value : 00H Run Clear WDT Counter (auto clear after 1 Cycle) Control WDT Clock Selection Bit 0 BIT overflow for WDT clock (WDTRC disable) 1 WDTRC for WDT xlock (WDTRC enable) When WDT I nterrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 WDT Interrupt no generation 1 WDT Interrupt generation PRELIMINARY 107 Z51F3220 Product Specification 11.4 Watch Timer 11.4.1 Overview The watch timer has the function for RTC (Real Time Clock) operation. It is generally used for RTC design. The internal structure of the watch timer consists of the clock source select circuit, timer counter circuit, output select circuit, and watch timer control register. To operate the watch timer, determine the input clock source, output interval, and set WTEN to ‘1’ in watch timer control register (WTCR). It is able to execute simultaneously or individually. To stop or reset WT, clear the WTEN bit in WTCR register. Even if CPU is STOP mode, sub clock is able to be so alive that WT can continue the operation. The watch timer counter circuits may be composed of 21bit counter which contains low 14-bit with binary counter and high 7-bit counter in order to raise resolution. In WTDR, it can control WT clear and set interval value at write time, and it can read 7-bit WT counter value at read time. The watch timer supplies the clock frequency for the LCD driver (fLCD). Therefore, if the watch timer is disabled, the LCD driver controller does not operate. 11.4.2 Block Diagram f S UB fx P r e s c a l e r f LCD =1024 Hz M U X fx/64 fx/128 f WCK 14Bit Binary C ounter Timer c ounter WTCL match fx/256 Match Clear 14 f WCK /2 14 f WCK /(2 X(7 bit WTDR Value +1)) Comparator f WCK /214 13 f WCK /2 7 f WCK /2 WTIFR MUX Clear 2 WTCR WTEN - - To interrupt block INT_ACK WTIFR WTIN1 WTIN0 WTCK1 WTCK0 Reload Match WTCL WTDR Write case WTCL WTCNT Read c ase - WTDR6 WTDR5 WTDR4 WTDR3 WTDR2 WTDR1 WTDR0 WTCNT6 WTCNT5 WTCNT4 WTCNT3 WTCNT2 WTCNT1 WTCNT0 Figure 11.5 Watch Timer Block Diagram PS029902-0212 PRELIMINARY 108 Z51F3220 Product Specification 11.4.3 Register Map Table 11-4 Watch Timer Register Map Name WTCNT Address Dir 89H Default R Description 00H Watch Timer Counter Register WTDR 89H W 7FH Watch Timer Data Register WTCR 96H R/W 00H Watch Timer Control Register 11.4.4 Watch Timer Register Description The watch timer register consists of watch timer counter register (WTCNT), watch timer data register (WTDR), and watch timer control register (WTCR). As WTCR is 6-bit writable/ readable register, WTCR can control the clock source (WTCK[1:0]), interrupt interval (WTIN[1:0]), and function enable/disable (WTEN). Also there is WT interrupt flag bit (WTIFR). 11.4.5 Register Description for Watch Timer WTCNT (Watch Timer Counter Register: Read Case) : 89H 7 6 5 4 3 2 1 0 – WTCNT 6 WTCNT 5 WTCNT 4 WTCNT 3 WTCNT 2 WTCNT 1 WTCNT0 – R R R R R R WTCNT[6:0] R Initial value : 00H WT Counter WTDR (Watch Timer Data Register: Write Case) : 89H 7 6 5 4 3 2 1 0 WTCL WTDR 6 WTDR 5 WTDR 4 WTDR 3 WTDR 2 WTDR 1 WTDR 0 R/W W W W W W W WTCL Clear WT Counter 0 Free 1 WTDR[6:0] W Initial value : 7FH Run Clear WT Counter (auto clear after 1 Cycle) Set WT period WT Interrupt Interval=fwck/(2^14 x(7bit WTDR Value+1)) NOTE) Do not write “0” in the WTDR register. PS029902-0212 PRELIMINARY 109 Z51F3220 Product Specification WTCR (Watch Timer Control Register) : 96H 7 6 5 4 3 2 1 0 WTEN – – WTIFR WTIN1 WTIN0 WTCK1 WTCK0 R/W – – R/W R/W R/W R/W WTEN WTIFR WTIN[1:0] Control Watch Timer 0 Di sable 1 En able When WT In terrupt occurs, this bi t becomes ‘1’. For c learing bi t, write ‘0’ to this bit or automatically clear by INT_ACK signal. 0 WT Interrupt no generation 1 WT Interrupt generation Determine interrupt interval WTIN1 WTI WTCK[1:0] N0 De X scription 00f WCK/2^7 01f WCK/2^13 10f WCK/2^14 11f WCK/(2^14 x (7bit WTDR Value+1)) Determine Source Clock WTCK1 WTCK0 De NOTE) f R/W Initial value : 00H scription 00f SUB 01f X/256 10f X/128 11f X/64 – System clock frequency (Where fx= 4.19MHz) fSUB – Sub clock oscillator frequency (32.768kHz) fWCK – Selected Watch timer clock fLCD – LCD frequency (Where fX= 4.19MHz, WTCK[1:0]=’10’; fLCD= 1024Hz) PS029902-0212 PRELIMINARY 110 Z51F3220 Product Specification 11.5 Timer 0 11.5.1 Overview The 8-bit timer 0 consists of multiplexer, timer 0 counter register, timer 0 data register, timer 0 capture data register and timer 0 control register (T0CNT, T0DR, T0CDR, T0CR). It has three operating modes: - 8-bit timer/counter mode - 8-bit PWM output mode - 8-bi t capture mode The timer/counter 0 can be clocked by an internal or an external clock source (EC0). The clock source is selected by clock selection logic which is controlled by the clock selection bits (T0CK[2:0]). - TIMER 0 clock source: fX/2, 4, 8, 32, 128, 512, 2048 and EC0 In the capture mode, by EINT10, the data is captured into input capture data register (T0CDR). In timer/counter mode, whenever counter value is equal to T0DR, T0O port toggles. Also the timer 0 outputs PWM waveform through PWM0O port in the PWM mode. Table 11-5 Timer 0 Operating Modes T0EN T0 1 PS029902-0212 MS[1:0] 00 T0CK[2:0] Timer 0 XXX 8 Bit Timer/Counter Mode 1 01 XXX 8 Bit PWM Mode 1 1X XXX 8 Bit Capture Mode PRELIMINARY 111 Z51F3220 Product Specification 11.5.2 8-Bit Timer/Counter Mode The 8-bit timer/counter mode is selected by control register as shown in Figure 11.6. The 8-bit timer have counter and data register. The counter register is increased by internal or external clock input. Timer 0 can use the input clock with one of 2, 4, 8, 32, 128, 512 and 2048 prescaler division rates (T0CK[2:0]). When the value of T0CNT and T0DR is identical in timer 0, a match signal is generated and the interrupt of Timer 0 occurs. T0CNT value is automatically cleared by match signal. It can be also cleared by software (T0CC). The external clock (EC0) counts up the timer at the rising edge. If the EC0 is selected as a clock source by T0CK[2:0], EC0 port should be set to the input port by P52IO bit. T0CR T0EN - T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC 1 - 0 0 x x x x ADDRESS : B2 H INITIAL VALUE: 0000 _0000B EC0 fx P r e s c a l e r fx/4 fx/8 fx/32 fx/128 Match signal Clear fx/2 T0 CC 8-bit T imer 0 C ounter M U X INT_ACK T0CNT(8Bit) Clear fx/512 Match T0 EN fx/2048 MUX T0IFR Comparator To interrupt block 2 3 T0DR(8Bit) T0CK[2:0 ] T0MS[1:0] 8-bit T imer 0 D ata R egister T0 O/PWM0O Figure 11.6 8-Bit Timer/Counter Mode for Timer 0 Match with T0DR n T0CNT Value n-1 n-2 Count Pulse Period PCP 6 Up-count 5 4 3 2 1 0 TIME Interrupt Period = PCP x (n+1) Timer 0 (T0IFR) Interrupt Occur Interrupt Occur Interrupt Occur Interrupt Figure 11.7 8-Bit Timer/Counter 0 Example PS029902-0212 PRELIMINARY 112 Z51F3220 Product Specification 11.5.3 8-Bit PWM Mode The timer 0 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, T0O/PWM0O pin outputs up to 8-bit resolution PWM output. This pin should be configured as a PWM output by setting the T0O/PWM0O function by P5FSR[4:3] bits. In the 8-bit timer/counter mode, a match signal is generated when the counter value is identical to the value of T0DR. When the value of T0CNT and T0DR is identical in timer 0, a match signal is generated and the interrupt of timer 0 occurs. In PWM mode, the match signal does not clear the counter. Instead, it runs continuously, overflowing at “FFH”, and then continues incrementing from “00H”. The timer 0 overflow interrupt is generated whenever a counter overflow occurs. T0CNT value is cleared by software (T0CC) bit. T0CR T0EN - T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC 1 - 0 1 x x x x ADDRESS : B2 H INITIAL VALUE: 0000 _0000B INT_ACK Clear To interrupt block T0OVIFR EC0 fx P r e s c a l e r fx/4 fx/8 fx/32 Match signal Clear fx/2 T0 CC 8-bit T imer 0 C ounter M U X INT_ACK T0CNT(8Bit) Clear fx/128 fx/512 Match T0 EN fx/2048 MUX Comparator 3 T0CK[2:0 ] T0IFR To interrupt block 2 T0DR(8Bit) 8-bit T imer 0 D ata R egister T0MS[1:0] T0 O/PWM0O Figure 11.8 8-Bit PWM Mode for Timer 0 PS029902-0212 PRELIMINARY 113 Z51F3220 Product Specification PWM Mode (T0MS = 01b) Set T0EN Timer 0 clock T0CNT XX 00H 01H 02H 4AH FEH FFH 00H T0DR T0 Overflow Interrupt 1. T0DR = 4AH T0PWM T0 Match Interrupt 2. T0DR = 00H T0PWM T0 Match Interrupt 3. T0DR = FFH T0PWM T0 Match Interrupt Figure 11.9 PWM Output Waveforms in PWM Mode for Timer 0 PS029902-0212 PRELIMINARY 114 Z51F3220 Product Specification 11.5.4 8-Bit Capture Mode The timer 0 capture mode is set by T0MS[1:0] as ‘1x’. The clock source can use the internal/external clock. Basically, it has the same function as the 8-bit timer/counter mode and the interrupt occurs when T0CNT is equal to T0DR. T0CNT value is automatically cleared by match signal and it can be also cleared by software (T0CC). This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer. The capture result is loaded into T0CDR. In the timer 0 capture mode, timer 0 output (T0O) waveform is not available. According to EIPOL1 registers setting, the external interrupt EINT10 function is chosen. Of cource, the EINT10 pin must be set to an input port. T0CDR and T0DR are in the same address. In the capture mode, reading operation reads T0CDR, not T0DR and writing operation will update T0DR. T0CR T0EN - T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC 1 - 1 x x x x x ADDRESS : B2 H INITIAL VALUE: 0000 _0000B EC0 P r e s c a l e r fx Match s ignal Clear fx/2 fx/4 fx/32 T0 CC 8-bit T imer 0 C ounter M U X fx/8 INT_ACK T0CNT(8Bit) Clear fx/128 fx/512 Clear Match T0 EN fx/2048 MUX T0IFR To interrupt block Comparator 2 3 T0DR(8Bit) T0CK[2:0 ] T0MS[1:0] 8-bit T imer 0 D ata R egister EIPOL1[1:0] 2 T0CDR(8 Bit) EINT10 INT_ACK 2 Clear T0 MS[1 :0] FLAG10 (EIFLAG 1.0 ) To interrupt block Figure 11.10 8-Bit Capture Mode for Timer 0 PS029902-0212 PRELIMINARY 115 Z51F3220 Product Specification T0CDR Load n T0CNT Value n-1 n-2 Count Pulse Period PCP 6 Up-count 5 4 3 2 1 0 TIME Ext. EINT10 PIN Interrupt Request (FLAG10) Interrupt Interval Period Figure 11.11 Input Capture Mode Operation for Timer 0 FFH FFH XXH T0CNT YYH 00H 00H 00H 00H 00H Interrupt Request (T0IFR) Ext. EINT10 PIN Interrupt Request (FLAG10) Interrupt Interval Period = FFH+01H+FFH +01H+YYH+01H Figure 11.12 Express Timer Overflow in Capture Mode PS029902-0212 PRELIMINARY 116 Z51F3220 Product Specification 11.5.5 Block Diagram INT_ACK Clear EC0 P r e s c a l e r fx To interrupt block T0 OVIFR fx/2 fx/4 8-bit T imer 0 C ounter M U X fx/8 fx/32 fx/128 Clear fx/512 T0CC Match T0 EN fx/2048 Match s ignal Clear T0CNT (8Bit) MUX INT_ACK Clear T0IFR To interrupt block Comparator 2 3 T0DR (8Bit) T0CK[2:0] T0MS[1:0 ] 8-bit T imer 0 D ata R egister EIPOL 1[1 :0] T0O/PWM0O 2 T0 CDR (8Bit) EINT10 INT_ACK 2 Clear T0MS[1 :0] FLAG10 (EIFLAG1.0) To interrupt block Figure 11.13 8-Bit Timer 0 Block Diagram PS029902-0212 PRELIMINARY 117 Z51F3220 Product Specification 11.5.6 Register Map Table 11-6 Timer 0 Register Map Name Address Dir T0CNT B3H Default Description R 00H Timer 0 Counter Register T0DR B4H R/W FFH Timer 0 Data Register T0CDR B4H R 00H Timer 0 Capture Data Register T0CR B2H R/W 00H Timer 0 Control Register 11.5.6.1 Timer/Counter 0 Register Description The timer/counter 0 register consists of timer 0 counter register (T0CNT), timer 0 data register (T0DR), timer 0 capture data register (T0CDR), and timer 0 control register (T0CR). T0IFR and T0OVIFR bits are in the external interrupt flag 1 register (EIFLAG1). 11.5.6.2 Register Description for Timer/Counter 0 T0CNT (Timer 0 Counter Register) : B3H 7 6 5 4 3 2 1 0 T0CNT7 T0CNT6 T0CNT5 T0CNT4 T0CNT3 T0CNT2 T0CNT1 T0CNT0 R R R R R R R T0CNT[7:0] R Initial value : 00H T0 Counter T0DR (Timer 0 Data Register) : B4H 7 6 5 4 3 2 1 0 T0DR7 T0DR6 T0DR5 T0DR4 T0DR3 T0DR2 T0DR1 T0DR0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH T0DR[7:0] T0 Data T0CDR (Timer 0 Capture Data Register: Read Case, Capture mode only) : B4H 7 6 5 4 3 2 1 0 T0CDR7 T0CDR6 T0CDR5 T0CDR4 T0CDR3 T0CDR2 T0CDR1 T0CDR0 R R R R R R R T0CDR[7:0] PS029902-0212 R Initial value : 00H T0 Capture Data PRELIMINARY 118 Z51F3220 Product Specification T0CR (Timer 0 Control Register) : B2H 7 6 5 4 3 2 1 0 T0EN – T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC R/W – R/W R/W R/W R/W R/W T0EN T0MS[1:0] R/W Initial value : 00H Control Timer 0 0T imer 0 disable 1 Ti mer 0 enable Control Timer 0 Operation Mode T0MS1 T0 MS0 Description 0 T0CK[2:0] T0CC 0 Timer/counter mode 01 PWM mode 1x Capture mode Select Timer 0 clock source. fx is a system clock frequency T0CK2 T0CK1 T0 CK0 De scription 0 00f x/2 0 01f x/4 0 10f x/8 0 11f x/32 1 00f x/128 1 01f x/512 1 10f x/2048 1 1 1 Ex ternal Clock (EC0) Clear timer 0 Counter 0 No 1 effect Clear the Timer 0 counter (When write, automatically cleared “0” after being cleared counter) NOTES) 1. Match Interrupt is generated in Capture mode. 2. Refer to the external interrupt flag 1 register (EIFLAG1) for the T0 interrupt flags. PS029902-0212 PRELIMINARY 119 Z51F3220 Product Specification 11.6 Timer 1 11.6.1.1 Overview The 16-bit timer 1 consists of multiplexer, timer 1 A data register high/low, timer 1 B data register high/low and timer 1 control register high/low (T1ADRH, T1ADRL, T1BDRH, T1BDRL, T1CRH, T1CRL). It has four operating modes: - 16-bit timer/counter mode - 16-bit capture mode - 16-bit PPG output mode (one-shot mode) - 16-bit PPG output mode (repeat mode) The timer/counter 1 can be clocked by an internal or an external clock source (EC1). The clock source is selected by clock selection logic which is controlled by the clock selection bits (T1CK[2:0]). - TIMER 1 clock source: fX/1, 2, 4, 8, 64, 512, 2048 and EC1 In the capture mode, by EINT11, the data is captured into input capture data register (T1BDRH/T1BDRL). Timer 1 outputs the comparision result between counter and data register through T1O port in timer/counter mode. Also Ttimer 1 outputs PWM wave form through PWM1O port in the PPG mode. Table 11-7 Timer 1 Operating Modes T1EN P 1FSRL[5:4] T1MS[1:0] T1 CK[2:0] Timer 1 1 11 00 XXX 16 Bit Timer/Counter Mode 1 00 01 XXX 16 Bit Capture Mode 10 XXX 1 11 1 11 11 XXX 16 Bit PPG Mode (one-shot mode) 16 Bit PPG Mode (repeat mode) 11.6.2 16-Bit Timer/Counter Mode The 16-bit timer/counter mode is selected by control register as shown in Figure 11.14. The 16-bit timer have counter and data register. The counter register is increased by internal or external clock input. Timer 1 can use the input clock with one of 1, 2, 4, 8, 64, 512 and 2048 prescaler division rates (T1CK[2:0]). When the value of T1CNTH, T1CNTL and the value of T1ADRH, T1ADRL are identical in Timer 1 respectively, a match signal is generated and the interrupt of Timer 1 occurs. The T1CNTH, T1CNTL value is automatically cleared by match signal. It can be also cleared by software (T1CC). The external clock (EC1) counts up the timer at the rising edge. If the EC1 is selected as a clock source by T1CK[2:0], EC1 port should be set to the input port by P13IO bit. PS029902-0212 PRELIMINARY 120 Z51F3220 Product Specification T1CRH T1CRL T1 EN – T1 MS1 T1MS0 – – – T1CC 1 – 0 0 – – – X T1CK2 T1 CK1 T1CK0 T1IFR – T1 POL X X X X – X ADDRESS:BBH INITIAL VALUE : 0000 _0000 B T1ECE T1CNTR X ADDRESS:BAH INITIAL VALUE : 0000 _0000 B X 16-bit A Data Register T1ADRH/T1ADRL A M atch T1CC T1EN Reload T1 CK[2:0] T1ECE EC1 Edge Detector fx INT_ACK Buffer R egister A 3 Clear A M atch P r e s c a l e r T1 EN fx/1 Comparator fx/2 M U X fx/4 fx/8 fx/64 To interrupt block T1IFR 16- bit C ounter T1CNTH/T1 CNTL R A M atch T1 CC T1 EN Clear Pulse Generator fx/512 fx/2048 T1O 2 T1MS[1 :0] T1POL Figure 11.14 16-Bit Timer/Counter Mode for Timer 1 Match with T1ADRH/L n T1CNTH/L Value n-1 n-2 Count Pulse Period PCP 6 Up-count 5 4 3 2 1 0 TIME Interrupt Period = PCP x (n+1) Timer 1 (T1IFR) Interrupt Occur Interrupt Occur Interrupt Occur Interrupt Figure 11.15 16-Bit Timer/Counter 1 Example PS029902-0212 PRELIMINARY 121 Z51F3220 Product Specification 11.6.3 16-Bit Capture Mode The 16-bit timer 1 capture mode is set by T1MS[1:0] as ‘01’. The clock source can use the internal/external clock. Basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when T1CNTH/T1CNTL is equal to T1ADRH/T1ADRL. The T1CNTH, T1CNTL values are automatically cleared by match signal. It can be also cleared by software (T1CC). This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer. The capture result is loaded into T1BDRH/T1BDRL. According to EIPOL1 registers setting, the external interrupt EINT11 function is chosen. Of cource, the EINT11 pin must be set as an input port. T1EN – T1MS1 T1MS0 – – – T1CC 1 – 0 1 – – – X T1CK1 T1CK1 T1CK0 T1IFR – T1POL X X X X – X T1CRH T1CRL T1 ECE T1CNTR X ADDRESS:BBH INITIAL VALU E : 0000 _0000B ADDRESS:BAH INITIAL VALU E : 0000 _0000B X 16-bit A D ata R egister T1ADRH/T1ADRL A M atch T1CC T1EN Reload T1 CK[2:0] T1ECE EC1 Edge Detector fx INT_ACK Buffer R egister A 3 Clear A M atch P r e s c a l e r T1 EN fx/1 fx/2 fx/4 fx/8 fx/64 T1IFR Comparator M U X 16- bit C ounter T1CNTH/T1 CNTL R Clear To interrupt block A M atch T1 CC T1 EN Clear fx/512 fx/2048 EIPOLB [1:0] 2 T1 CNTR 16-bit B D ata R egister T1 BDRH/T1 BDRL EINT11 2 INT_ACK Clear T1MS[1:0] FLAG11 (EIFLAG1.2) To interrupt block Figure 11.16 16-Bit Capture Mode for Timer 1 PS029902-0212 PRELIMINARY 122 Z51F3220 Product Specification T1BDRH/L Load n T1CNTH/L Value n-1 n-2 Count Pulse Period PCP 6 Up-count 5 4 3 2 1 0 TIME Ext. EINT11 PIN Interrupt Request (FLAG11) Interrupt Interval Period Figure 11.17 Input Capture Mode Operation for Timer 1 FFFFH FFFFH XXH T1CNTH/L YYH 00H 00H 00H 00H 00H Interrupt Request (T1IFR) Ext. EINT11 PIN Interrupt Request (FLAG11) Interrupt Interval Period = FFFFH+01H+FFFFH +01H+YYH+01H Figure 11.18 Express Timer Overflow in Capture Mode PS029902-0212 PRELIMINARY 123 Z51F3220 Product Specification 11.6.4 16-Bit PPG Mode The timer 1 has a PPG (Programmable Pulse Generation) function. In PPG mode, T1O/PWM1O pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by setting P1FSRL[5:4] to ‘11’ . The period of the PWM output is determined by the T1ADRH/T1ADRL. And the duty of the PWM output is determined by the T1BDRH/T1BDRL. T1 CRH T1CRL T1EN – T1MS1 T1MS0 – – – T1CC 1 – 1 1 – – – X T1CK2 T1CK1 T1CK0 T1IFR – T1POL X X X X – X ADDRESS:BBH INITIAL VALU E : 0000 _0000 B ADDRESS:BAH INITIAL VALU E : 0000 _0000 B T1ECE T1CNTR X X 16-bit A Data Register T1ADRH/T1ADRL A M atch T1CC T1EN Reload T1 CK[2:0] T1ECE EC1 Edge Detector fx INT_ACK Buffer R egister A 3 Clear A M atch P r e s c a l e r T1 EN fx/1 Comparator fx/2 fx/4 fx/8 fx/64 To interrupt block T1IFR M U X 16- bit C ounter T1CNTH/T1 CNTL R fx/512 T1 EN B M atch fx/2048 A M atch T1 CC Clear Comparator Buffer R egister B Reload Pulse Generator T1O/ PWM1O 2 T1MS[1 :0] T1POL A M atch T1CC T1EN 16-bit B Data Register T1 BDRH/T1 BDRL NOTE) The T1EN is automatically cleared to logic “0” after one pulse is generated at a PPG one-shot mode. Figure 11.19 16-Bit PPG Mode for Timer 1 PS029902-0212 PRELIMINARY 124 Z51F3220 Product Specification Repeat Mode(T1MS = 11b) and "Start High"(T1POL = 0b). Clear and Start Set T1EN Timer 1 clock Counter X T1ADRH/L M 0 1 2 3 4 5 6 7 8 M-1 M 0 1 2 3 T1 Interrupt 1. T1BDRH/L(5) < T1ADRH/L PWM1O B Match A Match 2. T1BDRH/L >= T1ADRH/L PWM1O A Match 3. T1BDRH/L = "0000H" PWM1O A Match Low Level One-shot Mode (T1MS = 10b) and "Start High"(T1POL = 0b). Clear and Start Set T1EN Timer 1 clock Counter X T1ADRH/L M 0 1 2 3 4 5 6 7 8 M-1 M 0 T1 Interrupt 1. T1BDRH/L(5) < T1ADRH/L PWM1O B Match A Match 2. T1BDRH/L >= T1ADRH/L PWM1O A Match 3. T1BDRH/L = "0000H" PWM1O A Match Low Level Figure 11.20 16-Bit PPG Mode Timming chart for Timer 1 PS029902-0212 PRELIMINARY 125 Z51F3220 Product Specification 11.6.5 Block Diagram 16-bit A Data Register T1ADRH/T1ADRL A M atch T1CC Reload T1EN T1CK[2:0] T1ECE Buffer R egister A 3 EC1 Edge Detector T1EN fx/1 fx/4 fx/8 fx/64 To interrupt block T1IFR Comparator fx/2 M U X 16-bit C ounter T1CNTH/T1CNTL R Clear fx/512 Comparator EIPOL1 [5:4] Buffer R egister B 2 A M atch T1CC Clear T1EN B M atch fx/2048 Pulse Generator T1O/ PWM1O 2 T1MS[1:0] T1POL A M atch T1CC Reload T1CNTR To Timer 2 block Clear A M atch P r e s c a l e r fx INT_ACK T1EN EINT11 2 16 -bit B Data Register T1BDRH/T1BDRL T1MS[1:0 ] INT_ACK Clear FLAG11 (EIFLAG1 .2) To interrupt block Figure 11.21 16-Bit Timer/Counter Mode for Timer 1 and Block Diagram 11.6.6 Register Map Table 11-8 Timer 2 Register Map Name Address Dir Default Description T1ADRH BDH R/W FFH Timer 1 A Data High Register T1ADRL BCH R/W FFH Timer 1 A Data Low Register T1BDRH BFH R/W FFH Timer 1 B Data High Register T1BDRL BEH R/W FFH Timer 1 B Data Low Register T1CRH BBH R/W 00H Timer 1 Control High Register T1CRL BAH R/W 00H Timer 1 Control Low Register PS029902-0212 PRELIMINARY 126 Z51F3220 Product Specification 11.6.6.1 Timer/Counter 1 Register Description The timer/counter 1 register consists of timer 1 A data high register (T1ADRH), timer 1 A data low register (T1ADRL), timer 1 B data high register (T1BDRH), timer 1 B data low register (T1BDRL), timer 1 control High register (T1CRH) and timer 1 control low register (T1CRL). 11.6.6.2 Register Description for Timer/Counter 1 T1ADRH (Timer 1 A data High Register) : BDH 7 6 5 4 3 2 1 0 T1ADRH7 T1ADRH6 T1ADRH5 T1ADRH4 T1ADRH3 T1ADRH2 T1ADRH1 T1ADRH0 R/W R/W R/W R/W R/W R/W R/W T1ADRH[7:0] R/W Initial value : FFH T1 A Data High Byte T1ADRL (Timer 1 A Data Low Register) : BCH 7 6 5 4 3 2 1 0 T1ADRL7 T1ADRL6 T1ADRL5 T1ADRL4 T1ADRL3 T1ADRL2 T1ADRL1 T1ADRL0 R/W R/W R/W R/W R/W R/W R/W T1ADRL[7:0] R/W Initial value : FFH T1 A Data Low Byte NOTE) Do not write “0000H” in the T1ADRH/T1ADRL register when PPG mode T1BDRH (Timer 1 B Data High Register) : BFH 7 6 5 4 3 2 1 0 T1BDRH7 T1BDRH6 T1BDRH5 T1BDRH4 T1BDRH3 T1BDRH2 T1BDRH1 T1BDRH0 R/W R/W R/W R/W R/W R/W R/W T1BDRH[7:0] R/W Initial value : FFH T1 B Data High Byte T1BDRL (Timer 1 B Data Low Register) : BEH 7 6 5 4 3 2 1 0 T1BDRL7 T1BDRL6 T1BDRL5 T1BDRL4 T1BDRL3 T1BDRL2 T1BDRL1 T1BDRL0 R/W R/W R/W R/W R/W R/W R/W T1BDRL[7:0] PS029902-0212 R/W Initial value : FFH T1 B Data Low Byte PRELIMINARY 127 Z51F3220 Product Specification T1CRH (Timer 1 Control High Register) : BBH 7 6 5 4 3 2 1 0 T1EN – T1MS1 T1MS0 – – – T1CC R/W – R/W R/W – – – T1EN Control Timer 1 0T 1 T1MS[1:0] R/W Initial value : 00H imer 1 disable Timer 1 enable (Counter clear and start) Control Timer 1 Operation Mode T1MS1 T1 MS0 Description 0 0 Timer/counter mode (T1O: toggle at A match) 0 1 Capture mode (The A match interrupt can occur) 1 0 PPG one-shot mode (PWM1O) 11 T1CC 0 No 1 PS029902-0212 PPG repeat mode (PWM1O) Clear Timer 1 Counter effect Clear the Timer 1 counter (When write, automatically cleared “0” after being cleared counter) PRELIMINARY 128 Z51F3220 Product Specification T1CRL (Timer 1 Control Low Register) : BAH 7 6 5 4 3 2 1 0 T1CK2 T1CK1 T1CK0 T1IFR – T1POL T1ECE T1CNTR R/W R/W R/W R/W – R/W R/W T1CK[2:0] T1IFR Select Timer 1 clock source. fx is main system clock frequency T1CK2 T1CK1 T1 CK0 De scription 0 00f x/2048 0 01f x/512 0 10f x/64 0 11f x/8 1 00f x/4 1 01f x/2 1 10f x/1 1 1 1 Ex 1T T1ECE 1 Interrupt generation 0 Start High (T1O/PWM1O is low level at disable) 1 Start Low (T1O/PWM1O is high level at disable) Timer 1 External Clock Edge Selection 1 ternal clock falling edge External clock rising edge Timer 1 Counter Read Control 0 No 1 PS029902-0212 T1 Interrupt no generation T1O/PWM1O Polarity Selection 0 Ex T1CNTR ternal clock (EC1) When T1 Interrupt occurs, t his bit b ecomes ‘1’ . For c learing bi t, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 T1POL R/W Initial value : 00H effect Load t he counter v alue t o t he B da ta re gister (Wh en write, automatically cleared “0” after being loaded) PRELIMINARY 129 Z51F3220 Product Specification 11.7 Timer 2 11.7.1.1 Overview The 16-bit timer 2 consists of multiplexer, timer 2 A data high/low register, timer 2 B data high/low register and timer 2 control high/low register (T2ADRH, T2ADRL, T2BDRH, T2BDRL, T2CRH, T2CRL). It has four operating modes: - 16-bit timer/counter mode - 16-bit capture mode - 16-bit PPG output mode (one-shot mode) - 16-bit PPG output mode (repeat mode) The timer/counter 2 can be divided clock of the system clock selectd from prescaler output and T1 A Match (timer 1 A match signal). The clock source is selected by clock selection logic which is controlled by the clock selection bits (T2CK[2:0]). - TIMER 2 clock source: fX/1, 2, 4, 8, 32, 128, 512 and T1 A Match In the capture mode, by EINT12, the data is captured into input capture data register (T2BDRH/T2BDRL). In timer/counter mode, whenever counter value is equal to T2ADRH/L, T2O port toggles. Also the timer 2 outputs PWM wave form to PWM2O port in the PPG mode. Table 11-9 Timer 2 Operating Modes T2EN P1FSRL T2MS[1:0] T2CK[2:0] Timer 2 1 11 00 XXX 16 Bit Timer/Counter Mode 1 00 01 XXX 16 Bit Capture Mode 10 XXX 1 11 1 11 PS029902-0212 [3:2] 11 XXX PRELIMINARY 16 Bit PPG Mode (one-shot mode) 16 Bit PPG Mode (repeat mode) 130 Z51F3220 Product Specification 11.7.2 16-Bit Timer/Counter Mode The 16-bit timer/counter mode is selected by control register as shown in Figure 11.22. The 16-bit timer have counter and data register. The counter register is increased by internal or timer 1 A match clock input. Timer 2 can use the input clock with one of 1, 2, 4, 8, 32, 128, 512 and T1 A Match prescaler division rates (T2CK[2:0]). When the values of T2CNTH/T2CNTL and T2ADRH/T2ADRL are identical in timer 2, a match signal is generated and the interrupt of Timer 2 occurs. The T2CNTH/T2CNTL values are automatically cleared by match signal. It can be also cleared by software (T2CC). T2CRH T2 CRL ADDRESS:C3H INITIAL VALUE: 0000_0000 B T2 EN – T2MS1 T2MS0 – – – T2CC 1 – 0 0 – – – X T2CK2 T2 CK1 T2CK0 T2IFR – T2POL – T2CNTR X X X X – X – X ADDRESS:C2H INITIAL VALUE: 0000_0000 B 16 -bit A D ata R egister T2ADRH/T2ADRL A M atch T2CC T2EN Reload T2CK[2:0 ] INT_ ACK Buffer R egister A 3 Clear A M atch T1 A Match fx P r e s c a l e r Comparator fx/2 fx/4 fx/8 fx/32 To interrupt block T2IFR T2EN fx/1 M U X 16 -bit C ounter T2 CNTH/T2CNTL R A M atch T2CC T2EN Clear Pulse Generator fx/128 fx/512 T2 O 2 T2MS[1:0] T2POL Figure 11.22 16-Bit Timer/Counter Mode for Timer 2 PS029902-0212 PRELIMINARY 131 Z51F3220 Product Specification Match with T2ADRH/L n T2CNTH/L Value n-1 n-2 Count Pulse Period PCP 6 Up-count 5 4 3 2 1 0 TIME Interrupt Period = PCP x (n+1) Timer 2 (T2IFR) Interrupt Occur Interrupt Occur Interrupt Occur Interrupt Figure 11.23 16-Bit Timer/Counter 2 Example PS029902-0212 PRELIMINARY 132 Z51F3220 Product Specification 11.7.3 16-Bit Capture Mode The timer 2 capture mode is set by T2MS[1:0] as ‘01’. The clock source can use the internal clock. Basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when T2CNTH/T2CNTL is equal to T2ADRH/T2ADRL. T2CNTH/T2CNTL values are automatically cleared by match signal and it can be also cleared by software (T2CC). This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer. The capture result is loaded into T2BDRH/T2BDRL. In the timer 2 capture mode, timer 2 output(T2O) waveform is not available. According to EIPOL1 registers setting, the external interrupt EINT12 function is chosen. Of cource, the EINT12 pin must be set to an input port. T2CRH T2CRL ADDRESS:C3H INITIAL VALUE : 0000 _0000B T2EN – T2MS1 T2MS0 – – – T2CC 1 – 0 1 – – – X T2 CK2 T2CK1 T2CK0 T2IFR – T2POL – T2CNTR X X X X – X – ADDRESS:C2H INITIAL VALUE : 0000 _0000B X 16 -bit A D ata R egister T2ADRH/T2ADRL A M atch T2CC T2EN Reload T2CK[2:0] INT_ACK Buffer R egister A 3 Clear A M atch T1 A Match P r e s c a l e r fx T2EN fx/1 fx/8 fx/32 To interrupt block Comparator fx/2 fx/4 T2IFR M U X 16 -bit C ounter T2CNTH/T2CNTL R Clear A M atch T2CC T2EN Clear fx/128 fx/512 EIPOL 1[7:6 ] 2 T2CNTR 16 -bit B D ata R egister T2BDRH/T2BDRL EINT12 2 INT_ACK Clear T2MS[1 :0] FLAG 12 (EIFLAG1.3) To interrupt block Figure 11.24 16-Bit Capture Mode for Timer 2 PS029902-0212 PRELIMINARY 133 Z51F3220 Product Specification T2BDRH/L Load n T2CNTH/L Value n-1 n-2 Count Pulse Period PCP 6 Up-count 5 4 3 2 1 0 TIME Ext. EINT12 PIN Interrupt Request (FLAG12) Interrupt Interval Period Figure 11.25 Input Capture Mode Operation for Timer 2 FFFFH FFFFH XXH T2CNTH/L YYH 00H 00H 00H 00H 00H Interrupt Request (T2IFR) Ext. EINT12 PIN Interrupt Request (FLAG12) Interrupt Interval Period = FFFFH+01H+FFFFH +01H+YYH+01H Figure 11.26 Express Timer Overflow in Capture Mode PS029902-0212 PRELIMINARY 134 Z51F3220 Product Specification 11.7.4 16-Bit PPG Mode The timer 2 has a PPG (Programmable Pulse Generation) function. In PPG mode, the T2O/PWM2O pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by set P1FSRL[3:2] to ‘11’ . The period of the PWM output is determined by the T2ADRH/T2ADRL. And the duty of the PWM output is determined by the T2BDRH/T2BDRL. T2CRH T2 CRL T2 EN – T2MS1 T2MS0 – – – T2CC 1 – 1 1 – – – X T2CK2 T2 CK1 T2CK0 T2IFR – T2POL – T2CNTR X X X X – X – X ADDRESS:C3H INITIAL VALUE: 0000_0000 B ADDRESS:C2H INITIAL VALUE: 0000_0000 B 16 -bit A D ata R egister T2ADRH/T2ADRL A M atch T2CC T2EN Reload T2CK[2 :0] INT_ACK Buffer R egister A 3 Clear T1 A Match fx A M atch P r e s c a l e r T2EN fx/1 Comparator fx/2 fx/4 fx/8 fx/32 M U X 16 -bit C ounter T2CNTH/T2CNTL A M atch T2CC T2EN Clear R B M atch fx/128 fx/512 To interrupt block T2 IFR Comparator Buffer R egister B Reload Pulse Generator T2O / PWM2 O 2 T2MS[1:0 ] T2POL A M atch T2CC T2EN 16-bit B Data R egister T2BDRH/T2BDRL NOTE) The T2EN is automatically cleared to logic “0” after one pulse is generated at a PPG one-shot mode. Figure 11.27 16-Bit PPG Mode for Timer 2 PS029902-0212 PRELIMINARY 135 Z51F3220 Product Specification Repeat Mode(T2MS = 11b) and "Start High"(T2POL = 0b). Clear and Start Set T2EN Timer 2 clock Counter X T2ADRH/L M 0 1 2 3 4 5 6 7 8 M-1 M 0 1 2 3 T2 Interrupt 1. T2BDRH/L(5) < T2ADRH/L PWM2O B Match A Match 2. T2BDRH/L >= T2ADRH/L PWM2O A Match 3. T2BDRH/L = "0000H" PWM2O A Match Low Level One-shot Mode (T2MS = 10b) and "Start High"(T2POL = 0b). Clear and Start Set T2EN Timer 2 clock Counter X T2ADRH/L M 0 1 2 3 4 5 6 7 8 M-1 M 0 T2 Interrupt 1. T2BDRH/L(5) < T2ADRH/L PWM2O B Match A Match 2. T2BDRH/L >= T2ADRH/L PWM2O A Match 3. T2BDRH/L = "0000H" PWM2O A Match Low Level Figure 11.28 16-Bit PPG Mode Timming chart for Timer 2 PS029902-0212 PRELIMINARY 136 Z51F3220 Product Specification 11.7.5 Block Diagram 16-bit A Data Register T2ADRH/T2ADRL A M atch T2CC Reload T2CK[2:0] T2EN INT_ACK Buffer R egister A 3 Clear T1 A M atch A M atch fx T2EN fx/1 P r e s c a l e r Comparator fx/2 fx/4 fx/8 fx/32 To interrupt block T2IFR M U X 16-bit C ounter T2CNTH/T2CNTL R Clear fx/128 T2EN B M atch fx/512 Comparator EIPOL 1[7:6 ] Buffer R egister B 2 A M atch T2CC Clear Pulse Generator 2 T2MS[1:0] T2POL A M atch T2CC Reload T2CNTR T2O/ PWM2O T2EN EINT12 2 16 -bit B Data Register T2BDRH/T2BDRL T2MS[1:0 ] INT_ACK Clear FLAG12 (EIFLAG1 .3) To interrupt block Figure 11.29 16-Bit Timer/Counter Mode for Timer 2 and Block Diagram 11.7.6 Register Map Table 11-10 Timer 3 Register Map Name Address Dir Default Description T2ADRH C5H R/W FFH Timer 2 A Data High Register T2ADRL C4H R/W FFH Timer 2 A Data Low Register T2BDRH C7H R/W FFH Timer 2 B Data High Register T2BDRL C6H R/W FFH Timer 2 B Data Low Register T2CRH C3H R/W 00H Timer 2 Control High Register T2CRL C2H R/W 00H Timer 2 Control Low Register PS029902-0212 PRELIMINARY 137 Z51F3220 Product Specification 11.7.6.1 Timer/Counter 2 Register Description The timer/counter 2 register consists of timer 2 A data high register (T2ADRH), timer 2 A data low register (T2ADRL), timer 2 B data high register (T2BDRH), timer 2 B data low register (T2BDRL), timer 2 control High register (T2CRH) and timer 2 control low register (T2CRL). 11.7.6.2 Register Description for Timer/Counter 2 T2ADRH (Timer 2 A data High Register) : C5H 7 6 5 4 3 2 1 0 T2ADRH7 T2ADRH6 T2ADRH5 T2ADRH4 T2ADRH3 T2ADRH2 T2ADRH1 T2ADRH0 R/W R/W R/W R/W R/W R/W R/W T2ADRH[7:0] R/W Initial value : FFH T2 A Data High Byte T2ADRL (Timer 2 A Data Low Register) : C4H 7 6 5 4 3 2 1 0 T2ADRL7 T2ADRL6 T2ADRL5 T2ADRL4 T2ADRL3 T2ADRL2 T2ADRL1 T2ADRL0 R/W R/W R/W R/W R/W R/W R/W T2ADRL[7:0] R/W Initial value : FFH T2 A Data Low Byte NOTE) Do not write “0000H” in the T2ADRH/T2ADRL register when PPG mode. T2BDRH (Timer 2 B Data High Register) : C7H 7 6 5 4 3 2 1 0 T2BDRH7 T2BDRH6 T2BDRH5 T2BDRH4 T2BDRH3 T2BDRH2 T2BDRH1 T2BDRH0 R/W R/W R/W R/W R/W R/W R/W T2BDRH[7:0] R/W Initial value : FFH T2 B Data High Byte T2BDRL (Timer 2 B Data Low Register) : C6H 7 6 5 4 3 2 1 0 T2BDRL7 T2BDRL6 T2BDRL5 T2BDRL4 T2BDRL3 T2BDRL2 T2BDRL1 T2BDRL0 R/W R/W R/W R/W R/W R/W R/W T2BDRL[7:0] PS029902-0212 R/W Initial value : FFH T2 B Data Low PRELIMINARY 138 Z51F3220 Product Specification T2CRH (Timer 2 Control High Register) : C3H 7 6 5 4 3 2 1 0 T2EN – T2MS1 T2MS0 – – – T2CC R/W – R/W R/W – – – T2EN Control Timer 2 0T 1 T2MS[1:0] R/W Initial value : 00H imer 2 disable Timer 2 enable (Counter clear and start) Control Timer 2 Operation Mode T2MS1 T2 MS0 Description 0 0 Timer/counter mode (T2O: toggle at A match) 0 1 Capture mode (The A match interrupt can occur) 1 0 11 T2CC Clear Timer 2 Counter 0 No 1 PS029902-0212 PPG one-shot mode (PWM2O) PPG repeat mode (PWM2O) effect Clear the Timer 2 counter (When write, automatically cleared “0” after being cleared counter) PRELIMINARY 139 Z51F3220 Product Specification T2CRL (Timer 2 Control Low Register) : CAH 7 6 5 4 3 2 1 0 T2CK2 T2CK1 T2CK0 T2IFR – T2POL – T2CNTR R/W R/W R/W R/W – R/W – T2CK[2:0] T2IFR T2POL T2CNTR Select Timer 2 clock source. fx is main system clock frequency T2CK2 T2CK1 T2 CK0 De scription 0 00f x/512 0 01f x/128 0 10f x/32 0 11f x/8 1 00f x/4 1 01f x/2 1 10f x/1 1 11T 1 A Match When T2 Match Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 T2 interrupt no generation 1 T2 interrupt generation T2O/PWM2O Polarity Selection 0 Start High (T2O/PWM2O is low level at disable) 1 Start Low (T2O/PWM2O is high level at disable) Timer 2 Counter Read Control 0 No 1 PS029902-0212 R/W Initial value : 00H effect Load t he counter v alue t o t he B da ta re gister (Wh en write, automatically cleared “0” after being loaded) PRELIMINARY 140 Z51F3220 Product Specification 11.8 Timer 3, 4 11.8.1 Overview Timer 3 and timer 4 can be used either two 8-bit timer/counter or one 16-bit timer/counter with combine them. Each 8-bit timer/event counter module has multiplexer, comparator, 8-bit timer data register, 8-bit counter register, control register and capture data register (T3CNT, T3DR, T3CAPR, T3CR, T4CNT, T4DR, T4CAPR, T4CR). For PWM, it has PWM register (T4PPRL. T4PPRH, T4ADRL, T4ADRH, T4BDRL, T4BDRH, T4CDRL, T4CDRH, T4DLYA, T4DLYB, T4DLYC). It has five operating modes: - 8-bit timer/counter mode - 8-bit capture mode - 16-bit timer/counter mode - 16-bit capture mode - 10-bit PWM mode The timer/counter 3 and 4 can be clocked by an internal or an external clock source (EC3). The clock source is selected by clock selection logic which is controlled by the clock selection bits (T3CK[2:0], T4CK[3:0]). Also the timer/counter 4 can use more clock sources than timer/counter 3. - TIMER 3 clock source: fX/2, 4, 8, 32, 128, 512, 2048 and EC3 - TIMER 4 clock source: fX/1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384 and T3 clock In the capture mode, by EINT0/EINT1, the data is captured into input capture data register (T3CAPR, T4CAPR). In 8-bit timer/counter 3/4 mode, whenever counter value is equal to T3DR/T4DR, T3O/T4O port toggles. Also In 16-bit timer/counter 3 mode, The timer 3 outputs the comparison result between counter and data register through T3O port. The PWM wave form to PWMAA, PWMAB, PWMBA, PWMBB, PWMCA, PWMCB Port (6-channel) in the PWM mode. Table 11-11 Timer 3, 4 Operating Modes 16BIT T3MS T4MS PWM4E T3CK[2:0] T4CK[3:0] Timer 3 Timer 4 0 0 0 0 XXX XXXX 8 Bit Timer/Counter Mode 8 Bit Timer/Counter Mode 0 1 1 0 XXX XXXX 8 Bit Capture Mode 8 Bit Capture Mode 1 0 0 0 XXX XXXX 16 Bit Tmer/Counter Mode 1 1 1 0 XXX XXXX 16 Bit Capture Mode 0 X X 1 XXX XXXX 10 Bit PWM Mode PS029902-0212 PRELIMINARY 141 Z51F3220 Product Specification 11.8.2 8-Bit Timer/Counter 3, 4 Mode The 8-bit timer/counter mode is selected by control register as shown in Figure 11.30. The two 8-bit timers have each counter and data register. The counter register is increased by internal or external clock input. Timer 3 can use the input clock with one of 2, 4, 8, 32, 128, 512, 2048 and EC3 prescaler division rates (T3CK[2:0]). Timer 4 can use the input clock with one of 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384 and timer 3 clock prescaler division rates (T4CK[3:0]). When the value of T3CNT, T4CNT and T3DR, T4DR are respectively identical in Timer 3, 4, the interrupt Timer 3, 4 occurs. The external clock (EC3) counts up the timer at the rising edge. If the EC3 is selected as a clock source by T3CK[2:0], EC3 port should be set to the input port by P00IO bit. Timer 4 can’t use the external EC3 clock. T3EN – T3MS T3 CK2 T3CK1 T3CK0 T3 CN T3ST 1 – 0 X X X X X 16BIT T4 MS T4CN T4ST T4CK3 T4CK2 T4CK1 T4CK0 0 0 X X X X X X T3CR T4CR ADDRESS:1000H (ESF R) INITIAL VALUE : 0000 _0000 B ADDRESS:1002H (ESF R) INITIAL VALUE : 0000 _0000 B T4O 8-bit T imer 4 D ata R egister T4CK[3:0] T4DR (8Bit) 4 fx P r e s c a l e r Comparator fx/1 fx/2 T4 CN fx/4 fx/8 To interrupt block Match M U X T4CNT (8Bit) Clear 8-bit T imer 4 Counter fx/16384 T4ST EC3 fx P r e s c a l e r T3ST fx/2 fx/4 fx/8 fx/32 8-bit T imer 3 Counter M U X Clear T3CNT (8Bit) INT_ACK Clear fx/128 fx/512 Match T3CN fx/2048 T3IFR To interrupt block Comparator 3 T3CK[2:0] T3DR (8Bit) 8-bit T imer 3 D ata R egister T3 O NOTE: Do not set to “1111b” in the T4CK[3:0], when two 8-bit timer 3/4 modes. Figure 11.30 8-Bit Timer/Counter Mode for Timer 3, 4 PS029902-0212 PRELIMINARY 142 Z51F3220 Product Specification 11.8.3 16-Bit Timer/Counter 3 Mode The 16-bit timer/counter mode is selected by control register as shown in Figure 11.31. The 16-bit timer have counter and data register. The counter register is increased by internal or external clock input. Timer 3 can use the input clock with one of 2, 4, 8, 32, 128, 512 and 2048 prescaler division rates (T3CK[2:0]). A 16-bit timer/counter register T3CNT, T4CNT are incremented from 0000H to FFFFH until it matches T3DR, T4DR and then cleared to 0000H. The match signal output generates the Timer 3 Interrupt (No timer 4 interrupt). The clock source is selected from T3CK[2:0] and 16BIT bit must be set to ‘1’. Timer 3 is LSB 8-bit, the timer 4 is MSB 8-bit. The external clock (EC3) counts up the timer at the rising edge. f the EC3 is selected as a clock source by T3CK[2:0], EC3 port should be set to the input port by P00IO bit. T3 CR T4 CR T3EN – T3MS T3CK2 T3CK1 T3CK0 T3CN T3 ST 1 – 0 X X X X X 16BIT T4MS T4CN T4ST T4CK3 T4CK2 T4CK1 T4 CK0 1 0 X X 1 1 1 1 ADDRESS:1000 H (ESFR) INITIAL VALU E : 0000 _0000B ADDRESS:1002 H (ESFR) INITIAL VALU E : 0000 _0000B EC3 fx P r e s c a l e r T3ST fx/2 fx/4 fx/8 fx/32 16-bit T imer 3 C ounter M U X Clear T4CNT/T3CNT (16Bit) MSB LSB Clear fx/128 fx/512 Match T3CN fx/2048 INT_ACK T3IFR To int errupt block Comparator 3 T3CK[2:0] T4DR/T3DR (16Bit) MSB LSB 16-bit T imer 3 D ata R egister T3 O NOTE) The T4CR.7 bit (16BIT) should be set to ‘1’ and the T4CK[3:0] should be set to “1111b”. Figure 11.31 16-Bit Timer/Counter Mode for Timer 3 PS029902-0212 PRELIMINARY 143 Z51F3220 Product Specification 11.8.4 8-Bit Timer 3, 4 Capture Mode The 8-bit Capture 3 and 4 mode is selected by control register as shown in Figure 11.32. The timer 3, 4 capture mode is set by T3MS, T4MS as ‘1’. The clock source can use the internal/external clock. Basically, it has the same function as the 8-bit timer/counter mode and the interrupt occurs when T3CNT, T4CNT is equal to T3DR, T4DR. The T3CNT, T4CNT value is automatically cleared by match signal. This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer. The capture result is loaded into T3CAPR, T4CAPR. In the timer 3, 4 capture mode, timer 3, 4 output (T3O, T4O) waveform is not available. According to the EIPOL0L register setting, the external interrupt EINT0 and EINT1 function is chose. Of cource, the EINT0 and EINT1 pins must be set to an input port. The T3CAPR and T3DR are in the same address. In the capture mode, reading operation reads T3CAPR, not T3DR and writing operation will update T3DR. The T4CAPR has the same function. PS029902-0212 PRELIMINARY 144 Z51F3220 Product Specification T3CR T4CR T3EN – T3MS T3CK2 T3CK1 T3 CK0 T3CN T3ST 1 – 1 X X X X X 16BIT T4MS T4CN T4ST T4CK3 T4 CK2 T4CK1 T4CK0 0 1 X X X X X X ADDRESS:1000H (ESFR) INITIAL VALUE : 0000 _0000 B ADDRESS:1002H (ESFR) INITIAL VALUE : 0000 _0000 B FLAG 0 (EIFLAG0.1) T4MS To interrupt block Clear 8-bit T imer 4 Capture Register EINT1 S/W T4CAPR (8Bit) 2 T4O EIPOL 0L[3:2 ] T4CK[3:0] 8-bit T imer 4 D ata R egister T4DR (8Bit) 4 P r e s c a l e r fx Comparator fx/1 fx/2 T4 CN fx/4 Clear fx/8 To interrupt block Match M U X T4CNT (8Bit) Clear 8-bit T imer 4 Counter fx/16384 T4ST EC3 P r e s c a l e r fx T3ST fx/2 fx/4 8-bit T imer 3 Counter M U X fx/8 fx/32 Clear T3CNT (8Bit) fx/128 Clear Clear fx/512 Match T3CN fx/2048 INT_ACK T3IFR To interrupt block Comparator 3 T3DR (8Bit) T3CK[2:0] EIPOL 0L[1:0 ] 8-bit T imer 3 D ata R egister T3 O 2 T3CAPR (8 Bit) EINT0 8-bit T imer 3 Capture Register S/W Clear T3MS FLAG 0 (EIFLAG0.0) To interrupt block NOTE: Do not set to “1111b” in the T4CK[3:0], when two 8-bit timer 3/4 modes. Figure 11.32 8-Bit Capture Mode for Timer 3, 4 PS029902-0212 PRELIMINARY 145 Z51F3220 Product Specification 11.8.5 16-Bit Timer 3 Capture Mode The 16-bit Capture mode is selected by control register as shown in Figure 11.33. The 16-bit capture mode is the same operation as 8-bit capture mode, except that the timer register uses 16 bits. The 16-bit timer 3 capture mode is set by T3MS, T4MS as ‘1’. The clock source is selected from T3CK[2:0] and 16BIT bit must be set to ‘1’. Timer 3 is LSB 8-bit, the timer 4 is MSB 8-bit. T3 CR T4 CR T3EN – T3MS T3CK2 T3CK1 T3CK0 T3CN T3 ST 1 – 1 X X X X X 16BIT T4MS T4CN T4ST T4CK3 T4CK2 T4CK1 T4 CK0 1 1 X X 1 1 1 1 ADDRESS:1000 H (ESFR) INITIAL VALU E : 0000 _0000B ADDRESS:1002 H (ESFR) INITIAL VALU E : 0000 _0000B EC3 P r e s c a l e r fx T3ST fx/2 fx/4 16-bit T imer 3 C ounter M U X fx/8 fx/32 Clear T4CNT/T3CNT (16Bit) MSB LSB fx/128 Clear fx/512 Clear Match T3CN fx/2048 INT_ACK T3IFR To int errupt block Comparator 3 T4DR/T3DR (16Bit) MSB LSB T3CK[2:0] EIPOL 0L[1:0 ] 16-bit T imer 3 D ata R egister T3 O 2 T4CAPR/T3CAPR (16Bit) MSB LSB EINT0 16-bit T imer 3 C apture R egister S/W Clear T3MS FLAG 0 (EIFLAG0.0) To interrupt block NOTE) The T4CR.7 bit (16BIT) should be set to ‘1’ and the T4CK[3:0] should be set to “1111b”. Figure 11.33 16-Bit Capture Mode for Timer 3 PS029902-0212 PRELIMINARY 146 Z51F3220 Product Specification 11.8.6 10-Bit Timer 4 PWM Mode The timer 4 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, the 6-channel pins output up to 10-bit resolution PWM output. This pin should be configured as a PWM output by set PWM4E to ‘1’. When the value of 2bit +T4CNT and T4PPRH/L are identical in timer 4, a period match signal is generated and the interrupt of timer 4 occurs. In 10-bit PWM mode, A, B, C, bottom(underflow) match signal are generated when the 10-bit counter value are identical to the value of T4xADRH/L. The period of the PWM output is determined by the T4PPRH/L (PWM period register), T4xDRH/L (each channel PWM duty register). PWM Period = [T4PPRH/T4PPRL ] X Source Clock PWM Duty(A-ch) = [ T4ADRH/T4ADRL ] X Source Clock Table 11-12 PWM Frequency vs. Resolution at 8 MHz Resolution Frequency T4CK[3:0]=0001 (250ns) T4CK[3:0]=0010 (500ns) T4CK[3:0]=0100 (2us) 10 Bit 3.9KHz 1.95KHz 0.49KHz 9 Bit 7.8KHz 3.9KHz 0.98KHz 8 Bit 15.6KHz 7.8KHz 1.95KHz 7 Bit 31.2KHz 15.6KHz 3.91KHz The POLxA bit of T4PCR3 register decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM output is determined by the bit POLxA (1: High, 0: Low). And if the duty value is set to "00H", the PWM output is determined by the bit POLxA (1: Low, 0: High). Table 11-13 PWM Channel Polarity PHLT:PxxOE POLx A 0 POLBO 0 POLxB PWM4xA Pin Output 0 Lo 1L 1x 0x, x0, 00 1 0 0 High1 High- 1x 0x 11 1x PS029902-0212 0 Pos PWM4xB Pin Output w-level Low-level ow-level High-level Low-level Low-level level High-level level Low-level High-level High-level itive-phase Positive-Phase 1 Pos itive-phase Negative-Phase 0 Ne gative-Phase Negative-Phase 1 Neg ative-Phase Positive-phase PRELIMINARY 147 Z51F3220 Product Specification T4CR T4PCR1 T4PCR2 T4PCR3 16BIT T4MS T4CN T4 ST T4CK3 T4CK2 T4CK1 T4CK0 0 X X X X X X X BMOD PHLT UPDT UALL NOPS1 NOPS0 X X PWM4E ESYNC 1 X X X X X FORCA – PAAOE PABOE PBAOE PBBOE 0 – X X X X X X HZCLR POLBO POLAA POLAB POLBA POLBB POLCA POLCB X X X X X X X X T4PPRH/T4PPRL (10 Bit) 4 T4CN fx/2 fx P r e s c a l e r T4 ST 10 -bit C ounter 2Bit + T4CNT fx/8 Control Up/Down A M atch fx/32 fx/128 fx/256 fx/512 M U X fx/4096 fx/8192 fx/16384 Interrupt Generator To interrupt block PWM Output Control PWM Delay Control A -ch A-ch PWM Output Control PWM Delay Control B-ch B-ch PWM Output Control PWM Delay Control C-ch C-ch PWM4AA PWM4AB Comparator 10 -bit A Data Register T4ADRH/T4ADRL B M atch fx/1024 fx/2048 ADDRESS:1005H (ESFR) INITIAL VALUE : 0000 _0000 B Bottom (Underflow) A M atch B M atch C Match Period M atch fx/16 fx/64 ADDRESS:1004H (ESFR) INITIAL VALUE : 0000 _0000 B PCAOE PCBOE Comparator fx/4 ADDRESS:1003H (ESFR) INITIAL VALUE : 0000 _0000 B Timer 4 PWM Period R egister T4CK[3:0 ] fx/1 ADDRESS:1002H (ESFR) INITIAL VALUE : 0000 _0000 B PWM4 BA PWM4 BB Comparator 10-bit B Data Register T4 BDRH/T4 BDRL C Match PWM4 CA PWM4 CB Comparator 10 -bit C Data Register T4CDRH/T4 CDRL NOTE: Do not set to “1111b” in the T4CK[3:0], when two 8-bit timer 3/4 modes. Figure 11.34 10-Bit PWM Mode (Force 6-ch) PS029902-0212 PRELIMINARY 148 Z51F3220 Product Specification T4CR T4PCR1 T4PCR2 T4PCR3 16BIT T4MS T4CN T4 ST T4CK3 T4CK2 T4CK1 T4CK0 0 X X X X X X X PWM4E ESYNC BMOD PHLT UPDT UALL NOPS1 NOPS0 1 X X X X X X X FORCA – PAAOE PABOE PBAOE PBBOE 1 – X X X X X X HZCLR POLBO POLAA POLAB POLBA POLBB POLCA POLCB X X X X X X X X T4PPRH/T4PPRL (10 Bit) 4 T4CN fx/2 fx T4 ST 10 -bit C ounter 2Bit + T4CNT fx/8 P r e s c a l e r fx/16 fx/128 fx/256 fx/512 ADDRESS:1005H (ESFR) INITIAL VALUE : 0000 _0000 B Bottom (Underflow) A M atch B M atch C Match Period M atch Control Up/Down A M atch fx/32 fx/64 ADDRESS:1004H (ESFR) INITIAL VALUE : 0000 _0000 B PCAOE PCBOE Comparator fx/4 ADDRESS:1003H (ESFR) INITIAL VALUE : 0000 _0000 B Timer 4 PWM Period R egister T4CK[3:0 ] fx/1 ADDRESS:1002H (ESFR) INITIAL VALUE : 0000 _0000 B M U X Interrupt Generator To interrupt block PWM Output Control PWM Delay Control A -ch A-ch PWM Output Control PWM Delay Control B-ch B-ch PWM Output Control PWM Delay Control C-ch C-ch PWM4AA PWM4AB Comparator 10 -bit A Data Register T4ADRH/T4ADRL fx/1024 fx/2048 PWM4 BA PWM4 BB fx/4096 fx/8192 fx/16384 PWM4 CA PWM4 CB NOTE: Do not set to “1111b” in the T4CK[3:0], when two 8-bit timer 3/4 modes. Figure 11.35 10-Bit PWM Mode (Force All-ch) PS029902-0212 PRELIMINARY 149 Z51F3220 Product Specification Source Clock (fx) T4CNT 00 01 02 03 04 7F 80 81 82 3FF 00 01 02 P02/PWM4AA POLAA = 1 P02/PWM4AA POLAA = 0 Duty Cycle(1+80H)X250ns = 32.25us Period Cycle(1+3FFH)X250ns = 256us  3.9kHz T4PPRH(2 Bit) T4CR = 00H (fXIN) T4PPRH = 03H T4PPRL = FFH T4ADRH = 00H T4ADRL = 80H T4PPRL(8 Bit) 03H T4ADRH(2 Bit) FFH T4ADRL(8 Bit) 00H 80H Figure 11.36 Example of PWM at 4 MHz T4CR = 03H (2us) T4PPRH = 00H T4PPRL = 0EH T4ADRH = 00H T4ADRL = 05H Write 0AH to T4PPRL Source Clock (fx) T4CNT 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 00 01 02 03 04 05 06 07 08 09 0A 00 01 02 03 04 05 06 P02/PWM4AA POLAA = 1 Duty Cycle (1+05H)X2us = 12us Duty Cycle (1+05H)X2us = 12us Period Cycle (1+0EH)X2us = 32us  31.25kHz Duty Cycle (1+05H)X2us = 12us Period Cycle (1+0AH)X2us = 22us  45.5kHz Figure 11.37 Example of Changing the Period in Absolute Duty Cycle at 4 MHz Update period & duty register value at once The period and duty of PWM comes to move from temporary registers to T4PPRH/L (PWM Period Register) and T4ADRH/L/T4BDRH/L/T4CDRH/L (PWM Duty Register) when always period match occurs. If you want that the period and duty is immediately changed, the UPDT bit in the T4PCR1 register must set to ‘1’. It should be noted that it needs the 3 cycle of timer clock for data transfer in the internal clock synchronization circuit. So the update data is written before 3 cycle of timer clock to get the right output waveform. PS029902-0212 PRELIMINARY 150 Z51F3220 Product Specification Phase correction & Frequency correction On operating PWM, it is possible that it is changed the phase and the frequency by using BMOD bit (back-toback mode) in T4PCR1 register. (Figure 1.38, Figure 11.39, Figure 11.40 referred) In the back-to-back mode, the counter of PWM repeats up/down count. In fact, the effective duty and period becomes twofold of the register set values. (Figure 1.38, Figure 11.39 referred) MAX MAX 00H 00H Duty, Period Update MAX MAX 00H 00H T4CNT 00H Normal PWM mode Duty Period MAX MAX Duty, Period Update MAX T4CNT 00H 00H Back-to-Back mode 00H Duty Duty Period Non Back-to-Back mode Period Back-to-Back mode Figure 11.38 Example of PWM Output Waveform T4CR = 03H (2us) T4PPRH = 00H T4PPRL = 0BH T4ADRH = 00H T4ADRL = 05H Duty match detect Start down Counter Duty match detect Start up Counter Source Clock (fX) T4CNT 00 01 02 03 04 05 06 07 08 09 0A 0B 0B 0A 09 08 07 06 05 04 03 02 01 00 00 01 02 03 04 05 06 07 08 P02/PWM4AA POLAA = 1 Duty Cycle (1+05H)X2us = 12us Duty Cycle Duty Cycle (1+05H)X2us = 12us (1+05H)X2us = 12us Period Cycle (1+0BH)X2us = 26us  38.46kHz Period Cycle (1+0BH)X2us = 26us  38.46kHz Figure 11.39 Example of PWM waveform in Back-to-Back mode at 4 MHz PS029902-0212 PRELIMINARY 151 Z51F3220 Product Specification Duty, Period Update MAX MAX MAX T4CNT 00H 00H Back-to-Back mode 00H Duty1 Duty2 Period1 Duty3 Period2 Period3 Interrupt Timing Overflow INT. Overflow INT. Bottom INT. Overflow INT. Figure 11.40 Example of Phase Correction and Frequency correction of PWM External Sync If using ESYNC bit of T4PCR1 register, it is possible to synchronize the output of PWM from external signal. If ESYNC bit sets to ‘1’, the external signal moves to PWM module through the BLNK pin. If BLNK signal is low, immediately PWM output becomes a reset value, and internal counter becomes reset. If BLNK signal returns to ‘1’, the counter is started again and PWM output is normally generated. (Figure 11.41 referred) PWM Halt If using PHLT bit of T4PCR1 register, it is possible to stop PWM operation by the software. During PHLT bit being ‘1’, PWM output becomes a reset value, and internal counter becomes reset as 0. Without changing PWM setting, temporarily it is able to stop PWM. In case of T4CNT, when stopping counter, PWM output pin remains before states. But if PHLT bit sets to ‘1’, PWM output pin has reset value. T4PCR1 = 40H (EYNC=1) T4PPRH = 00H T4PPRL = 2AH T4ADRH = 00H T4ADRL = 12H BLNK “0” PWM STOP BLNK “1” PWM Restart Source Clock (fx) T4 P02/PWM POLAA = 1 00 01 02 12 13 14 2A 00 01 02 00 00 00 01 02 03 12 13 14 00 12 13 14 2A 00 01 02 Counter Stop BLNK ESYNC = 1 Figure 11.41 Example of PWM External Synchronization with BLNK Input PS029902-0212 PRELIMINARY 152 Z51F3220 Product Specification FORCE Drive ALL Channel with A-ch mode If FORCA bit sets to ‘1’, it is possible to enable or disable all PWM output pins through PWM outputs which occur from A-ch duty counter. It is noted that the inversion outputs of A, B, C channel have the same A-ch output waveform. According to POLAA/BB/CC, it is able to control the inversion of outputs. T4PCR2 FORCA - 1 - PAAOE PABOE PBAOE PBBOE PCAOE PCBOE X XX X ADDRESS : 1004H (ESFR) INITIAL VALUE : 0-00_0000B XX PWMA PAAOE PWM4AA PABOE PWM4AB PBAOE PWM4BA PBBOE PWM4BB ※C-ch operation is the same with channel A and B waveform Figure 11.42 Example of Force Drive All Channel with A-ch PS029902-0212 PRELIMINARY 153 Z51F3220 Product Specification FORCE 6-Ch Drive If FORCA bit sets to ‘0’, it is possible to enable or disable PWM output pin and inversion output pin generated through the duty counter of each channel. The inversion output is the reverse phase of the PWM output. A AA/AB output of the A-channel duty register, a BA/BB output of the B-channel duty register, a CA/CB output of the Cchannel duty register are controlled respectively. If the UALL bit is set to ‘1’, it is updated B/C channel duty at the same time, when it is written by a A-channel duty register. T4PCR2 FORCA - 0 - PAAOE PABOE PBAOE PBBOE PCAOE PCBOE XX X X X ADDRESS : 1004H (ESFR) INITIAL VALUE : 0-00_0000B X PWMA PAAOE PWM4AA PABOE PWM4AB PWMB PBAOE PWM4BA PBBOE PWM4BB ※C-ch operation is the same with channel A and B waveform Figure 11.43 Example of Force Drive 6-ch Mode PS029902-0212 PRELIMINARY 154 Z51F3220 Product Specification PWM output Delay If using the T4DLYA, T4DLYB, T4DLYC register, it can delay PWM output based on the rising edge. At that time, it does not change the falling edge, so the duty is reduced as the time delay. In POLAA/BA/CA setting to ‘0’, the delay is applied to the falling edge. In POLAA/BA/CA setting to ‘1’, the delay is applied to the rising edge. It can produce a pair of Non-overlapping clock. The each channel is able to have 4-bit delay. As it can select the clock up to 1/8 divided clock using NOPS[1:0] the delay of its maximum 128 timer clock cycle is produced. PS029902-0212 PRELIMINARY 155 Z51F3220 Product Specification T4PCR2 T4PCR3 FORCA - PAAOE 0 - HZCLR POLBO XX XX T4DLYA T4DLYAA3 PABOE T4DLYAA2 00 PBAOE PBBOE PCAOE PCBOE X X X X POLAA POLAB POLBA POLBB POLCA POLCB 1 1 X X X X T4DLYAA1 T4DLYAA0 T4DLYAB3 T4DLYAB2 T4DLYAB1 T4DLYAB0 0 0 0 0 0 0 PAAOE PABOE PBAOE PBBOE PCAOE PCBOE X X X X POLBA POLBB POLCA POLCB X X X X ADDRESS : 1004H (ESFR) INITIAL VALUE : 0-00_0000B ADDRESS : 1005H (ESFR) INITIAL VALUE : 0000_0000B ADDRESS : 1010H (ESFR) INITIAL VALUE : 0000_0000B PWMA PWM4AA PWM4AB T4PCR2 T4PCR3 FORCA - 0 - HZCLR POLBO X T4DLYA T4DLYAA3 XX POLAA X POLAB 11 T4DLYAA2 00 T4DLYAA1 T4DLYAA0 T4DLYAB3 T4DLYAB2 T4DLYAB1 T4DLYAB0 1 0 0 1 0 0 PABOE PBAOE PBBOE PCAOE PCBOE X X X X POLBA POLBB POLCA POLCB X X X X ADDRESS : 1004H (ESFR) INITIAL VALUE : 0-00_0000B ADDRESS : 1005H (ESFR) INITIAL VALUE : 0000_0000B ADDRESS : 1010H (ESFR) INITIAL VALUE : 0000_0000B PWMA T4DLYAA = 02H PWM4AA PWM4AB T4DLYAB = 04H T4PCR2 T4PCR3 FORCA - 0 - HZCLR POLBO PAAOE XX POLAA XX T4DLYA T4DLYAA3 POLAB 01 T4DLYAA2 00 T4DLYAA1 T4DLYAA0 T4DLYAB3 T4DLYAB2 T4DLYAB1 T4DLYAB0 1 0 0 1 0 0 ADDRESS : 1004H (ESFR) INITIAL VALUE : 0-00_0000B ADDRESS : 1005H (ESFR) INITIAL VALUE : 0000_0000B ADDRESS : 1010H (ESFR) INITIAL VALUE : 0000_0000B PWMA T4DLYAA = 02H PWM4AA PWM4AB T4DLYAB = 04H ※B-ch and C-ch operation is the same with channel A waveform PS029902-0212 PRELIMINARY 156 Z51F3220 Product Specification Figure 11.44 Example of PWM Delay 11.8.7 Block Diagram FLAG 0 (EIFLAG0.1) T4MS To interrupt block Clear 8-bit T imer 4 Capture Register EINT1 INT_ ACK T4CAPR (8Bit) 2 T4O EIPOL 0L[3:2 ] T4CK[3:0] 8-bit T imer 4 D ata R egister T4DR (8Bit) 4 P r e s c a l e r fx Comparator fx/1 fx/2 T4 CN fx/4 To interrupt block Match Clear fx/8 M U X T4CNT (8Bit) Clear 8-bit T imer 4 Counter fx/16384 T4ST EC3 P r e s c a l e r fx T3ST fx/2 fx/4 8-bit T imer 3 Counter M U X fx/8 fx/32 Clear T3CNT (8Bit) fx/128 Clear Clear fx/512 Match T3CN fx/2048 INT_ACK T3IFR To interrupt block Comparator 3 T3DR (8Bit) T3CK[2:0] EIPOL 0L[1:0 ] 8-bit T imer 3 D ata R egister T3 O 2 T3CAPR (8 Bit) EINT0 8-bit T imer 3 Capture Register INT_ACK Clear T3MS FLAG 0 (EIFLAG0.0) To interrupt block NOTE: Do not set to “1111b” in the T4CK[3:0], when two 8-bit timer 3/4 modes. Figure 11.45 Two 8-Bit Timer 3, 4 Block Diagram PS029902-0212 PRELIMINARY 157 Z51F3220 Product Specification EC3 fx T3ST fx/2 P r e s c a l e r fx/4 16-bit T imer 3 Counter M U X fx/8 fx/32 Clear T4CNT/T3CNT (16Bit) MSB LSB fx/128 Clear fx/512 Clear Match T3CN fx/2048 INT_ACK T3IFR To interrupt block Comparator 3 T4DR/T3DR (16Bit) MSB LSB 16-bit T imer 3 D ata Register T3CK[2:0] EIPOL 0L[1:0 ] T3 O 2 T4CAPR/T3CAPR (16 Bit) MSB LSB EINT0 INT_ACK 16-bit T imer 3 Capture R egister Clear T3MS FLAG 0 (EIFLAG0.0) To interrupt block NOTE) The T4CR.7 bit (16BIT) should be set to ‘1’ and the T4CK[3:0] should be set to “1111b”. Figure 11.46 16-Bit Timer 3 Block Diagram Timer 4 PWM Period Register T4CK[3:0] T4PPRH/T4PPRL (10Bit) 4 fx/1 T4CN fx/2 Comparator fx/4 10 -bit C ounter 2Bit + T4CNT fx/8 fx P r e s c a l e r T4ST Bottom (Underflow) A M atch B M atch C Match Period M atch fx/16 Control Up/Down A M atch fx/32 fx/64 fx/128 fx/256 fx/512 M U X 10-bit A Data Register T4ADRH/T4ADRL B M atch fx/2048 fx/8192 fx/16384 To interrupt block PWM Output Control PWM Delay Control A -ch A-ch PWM Output Control PWM Delay Control B-ch B-ch PWM Output Control PWM Delay Control C-ch C-ch PWM4AA PWM4AB Comparator fx/1024 fx/4096 Interrupt Generator PWM4 BA PWM4 BB Comparator 10-bit B Data Register T4BDRH/T4BDRL C Match PWM4 CA PWM4 CB Comparator 10-bit C Data Register T4CDRH/T4CDRL NOTE: Do not set to “1111b” in the T4CK[3:0], when two 8-bit timer 3/4 modes. Figure 11.47 10-Bit PWM Timer 4 Block Diagram PS029902-0212 PRELIMINARY 158 Z51F3220 Product Specification 11.8.8 Register Map Table 11-14 Timer 3, 4 Register Map Name T3CNT 1001H Address Dir (ESFR) R T3DR 1001H (ESFR) T3CAPR 1001H (ESFR) T3CR 1000H Default Description 00H Timer 3 Counter Register W FFH Timer 3 Data Register R 00H Timer 3 Capture Data Register (ESFR) R/W 00H Timer 3 Control Register T4PPRH 1009H (ESFR) R/W 00H Timer 4 PWM Period High Register T4PPRL 1008H (ESFR) R/W FFH Timer 4 PWM Period Low Register T4ADRH 100BH (ESFR) R/W 00H Timer 4 PWM A Duty High Register T4ADRL 100AH (ESFR) R/W 7FH Timer 4 PWM A Duty Low Register (ESFR) R/W 00H Timer 4 PWM B Duty High Register T4BDRH 100DH T4BDRL 100CH (ESFR) R/W 7FH Timer 4 PWM B Duty Low Register 100FH (ESFR) R/W 00H Timer 4 PWM C Duty High Register T4CDRL 100EH (ESFR) R/W 7FH Timer 4 PWM C Duty Low Register T4DLYA 1010H (ESFR) R/W 00H Timer 4 PWM A Delay Register T4DLYB 1011H (ESFR) R/W 00H Timer 4 PWM B Delay Register (ESFR) R/W 00H Timer 4 PWM C Delay Register T4CDRH T4DLYC 1012H T4DR 1013H T4CAPR (ESFR) 1014H (ESFR) R/W FFH Timer 4 Data Register R 00H Timer 4 Capture Data Register T4CNT 1015H (ESFR) R 00H Timer 4 Counter Register T4CR 1002H (ESFR) R/W 00H Timer 4 Control Register T4PCR1 1003H (ESFR) R/W 00H Timer 4 PWM Control Register 1 T4PCR2 1004H (ESFR) R/W 00H Timer 4 PWM Control Register 2 T4PCR3 1005H (ESFR) R/W 00H Timer 4 PWM Control Register 3 T4ISR 1006H (ESFR) R/W 00H Timer 4 Interrupt Status Register T4MSK 1007H (ESFR) R/W 00H Timer 4 Interrupt Mask Register PS029902-0212 PRELIMINARY 159 Z51F3220 Product Specification 11.8.8.1 Timer/Counter 3 Register Description The timer/counter 3 register consists of timer 3 counter register (T3CNT), timer 3 data register (T3DR), timer 3 capture data register (T3CAPR) and timer 3 control register (T3CR). 11.8.8.2 Register Description for Timer/Counter 3 T3CNT (Timer 3 Counter Register: Read Case, Timer mode only) : 1001H (ESFR) 7 6 5 4 3 2 1 0 T3CNT7 T3CNT6 T3CNT5 T3CNT4 T3CNT3 T3CNT2 T3CNT1 T3CNT0 R R R R R R R T3CNT[7:0] R Initial value : 00H T3 Counter T3DR (Timer 3 Data Register: Write Case) : 1001H (ESFR) 7 6 5 4 3 2 1 0 T3DR7 T3DR6 T3DR5 T3DR4 T3DR3 T3DR2 T3DR1 T3DR0 W W W W W W W W Initial value : FFH T3DR[7:0] T3 Data T3CAPR (Timer 3 Capture Data Register: Read Case, Capture mode only) : 1001H (ESFR) 7 6 5 4 3 2 1 0 T3CAPR7 T3CAPR 6 T3CAPR 5 T3CAPR 4 T3CAPR 3 T3CAPR 2 T3CAPR 1 T3CAPR 0 R R R R R R R T3CAPR[7:0] PS029902-0212 R Initial value : 00H T3 Capture Data PRELIMINARY 160 Z51F3220 Product Specification T3CR (Timer 3 Control Register) : 1000H (ESFR) 7 6 5 4 3 2 1 0 T3EN – T3MS T3CK2 T3CK1 T3CK0 T3CN T3ST R/W – R/W R/W R/W R/W R/W T3EN T3MS T3CK[2:0] T3CN Control Timer 3 0T imer 3 disable 1 Ti mer 3 enable Control Timer 3 Operation Mode 0 Timer/counter mode (T3O: toggle at match) 1 Capture mode (the match interrupt can occur) Select Timer 3 clock source. fx is main system clock frequency T3CK2 T3CK1 T3 CK0 De scription 0 00f x/2 0 01f x/4 0 10f x/8 0 11f x/32 1 00f x/128 1 01f x/512 1 10f x/2048 1 1 1 Ex ternal Clock (EC3) Control Timer 3 Count Pause/Continue 0T emporary count stop 1 Con T3ST R/W Initial value : 00H tinue count Control Timer 3 Start/Stop 0 Co unter stop 1 Clear counter and start NOTE) Refer to the external interrupt flag 1 register (EIFLAG1) tor the T3 interrupt flag. PS029902-0212 PRELIMINARY 161 Z51F3220 Product Specification 11.8.8.3 Timer/Counter 4 Register Description The timer/counter 4 register consists of timer 4 PWM period high/low register (T4PPRH/L), timer 4 PWM A duty high/low register (T4ADRH/L), timer 4 PWM B duty high/low register (T4BDRH/L), ), timer 4 PWM C duty high/low register (T4CDRH/L), timer 4 PWM A delay register (T4DLYA), timer 4 PWM B delay register (T4DLYB), timer 4 PWM C delay register (T4DLYC), timer 4 data register (T4DR), timer 4 capture data register (T4CAPR), timer 4 counter register (T4CNT), timer 4 control register (T4CR), timer 4 PWM control register 1 (T4PCR1), timer 4 PWM control register 2 (T4PCR2), timer 4 PWM control register 3 (T4PCR3), timer 4 interrupt status register (T4ISR) and timer 4 interrupt mask register (T4MSK). 11.8.8.4 Register Description for Timer/Counter 4 T4PPRH (Timer 4 PWM Period High Register : 6-ch PWM mode only) : 1009H (ESFR) 7 6 5 4 3 2 1 0 – – – – – – T4PPRH1 T4PPRH0 – – – – – – R/W T4PPRL[1:0] R/W Initial value : 00H T4 PWM Period Data High Byte T4PPRL (Timer 4 PWM Period Low Register : 6-ch PWM mode only) : 1008H (ESFR) 7 6 5 4 3 2 1 0 T4PPRL7 T4PPRL6 T4PPRL5 T4PPRL4 T4PPRL3 T4PPRL2 T4PPRL1 T4PPRL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH T4PPRL[7:0] T4 PWM Period Data Low Byte T4ADRH (Timer 4 PWM A Duty High Register : 6-ch PWM mode only) : 100BH (ESFR) 7 6 5 4 3 2 1 0 – – – – – – T4ADRH1 T4ADRH0 – – – – – – R/W T4ADRL[1:0] R/W Initial value : 00H T4 PWM A Duty Data High Byte T4ADRL (Timer 4 PWM A Duty Low Register : 6-ch PWM mode only) : 100AH (ESFR) 7 6 5 4 3 2 1 0 T4ADRL7 T4ADRL6 T4ADRL5 T4ADRL4 T4ADRL3 T4ADRL2 T4ADRL1 T4ADRL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 7FH T4ADRL[7:0] PS029902-0212 T4 PWM A Duty Data Low Byte PRELIMINARY 162 Z51F3220 Product Specification T4BDRH (Timer 4 PWM B Duty High Register : 6-ch PWM mode only) : 100DH (ESFR) 7 6 5 4 3 2 1 0 – – – – – – T4BDRH1 T4BDRH0 – – – – – – R/W T4BDRL[1:0] R/W Initial value : 00H T4 PWM B Duty Data High Byte T4BDRL (Timer 4 PWM B Duty Low Register : 6-ch PWM mode only) : 100CH (ESFR) 7 6 5 4 3 2 1 0 T4BDRL7 T4BDRL6 T4BDRL5 T4BDRL4 T4BDRL3 T4BDRL2 T4BDRL1 T4BDRL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 7FH T4BDRL[7:0] T4 PWM B Duty Data Low Byte T4CDRH (Timer 4 PWM C Duty High Register : 6-ch PWM mode only) : 100FH (ESFR) 7 6 5 4 3 2 1 0 – – – – – – T4CDRH1 T4CDRH0 – – – – – – R/W T4CDRL[1:0] R/W Initial value : 00H T4 PWM C Duty Data High Byte T4CDRL (Timer 4 PWM C Duty Low Register : 6-ch PWM mode only) : 100EH (ESFR) 7 6 5 4 3 2 1 0 T4CDRL7 T4CDRL6 T4CDRL5 T4CDRL4 T4CDRL3 T4CDRL2 T4CDRL1 T4CDRL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 7FH T4CDRL[7:0] T4 PWM C Duty Data Low Byte T4DLYA (Timer 4 PWM A Delay Register : 6-ch PWM mode only) : 1010H (ESFR) 7 6 5 4 3 2 1 0 T4DLYAA3 T4DLYAA2 T4DLYAA1 T4DLYAA0 T4DLYAB3 T4DLYAB2 T4DLYAB1 T4DLYAB0 R/W R/W R/W R/W R/W R/W R/W T4DLYAA[3:0] PWM4AA Delay Data (Rising edge only) T4DLYAB[3:0] PWM4AB Delay Data (Rising edge only) R/W Initial value : 00H T4DLYB (Timer 4 PWM B Delay Register : 6-ch PWM mode only) : 1011H (ESFR) 7 6 5 4 3 2 1 0 T4DLYBA3 T4DLYBA2 T4DLYBA1 T4DLYBA0 T4DLYBB3 T4DLYBB2 T4DLYBB1 T4DLYBB0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 00H T4DLYBA[3:0] PWM4BA Delay Data (Rising edge only) T4DLYBB[3:0] PWM4BB Delay Data (Rising edge only) PS029902-0212 PRELIMINARY 163 Z51F3220 Product Specification T4DLYC (Timer 4 PWM C Delay Register : 6-ch PWM mode only) : 1012H (ESFR) 7 6 5 4 3 2 1 0 T4DLYCA3 T4DLYCA2 T4DLYCA1 T4DLYCA0 T4DLYCB3 T4DLYCB2 T4DLYCB1 T4DLYCB0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 00H T4DLYCA[3:0] PWM4CA Delay Data (Rising edge only) T4DLYCB[3:0] PWM4CB Delay Data (Rising edge only) T4DR (Timer 4 Data Register: Timer and Capture mode only) : 1013H (ESFR) 7 6 5 4 3 2 1 0 T4DR7 T4DR6 T4DR5 T4DR4 T4DR3 T4DR2 T4DR1 T4DR0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH T4DR[7:0] T4 Data T4CAPR (Timer 4 Capture Data Register: Read Case, Capture mode only) : 1014H (ESFR) 7 6 5 4 3 2 1 0 T4CAPR7 T4CAPR6 T4CAPR5 T4CAPR4 T4CAPR3 T4CAPR2 T4CAPR1 T4CAPR0 R R R R R R R T4CAPR[7:0] R Initial value : 00H T4 Capture Data T4CNT (Timer 4 Counter Register: Read Case, Timer mode only) : 1015H (ESFR) 7 6 5 4 3 2 1 0 T4CNT7 T4CNT6 T4CNT5 T4CNT4 T4CNT3 T4CNT2 T4CNT1 T4CNT0 R R R R R R R T4CNT[7:0] PS029902-0212 R Initial value : 00H T4 Counter PRELIMINARY 164 Z51F3220 Product Specification T4CR (Timer 4 Control Register) : 1002H (ESFR) 7 6 5 4 3 2 1 0 16BIT T4MS T4CN T4ST T4CK3 T4CK2 T4CK1 T4CK0 R/W R/W R/W R/W R/W R/W R/W 16BIT T4MS T4CN Select Two 8-bit or 16-bit Mode for Timer 3/4 0 Two 8-bit Timer 3/4 1 16-bit Timer 3 Control Timer 4 Operation Mode 0 Timer/counter mode (T4O: toggle at match) 1 Capture mode (the match interrupt can occur) Control Timer 4 Count Pause/Continue 0T emporary count stop 1 Con T4ST tinue count Control Timer 4 Start/Stop 0 Co unter stop 1 Clear T4CK[3:0] PS029902-0212 R/W Initial value : 00H counter and start Select Timer 4 clock source. fx is main system clock frequency T4CK3 T4CK2 T4 CK1 T4 CK0 De scription 0 000f x/1 0 001f x/2 0 010f x/3 0 011f x/8 0 100f x/16 0 101f x/32 0 110f x/64 0 111f x/128 1 000f x/256 1 001f x/512 1 010f x/1024 1 011f x/2048 1 100f x/406 1 101f x/8192 1 110f x/16384 1 1 1 PRELIMINARY 1 Timer 3 clock (only 16-Bit Timer 3) 165 Z51F3220 Product Specification T4PCR1 (Timer 4 PWM Control Register 1) : 1003H (ESFR) 7 6 5 4 3 2 1 0 PWM4E ESYNC BMOD PHLT UPDT UALL NOPS1 NOPS0 R/W R/W R/W R/W R/W R/W R/W PWM4E ESYNC BMOD PHLT UPDT UALL NOPS[1:0] R/W Initial value : 00H Control Timer 4 Mode 0 Select timer/counter or capture mode of Timer 4 1 Select 10-bit PWM mode of Timer 4 Select the Operation of External Sync with the BLNK pin 0 Disable external sync operation 1 Enable external sync operation (The al l PWM4xA/PWM4xB pi ns are high-impedance o utputs on rising edge of the BLNK input pin. Where x= A, B and C) Control Back-to-Back Mode Operation 0 Disable back-to-back mode (up count only) 1 Enable back-to-back mode (up/down count only) Control Timer 4 PWM Operation 0 Run 10-bit PWM 1 Stop 10-bit PWM (counter hold and output disable) Select the Update Timer of T4PPR/T4ADR/T4BDR/T4CDR 0 Update at period match of T4CNT and T4PPR 1 Update at any time when written Control Update All Duty Registers (T4ADR/T4BDR/T4CDR) 0 Write a duty register separately 1 Wrtie all duty registers via Timer 4 PWM A dury register (T4ADR) Select on-Overlap Prescaler NOPS1 NOPS0 Description 00 fPWM/1 01 fPWM /2 10 fPWM /4 11 fPWM /8 NOTE) Where the fPWM is the clock frequency of the Timer 4 PWM. PS029902-0212 PRELIMINARY 166 Z51F3220 Product Specification T4PCR2 (Timer 4 PWM Control Register 2) : 1004H (ESFR) 7 6 5 4 3 2 1 0 FORCA – PAAOE PABOE PBAOE PBBOE PCAOE PCBOE R/W – R/W R/W R/W R/W R/W FORCA PAAOE PABOE PBAOE PBBOE PCAOE Control The PWM outputs Mode 0 6-c hannel mode (The PWM4xA/PWM4xB pins are output according to the T4xDR registers, respectively. Where x = A, B and C) 1 Fo rce A-channel mode (The all PWM4xA/PWM4xB pins are output according to the only T4ADR registers. Where x = A, B and C) Select Channel PWM4AA Operation 0 Disable PWM4AA output 1 Enable PWM4AA output Select Channel PWM4AB Operation 0 Disable PWM4AB output 1 Enable PWM4AB output Select Channel PWM4BA Operation 0 Disable PWM4BA output 1 Enable PWM4BA output Select Channel PWM4BB Operation 0 Disable PWM4BB output 1 Enable PWM4BB output Select Channel PWM4CA Operation 0 Di sable PWM4CA output 1 Ena PCBOE ble PWM4CA output Select Channel PWM4CB Operation 0 Di sable PWM4CB output 1 Ena PS029902-0212 R/W Initial value : 00H ble PWM4CB output PRELIMINARY 167 Z51F3220 Product Specification T4PCR3 (Timer 4 PWM Control Register 3) : 1005H (ESFR) 7 6 5 4 3 2 1 0 HZCLR POLBO POLAA POLAB POLBA POLBB POLCA POLCB R/W R/W R/W R/W R/W R/W R/W HZCLR High-Impedance Output Clear Bit 0 No effect 1 Clear POLBO POLAA POLAB POLBA POLBB POLCA POLCB PS029902-0212 R/W Initial value : 00H high-impedance output (The PWM4xA/PWM4xB pins are back to output and this bit is automatically cleared to logic ‘0’. where x = A, B and C) Configure PWM 4AB/PWM4BB/PWMCB Channel Po larity When th ese pins are disabled 0 These p ins ar e output according t o t he p olarity setting when disable (POLAB/POLBB/POLCB bits) 1 These pins are same level as the PWM4xA pins regardless of the polarity setting when disable (POLAB/POLBB/POLCB bits, where x = A, B and C) Configure PWM4AA Channel Polarity 0 Start at high level (This pin is low level when disable) 1 Start at low level (This pin is high level when disable) Configure PWM4AB Channel Polarity 0 Non-inversion signal of PWM4AA pin 1 Inversion signal of PWM4AA pin Configure PWM4AA Channel Polarity 0 Start at high level (This pin is low level when disable) 1 Start at low level (This pin is high level when disable) Configure PWM4AB Channel Polarity 0 Non-inversion signal of PWM4BA pin 1 Inversion signal of PWM4BA pin Configure PWM4CA Channel Polarity 0 Start at high level (This pin is low level when disable) 1 Start at low level (This pin is high level when disable) Configure PWM4CB Channel Polarity 0 Non-inversion signal of PWM4CA pin 1 Inversion signal of PWM4CA pin PRELIMINARY 168 Z51F3220 Product Specification T4ISR (Timer 4 Interrupt Status Register) : 1006H (ESFR) 7 6 5 4 3 2 1 0 IOVR IBTM ICMA ICMB ICMC – – – R/W R/W R/W R/W R/W – – – Initial value : 00H Timer 4 Overflow Interrupt Status, Write ‘1’ to this bit for clear IOVR 0O verflow occurrence 1O verflow no occurrence Timer 4 Bottom Interrupt Status, Write ‘1’ to this bit for clear (In the Back-to-Back mode) IBTM 0 Bot tom occurrence 1 Bo ttom no occurrence Timer 4 Compare Match or PWM A-ch Match Interrupt Staus, Write ‘1’ to this bit for clear ICMA 0 Compare match or PWM A-ch match occurrence 1 Compare match or PWM A-ch match no occurrence Timer 4 PWM B-ch Match Interrupt Status, Write ‘1’ to this bit for clear ICMB 0 PWm B-ch match occurrence 1 PWm B-ch match no occurrence Timer 4 PWM C-ch Match Interrupt Status, Write ‘1’ to this bit for clear ICMC 0 PWm C-ch match occurrence 1 PWm C-ch match no occurrence T4MSK (Timer 4 Interrupt Mask Register) : 1007H (ESFR) 7 6 5 4 3 2 1 0 OVRMSK BTMMSK CMAMSK CMBMSK CMCMSK – – – R/W R/W R/W R/W R/W – – OVRMSK Control Timer 4 Overflow Interrupt 0 Disbl 1 BTMMSK Control Timer 4 Bottom Interrupt 1 CMBMSK CMCMSK PS029902-0212 e overflow interrupt Enable overflow interrupt 0 Disbl CMAMSK – Initial value : 00H e bottom interrupt Enable bottom interrupt Control Timer 4 Compare Match or PWM A-ch Match Interrupt 0 Disble compare match or PWM A-ch match interrupt 1 Enable compare match or PWM A-ch match interrupt Control Timer 4 PWM B-ch Match Interrupt 0 Disble PWM B-ch match interrupt 1 Enable PWM B-ch match interrupt Control Timer 4 PWM C-ch Match Interrupt 0 Disble PWM C-ch match interrupt 1 Enable PWM C-ch match interrupt PRELIMINARY 169 Z51F3220 Product Specification 11.9 Buzzer Driver 11.9.1 Overview The Buzzer consists of 8 bit counter, buzzer data register (BUZDR), and buzzer control register (BUZCR). The Square Wave (61.035Hz~125.0 kHz @8MHz) is outputted through P13/SEG17/AN10/EC1/BUZO pin. The buzzer data register (BUZDR) controls the bsuzzer frequency (look at the following expression). In buzzer control register (BUZCR), BUCK[1:0] selects source clock divided by prescaler. f BUZ (Hz)  Oscillator Frequency 2  Prescaler Ratio  (BUZDR  1) Table 11-15 Buzzer Frequency at 8 MHz BUZDR[7:0] Buzzer Frequency (kHz) BUZCR[2:1]=00 BUZCR[2:1]=01 0000_0000 125kHz 0000_0001 6 2.5kHz …… BUZCR[2:1]=10 BUZCR[2:1]=11 62.5kHz 31.25kHz 15.625kH z 31.25kHz 15.625kHz 7.812kHz … … … 1111_1101 4 92.126Hz 246.063Hz 123.031Hz 61.515Hz 1111_1110 4 90.196Hz 245.098Hz 122.549Hz 61.274Hz 1111_1111 4 88.281Hz 244.141Hz 122.07Hz 61.035Hz 11.9.2 Block Diagram BUZEN fx/32 fx Pre scaler fx/64 fx/128 8-bit U p-Counter Clear Counter MUX fx/256 F/F 2 BUZO Comparator BUCK[1:0] BUZDR Figure 11.48 Buzzer Driver Block Diagram PS029902-0212 PRELIMINARY 170 Z51F3220 Product Specification 11.9.3 Register Map Table 11-16 Buzzer Driver Register Map Name Address Dir Default Description BUZDR 8FH R/W FFH Buzzer Data Register BUZCR 97H R/W 00H Buzzer Control Register 11.9.4 Buzzer Driver Register Description Buzzer driver consists of buzzer data register (BUZDR) and buzzer control register (BUZCR). 11.9.5 Register Description for Buzzer Driver BUZDR (Buzzer Data Register) : 8FH 7 6 5 4 3 2 1 0 BUZDR7 BUZDR6 BUZDR5 BUZDR4 BUZDR3 BUZDR2 BUZDR1 BUZDR0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH BUZDR[7:0] This bits control the Buzzer frequency Its resolution is 00H ~ FFH BUZCR (Buzzer Control Register) : 97H 7 6 5 4 3 2 1 0 – – – – – BUCK1 BUCK0 BUZEN – – – – – R/W R/W BUCK[1:0] BUZEN R/W Initial value : 00H Buzzer Driver Source Clock Selection BUCK1 BUCK0 Description 00 fx/32 01 fx/64 10 fx/128 11 fx/256 Buzzer Driver Operation Control 0 Buz zer Driver disable 1 Buz zer Driver enable NOTE) fx: System clock oscillation frequency. PS029902-0212 PRELIMINARY 171 Z51F3220 Product Specification 11.10 SPI 2 11.10.1 Overview There is serial peripheral interface (SPI 2) one channel in Z51F3220. The SPI 2 allows synchronous serial data transfer between the external serial devices. It can do Full-duplex communication by 4-wire (MOSI2, MISO2, SCK2, SS2), support master/slave mode, can select serial clock (SCK2) polarity, phase and whether LSB first data transfer or MSB first data transfer. 11.10.2 Block Diagram fx SPIEN fx/2 P r e s c a l e r fx/4 fx/8 M U X M U X fx/16 fx/32 Edge Detector SPI Control Circuit fx/64 fx/128 CPOL MS CPHA WCOL SPIIFR To interrupt block Clear 3 INT_ ACK SPICR[2 :0] MS SCK Control SCK2 MISO2 M U X FXCH MS MOSI2 D E P 8-bit Shif t Register FLSB 8 SPIDR (8-bit) SS Control SS2 SSENA MS Internal Bus Line Figure 11.49 SPI 2 Block Diagram PS029902-0212 PRELIMINARY 172 Z51F3220 Product Specification 11.10.3 Data Transmit / Receive Operation User can use SPI 2 for serial data communication by following step 1. Select SPI 2 operation mode(master/slave, polarity, phase) by control register SPICR. 2. When the SPI 2 is configured as a Master, it selects a Slave by SS2 signal (active low). When the SPI 2 is configured as a Slave, it is selected by SS2 signal incoming from Master 3. When the user writes a byte to the data register SPIDR, SPI 2 will start an operation. 4. In this time, if the SPI 2 is configured as a Master, serial clock will come out of SCK2 pin. And Master shifts the eight bits into the Slave (transmit), Slave shifts the eight bits into the Master at the same time (receive). If the SPI 2 is configured as a Slave, serial clock will come into SCK2 pin. And Slave shifts the eight bits into the Master (transmit), Master shifts the eight bits into the Slave at the same time (receive). 5. When transmit/receive is done, SPIIFR bit will be set. If the SPI 2 interrupt is enabled, an interrupt is requested. And SPIIFR bit is cleared by hardware when executing the corresponding interrupt. If SPI 2 interrupt is disable, SPIIFR bit is cleared when user read the status register SPISR, and then access (read/write) the data register SPIDR. 11.10.4 SS2 pin function 1. When the SPI 2 is configured as a Slave, the SS2 pin is always input. If LOW signal come into SS2 pin, the SPI 2 logic is active. And if ‘HIGH’ signal come into SS2 pin, the SPI 2 logic is stop. In this time, SPI 2 logic will be reset, and invalidated any received data. 2. When the SPI 2 is configured as a Master, the user can select the direction of the SS2 pin by port direction register (P17IO). If the SS2 pin is configured as an output, user can use general P17IO output mode. If the SS2 pin is configured as an input, ‘HIGH’ signal must come into SS2 pin to guarantee Master operation. If ‘LOW’ signal come into SS2 pin, the SPI 2 logic interprets this as another master selecting the SPI 2 as a slave and starting to send data to it. To avoid bus contention, MSB bit of SPICR will be cleared and the SPI 2 becomes a Slave and then, SPIIFR bit of SPISR will be set, and if the SPI 2 interrupt is enabled, an interrupt is requested. NOTES) - When the SS2 pin is configured as an output at Master mode, SS2 pin’s output value is defined by user’s software (P17IO). Before SPICR setting, the direction of SS2 pin must be defined - If you don’t need to use SS2 pin, clear the SSENA bit of SPISR. So, you can use disabled pin by P17IO freely. In this case, SS2 signal is driven by ‘HIGH’ or ‘LOW’ internally. In other words, master is ‘HIGH’, salve is ‘LOW’ - When SS2 pin is configured as input, if ‘HIGH’ signal come into SS2 pin, SS_HIGH flag bit will be set. And you can clear it by writing ‘0’. PS029902-0212 PRELIMINARY 173 Z51F3220 Product Specification 11.10.5 SPI 2 Timing Diagram SCK2 (CPOL = 0) SCK2 (CPOL = 1) MISO2/MOSI2 (Output) D0 D1 D2 D3 D4 D5 D6 D7 MOSI2/MISO2 (Input) D0 D1 D2 D3 D4 D5 D6 D7 SS2 SPIIFR Figure 11.50 SPI 2 Transmit/Receive Timing Diagram at CPHA = 0 SCK2 (CPOL = 0) SCK2 (CPOL = 1) MISO2/MOSI2 (Output) D0 D1 D2 D3 D4 D5 D6 D7 MOSI2/MISO2 (Input) D0 D1 D2 D3 D4 D5 D6 D7 SS2 SPIIFR Figure 11.51 SPI 2 Transmit/Receive Timing Diagram at CPHA = 1 PS029902-0212 PRELIMINARY 174 Z51F3220 Product Specification 11.10.6 Register Map Table 11-17 SPI 2 Register Map Name SPISR Address Dir B7H Default R/W Description 00H SPI 2 Status Register SPIDR B6H R/W 00H SPI 2 Data Register SPICR B5H R/W 00H SPI 2 Control Register 11.10.7 SPI 2 Register Description The SPI 2 register consists of SPI 2 control register (SPICR), SPI 2 status register (SPISR) and SPI 2 data register (SPIDR) 11.10.8 Register Description for SPI 2 SPIDR (SPI 2 Data Register) : B6H 7 6 5 4 3 2 1 0 SPIDR7 SPIDR6 SPIDR5 SPIDR4 SPIDR3 SPIDR2 SPIDR1 SPIDR0 R/W R/W R/W R/W R/W R/W R/W SPIDR [7:0] PS029902-0212 R/W Initial value : 00H SPI 2 Data When it is written a byte to this data register, the SPI 2 will start an operation. PRELIMINARY 175 Z51F3220 Product Specification SPISR (SPI 2 Status Register) : B7H 7 6 5 4 3 2 1 0 SPIIFR WCOL SS_HIGH – FXCH SSENA – – R/W R R/W – R/W R/W – SPIIFR WCOL SS_HIGH FXCH When SPI 2 Interrupt occurs, th is bit becomes ‘1’. I F SP I 2 in terrupt is enable, this bit is auto cleared by INT_ACK signal. And if SPI 2 Interrupt is disable, this bit is cleared when the status register SPISR is read, and then access (read/write) the data register SPIDR 0 SPI 2 Interrupt no generation 1 SPI 2 Interrupt generation This bi t is set if any d ata are w ritten to the da ta register SPIDR during transfer. This bit is cleared when the status register SPI SR is read, and then access (read/write) the data register SPIDR 0 No collision 1 Coll ision When the SS2 pin is configured as input, if “HIGH” signal comes into the pin, this flag bit will be set. 0 Cleared when ‘0’ is written 1 No effect when ‘1’ is written SPI 2 port function exchange control bit. 0 No 1 SSENA effect Exchange MOSI2 and MISO2 function This bit controls the SS2 pin operation 0 Di 1 PS029902-0212 – Initial value : 00H sable Enable (The P17 should be a normal input) PRELIMINARY 176 Z51F3220 Product Specification SPICR (SPI 2 Control Register) : B5H 7 6 5 4 3 2 1 0 SPIEN FLSB MS CPOL CPHA DSCR SCR1 SCR0 R/W R/W R/W R/W R/W R/W R/W SPIEN This bit controls the SPI 2 operation 0 Disable SPI 2 operation 1 En FLSB MS CPOL CPHA DSCR SCR[2:0] PS029902-0212 R/W Initial value : 00H able SPI 2 operation This bit selects the data transmission sequence 0 MSB first 1 LSB first This bit selects whether Master or Slave mode 0 Slav e mode 1 Mas ter mode This two bits control the serial clock (SCK2) mode. Clock polarity(CPOL) bit determine SCK2’s value at idle mode. Clcok phase (CPHA) bit determine if data are sampled on the leading or trailing edge of SCK2. CPOL CPHA Leading edge T railing edge 0 0 Sample (Rising) Setup (Falling) 0 1 Setup (Rising) Sample (Falling) 1 0 Sample (Falling) Setup (Rising) 1 1 Setup (Falling) Sample (Rising) These three b its s elect the S CK2 r ate of th e device configured as a master. Wh en DSCR bit is written one, SCK2 will be do ubled in master mode. DSCR SCR1 SCR0 SCK2 frequency 00 0 fx/4 00 1 fx/16 01 0 fx/64 01 1 fx/128 10 0 fx/2 10 1 fx/8 11 0 fx/32 11 1 fx/64 PRELIMINARY 177 Z51F3220 Product Specification 11.11 12-Bit A/D Converter 11.11.1 Overview The analog-to-digital converter (A/D) allows conversion of an analog input signal to corresponding 12-bit digital value. The A/D module has eight analog inputs. The output of the multiplexer is the input into the converter which generates the result through successive approximation. The A/D module has four registers which are the A/D converter control high register (ADCCRH), A/D converter control low register (ADCCRL), A/D converter data high register (ADCDRH), and A/D converter data low register (ADCDRL). The channels to be converted are selected by setting ADSEL[3:0]. To execute A/D conversion, TRIG[2:0] bits should be set to ‘xxx’. The register ADCDRH and ADCDRL contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCDRH and ADCDRL, the A/D conversion status bit AFLAG is set to ‘1’, and the A/D interrupt is set. During A/D conversion, AFLAG bit is read as ‘0’. 11.11.2 Conversion Timing The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set up A/D conversion. Therefore, total of 58 clocks are required to complete a 12-bit conversion: When fxx/8 is selected for conversion clock with a 12MHz fxx clock frequency, one clock cycle is 0.66 μs. Each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit × 12 bits + set-up time = 58 clocks, 58 clock × 0.66 μs = 38.28 μs at 1.5 MHz (12 MHz/8) NOTE) The A/D converter needs at least 20 μs for conversion time. So you must set the conversion time more than 20 μs. PS029902-0212 PRELIMINARY 178 Z51F3220 Product Specification 11.11.3 Block Diagram TRIG[2:0] 3 ADSEL[3:0] (Select one input pin of the assigned pins) M U X Start Clock Selector ADCLK Input Pins AN0 AN1 AN2 AN14 AN15 Clear AFLAG M U X + Comparator - Control Logic ADCIFR To interrupt block Clear INT_ACK Reference Voltage REFSEL ADST T1 A match signal T4 overflow event signal T4 A match event signal T4 B match event signal T4 C match event signal MUX ADCDRH (R), ADCDRL (R) AVSS VDD AVREF Figure 11.52 12-bit ADC Block Diagram Analog Power Input AN0~ AN15 Analog Input 22uF 0~1000pF Figure 11.53 A/D Analog Input Pin with Capacitor PS029902-0212 AVREF Figure 11.54 A/D Power (AVREF) Pin with Capacitor PRELIMINARY 179 MC96F6432 11.11.4 ADC Operation Align bit set“0” ADCO11 ADCO10 ADCO9 ADCDRH7 ADCDRH6 ADCDRH5 ADCO8 ADCO7 ADCO6 ADCDRH4 ADCDRH3 ADCDRH2 ADCO5 ADCO4 ADCDRH1 ADCDRH0 ADCO3 ADCO2 ADCO1 ADCO0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRH[7:0] ADCDRL[7:4 ] ADCDRL[3 :0] bit s are “0 ” Align bit set“1” ADCO11 ADCO10 ADCO9 ADCDRH3 ADCDRH2 ADCDRH1 ADCO8 ADCO7 ADCDRH0 ADCDRL7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRL3 ADCDRL2 ADCDRL1 ADCDRL0 ADCDRL[7:0] ADCDRL[3:0] ADCDRL[7:4] bits are “0” Figure 11.55 ADC Operation for Align Bit PS029902-0212 PRELIMINARY 180 Z51F3220 Product Specification SET ADCCRH Select ADC Clock and Data Align Bit. SET ADCCRL ADC enable & Select AN Input Channel. Converting START N Start ADC Conversion. If Conversion is completed, AFLAG is set “1” and ADC interrupt is occurred. AFLAG = 1? Y After Conversion is completed, read ADCDRH and ADCDRL. READ ADCDRH/L ADC END Figure 11.56 A/D Converter Operation Flow 11.11.5 Register Map Table 11-18 ADC Register Map Name Address Dir Default Description ADCDRH 9FH R xxH A/D Converter Data High Register ADCDRL 9EH R xxH A/D Converter Data Low Register ADCCRH 9DH R/W 00H A/D Converter Control High Register ADCCRL 9CH R/W 00H A/D Converter Control Low Register 11.11.6 ADC Register Description The ADC register consists of A/D converter data high register (ADCDRH), A/D converter data low register (ADCDRL), A/D converter control high register (ADCCRH) and A/D converter control low register (ADCCRL). PS029902-0212 PRELIMINARY 182 Z51F3220 Product Specification 11.11.7 Register Description for ADC ADCDRH (A/D Converter Data High Register) : 9FH 7 6 5 4 3 2 1 0 ADDM11 ADDM10 ADDM9 ADDM8 ADDM7 ADDL11 ADDM6 ADDL10 ADDM5 ADDL9 ADDM4 ADDL8 R R R R R R R ADDM[11:4] MSB align, A/D Converter High Data (8-bit) ADDL[11:8] LSB align, A/D Converter High Data (4-bit) R Initial value : xxH ADCDRL (A/D Converter Data Low Register) : 9EH 7 6 5 4 3 2 1 0 ADDM3 ADDL7 ADDM2 ADDL6 ADDM1 ADDL5 ADDM0 ADDL4 ADDL3 ADDL2 ADDL1 ADDL0 R R R R R- R R ADDM[3:0] MSB align, A/D Converter Low Data (4-bit) ADDL[7:0] LSB align, A/D Converter Low Data (8-bit) R Initial value : xxH ADCCRH (A/D Converter High Register) : 9DH 7 6 5 4 3 2 1 0 ADCIFR – TRIG2 TRIG1 TRIG0 ALIGN CKSEL1 CKSEL0 R/W – R/W R/W R/W R/W R/W ADCIFR TRIG[2:0] When ADC interrupt o ccurs, t his b it becomes ‘1’. Fo r clearing b it, write ‘0’ to this bit or auto clear by INT_ACK signal. 0 ADC Interrupt no generation 1 ADC Interrupt generation A/D Trigger Signal Selection TRIG2 TR IG1 00 TRIG0 Description 0 ADST 0 0 1 Timer 1 A match signal 0 1 0 Timer 4 overflow event signal 0 1 1 Timer 4 A match event signal 1 0 0 Timer 4 B match event signal 1 0 1 Timer 4 C match event signal Other Values ALIGN CKSEL[1:0] PS029902-0212 R/W Initial value : 00H Not used A/D Converter data align selection. 0 MSB align (ADCDRH[7:0], ADCDRL[7:4]) 1 LSB align (ADCRDH[3:0], ADCDRL[7:0]) A/D Converter Clock selection CKSEL1 CKSEL0 Description 00 fx/1 01 fx/2 10 fx/4 11 fx/8 PRELIMINARY 183 Z51F3220 Product Specification ADCCRL (A/D Converter Counter Low Register) : 9CH 7 6 5 4 3 2 1 0 STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 R/W R/W R/W R R/W R/W R/W STBY ADST Control Operation of A/D (The ADC module is automatically disabled at stop mode) 0 ADC module disable 1 ADC module enable Control A/D Conversion stop/start. 0 No 1 REFSEL effect ADC Conversion Start and auto clear A/D Converter Reference Selection 0 In ternal Reference (VDD) 1 Ex AFLAG ADSEL[3:0] PS029902-0212 R/W Initial value : 00H ternal Reference (AVREF) A/D Converter Operation State (This bit is cleared to ‘0’ when the STBY bit is set to ‘0’ or when the CPU is at STOP mode) 0 During A/D Conversion 1 A/D Conversion finished A/D Converter input selection ADSEL3 ADSEL2 ADSEL1 ADSEL0 De scription 0 0 00 A N0 0 0 01 A N1 0 0 10 A N2 0 0 11 A N3 0 1 00 A N4 0 1 01 A N5 0 1 10 A N6 0 1 11 A N7 1 0 00 A N8 1 0 01 A N9 1 0 10 A N10 1 0 11 A N11 1 1 00 A N12 1 1 01 A N13 1 1 10 A N14 1 1 11 A N15 PRELIMINARY 184 Z51F3220 Product Specification 11.12 USI0 (UART + SPI + I2C) 11.12.1 Overview The USI0 consists of USI0 control register1/2/3/4, USI0 status register 1/2, USI0 baud-rate generation register, USI0 data register, USI0 SDA hold time register, USI0 SCL high period register, USI0 SCL low period register, and USI0 slave address register (USI0CR1, USI0CR2, USI0CR3, USI0CR4, USI0ST1, USI0ST2, USI0BD, USI0DR, USI0SDHR, USI0SCHR, USI0SCLR, USI0SAR). The operation mode is selected by the operation mode of USI0 selection bits (USI0MS[1:0]). It has four operating modes: - Asynchronous mode (UART) - Synchronous mode - SPI mode - I2C mode PS029902-0212 PRELIMINARY 185 Z51F3220 Product Specification 11.12.2 USI0 UART Mode The universal synchronous and asynchronous serial receiver and transmitter (UART) is a highly flexible serial communication device. The main features are listed below. - Full Duplex Operation (Independent Serial Receive and Transmit Registers) - Asynchronous or Synchronous Operation - Baud Rate Generator - Supports Serial Frames with 5,6,7,8, or 9 Data Bits and 1 or 2 Stop Bits - Odd or Even Parity Generation and Parity Check Supported by Hardware - Data OverRun Detection - Framing Error Detection - Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete - Double Speed Asynchronous communication mode USI0 has three main parts of clock generator, Transmitter and receiver. The clock generation logic consists of synchronization logic for external clock inut used by synchronous or SPI slave operation, and the baud rate generator for asynchronous or master (synchronous or SPI) operation. The Transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats. The write buffer allows continuous transfer of data without any delay between frames. The receiver is the most complex part of the UART module due to its clock and data recovery units. The recovery unit is used for asynchronous data reception. In addition to the recovery unit, the receiver includes a parity checker, a shift register, a two-level receive FIFO (USI0DR) and control logic. The receiver supports the same frame formats as the transmitter and can detect frame error, data overrun and parity errors. PS029902-0212 PRELIMINARY 186 Z51F3220 Product Specification 11.12.3 USI0 UART Block Diagram Master ACK Control SCK0 2 USI0MS[1:0] SCLK (fx: System clock) To interrupt block USI0BD Baud R ate Generator WAKEIE0 Clock Sync Logic At St op mode WAKE0 DBLS0 RXCIE0 Low level detector RXD0 RXC0 M U X Clock Recovery Rx Control USI0S[2:0] LOOPS 0 3 RXE0 Data Recovery Receive Shif t R egister (RXSR) 2 USI0 DR[0], USI0RX8 [0], (Rx) USI0MS[1:0 ] DOR0/PE 0/FE0 Checker USI0 DR[1], USI0RX8 [1], (Rx) USI0SB TXE0 Tx Control TXD0 INT_ACK Clear TXC0 TXCIE0 M U X Stop bit Generator USI0P[1:0] USI0S[2:0] 2 3 Parity Generator Transmit Shift R egister (TXSR) USI0MS[1:0] 2 I N T E R N A L B U S L I N E M U X Empty s ignal DRE0 USI0DR, USI0 TX8 , (Tx) DRIE0 To interrupt block Figure 11.57 USI0 UART Block Diagram PS029902-0212 PRELIMINARY 187 Z51F3220 Product Specification 11.12.4 USI0 Clock Generation USI0BD DBLS0 fSCLK Prescaling Up-Counter (USI0BD+1) /8 /2 M U X SCLK M U X txclk MASTER0 Sync Register Edge Detector M U X USI0MS[1:0] CPOL0 SCK0 /2 M U X rxclk Figure 11.58 Clock Generation Block Diagram (USI0) The clock generation logic generates the base clock for the transmitter and receiver. The USI0 supports four modes of clock operation and those are normal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode. The clock generation scheme for master SPI and slave SPI mode is the same as master synchronous and slave synchronous operation mode. The USI0MS[1:0] bits in USI0CR1 register selects asynchronous or synchronous operation. Asynchronous double speed mode is controlled by the DBLS0 bit in the USI0CR2 register. The MASTER0 bit in USI0CR3 register controls whether the clock source is internal (master mode, output pin) or external (slave mode, input pin). The SCK0 pin is active only when the USI0 operates in synchronous or SPI mode. Following table shows the equations for calculating the baud rate (in bps). Table 11-19 Equations for Calculating USI0 Baud Rate Register Setting Operating Mode Equation for Calculating Baud Rate Asynchronous Normal Mode (DBLS0=0) Baud Rate fx 16 USI0BD 1 Asynchronous Double Speed Mode (DBLS0=1) Baud Rate fx 8 USI0BD 1 Synchronous or SPI Master Mode Baud Rate fx 2 USI0BD 1 PS029902-0212 PRELIMINARY 188 Z51F3220 Product Specification 11.12.5 USI0 External Clock (SCK0) External clocking is used in the synchronous mode of operation. External clock input from the SCK0 pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver. This process introduces two CPU clock period delay. The maximum frequency of the external SCK0 pin is limited up-to 1MHz. 11.12.6 USI0 Synchronous mode operation When synchronous or SPI mode is used, the SCK0 pin will be used as either clock input (slave) or clock output (master). Data sampling and transmitter is issued on the different edge of SCK0 clock each other. For example, if data input on RXD0 (MISO0 in SPI mode) pin is sampled on the rising edge of SCK0 clock, data output on TXD0 (MOSI0 in SPI mode) pin is altered on the falling edge. The CPOL0 bit in USI0CR1 register selects which SCK0 clock edge is used for data sampling and which is used for data change. As shown in the figure below, when CPOL0 is zero, the data will be changed at rising SCK0 edge and sampled at falling SCK0 edge. CPOL0 = 1 SCK0 TXD0/RXD0 Sample CPOL0 = 0 SCK0 TXD0/RXD0 Sample Figure 11.59 Synchronous Mode SCK0 Timing (USI0) PS029902-0212 PRELIMINARY 189 Z51F3220 Product Specification 11.12.7 USI0 UART Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error detection. The UART supports all 30 combinations of the following as valid frame formats. - 1 start bit - 5, 6, 7, 8 or 9 data bits - no, even or odd parity bit - 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit (LSB). Then the next data bits, up to nine, are succeeding, ending with the most significant bit (MSB). If parity function is enabled, the parity bit is inserted between the last data bit and the stop bit. A high-to-low transition on data pin is considered as start bit. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle state. The idle means high state of data pin. The following figure shows the possible combinations of the frame formats. Bits inside brackets are optional. 1 data frame Idle St D0 D1 D2 D3 D4 [D5] [D6] [D7] [D8] [P] Sp1 [Sp2] Idle / St Character bits Figure 11.60 Frame Format (USI0) 1 data frame consists of the following bits • Idle No communication on communication line (TXD0/RXD0) • St Start bit (Low) • Dn Data bits (0~8) • Parity bit ------------ Even parity, Odd parity, No parity • Stop bit(s) ---------- 1 bit or 2 bits The frame format used by the UART is set by the USI0S[2:0], USI0PM[1:0] bits in USI0CR1 register and USI0SB bit in USI0CR3 register. The Transmitter and Receiver use the same setting. 11.12.8 USI0 UART Parity bit The parity bit is calculated by doing an exclusive-OR of all the data bits. If odd parity is used, the result of the exclusive-O is inverted. The parity bit is located between the MSB and first stop bit of a serial frame. Peven = Dn-1 ^ … ^ D 3 ^ D2 ^ D1 ^ D0 ^ 0 Podd = Dn-1 ^ … ^ D3 ^ D2 ^ D 1 ^ D 0 ^ 1 Peven : Parity bit using even parity Podd : Parity bit using odd parity Dn : Data bit n of the character PS029902-0212 PRELIMINARY 190 Z51F3220 Product Specification 11.12.9 USI0 UART Transmitter The UART transmitter is enabled by setting the TXE0 bit in USI0CR2 register. When the Transmitter is enabled, the TXD0 pin should be set to TXD0 function for the serial output pin of UART by the P4FSR[3:2]. The baud-rate, operation mode and frame format must be setup once before doing any transmission. In synchronous operation mode, the SCK0 pin is used as transmission clock, so it should be selected to do SCK0 function by P4FSR[5:4] . 11.12.9.1 USI0 UART Sending Tx data A data transmission is initiated by loading the transmit buffer (USI0DR register I/O location) with the data to be transmitted. The data written in transmit buffer is moved to the shift register when the shift register is ready to send a new frame. The shift register is loaded with the new data if it is in idle state or immediately after the last stop bit of the previous frame is transmitted. When the shift register is loaded with new data, it will transfer one complete frame according to the settings of control registers. If the 9-bit characters are used in asynchronous or synchronous operation mode, the ninth bit must be written to the USI0TX8 bit in USI0CR3 register before it is loaded to the transmit buffer (USI0DR register). 11.12.9.2 USI0 UART Transmitter flag and interrupt The UART transmitter has 2 flags which indicate its state. One is UART data register empty flag (DRE0) and the other is transmit complete flag (TXC0). Both flags can be interrupt sources. DRE0 flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty and cleared when the transmit buffer contains data to be transmitted but has not yet been moved into the shift register. And also this flag can be cleared by writing ‘0’ to this bit position. Writing ‘1’ to this bit position is prevented. When the data register empty interrupt enable (DRIE0) bit in USI0CR2 register is set and the global interrupt is enabled, USI0ST1 status register empty interrupt is generated while DRE0 flag is set. The transmit complete (TXC0) flag bit is set when the entire frame in the transmit shift register has been shifted out and there is no more data in the transmit buffer. The TXC0 flag is automatically cleared when the transmit complete interrupt service routine is executed, or it can be cleared by writing ‘0’ to TXC0 bit in USI0ST1 register. When the transmit complete interrupt enable (TXCIE0) bit in USI0CR2 register is set and the global interrupt is enabled, UART transmit complete interrupt is generated while TXC0 flag is set. PS029902-0212 PRELIMINARY 191 Z51F3220 Product Specification 11.12.9.3 USI0 UART Parity Generator The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled (USI0PM1=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the frame to be sent. 11.12.9.4 USI0 UART Disabling Transmitter Disabling the transmitter by clearing the TXE0 bit will not become effective until ongoing transmission is completed. When the Transmitter is disabled, the TXD0 pin can be used as a normal general purpose I/O (GPIO). 11.12.10 USI0 UART Receiver The UART receiver is enabled by setting the RXE0 bit in the USI0CR2 register. When the receiver is enabled, the RXD0 pin should be set to RXD0 function for the serial input pin of UART by P4FSR[1:0]. The baud-rate, mode of operation and frame format must be set before serial reception. In synchronous or SPI operation mode the SCK0 pin is used as transfer clock, so it should be selected to do SCK0 function by P4FSR[5:4]. In SPI operation mode the SS0 input pin in slave mode or can be configured as SS0 output pin in master mode. This can be done by setting USI0SSEN bit in USI0CR3 register. 11.12.10.1 USI0 UART Receiving Rx data When UART is in synchronous or asynchronous operation mode, the receiver starts data reception when it detects a valid start bit (LOW) on RXD0 pin. Each bit after start bit is sampled at pre-defined baud-rate (asynchronous) or sampling edge of SCK0 (synchronous), and shifted into the receive shift register until the first stop bit of a frame is received. Even if there’s 2nd stop bit in the frame, the 2nd stop bit is ignored by the receiver. That is, receiving the first stop bit means that a complete serial frame is present in the receiver shift register and contents of the shift register are to be moved into the receive buffer. The receive buffer is read by reading the USI0DR register. If 9-bit characters are used (USI0S[2:0] = “111”), the ninth bit is stored in the USI0RX8 bit position in the th USI0CR3 register. The 9 bit must be read from the USI0RX8 bit before reading the low 8 bits from the USI0DR register. Likewise, the error flags FE0, DOR0, PE0 must be read before reading the data from USI0DR register. It’s because the error flags are stored in the same FIFO position of the receive buffer. PS029902-0212 PRELIMINARY 192 Z51F3220 Product Specification 11.12.10.2 USI0 UART Receiver Flag and Interrupt The UART receiver has one flag that indicates the receiver state. The receive complete (RXC0) flag indicates whether there are unread data in the receive buffer. This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty. If the receiver is disabled (RXE0=0), the receiver buffer is flushed and the RXC0 flag is cleared. When the receive complete interrupt enable (RXCIE0) bit in the USI0CR2 register is set and global interrupt is enabled, the UART receiver complete interrupt is generated while RXC0 flag is set. The UART receiver has three error flags which are frame error (FE0), data overrun (DOR0) and parity error (PE0). These error flags can be read from the USI0ST1 register. As received data are stored in the 2-level receive buffer, these error flags are also stored in the same position of receive buffer. So, before reading received data from USI0DR register, read the USI0ST1 register first which contains error flags. The frame error (FE0) flag indicates the state of the first stop bit. The FE0 flag is ‘0’ when the stop bit was correctly detected as “1”, and the FE0 flag is “1” when the stop bit was incorrect, i.e. detected as “0”. This flag can be used for detecting out-of-sync conditions between data frames. The data overrun (DOR0) flag indicates data loss due to a receive buffer full condition. DOR0 occurs when the receive buffer is full, and another new data is present in the receive shift register which are to be stored into the receive buffer. After the DOR0 flag is set, all the incoming data are lost. To prevent data loss or clear this flag, read the receive buffer. The parity error (PE0) flag indicates that the frame in the receive buffer had a parity error when received. If parity check function is not enabled (USI0PM1=0), the PE bit is always read “0”. 11.12.10.3 USI0 UART Parity Checker If parity bit is enabled (USI0PM1=1), the Parity Checker calculates the parity of the data bits in incoming frame and compares the result with the parity bit from the received serial frame. 11.12.10.4 USI0 UART Disabling Receiver In contrast to transmitter, disabling the Receiver by clearing RXE0 bit makes the Receiver inactive immediately. When the receiver is disabled, the receiver flushes the receive buffer, the remaining data in the buffer is all reset, and the RXD0 pin can be used as a normal general purpose I/O (GPIO). PS029902-0212 PRELIMINARY 193 Z51F3220 Product Specification 11.12.10.5 USI0 Asynchronous Data Reception To receive asynchronous data frame, the UART includes a clock and data recovery unit. The clock recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the RXD0 pin. The data recovery logic samples and low pass filters the incoming bits, and this removes the noise of RXD0 pin. The next figure illustrates the sampling process of the start bit of an incoming frame. The sampling rate is 16 times of the baud-rate in normal mode and 8 times the aud-rate for double speed mode (DBLS0=1). The horizontal arrows show the synchronization variation due to the asynchronous sampling process. Note that larger time variation is shown when using the double speed mode. START RXD0 IDLE BIT0 Sample (DBLS0 = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (DBLS0 = 1) 0 1 2 3 4 5 6 7 8 1 2 Figure 11.61 Asynchronous Start Bit Sampling (USI0) When the receiver is enabled (RXE0=1), the clock recovery logic tries to find a high-to-low transition on the RXD0 line, the start bit condition. After detecting high to low transition on RXD0 line, the clock recovery logic uses samples 8, 9 and 10 for normal mode to decide if a valid start bit is received. If more than 2 samples have logical low level, it is considered that a valid start bit is detected and the internally generated clock is synchronized to the incoming data frame. And the data recovery can begin. The synchronization process is repeated for each start bit. As described above, when the receiver clock is synchronized to the start bit, the data recovery can begin. Data recovery process is almost similar to the clock recovery process. The data recovery logic samples 16 times for each incoming bits for normal mode and 8 times for double speed mode, and uses sample 8, 9 and 10 to decide data value. If more than 2 samples have low levels, the received bit is considered to a logic ‘0’ and if more than 2 samples have high levels, the received bit is considered to a logic ‘1’. The data recovery process is then repeated until a complete frame is received including the first stop bit. The decided bit value is stored in the receive shift register in order. Note that the Receiver only uses the first stop bit of a frame. Internally, after receiving the first stop bit, the Receiver is in idle state and waiting to find start bit. BIT n RXD0 Sample (DBLS0 = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 Sample (DBLS0 = 1) 1 2 3 4 5 6 7 8 1 Figure 11.62 Asynchronous Sampling of Data and Parity Bit (USI0) PS029902-0212 PRELIMINARY 194 Z51F3220 Product Specification The process for detecting stop bit is like clock and data recovery process. That is, if 2 or more samples of 3 center values have high level, correct stop bit is detected, else a frame error (FE0) flag is set. After deciding whether the first stop bit is valid or not, the Receiver goes to idle state and monitors the RXD0 line to check a valid high to low transition is detected (start bit detection). STOP 1 RXD0 (A) (B) (C) Sample (DBLS0 = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 Sample (DBLS0 = 1) 1 2 3 4 5 6 7 Figure 11.63 Stop Bit Sampling and Next Start Bit Sampling (USI0) PS029902-0212 PRELIMINARY 195 Z51F3220 Product Specification 11.12.11 USI0 SPI Mode The USI0 can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. - Full Duplex, Three-wire synchronous data transfer - Mater and Slave Operation - Supports all four SPI0 modes of operation (mode 0, 1, 2, and 3) - Selectable LSB first or MSB first data transfer - Double buffered transmit and receive - Programmable transmit bit rate When SPI mode is enabled (USI0MS[1:0]=”11”), the slave select (SS0) pin becomes active LOW input in slave mode operation, or can be output in master mode operation if USI0SSEN bit is set to ‘0’. Note that during SPI mode of operation, the pin RXD0 is renamed as MISO0 and TXD0 is renamed as MOSI0 for compatibility to other SPI devices. 11.12.12 USI0 SPI Clock Formats and Timing To accommodate a wide variety if synchronus serial peripherals from different manufacturers, the USI0 has a clock polarity bit (CPOL0) and a clock phase control bit (CPHA0) to select one of four clock formats for data transfers. CPOL0 selectively insert an inverter in series with the clock. CPHA0 chooses between two different clock phase relationships between the clock and data. Note that CPHA0 and CPOL0 bits in USI0CR1 register have different meanings according to the USI0MS[1:0] bits which decides the operating mode of USI0. Table below shows four combinations of CPOL0 and CPHA0 for SPI mode 0, 1, 2, and 3. Table 11-20 CPOL0 Functionality SPI Mode CPOL0 CPHA0 00 0 Sam 10 1 Set 21 0 Sam 31 1 Set PS029902-0212 Leading Edge ple (Rising) up (Rising) ple (Falling) up (Falling) PRELIMINARY Trailing Edge Setup (Falling) Sample (Falling) Setup (Rising) Sample (Rising) 196 Z51F3220 Product Specification SCK0 (CPOL0=0) SCK0 (CPOL0=1) SAMPLE MOSI0 MSB First LSB First BIT7 BIT0 BIT6 BIT1 … … BIT2 BIT5 BIT1 BIT6 BIT0 BIT7 MISO0 /SS0 OUT (MASTER) /SS0 IN (SLAVE) Figure 11.64 USI0 SPI Clock Formats when CPHA0=0 When CPHA0=0, the slave begins to drive its MISO0 output with the first data bit value when SS0 goes to active low. The first SCK0 edge causes both the master and the slave to sample the data bit value on their MISO0 and MOSI0 inputs, respectively. At the second SCK0 edge, the USI0 shifts the second data bit value out to the MOSI0 and MISO0 outputs of the master and slave, respectively. Unlike the case of CPHA0=1, when CPHA0=0, the slave’s SS0 input must go to its inactive high level between transfers. This is because the slave can prepare the first data bit when it detects falling edge of SS0 input. PS029902-0212 PRELIMINARY 197 Z51F3220 Product Specification SCK0 (CPOL0=0) SCK0 (CPOL0=1) SAMPLE MOSI0 MSB First LSB First BIT7 BIT0 BIT6 BIT1 … … BIT2 BIT5 BIT1 BIT6 BIT0 BIT7 MISO0 /SS0 OUT (MASTER) /SS0 IN (SLAVE) Figure 11.65 USI0 SPI Clock Formats when CPHA0=1 When CPHA0=1, the slave begins to drive its MISO0 output when SS0 goes active low, but the data is not defined until the first SCK0 edge. The first SCK0 edge shifts the first bit of data from the shifter onto the MOSI0 output of the master and the MISO0 output of the slave. The next SCK0 edge causes both the master and slave to sample the data bit value on their MISO0 and MOSI0 inputs, respectively. At the third SCK0 edge, the USI0 shifts the second data bit value out to the MOSI0 and MISO0 output of the master and slave respectively. When CPHA0=1, the slave’s SS0 input is not required to go to its inactive high level between transfers. Because the SPI logic reuses the USI0 resources, SPI mode of operation is similar to that of synchronous or asynchronous operation. An SPI transfer is initiated by checking for the USI0 Data Register Empty flag (DRE0=1) and then writing a byte of data to the USI0DR Register. In master mode of operation, even if transmission is not enabled (TXE0=0), writing data to the USI0DR register is necessary because the clock SCK0 is generated from transmitter block. PS029902-0212 PRELIMINARY 198 Z51F3220 Product Specification 11.12.13 USI0 SPI Block Diagram SS 0 USI0BD SS Control SCLK (fx: Sy stem c lock) MASTER0 USI0 SSEN Baud R ate Generator M U X SCK Control SCK0 FXCH0 RXE0 MISO0 M U X M U X Edge D etector And Controller CPOL0 Data Recovery Rx Control CPHA0 Receive Shift R egister (RXSR) RXC0 RXCIE0 LOOPS 0 DOR0 Checker USI0 DR[0], (Rx) USI0 DR[1], (Rx) MOSI0 To interrupt block MASTER0 TXE0 D E P Clear TXC0 B U S L I N E ORD0 ( MSB/LSB -1st) Transmit Shift Register (TXSR) Tx C ontrol INT_ ACK I N T E R N A L Empty s ignal DRE0 TXCIE0 USI0DR, (Tx) DRIE0 To interrupt block Figure 11.66 USI0 SPI Block Diagram PS029902-0212 PRELIMINARY 199 Z51F3220 Product Specification 11.12.14 USI0 I2C Mode The USI0 can be set to operate in industrial standard serial communicatin protocols mode. The I2C mode uses 2 bus lines serial data line (SDA0) and serial clock line (SCL0) to exchange data. Because both SDA0 and SCL0 lines are open-drain output, each line needs pull-up resistor. The features are as shown below. - Compatible with I2C bus standard - Multi-master operation - Up to 400kHz data transfer read speed - 7 bit address - Both master and slave operation - Bus busy detection 11.12.15 USI0 I2C Bit Transfer The data on the SDA0 line must be stable during HIGH period of the clock, SCL0. The HIGH or LOW state of the data line can only change when the clock signal on the SCL0 line is LOW. The exceptions are START(S), repeated START(Sr) and STOP(P) condition where data line changes when clock line is high. SDA0 SCL0 Data line Stable: Data valid exept S, Sr, P Change of Data allowed Figure 11.67 Bit Transfer on the I2C-Bus (USI0) PS029902-0212 PRELIMINARY 200 Z51F3220 Product Specification 11.12.16 USI0 I2C Start / Repeated Start / Stop One master can issue a START (S) condition to notice other devices connected to the SCL0, SDA0 lines that it will use the bus. A STOP (P) condition is generated by the master to release the bus lines so that other devices can use it. A high to low transition on the SDA0 line while SCL0 is high defines a START (S) condition. A low to high transition on the SDA0 line while SCL0 is high defines a STOP (P) condition. START and STOP conditions are always generated by the master. The bus is considered to be busy after START condition. The bus is considered to be free again after STOP condition, ie, the bus is busy between START and STOP condition. If a repeated START condition (Sr) is generated instead of STOP condition, the bus stays busy. So, the START and repeated START conditions are functionally identical. SDA0 SCL0 S P START Condition STOP Condition Figure 11.68 START and STOP Condition (USI0) 11.12.17 USI0 I2C Data Transfer Every byte put on the SDA0 line must be 8-bits long. The number of bytes that can be transmitted per transfer is unlimited. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. If a slave can’t receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL0 LOW to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL0. P SDA0 MSB Acknowledgement Signal form Slave Byte Complete, Interrupt within Device SCL0 1 S or Sr 9 Acknowledgement Signal form Slave Sr Clock line held low while interrupts are served. 1 ACK 9 ACK START or Repeated START Condition Sr or P STOP or Repeated START Condition Figure 11.69 Data Transfer on the I2C-Bus (USI0) PS029902-0212 PRELIMINARY 201 Z51F3220 Product Specification 11.12.18 USI0 I2C Acknowledge The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA0 line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA0 line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. When a slave is addressed by a master (Address Packet), and if it is unable to receive or transmit because it’s performing some real time function, the data line must be left HIGH by the slave. And also, when a slave addressed by a master is unable to receive more data bits, the slave receiver must release the SDA0 line (Data Packet). The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. If a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave transmitter must release the data line to allow the master to generate a STOP or repeated START condition. Data Output By Transmitter NACK Data Output By Receiver ACK SCL0 From MASTER 1 2 8 9 Clock pulse for ACK Figure 11.70 Acknowledge on the I2C-Bus (USI0) 11.12.19 USI0 I2C Synchronization / Arbitration Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL0 line. This means that a HIGH to LOW transition on the SCL0 line will cause the devices concerned to start counting off their LOW period and it will hold the SCL0 line in that state until the clock HIGH state is reached. However the LOW to HIGH transition of this clock may not change the state of the SCL0 line if another clock is still within its LOW period. In this way, a synchronized SCL0 clock is generated with its LOW period determined by the device with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period. A master may start a transfer only if the bus is free. Two or more masters may generate a START condition. Arbitration takes place on the SDA0 line, while the SCL0 line is at the HIGH level, in such a way that the master which transmits a HIGH level, while another master is transmitting a LOW level will switch off its DATA output state because the level on the bus doesn’t correspond to its own level. Arbitration continues for many bits until a winning master gets the ownership of I2C bus. Its first stage is comparison of the address bits. PS029902-0212 PRELIMINARY 202 Z51F3220 Product Specification Wait High Counting Start High Counting Fast Device SCLOUT High Counter Reset Slow Device SCLOUT SCL0 Figure 11.71 Clock Synchronization during Arbitration Procedure (USI0) Arbitration Process not adaped Device 1 loses Arbitration Device1 outputs High Device1 DataOut Device2 DataOut SDA0 on BUS SCL0 on BUS S Figure 11.72 Arbitration Procedure of Two Masters (USI0) 11.12.20 USI0 I2C Operation The I2C is byte-oriented and interrupt based. Interrupts are issued after all bus events except for a transmission of a START condition. Because the I2C is interrupt based, the application software is free to carry on other operations during a I2C byte transfer. Note that when a I2C interrupt is generated, IIC0IFR flag in USI0CR4 register is set, it is cleared by writing an any value to USI0ST2. When I2C interrupt occurs, the SCL0 line is hold LOW until writing any value to USI0ST2. When the IIC0IFR flag is set, the USI0ST2 contains a value indicating the current state of the I2C bus. According to the value in USI0ST2, software can decide what to do next. I2C can operate in 4 modes by configuring master/slave, transmitter/receiver. The operating mode is configured by a winning master. A more detailed explanation follows below. PS029902-0212 PRELIMINARY 203 Z51F3220 Product Specification 11.12.20.1 USI0 I2C Master Transmitter To operate I2C in master transmitter, follow the recommended steps below. 1. Enable I2C by setting USI0MS[1:0] bits in USI0CR1 and USI0EN bit in USI0CR2. This provides main clock to the peripheral. 2. Load SLA0+W into the USI0DR where SLA0 is address of slave device and W is transfer direction from the viewpoint of the master. For master transmitter, W is ‘0’. Note that USI0DR is used for both address and data. 3. Configure baud rate by writing desired value to both USI0SCLR and USI0SCHR for the Low and High period of SCL0 line. 4. Configure the USI0SDHR to decide when SDA0 changes value from falling edge of SCL0. If SDA0 should change in the middle of SCL0 LOW period, load half the value of USI0SCLR to the USI0SDHR. 5. Set the STARTC0 bit in USI0CR4. This transmits a START condition. And also configure how to handle interrupt and ACK signal. When the STARTC0 bit is set, 8-bit data in USI0DR is transmitted out according to the baud-rate. 6. This is ACK signal processing stage for address packet transmitted by master. When 7-bit address and 1-bit transfer direction is transmitted to target slave device, the master can know whether the slave th acknowledged or not in the 9 high period of SCL0. If the master gains bus mastership, I2C generates GCALL interrupt regardless of the reception of ACK from the slave device. When I2C loses bus mastership during arbitration process, the MLOST0 bit in USI0ST2 is set, and I2C waits in idle state or can be operate as an addressed slave. To operate as a slave when the MLOST0 bit in USI0ST2 is set, the ACK0EN bit in USI0CR4 must be set and the received 7-bit address must equal to the USI0SLA[6:0] bits in USI0SAR. In this case I2C operates as a slave transmitter or a slave receiver (go to appropriate section). In this stage, I2C holds the SCL0 LOW. This is because to decide whether I2C continues serial transfer or stops communication. The following steps continue assuming that I2C does not lose mastership during first data transfer. I2C (Master) can choose one of the following cases regardless of the reception of ACK signal from slave. 1) Master receives ACK signal from slave, so continues data transfer because slave can receive more data from master. In this case, load data to transmit to USI0DR. 2) Master stops data transfer even if it receives ACK signal from slave. In this case, set the STOPC0 bit in USI0CR4. 3) Master transmits repeated START condition with not checking ACK signal. In this case, load SLA0+R/W into the USI0DR and set STARTC0 bit in USI0CR4. After doing one of the actions above, write any arbitrary to USI0ST2 to release SCL0 line. In case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of 3), move to step 6 after transmitting the data in USI0DR and if transfer direction bit is ‘1’ go to master receiver section. 7. 1-Byte of data is being transmitted. During data transfer, bus arbitration continues. 8. This is ACK signal processing stage for data packet transmitted by master. I2C holds the SCL0 LOW. When I2C loses bus mastership while transmitting data arbitrating other masters, the MLOST0 bit in USI0ST2 is set. If then, I2C waits in idle state. When the data in USI0DR is transmitted completely, I2C generates TEND0 interrupt. I2C can choose one of the following cases regardless of the reception of ACK signal from slave. 1) Master receives ACK signal from slave, so continues data transfer because slave can receive more data from master. In this case, load data to transmit to USI0DR. 2) Master stops data transfer even if it receives ACK signal from slave. In this case, set the STOPC0 bit in USI0CR4. 3) Master transmits repeated START condition with not checking ACK signal. In this case, load SLA0+R/W into the USI0DR and set the STARTC0 bit in USI0CR4. After doing one of the actions above, write any arbitrary to USI0ST2 to release SCL0 line. In case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of 3), move to step 6 after transmitting the data in USI0DR, and if transfer direction bit is ‘1’ go to master receiver section. 9. This is the final step for master transmitter function of I2C, handling STOP interrupt. The STOP bit indicates that data transfer between master and slave is over. To clear USI0ST2, write any value to USI0ST2. After this, I2C enters idle state. PS029902-0212 PRELIMINARY 204 Z51F3220 Product Specification The next figure depicts above process for master transmitter operation of I2C. Master Receiver S or Sr SLA+R SLA+W 0x86 ACK 0x87 DATA Rs Lost? 0x47 N LOST LOST& 0x0F 0x1D 0x1F Slave Receiver (0x1D) or Transmitter (0x1F) 0x22 STOP LOST Cont? 0x0E P 0x0E Y Y P LOST 0x46 ACK STOP Y STOP N 0x22 N Other master continues Y From master to slave / Master command or Data Write 0x0F From slave to master STOP 0x22 P 0xxx Value of Status Register ACK Interrupt, SCL0 line is held low P Interrupt after stop command LOST& Arbitration lost as master and addressed as slave Figure 11.73 Formats and States in the Master Transmitter Mode (USI0) PS029902-0212 PRELIMINARY 205 Z51F3220 Product Specification 11.12.20.2 USI0 I2C Master Receiver To operate I2C in master receiver, follow the recommended steps below. 1. Enable I2C by setting USI0MS[1:0] bits in USI0CR1 and USI0EN bit in USI0CR2. This provides main clock to the peripheral. 2. Load SLA0+R into the USI0DR where SLA is address of slave device and R is transfer direction from the viewpoint of the master. For master receiver, R is ‘1’. Note that USI0DR is used for both address and data. 3. Configure baud rate by writing desired value to both USI0SCLR and USI0SCHR for the Low and High period of SCL0 line. 4. Configure the USI0SDHR to decide when SDA0 changes value from falling edge of SCL0. If SDA0 should change in the middle of SCL0 LOW period, load half the value of USI0SCLR to the USI0SDHR. 5. Set the STARTC0 bit in USI0CR4. This transmits a START condition. And also configure how to handle interrupt and ACK signal. When the STARTC0 bit is set, 8-bit data in USI0DR is transmitted out according to the baud-rate. 6. This is ACK signal processing stage for address packet transmitted by master. When 7-bit address and 1-bit transfer direction is transmitted to target slave device, the master can know whether the slave th acknowledged or not in the 9 high period of SCL0. If the master gains bus mastership, I2C generates GCALL interrupt regardless of the reception of ACK from the slave device. When I2C loses bus mastership during arbitration process, the MLOST0 bit in USI0ST2 is set, and I2C waits in idle state or can be operate as an addressed slave. To operate as a slave when the MLOST0 bit in USI0ST2 is set, the ACK0EN bit in USI0CR4 must be set and the received 7-bit address must equal to the USI0SLA[6:0] bits in USI0SAR. In this case I2C operates as a slave transmitter or a slave receiver (go to appropriate section). In this stage, I2C holds the SCL0 LOW. This is because to decide whether I2C continues serial transfer or stops communication. The following steps continue assuming that I2C does not lose mastership during first data transfer. I2C (Master) can choose one of the following cases according to the reception of ACK signal from slave. 1) Master receives ACK signal from slave, so continues data transfer because slave can prepare and transmit more data to master. Configure ACK0EN bit in USI0CR4 to decide whether I2C ACKnowledges the next data to be received or not. 2) Master stops data transfer because it receives no ACK signal from slave. In this case, set the STOPC0 bit in USI0CR4. 3) Master transmits repeated START condition due to no ACK signal from slave. In this case, load SLA0+R/W into the USI0DR and set STARTC0 bit in USI0CR4. After doing one of the actions above, write arbitrary value to USI0ST2 to release SCL0 line. In case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of 3), move to step 6 after transmitting the data in USI0DR and if transfer direction bit is ‘0’ go to master transmitter section. 7. 1-Byte of data is being received. 8. This is ACK signal processing stage for data packet transmitted by slave. I2C holds the SCL0 LOW. When 1-Byte of data is received completely, I2C generates TEND0 interrupt. I2C0 can choose one of the following cases according to the RXACK0 flag in USI0ST2. 1) Master continues receiving data from slave. To do this, set ACK0EN bit in USI0CR4 to ACKnowledge the next data to be received. 2) Master wants to terminate data transfer when it receives next data by not generating ACK signal. This can be done by clearing ACK0EN bit in USI0CR4. 3) Because no ACK signal is detected, master terminates data transfer. In this case, set the STOPC0 bit in USI0CR4. 4) No ACK signal is detected, and master transmits repeated START condition. In this case, load SLA0+R/W into the USI0DR and set the STARTC0 bit in USI0CR4. After doing one of the actions above, write arbitrary value to USI0ST2 to release SCL0 line. In case of 1) and 2), move to step 7. In case of 3), move to step 9 to handle STOP interrupt. In case of 4), move to step 6 after transmitting the data in USI0DR, and if transfer direction bit is ‘0’ go to master transmitter section. PS029902-0212 PRELIMINARY 206 Z51F3220 Product Specification 9. This is the final step for master receiver function of I2C, handling STOP interrupt. The STOP bit indicates that data transfer between master and slave is over. To clear USI0ST2, write any value to USI0ST2. After this, I2C enters idle state. The processes described above for master receiver operation of I2C can be depicted as the following figure. Master Transmitter S or Sr SLA+W SLA+R 0x84 ACK 0x85 DATA 0x20 N STOP P 0x0C Y LOST Rs LOST LOST& 0x0D 0x1D 0x1F Slave Receiver (0x1D) or Transmitter (0x1F) 0x44 Sr 0x44 ACK 0x45 Y N 0x20 STOP LOST 0xxx P 0x0C Other master continues From master to slave / Master command or Data Write ACK From slave to master ACK Value of Status Register Interrupt, SCL0 line is held low P Interrupt after stop command LOST& Arbitration lost as master and addressed as slave Figure 11.74 Formats and States in the Master Receiver Mode (USI0) PS029902-0212 PRELIMINARY 207 Z51F3220 Product Specification 11.12.20.3 USI0 I2C Slave Transmitter To operate I2C in slave transmitter, follow the recommended steps below. 1. If the main operating clock (SCLK) of the system is slower than that of SCL0, load value 0x00 into USI0SDHR to make SDA0 change within one system clock period from the falling edge of SCL0. Note that the hold time of SDA0 is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from USI0SDHR. When the hold time of SDA0 is longer than the period of SCLK, I2C (slave) cannot transmit serial data properly. 2. Enable I2C by setting USI0MS[1:0] bits in USI0CR1 , IIC0IE bit in USI0CR4 and USI0EN bit in USI0CR2. This provides main clock to the peripheral. 3. When a START condition is detected, I2C receives one byte of data and compares it with USI0SLA[6:0] bits in USI0SAR. If the GCALL0 bit in USI0SAR is enabled, I2C compares the received data with value 0x00, the general call address. 4. If the received address does not equal to USI0SLA[6:0] bits in USI0SAR, I2C enters idle state ie, waits for another START condition. Else if the address equals to USI0SLA[6:0] bits and the ACK0EN bit is enabled, I2C generates SSEL0 interrupt and the SCL0 line is held LOW. Note that even if the address equals to USI0SLA[6:0] bits, when the ACK0EN bit is disabled, I2C enters idle state. When SSEL0 interrupt occurs, load transmit data to USI0DR and write arbitrary value to USI0ST2 to release SCL0 line. 5. 1-Byte of data is being transmitted. 6. In this step, I2C generates TEND0 interrupt and holds the SCL0 line LOW regardless of the reception of ACK signal from master. Slave can select one of the following cases. 1) No ACK signal is detected and I2C waits STOP or repeated START condition. 2) ACK signal from master is detected. Load data to transmit into USI0DR. After doing one of the actions above, write arbitrary value to USI0ST2 to release SCL0 line. In case of 1) move to step 7 to terminate communication. In case of 2) move to step 5. In either case, a repeated START condition can be detected. For that case, move step 4. 7. This is the final step for slave transmitter function of I2C, handling STOP interrupt. The STOPC0 bit indicates that data transfer between master and slave is over. To clear USI0ST2, write any value to USI0ST2. After this, I2C enters idle state. PS029902-0212 PRELIMINARY 208 Z51F3220 Product Specification The next figure shows flow chart for handling slave transmitter function of I2C. IDLE S or Sr SLA+R GCALL 0x97 0x1F ACK LOST& Y 0x17 DATA 0x22 Y 0x47 ACK Y N STOP P 0x46 IDLE From master to slave / Master command or Data Write From slave to master 0xxx Value of Status Register ACK Interrupt, SCL0 line is held low P Interrupt after stop command LOST& Arbitration lost as master and addressed as slave GCALL General Call Address Figure 11.75 Formats and States in the Slave Transmitter Mode (USI0) PS029902-0212 PRELIMINARY 209 Z51F3220 Product Specification 11.12.20.4 USI0 I2C Slave Receiver To operate I2C in slave receiver, follow the recommended steps below. 1. If the main operating clock (SCLK) of the system is slower than that of SCL0, load value 0x00 into USI0SDHR to make SDA0 change within one system clock period from the falling edge of SCL0. Note that the hold time of SDA0 is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from USI0SDHR. When the hold time of SDA0 is longer than the period of SCLK, I2C (slave) cannot transmit serial data properly. 2. Enable I2C by setting USI0MS[1:0] bits in USI0CR1, IIC0IE bit in USI0CR4 and USI0EN bit in USI0CR2. This provides main clock to the peripheral. 3. When a START condition is detected, I2C receives one byte of data and compares it with USI0SLA[6:0] bits in USI0SAR. If the GCALL0 bit in USI0SAR is enabled, I2C0 compares the received data with value 0x00, the general call address. 4. If the received address does not equal to SLA0bits in USI0SAR, I2C enters idle state ie, waits for another START condition. Else if the address equals to SLA0 bits and the ACK0EN bit is enabled, I2C generates SSEL0 interrupt and the SCL0 line is held LOW. Note that even if the address equals to SLA0 bits, when the ACK0EN bit is disabled, I2C enters idle state. When SSEL0 interrupt occurs and I2C is ready to receive data, write arbitrary value to USI0ST2 to release SCL0 line. 5. 1-Byte of data is being received. 6. In this step, I2C generates TEND0 interrupt and holds the SCL0 line LOW regardless of the reception of ACK signal from master. Slave can select one of the following cases. 1) No ACK signal is detected (ACK0EN=0) and I2C waits STOP or repeated START condition. 2) ACK signal is detected (ACK0EN=1) and I2C can continue to receive data from master. After doing one of the actions above, write arbitrary value to USI0ST2 to release SCL0 line. In case of 1) move to step 7 to terminate communication. In case of 2) move to step 5. In either case, a repeated START condition can be detected. For that case, move step 4. 7. This is the final step for slave receiver function of I2C, handling STOP interrupt. The STOPC0 bit indicates that data transfer between master and slave is over. To clear USI0ST2, write any value to USI0ST2. After this, I2C enters idle state. PS029902-0212 PRELIMINARY 210 Z51F3220 Product Specification The process can be depicted as following figure when I2C operates in slave receiver mode. IDLE S or Sr SLA+W GCALL 0x95 0x1D ACK LOST& N Y 0x15 DATA 0x20 Y 0x45 ACK Y N STOP P 0x44 IDLE From master to slave / Master command or Data Write From slave to master 0xxx Value of Status Register ACK Interrupt, SCL0 line is held low P Interrupt after stop command LOST& Arbitration lost as master and addressed as slave GCALL General Call Address Figure 11.76 Formats and States in the Slave Receiver Mode (USI0) PS029902-0212 PRELIMINARY 211 Z51F3220 Product Specification 11.12.21 USI0 I2C Block Diagram IIC0IFR RXACK0, GCALL 0, TEND0, STOPD0, SSEL 0, MLOST0, BUSY0, TMODE0 Interrupt Generator To interrupt block Slave Address R egister USI0SAR IIC0IE General C all And Address D etector Receive Shift Register ( RXSR) SDA0 SDA0 I n/Out Controller N-ch VSS ACK Signal Generator USI0DR, (Rx) ACK0EN STOPC0 STOP /START Condition Generator SCL0 Out Controller SCL0 USI0DR, (Tx) SDA H old T ime R egister USI0SDHR Time Generator And Time C ontroller I N T E R N A L B U S STARTC0 Transmit Shift R egister (TXSR) USI0GCE L I N E SCL H igh Period R egister USI0SCHR SCL Low Period R egister USI0SCLR N-ch SCLK (fx: Sy stem c lock) VSS NOTE) When the USI0 block is an I2C mode and the corresponding port is an sub-function for SCL0/SDA0 pin, the SCL0/SDA0 pins are automatically set to the N-channel open-drain outputs and the input latch is read in the case of reading the pins. The corresponding pull-up resistor is determined by the control register. Figure 11.77 USI0 I2C Block Diagram PS029902-0212 PRELIMINARY 212 Z51F3220 Product Specification 11.12.22 Register Map Table 11-21 USI0 Register Map Name Address Dir R/W Default USI0BD E3H USI0DR E5H R/W 00H USI0 Data Register USI0SDHR E4H R/W 01H USI0 SDA Hold Time Register USI0SCHR E7H R/W 3FH USI0 SCL High Period Register USI0SCLR R/W 3FH USI0 SCL Low Period Register E6H FFH Description USI0 Baud Rate Generation Register USI0SAR DDH R/W 00H USI0 Slave Address Register USI0CR1 D9H R/W 00H USI0 Control Register 1 USI0CR2 DAH R/W 00H USI0 Control Register 2 USI0CR3 DBH R/W 00H USI0 Control Register 3 USI0CR4 DCH R/W 00H USI0 Control Register 4 USI0ST1 E1H R/W 80H USI0 Status Register 1 USI0ST2 E2H R 00H USI0 Status Register 2 11.12.23 USI0 Register Description USI0 module consists of USI0 baud rate generation register (USI0BD), USI0 data register (USI0DR), USI0 SDA hold time register (USI0SDHR), USI0 SCL high period register (USI0SCHR), USI0 SCL low period Register (USI0SCLR), USI0 slave address register (USI0SAR), USI0 control register 1/2/3/4 (USI0CR1/2/3/4), USI0 status register 1/2 (USI0ST1/2). 11.12.24 Register Description for USI0 USI0BD (USI0 Baud- Rate Generation Register: For UART and SPI mode) : E3H 7 6 5 4 3 2 1 0 USI0BD7 USI0BD 6 USI0BD 5 USI0BD 4 USI0BD 3 USI0BD 2 USI0BD 1 USI0BD 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH USI0BD[7:0] The value in this register is used to generate internal baud rate in asynchronous mode or to g enerate S CK0 c lock in SPI m ode. To prevent malfunction, do not write ‘0’ in asynchronous mode and do not write ‘0’ or ‘1’ in SPI mode. NOTE) In co mmon with U SI0SAR register, USI0BD r egister i s used for slave address register when the USI0 I2C mode. PS029902-0212 PRELIMINARY 213 Z51F3220 Product Specification USI0DR (USI0 Data Register: For UART, SPI, and I2C mode) : E5H 7 6 5 4 3 2 1 0 USI0DR7 USI0DR 6 USI0DR 5 USI0DR 4 USI0DR 3 USI0DR 2 USI0DR 1 USI0DR 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 00H The USI0 transmit b uffer a nd r eceive buffer s hare the s ame I/O address with t his DAT A register. The t ransmit da ta buffer is th e destination for data written t o the USI 0DR register. Rea ding the USI0DR register returns the contents of the receive buffer. Write to this register only when the DRE0 flag is set. In SPI master mode, the S CK cl ock is generated when d ata ar e written to this register. USI0DR[7:0] USI0SDHR (USI0 SDA Hold Time Register: For I2C mode) : E4H 7 6 5 4 3 2 1 0 USI0SDHR7 USI0SDHR6 USI0SDHR5 USI0SDHR 4 USI0SDHR 3 USI0SDHR 2 USI0SDHR 1 USI0SDHR 0 R/W R/W R/W R/W R/W R/W R/W USI0SDHR[7:0] R/W Initial value : 00H The register is us ed to control SDA0 output timing from the falling edge of SCI in I2C mode. NOTE) That S DA0 is changed after tSCLK X ( USI0SDHR+2), in master SDA 0 change in the middle of SCL0. In s lave mode, configure this reg ister r egarding the frequency of SCL0 from master. The SDA0 i s ch anged after t sclk X (USI0SDHR+2) in master mode. So, to insure operation in slave mode, the value tSCLK X (USI0SDHR +2) must be smaller than the period of SCL. USI0SCHR (USI0 SCL High Period Register: For I2C mode) : E7H 7 6 5 4 3 2 1 0 USI0SCHR7 USI0SCHR6 USI0SCHR5 USI0SCHR 4 USI0SCHR 3 USI0SCHR 2 USI0SCHR 1 USI0SCHR 0 R/W R/W R/W R/W R/W R/W R/W USI0SCHR[7:0] R/W Initial value : 00H This register defines the high period of SCL0 when it operates in I2C master mode. The b ase c lock is S CLK, the s ystem c lock, and t he p eriod i s calculated by the formula: tSCLK X (4 X USI0SCHR +2) where tSCLK is the period of SCLK. So, the operating frequency of I2C master mode is calculated by the following equation. fI2C = PS029902-0212 1 tSCLK X (4 X (USI0SCLR + USI0SCHR + 4)) PRELIMINARY 214 Z51F3220 Product Specification USI0SCLR (USI0 SCL Low Period Register: For I2C mode) : E6H 7 6 5 4 3 2 1 0 USI0SCLR7 USI0SCLR6 USI0SCLR5 USI0SCLR 4 USI0SCLR 3 USI0SCLR 2 USI0SCLR 1 USI0SCLR 0 R/W R/W R/W R/W R/W R/W R/W USI0SCLR[7:0] R/W Initial value : 00H This register defines the high period of SCL0 when it operates in I2C master mode. The b ase c lock is S CLK, the s ystem c lock, and t he p eriod i s calculated by the formula: tSCLK X (4 X USI0SCLR +2) where tSCLK is the period of SCLK. USI0SAR (USI0 Slave Address Register: For I2C mode) : DDH 7 6 5 4 3 2 1 0 USI0SLA6 USI0SLA5 USI0SLA4 USI0SLA3 USI0SLA2 USI0SLA1 USI0SLA0 USI0GCE R/W R/W R/W R/W R/W R/W R/W PS029902-0212 R/W Initial value : 00H USI0SLA[6:0] These bits c onfigure the slave address of I2C when it operaties in I2C slave mode. UPM[1:0] This bi t dec ides whether I2 C allows general cal l ad dress o r not i n I2C slave mode. 0 Ignore general call address 1 Allow general call address PRELIMINARY 215 Z51F3220 Product Specification USI0CR1 (USI0 Control Register 1: For UART, SPI, and I2C mode) : D9H 7 6 5 4 3 2 1 0 USI0S0 CPHA0 CPOL0 R/W USI0MS1 USI0MS0 USI0PM1 USI0PM0 USI0S2 USI0S1 ORD0 R/W R/W R/W R/W R/W R/W USI0MS[1:0] USI0PM[1:0] USI0S[2:0] Selects operation mode of USI0 USI0MS1 USI 0MS0 Operation mode 00 Asynchronous Mode (UART) 01 Synchronous Mode 10 I2C mode 11 SPI mode Selects parity generation and check methods (only UART mode) USI0PM1 USI0PM0 Parity 00 No Parity 01 Reserved 10 Even Parity 11 Odd Parity When in asynchronous or synchronous mode of operation, selects the length of data bits in frame USI0S2 USI0 ORD0 USI0S0 Data Length 00 0 5 bit 00 1 6 bit 01 0 7 bit 01 1 8 bit 10 0 Reserved 10 1 Reserved S1 11 0 Reserved 11 1 9 bit This bit in the sam e bi t position w ith USI0S1. The M SB of the da ta byte is t ransmitted first when set to ‘1 ’ and t he LSB when s et t o ‘ 0’ (onl SPI mode) 0 LS B-first 1 MSBCPOL0 CPHA0 PS029902-0212 R/W Initial value : 00H first This bit determines the cl ock p olarity of A CK in s ynchronous or SP I mode. 0 TXD change@Rising Edge, RXD change@Falling Edge 1 TXD change@Falling Edge, RXD change@Rising Edge This bit is in the same bit position with USI0S0. This bit determines if data are sampled on t he le ading or trailing ed ge of SCK 0 (only SPI mode). CPOL0 CPHA0 Leading edge Trailing edge 0 0 Sample (Rising) Setup (Falling) 0 1 Setup (Rising) Sample (Falling) 1 0 Sample (Falling) Setup (Rising) 1 1 Setup (Falling) Sample (Rising) PRELIMINARY 216 Z51F3220 Product Specification USI0CR2 (USI0 Control Register 2: For UART, SPI, and I2C mode) : DAH 7 6 5 4 3 2 1 0 DRIE0 TXCIE0 RXCIE0 WAKEIE0 TXE0 RXE0 USI0EN DBLS0 R/W R/W R/W R/W R/W R/W R/W DRIE0 TXCIE0 RXCIE0 WAKEIE0 TXE0 RXE0 USI0EN DBLS0 PS029902-0212 R/W Initial value : 00H Interrupt enable bit for data register empty (only UART and SPI mode). 0 Interrupt from DRE0 is inhibited (use polling) 1 When DRE0 is set, request an interrupt Interrupt enable bit for transmit complete (only UART and SPI mode). 0 Interrupt from TXC0 is inhibited (use polling) 1 When TXC0 is set, request an interrupt Interrupt enable bit for receive complete (only UART and SPI mode). 0 Interrupt from RXC0 is inhibited (use polling) 1 When RXC0 is set, request an interrupt Interrupt enable bit for asynchronous wake in STOP mode. When device is in stop mode, if RXD0 goes to low level an interrupt can be requested to wake-up system. (o nly UAR T mode). At t hat time the DRIE0 b it and USI0ST1 register value should be set to ‘0b’ and “00H”, respectively. 0 Interrupt from Wake is inhibited 1 When WAKE0 is set, request an interrupt Enables the transmitter unit (only UART and SPI mode). 0 Tr ansmitter is disabled 1 Tr ansmitter is enabled Enables the receiver unit (only UART and SPI mode). 0 Receiv er is disabled 1 Receiv er is enabled Activate USI0 function block by supplying. 0 USI 0 is disabled 1 USI 0 is enabled This bit selects receiver sampling rate (only UART). 0 Normal asynchronous operation 1 Double Speed asynchronous operation PRELIMINARY 217 Z51F3220 Product Specification USI0CR3 (USI0 Control Register 3: For UART, SPI, and I2C mode) : DBH 7 6 5 4 3 2 1 0 MASTER0 LOOPS0 DISSCK0 USI0SSEN FXCH0 USI0SB USI0TX8 USI0RX8 R/W R/W R/W R/W R/W R/W R/W MASTER0 LOOPS0 DISSCK0 USI0SSEN Selects master or s lave in S PI a nd s ynchronous mode operation an d controls the direction of SCK0 pin 0 Slave mode operation (External clock for SCK0). 1 Master mode operation(Internal clock for SCK0). Controls the loop back mode of USI0 for test mode (only UART and SPI mode) 0 Nor mal operation 1 Loo p Back mode In synchronous mode of operation, selects the waveform of SCK0 output 0 ACK i s f ree-running while UART is en abled i n s ynchronous master mode 1 ACK is active while any frame is on transferring This bit controls the SS0 pin operation (only SPI mode) 0 Di sable 1 FXCH0 Enable (The SS0 pin should be a normal input) SPI port function exchange control bit (only SPI mode) 0 No effect 1 USI0SB USI0TX8 USI0RX8 PS029902-0212 R Initial value : 00H Exchange MOSI0 and MISO0 function Selects the length o f stop b it i n a synchronous o r synchronous mode of operation. 0 1 Stop Bit 1 2 Stop Bit The ninth bit of data frame in asynchronous or s ynchronous mode of operation. Write this bit first before loading the USI0DR register 0 MSB (9th bit) to be transmitted is ‘0’ 1 MSB (9th bit) to be transmitted is ‘1’ The ninth bit of data frame in asynchronous or s ynchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode). 0 MSB (9th bit) received is ‘0’ 1 MSB (9th bit) received is ‘1’ PRELIMINARY 218 Z51F3220 Product Specification USI0CR4 (USI0 Control Register 4: For I2C mode) : DCH 7 6 5 4 3 2 1 0 IIC0IFR – TXDLYENB0 IIC0IE ACK0EN IMASTER0 STOPC0 STARTC0 R – R/W R/W R/W R R/W IIC0IFR TXDLYENB0 This is an interrupt flag bit for I2C mode. When an interrupt occurs, this bit becomes ‘1’. This bit is cleared when write any values in th USI0ST2. 0 I2C interrupt no generation 1 I2C interrupt generation USI0SDHR register control bit 0 Enab 1 IIC0IE ACK0EN R/W Initial value : 00H le USI0SDHR register Disable USI0SDHR register Interrupt Enable bit for I2C mode 0 Interrupt from I2C is inhibited (use polling) 1 Enable interrupt for I2C Controls ACK signal Generation at ninth SCL0 period. 0 No ACK signal is generated (SDA0 =1) 1 ACK signal is generated (SDA0 =0) NOTES) ACK signal is output (SDA =0) for the following 3 cases. 1. When received address packet equals to USI0SLA bits in USI0SAR. 2. When re ceived a ddress packet eq uals to value 0x0 0 with GC ALL0 enabled. 3. When I2C operates as a receiver (master or slave) IMASTER0 STOPC0 Represent operating mode of I2C 0 I2C is in slave mode 1 I2C is in master mode When I2C is master, STOP condition generation 0 No 1 STARTC0 When I2C is master, START condition generation 0 No 1 PS029902-0212 effect STOP condition is to be generated effect START or repeated START condition is to be generated PRELIMINARY 219 Z51F3220 Product Specification USI0ST1 (USI0 Status Register 1: For UART and SPI mode) : E1H 7 6 5 4 3 2 1 0 DRE0 TXC0 RXC0 WAKE0 USI0RST DOR0 FE0 PE0 R/W R/W R R/W R/W R R/W DRE0 TXC0 RXC0 WAKE0 USI0RST The DR E0 flag i ndicates if the t ransmit buffer (U SI0DR) i s rea dy to receive ne w da ta. If DRE0 is ‘ 1’, the buf fer i s em pty and re ady to be written. This flag can generate a DRE0 interrupt. 0 Transmit buffer is not empty. 1 Transmit buffer is empty. This flag i s s et when the entire f rame i n the transmit s hift reg ister has been s hifted out a nd ther e is no new data cu rrently present in the transmit b uffer. T his flag is automatically cleared when the i nterrupt service routine of a TXC0 interrupt is executed. This flag can generate a TXC0 interrupt. This bit is automatically cleared. 0 Transmission is ongoing. 1 Transmit buffer i s emp ty and th e dat a i n transmit sh ift reg ister are shifted out completely. This flag is s et when there are unread dat a i n the re ceive bu ffer and cleared when all the data in the receive buffer are read. The RXC0 flag can be used to generate a RXC0 interrupt. 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer This flag is set when the RXD0 pin is detected low while the CPU is in STOP mode. This flag can be used to generate a WAKE0 interrupt. This bit is set only when in asynchronous mode of operation. This bit should be cleared by program software. (only UART mode) 0 No WAKE interrupt is generated. 1 WAKE interrupt is generated This is an internal reset and only has effect on USI0. Writing ‘1’ to this bit initializes the internal logic of USI0 and this bit is automatically cleared to ‘0’. 0 No operation 1 Reset DOR0 No Data OverRun 1 Data PE0 OverRun detected This bit is set if the first stop bit of next character in the receive buffer is detected as ‘0’. This bit i s va lid u ntil the re ceive buffer is read. (o nly UART mode) 0 No Frame Error 1 Frame Error detected This bit is set if the next character in the receive buffer has a Parity Error to be received while Parity Checking is enabled. This bit is valid until the receive buffer is read. (only UART mode) 0N o Parity Error 1 Parit PS029902-0212 USI0 This bit is set if a Data OverRun occurs. While this bit is set, the incoming data frame is ignored. This flag is valid until the receive buffer is read. 0 FE0 R/W Initial value : 80H y Error detected PRELIMINARY 220 Z51F3220 Product Specification USI0ST2 (USI0 Status Register 2: For I2C mode) : E2H 7 6 5 4 3 2 1 0 GCALL0 TEND0 STOPD0 SSEL0 MLOST0 BUSY0 TMODE0 RXACK0 R R/W R/W R/W R/W R/W R/W R/W Initial value : 00H GCALL0(NOTE) This bit has d ifferent m eaning depending on whether I 2C is ma ster o r slave. Wh en I2 C i s a ma ster, this bit represents whether it received AACK (address ACK) from slave. 0 No AACK is received (Master mode) 1 AACK is received (Master mode) When I2C is a slave, this bit is used to indicated general call. (NOTE) TEND0 0 General call address is not detected (Slave mode) 1 General call address is detected (Slave mode) This bit is set when 1-byte of data is transferred completely 0 1 byte of data is not completely transferred 1 1 byte of data is completely transferred STOPD0(NOTE) This bit is set when a STOP condition is detected. (NOTE) SSEL0 MLOST0 (NOTE) BUSY0 TMODE0 RXACK0 0 No STOP condition is detected 1 STOP condition is detected This bit is set when I2C is addressed by other master. 0 I2C is not selected as a slave 1 I2C is addressed by other master and acts as a slave This bit represents the result of bus arbitration in master mode. 0I 2C maintains bus mastership 1 I2C maintains bus mastership during arbitration process This bit reflects bus status. 0 I2C bus is idle, so a master can issue a START condition 1 I2C bus is busy This bit is used to indicate whether I2C is transmitter or receiver. 0I 2C is a receiver 1 I2C is a transmitter This bit shows the state of ACK signal 0 No ACK is received 1 ACK is received at ninth SCL period NOTE) These bits can be source of interrupt. When an I2C interrupt oc curs e xcept f or S TOP mo de, t he S CL0 line is h old LOW. T o release SC L0, write r bitrary value to USI 0ST2. When USI0ST2 is written, the T END0, STOPD0, SSEL0, MLOST0, and RXACK0 bits are cleared. PS029902-0212 PRELIMINARY 221 Z51F3220 Product Specification 11.13 USI1 (UART + SPI + I2C) 11.13.1 Overview The USI1 consists of USI1 control register1/2/3/4, USI1 status register 1/2, USI1 baud-rate generation register, USI1 data register, USI1 SDA hold time register, USI1 SCL high period register, USI1 SCL low period register, and USI1 slave address register (USI1CR1, USI1CR2, USI1CR3, USI1CR4, USI1ST1, USI1ST2, USI1BD, USI1DR, USI1SDHR, USI1SCHR, USI1SCLR, USI1SAR). The operation mode is selected by the operation mode of USI1 selection bits (USI1MS[1:0]). It has four operating modes: - Asynchronous mode (UART) - Synchronous mode - SPI mode - I2C mode PS029902-0212 PRELIMINARY 222 Z51F3220 Product Specification 11.13.2 USI1 UART Mode The universal synchronous and asynchronous serial receiver and transmitter (UART) is a highly flexible serial communication device. The main features are listed below. - Full Duplex Operation (Independent Serial Receive and Transmit Registers) - Asynchronous or Synchronous Operation - Baud Rate Generator - Supports Serial Frames with 5,6,7,8, or 9 Data Bits and 1 or 2 Stop Bits - Odd or Even Parity Generation and Parity Check Supported by Hardware - Data OverRun Detection - Framing Error Detection - Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete - Double Speed Asynchronous communication mode USI1 has three main parts of clock generator, Transmitter and receiver. The clock generation logic consists of synchronization logic for external clock inut used by synchronous or SPI slave operation, and the baud rate generator for asynchronous or master (synchronous or SPI) operation. The Transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats. The write buffer allows continuous transfer of data without any delay between frames. The receiver is the most complex part of the UART module due to its clock and data recovery units. The recovery unit is used for asynchronous data reception. In addition to the recovery unit, the receiver includes a parity checker, a shift register, a two-level receive FIFO (USI1DR) and control logic. The receiver supports the same frame formats as the transmitter and can detect frame error, data overrun and parity errors. PS029902-0212 PRELIMINARY 223 Z51F3220 Product Specification 11.13.3 USI1 UART Block Diagram Master ACK Control SCK1 2 USI1MS[1:0] SCLK (fx: System clock) To interrupt block USI1BD Baud R ate Generator WAKEIE1 Clock Sync Logic At St op mode WAKE1 DBLS1 RXCIE1 Low level detector RXD1 RXC1 M U X Clock Recovery Rx Control USI1S[2:0] LOOPS 1 3 RXE1 Data Recovery Receive Shif t R egister (RXSR) 2 USI1 DR[0], USI1RX8 [0], (Rx) USI1MS[1:0 ] DOR1/PE 1/FE1 Checker USI1 DR[1], USI1RX8 [1], (Rx) USI1SB TXE1 Tx Control TXD1 INT_ACK Clear TXC1 TXCIE1 M U X Stop bit Generator USI1P[1:0] USI1S[2:0] 2 3 Parity Generator Transmit Shift R egister (TXSR) USI1MS[1:0] 2 I N T E R N A L B U S L I N E M U X Empty s ignal DRE1 USI1DR, USI1 TX8 , (Tx) DRIE1 To interrupt block Figure 11.78 USI1 UART Block Diagram PS029902-0212 PRELIMINARY 224 Z51F3220 Product Specification 11.13.4 USI1 Clock Generation USI1BD DBLS1 fSCLK Prescaling Up-Counter (USI1BD+1) /8 /2 M U X SCLK M U X txclk MASTER1 Sync Register Edge Detector M U X USI1MS[1:0] CPOL1 SCK1 /2 M U X rxclk Figure 11.79 Clock Generation Block Diagram (USI1) The clock generation logic generates the base clock for the transmitter and receiver. The USI1 supports four modes of clock operation and those are normal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode. The clock generation scheme for master SPI and slave SPI mode is the same as master synchronous and slave synchronous operation mode. The USI1MS[1:0] bits in USI1CR1 register selects asynchronous or synchronous operation. Asynchronous double speed mode is controlled by the DBLS1 bit in the USI1CR2 register. The MASTER1 bit in USI1CR3 register controls whether the clock source is internal (master mode, output pin) or external (slave mode, input pin). The SCK1 pin is active only when the USI1 operates in synchronous or SPI mode. Following table shows the equations for calculating the baud rate (in bps). Table 11-22 Equations for Calculating USI1 Baud Rate Register Setting Operating Mode Equation for Calculating Baud Rate Asynchronous Normal Mode (DBLS1=0) Baud Rate fx 16 USI1BD 1 Asynchronous Double Speed Mode (DBLS1=1) Baud Rate fx 8 USI1BD 1 Synchronous or SPI Master Mode Baud Rate fx 2 USI1BD 1 PS029902-0212 PRELIMINARY 225 Z51F3220 Product Specification 11.13.5 USI1 External Clock (SCK1) External clocking is used in the synchronous mode of operation. External clock input from the SCK1 pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver. This process introduces two CPU clock period delay. The maximum frequency of the external SCK1 pin is limited up-to 1MHz. 11.13.6 USI1 Synchronous mode operation When synchronous or SPI mode is used, the SCK1 pin will be used as either clock input (slave) or clock output (master). Data sampling and transmitter is issued on the different edge of SCK1 clock each other. For example, if data input on RXD1 (MISO1 in SPI mode) pin is sampled on the rising edge of SCK1 clock, data output on TXD1 (MOSI1 in SPI mode) pin is altered on the falling edge. The CPOL1 bit in USI1CR1 register selects which SCK1 clock edge is used for data sampling and which is used for data change. As shown in the figure below, when CPOL1 is zero, the data will be changed at rising SCK1 edge and sampled at falling SCK1 edge. CPOL1 = 1 SCK1 TXD1/RXD1 Sample CPOL1 = 0 SCK1 TXD1/RXD1 Sample Figure 11.80 Synchronous Mode SCK1 Timing (USI1) PS029902-0212 PRELIMINARY 226 Z51F3220 Product Specification 11.13.7 USI1 UART Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error detection. The UART supports all 30 combinations of the following as valid frame formats. - 1 start bit - 5, 6, 7, 8 or 9 data bits - no, even or odd parity bit - 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit (LSB). Then the next data bits, up to nine, are succeeding, ending with the most significant bit (MSB). If parity function is enabled, the parity bit is inserted between the last data bit and the stop bit. A high-to-low transition on data pin is considered as start bit. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle state. The idle means high state of data pin. The following figure shows the possible combinations of the frame formats. Bits inside brackets are optional. 1 data frame Idle St D0 D1 D2 D3 D4 [D5] [D6] [D7] [D8] [P] Sp1 [Sp2] Idle / St Character bits Figure 11.81 Frame Format (USI1) 1 data frame consists of the following bits • Idle No communication on communication line (TXD0/RXD0) • St Start bit (Low) • Dn Data bits (0~8) • Parity bit ------------ Even parity, Odd parity, No parity • Stop bit(s) ---------- 1 bit or 2 bits The frame format used by the UART is set by the USI1S[2:0], USI1PM[1:0] bits in USI1CR1 register and USI1SB bit in USI1CR3 register. The Transmitter and Receiver use the same setting. 11.13.8 USI1 UART Parity bit The parity bit is calculated by doing an exclusive-OR of all the data bits. If odd parity is used, the result of the exclusive-O is inverted. The parity bit is located between the MSB and first stop bit of a serial frame. Peven = Dn-1 ^ … ^ D 3 ^ D2 ^ D1 ^ D0 ^ 0 Podd = Dn-1 ^ … ^ D3 ^ D2 ^ D 1 ^ D 0 ^ 1 Peven : Parity bit using even parity Podd : Parity bit using odd parity Dn : Data bit n of the character PS029902-0212 PRELIMINARY 227 Z51F3220 Product Specification 11.13.9 USI1 UART Transmitter The UART transmitter is enabled by setting the TXE1 bit in USI1CR2 register. When the Transmitter is enabled, the TXD1 pin should be set to TXD1 function for the serial output pin of UART by the P2FSR[1:0]. The baud-rate, operation mode and frame format must be setup once before doing any transmission. In synchronous operation mode, the SCK1 pin is used as transmission clock, so it should be selected to do SCK1 function by P2FSR[3:2] . 11.13.9.1 USI1 UART Sending Tx data A data transmission is initiated by loading the transmit buffer (USI1DR register I/O location) with the data to be transmitted. The data written in transmit buffer is moved to the shift register when the shift register is ready to send a new frame. The shift register is loaded with the new data if it is in idle state or immediately after the last stop bit of the previous frame is transmitted. When the shift register is loaded with new data, it will transfer one complete frame according to the settings of control registers. If the 9-bit characters are used in asynchronous or synchronous operation mode, the ninth bit must be written to the USI1TX8 bit in USI1CR3 register before it is loaded to the transmit buffer (USI1DR register). 11.13.9.2 USI1 UART Transmitter flag and interrupt The UART transmitter has 2 flags which indicate its state. One is UART data register empty flag (DRE1) and the other is transmit complete flag (TXC1). Both flags can be interrupt sources. DRE1 flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty and cleared when the transmit buffer contains data to be transmitted but has not yet been moved into the shift register. And also this flag can be cleared by writing ‘0’ to this bit position. Writing ‘1’ to this bit position is prevented. When the data register empty interrupt enable (DRIE1) bit in USI1CR2 register is set and the global interrupt is enabled, USI1ST1 status register empty interrupt is generated while DRE1 flag is set. The transmit complete (TXC1) flag bit is set when the entire frame in the transmit shift register has been shifted out and there is no more data in the transmit buffer. The TXC1 flag is automatically cleared when the transmit complete interrupt service routine is executed, or it can be cleared by writing ‘0’ to TXC1 bit in USI1ST1 register. When the transmit complete interrupt enable (TXCIE1) bit in USI1CR2 register is set and the global interrupt is enabled, UART transmit complete interrupt is generated while TXC1 flag is set. PS029902-0212 PRELIMINARY 228 Z51F3220 Product Specification 11.13.9.3 USI1 UART Parity Generator The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled (USI1PM1=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the frame to be sent. 11.13.9.4 USI1 UART Disabling Transmitter Disabling the transmitter by clearing the TXE1 bit will not become effective until ongoing transmission is completed. When the Transmitter is disabled, the TXD1 pin can be used as a normal general purpose I/O (GPIO). 11.13.10 USI1 UART Receiver The UART receiver is enabled by setting the RXE1 bit in the USI1CR2 register. When the receiver is enabled, the RXD1 pin should be set to RXD1 function for the serial input pin of UART by P1FSR[1:0]. The baud-rate, mode of operation and frame format must be set before serial reception. In synchronous or SPI operation mode the SCK1 pin is used as transfer clock, so it should be selected to do SCK1 function by P2FSR[3:2]. In SPI operation mode the SS1 input pin in slave mode or can be configured as SS1 output pin in master mode. This can be done by setting USI1SSEN bit in USI1CR3 register. 11.13.10.1 USI1 UART Receiving Rx data When UART is in synchronous or asynchronous operation mode, the receiver starts data reception when it detects a valid start bit (LOW) on RXD1 pin. Each bit after start bit is sampled at pre-defined baud-rate (asynchronous) or sampling edge of SCK1 (synchronous), and shifted into the receive shift register until the first stop bit of a frame is received. Even if there’s 2nd stop bit in the frame, the 2nd stop bit is ignored by the receiver. That is, receiving the first stop bit means that a complete serial frame is present in the receiver shift register and contents of the shift register are to be moved into the receive buffer. The receive buffer is read by reading the USI1DR register. If 9-bit characters are used (USI1S[2:0] = “111”), the ninth bit is stored in the USI1RX8 bit position in the th USI1CR3 register. The 9 bit must be read from the USI1RX8 bit before reading the low 8 bits from the USI1DR register. Likewise, the error flags FE1, DOR1, PE1 must be read before reading the data from USI1DR register. It’s because the error flags are stored in the same FIFO position of the receive buffer. PS029902-0212 PRELIMINARY 229 Z51F3220 Product Specification 11.13.10.2 USI1 UART Receiver Flag and Interrupt The UART receiver has one flag that indicates the receiver state. The receive complete (RXC1) flag indicates whether there are unread data in the receive buffer. This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty. If the receiver is disabled (RXE1=1), the receiver buffer is flushed and the RXC1 flag is cleared. When the receive complete interrupt enable (RXCIE1) bit in the USI1CR2 register is set and global interrupt is enabled, the UART receiver complete interrupt is generated while RXC1 flag is set. The UART receiver has three error flags which are frame error (FE1), data overrun (DOR1) and parity error (PE1). These error flags can be read from the USI1ST1 register. As received data are stored in the 2-level receive buffer, these error flags are also stored in the same position of receive buffer. So, before reading received data from USI1DR register, read the USI1ST1 register first which contains error flags. The frame error (FE1) flag indicates the state of the first stop bit. The FE1 flag is ‘0’ when the stop bit was correctly detected as “1”, and the FE1 flag is “1” when the stop bit was incorrect, i.e. detected as “0”. This flag can be used for detecting out-of-sync conditions between data frames. The data overrun (DOR1) flag indicates data loss due to a receive buffer full condition. DOR1 occurs when the receive buffer is full, and another new data is present in the receive shift register which are to be stored into the receive buffer. After the DOR1 flag is set, all the incoming data are lost. To prevent data loss or clear this flag, read the receive buffer. The parity error (PE1) flag indicates that the frame in the receive buffer had a parity error when received. If parity check function is not enabled (USI1PM1=0), the PE bit is always read “0”. 11.13.10.3 USI1 UART Parity Checker If parity bit is enabled (USI1PM1=1), the Parity Checker calculates the parity of the data bits in incoming frame and compares the result with the parity bit from the received serial frame. 11.13.10.4 USI1 UART Disabling Receiver In contrast to transmitter, disabling the Receiver by clearing RXE1 bit makes the Receiver inactive immediately. When the receiver is disabled, the receiver flushes the receive buffer, the remaining data in the buffer is all reset, and the RXD1 pin can be used as a normal general purpose I/O (GPIO). PS029902-0212 PRELIMINARY 230 Z51F3220 Product Specification 11.13.10.5 USI1 Asynchronous Data Reception To receive asynchronous data frame, the UART includes a clock and data recovery unit. The clock recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the RXD1 pin. The data recovery logic samples and low pass filters the incoming bits, and this removes the noise of RXD1 pin. The next figure illustrates the sampling process of the start bit of an incoming frame. The sampling rate is 16 times of the baud-rate in normal mode and 8 times the aud-rate for double speed mode (DBLS1=1). The horizontal arrows show the synchronization variation due to the asynchronous sampling process. Note that larger time variation is shown when using the double speed mode. START RXD1 IDLE BIT0 Sample (DBLS1 = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (DBLS1 = 1) 0 1 2 3 4 5 6 7 8 1 2 Figure 11.82 Asynchronous Start Bit Sampling (USI1) When the receiver is enabled (RXE1=1), the clock recovery logic tries to find a high-to-low transition on the RXD1 line, the start bit condition. After detecting high to low transition on RXD1 line, the clock recovery logic uses samples 8, 9 and 10 for normal mode to decide if a valid start bit is received. If more than 2 samples have logical low level, it is considered that a valid start bit is detected and the internally generated clock is synchronized to the incoming data frame. And the data recovery can begin. The synchronization process is repeated for each start bit. As described above, when the receiver clock is synchronized to the start bit, the data recovery can begin. Data recovery process is almost similar to the clock recovery process. The data recovery logic samples 16 times for each incoming bits for normal mode and 8 times for double speed mode, and uses sample 8, 9 and 10 to decide data value. If more than 2 samples have low levels, the received bit is considered to a logic ‘0’ and if more than 2 samples have high levels, the received bit is considered to a logic ‘1’. The data recovery process is then repeated until a complete frame is received including the first stop bit. The decided bit value is stored in the receive shift register in order. Note that the Receiver only uses the first stop bit of a frame. Internally, after receiving the first stop bit, the Receiver is in idle state and waiting to find start bit. BIT n RXD1 Sample (DBLS1 = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 Sample (DBLS1 = 1) 1 2 3 4 5 6 7 8 1 Figure 11.83 Asynchronous Sampling of Data and Parity Bit (USI1) PS029902-0212 PRELIMINARY 231 Z51F3220 Product Specification The process for detecting stop bit is like clock and data recovery process. That is, if 2 or more samples of 3 center values have high level, correct stop bit is detected, else a frame error (FE1) flag is set. After deciding whether the first stop bit is valid or not, the Receiver goes to idle state and monitors the RXD1 line to check a valid high to low transition is detected (start bit detection). STOP 1 RXD1 (A) (B) (C) Sample (DBLS1 = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 Sample (DBLS1 = 1) 1 2 3 4 5 6 7 Figure 11.84 Stop Bit Sampling and Next Start Bit Sampling (USI1) PS029902-0212 PRELIMINARY 232 Z51F3220 Product Specification 11.13.11 USI1 SPI Mode The USI1 can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. - Full Duplex, Three-wire synchronous data transfer - Mater and Slave Operation - Supports all four SPI0 modes of operation (mode 0, 1, 2, and 3) - Selectable LSB first or MSB first data transfer - Double buffered transmit and receive - Programmable transmit bit rate When SPI mode is enabled (USI1MS[1:0]=”11”), the slave select (SS1) pin becomes active LOW input in slave mode operation, or can be output in master mode operation if USI1SSEN bit is set to ‘0’. Note that during SPI mode of operation, the pin RXD1 is renamed as MISO1 and TXD1 is renamed as MOSI1 for compatibility to other SPI devices. 11.13.12 USI1 SPI Clock Formats and Timing To accommodate a wide variety if synchronus serial peripherals from different manufacturers, the USI1 has a clock polarity bit (CPOL1) and a clock phase control bit (CPHA1) to select one of four clock formats for data transfers. CPOL1 selectively insert an inverter in series with the clock. CPHA1 chooses between two different clock phase relationships between the clock and data. Note that CPHA1 and CPOL1 bits in USI1CR1 register have different meanings according to the USI1MS[1:0] bits which decides the operating mode of USI1. Table below shows four combinations of CPOL1 and CPHA1 for SPI mode 0, 1, 2, and 3. Table 11-23 CPOL1 Functionality SPI Mode PS029902-0212 CPOL1 CPHA1 Leading Edge Trailing Edge 00 0 Sample (Rising) Setup (Falling) 10 1 Setup (Rising) Sample (Falling) 2 1 0 Sample (Falling) Setup (Rising) 3 1 1 Setup (Falling) Sample (Rising) PRELIMINARY 233 Z51F3220 Product Specification SCK1 (CPOL1=0) SCK1 (CPOL1=1) SAMPLE MOSI1 MSB First LSB First BIT7 BIT0 BIT6 BIT1 … … BIT2 BIT5 BIT1 BIT6 BIT0 BIT7 MISO1 /SS0 OUT (MASTER) /SS1 IN (SLAVE) Figure 11.85 USI1 SPI Clock Formats when CPHA1=0 When CPHA1=0, the slave begins to drive its MISO1 output with the first data bit value when SS1 goes to active low. The first SCK1 edge causes both the master and the slave to sample the data bit value on their MISO1 and MOSI1 inputs, respectively. At the second SCK1 edge, the USI1 shifts the second data bit value out to the MOSI1 and MISO1 outputs of the master and slave, respectively. Unlike the case of CPHA1=1, when CPHA1=0, the slave’s SS1 input must go to its inactive high level between transfers. This is because the slave can prepare the first data bit when it detects falling edge of SS1 input. PS029902-0212 PRELIMINARY 234 Z51F3220 Product Specification SCK1 (CPOL1=0) SCK1 (CPOL1=1) SAMPLE MOSI1 MSB First LSB First BIT7 BIT0 BIT6 BIT1 … … BIT2 BIT5 BIT1 BIT6 BIT0 BIT7 MISO1 /SS0 OUT (MASTER) /SS0 IN (SLAVE) Figure 11.86 USI1 SPI Clock Formats when CPHA1=1 When CPHA1=1, the slave begins to drive its MISO1 output when SS1 goes active low, but the data is not defined until the first SCK1 edge. The first SCK1 edge shifts the first bit of data from the shifter onto the MOSI1 output of the master and the MISO1 output of the slave. The next SCK1 edge causes both the master and slave to sample the data bit value on their MISO1 and MOSI1 inputs, respectively. At the third SCK1 edge, the USI1 shifts the second data bit value out to the MOSI1 and MISO1 output of the master and slave respectively. When CPHA1=1, the slave’s SS1 input is not required to go to its inactive high level between transfers. Because the SPI logic reuses the USI1 resources, SPI mode of operation is similar to that of synchronous or asynchronous operation. An SPI transfer is initiated by checking for the USI1 Data Register Empty flag (DRE1=1) and then writing a byte of data to the USI1DR Register. In master mode of operation, even if transmission is not enabled (TXE1=0), writing data to the USI1DR register is necessary because the clock SCK1 is generated from transmitter block. PS029902-0212 PRELIMINARY 235 Z51F3220 Product Specification 11.13.13 USI1 SPI Block Diagram SS 1 USI1BD SS Control SCLK (fx: Sy stem c lock) MASTER1 USI1 SSEN Baud R ate Generator M U X SCK Control SCK1 FXCH1 RXE1 MISO1 M U X M U X Edge D etector And Controller CPOL1 Data Recovery Rx Control CPHA1 Receive Shift R egister (RXSR) RXC1 RXCIE1 LOOPS 1 DOR1 Checker USI1 DR[0], (Rx) USI1 DR[1], (Rx) MOSI1 To interrupt block MASTER1 TXE1 D E P Clear TXC1 B U S L I N E ORD1 ( MSB/LSB -1st) Transmit Shift Register (TXSR) Tx C ontrol INT_ ACK I N T E R N A L Empty s ignal DRE1 TXCIE1 USI1DR, (Tx) DRIE1 To interrupt block Figure 11.87 USI1 SPI Block Diagram PS029902-0212 PRELIMINARY 236 Z51F3220 Product Specification 11.13.14 USI1 I2C Mode The USI1 can be set to operate in industrial standard serial communicatin protocols mode. The I2C mode uses 2 bus lines serial data line (SDA1) and serial clock line (SCL1) to exchange data. Because both SDA1 and SCL1 lines are open-drain output, each line needs pull-up resistor. The features are as shown below. - Compatible with I2C bus standard - Multi-master operation - Up to 400kHz data transfer read speed - 7 bit address - Both master and slave operation - Bus busy detection 11.13.15 USI1 I2C Bit Transfer The data on the SDA1 line must be stable during HIGH period of the clock, SCL1. The HIGH or LOW state of the data line can only change when the clock signal on the SCL1 line is LOW. The exceptions are START(S), repeated START(Sr) and STOP(P) condition where data line changes when clock line is high. SDA1 SCL1 Data line Stable: Data valid exept S, Sr, P Change of Data allowed Figure 11.88 Bit Transfer on the I2C-Bus (USI1) PS029902-0212 PRELIMINARY 237 Z51F3220 Product Specification 11.13.16 USI1 I2C Start / Repeated Start / Stop One master can issue a START (S) condition to notice other devices connected to the SCL1, SDA1 lines that it will use the bus. A STOP (P) condition is generated by the master to release the bus lines so that other devices can use it. A high to low transition on the SDA1 line while SCL1 is high defines a START (S) condition. A low to high transition on the SDA1 line while SCL1 is high defines a STOP (P) condition. START and STOP conditions are always generated by the master. The bus is considered to be busy after START condition. The bus is considered to be free again after STOP condition, ie, the bus is busy between START and STOP condition. If a repeated START condition (Sr) is generated instead of STOP condition, the bus stays busy. So, the START and repeated START conditions are functionally identical. SDA1 SCL1 S P START Condition STOP Condition Figure 11.89 START and STOP Condition (USI1) 11.13.17 USI1 I2C Data Transfer Every byte put on the SDA1 line must be 8-bits long. The number of bytes that can be transmitted per transfer is unlimited. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. If a slave can’t receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL1 LOW to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL1. P SDA1 MSB Acknowledgement Signal form Slave Byte Complete, Interrupt within Device SCL1 1 S or Sr 9 Acknowledgement Signal form Slave Sr Clock line held low while interrupts are served. 1 ACK 9 ACK START or Repeated START Condition Sr or P STOP or Repeated START Condition Figure 11.90 Data Transfer on the I2C-Bus (USI1) PS029902-0212 PRELIMINARY 238 Z51F3220 Product Specification 11.13.18 USI1 I2C Acknowledge The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA1 line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA1 line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. When a slave is addressed by a master (Address Packet), and if it is unable to receive or transmit because it’s performing some real time function, the data line must be left HIGH by the slave. And also, when a slave addressed by a master is unable to receive more data bits, the slave receiver must release the SDA1 line (Data Packet). The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. If a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. The slave transmitter must release the data line to allow the master to generate a STOP or repeated START condition. Data Output By Transmitter NACK Data Output By Receiver ACK SCL1 From MASTER 1 2 8 9 Clock pulse for ACK Figure 11.91 Acknowledge on the I2C-Bus (USI1) 11.13.19 USI1 I2C Synchronization / Arbitration Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL1 line. This means that a HIGH to LOW transition on the SCL1 line will cause the devices concerned to start counting off their LOW period and it will hold the SCL1 line in that state until the clock HIGH state is reached. However the LOW to HIGH transition of this clock may not change the state of the SCL1 line if another clock is still within its LOW period. In this way, a synchronized SCL1 clock is generated with its LOW period determined by the device with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period. A master may start a transfer only if the bus is free. Two or more masters may generate a START condition. Arbitration takes place on the SDA1 line, while the SCL1 line is at the HIGH level, in such a way that the master which transmits a HIGH level, while another master is transmitting a LOW level will switch off its DATA output state because the level on the bus doesn’t correspond to its own level. Arbitration continues for many bits until a winning master gets the ownership of I2C bus. Its first stage is comparison of the address bits. PS029902-0212 PRELIMINARY 239 Z51F3220 Product Specification Wait High Counting Start High Counting Fast Device SCLOUT High Counter Reset Slow Device SCLOUT SCL1 Figure 11.92 Clock Synchronization during Arbitration Procedure (USI1) Arbitration Process not adaped Device 1 loses Arbitration Device1 outputs High Device1 DataOut Device2 DataOut SDA1 on BUS SCL1 on BUS S Figure 11.93 Arbitration Procedure of Two Masters (USI1) 11.13.20 USI1 I2C Operation The I2C is byte-oriented and interrupt based. Interrupts are issued after all bus events except for a transmission of a START condition. Because the I2C is interrupt based, the application software is free to carry on other operations during a I2C byte transfer. Note that when a I2C interrupt is generated, IIC1IFR flag in USI1CR4 register is set, it is cleared by writing an any value to USI1ST2. When I2C interrupt occurs, the SCL1 line is hold LOW until writing any value to USI1ST2. When the IIC1IFR flag is set, the USI1ST2 contains a value indicating the current state of the I2C bus. According to the value in USI1ST2, software can decide what to do next. I2C can operate in 4 modes by configuring master/slave, transmitter/receiver. The operating mode is configured by a winning master. A more detailed explanation follows below. PS029902-0212 PRELIMINARY 240 Z51F3220 Product Specification 11.13.20.1 USI1 I2C Master Transmitter To operate I2C in master transmitter, follow the recommended steps below. 10. Enable I2C by setting USI1MS[1:0] bits in USI1CR1 and USI1EN bit in USI1CR2. This provides main clock to the peripheral. 11. Load SLA1+W into the USI1DR where SLA1 is address of slave device and W is transfer direction from the viewpoint of the master. For master transmitter, W is ‘0’. Note that USI1DR is used for both address and data. 12. Configure baud rate by writing desired value to both USI1SCLR and USI1SCHR for the Low and High period of SCL1 line. 13. Configure the USI0SDHR to decide when SDA1 changes value from falling edge of SCL1. If SDA1 should change in the middle of SCL1 LOW period, load half the value of USI1SCLR to the USI1SDHR. 14. Set the STARTC1 bit in USI1CR4. This transmits a START condition. And also configure how to handle interrupt and ACK signal. When the STARTC1 bit is set, 8-bit data in USI1DR is transmitted out according to the baud-rate. 15. This is ACK signal processing stage for address packet transmitted by master. When 7-bit address and 1-bit transfer direction is transmitted to target slave device, the master can know whether the slave th acknowledged or not in the 9 high period of SCL1. If the master gains bus mastership, I2C generates GCALL interrupt regardless of the reception of ACK from the slave device. When I2C loses bus mastership during arbitration process, the MLOST1 bit in USI1ST2 is set, and I2C waits in idle state or can be operate as an addressed slave. To operate as a slave when the MLOST1 bit in USI1ST2 is set, the ACK1EN bit in USI1CR4 must be set and the received 7-bit address must equal to the USI1SLA[6:0] bits in USI1SAR. In this case I2C operates as a slave transmitter or a slave receiver (go to appropriate section). In this stage, I2C holds the SCL1 LOW. This is because to decide whether I2C continues serial transfer or stops communication. The following steps continue assuming that I2C does not lose mastership during first data transfer. I2C (Master) can choose one of the following cases regardless of the reception of ACK signal from slave. 1) Master receives ACK signal from slave, so continues data transfer because slave can receive more data from master. In this case, load data to transmit to USI1DR. 2) Master stops data transfer even if it receives ACK signal from slave. In this case, set the STOPC1 bit in USI1CR4. 3) Master transmits repeated START condition with not checking ACK signal. In this case, load SLA1+R/W into the USI1DR and set STARTC1 bit in USI1CR4. After doing one of the actions above, write any arbitrary to USI1ST2 to release SCL1 line. In case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of 3), move to step 6 after transmitting the data in USI1DR and if transfer direction bit is ‘1’ go to master receiver section. 16. 1-Byte of data is being transmitted. During data transfer, bus arbitration continues. 17. This is ACK signal processing stage for data packet transmitted by master. I2C holds the SCL1 LOW. When I2C loses bus mastership while transmitting data arbitrating other masters, the MLOST1 bit in USI1ST2 is set. If then, I2C waits in idle state. When the data in USI1DR is transmitted completely, I2C generates TEND1 interrupt. I2C can choose one of the following cases regardless of the reception of ACK signal from slave. 1) Master receives ACK signal from slave, so continues data transfer because slave can receive more data from master. In this case, load data to transmit to USI1DR. 2) Master stops data transfer even if it receives ACK signal from slave. In this case, set the STOPC1 bit in USI1CR4. 3) Master transmits repeated START condition with not checking ACK signal. In this case, load SLA1+R/W into the USI1DR and set the STARTC1 bit in USI1CR4. After doing one of the actions above, write any arbitrary to USI1ST2 to release SCL1 line. In case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of 3), move to step 6 after transmitting the data in USI1DR, and if transfer direction bit is ‘1’ go to master receiver section. 18. This is the final step for master transmitter function of I2C, handling STOP interrupt. The STOP bit indicates that data transfer between master and slave is over. To clear USI1ST2, write any value to USI1ST2. After this, I2C enters idle state. PS029902-0212 PRELIMINARY 241 Z51F3220 Product Specification The next figure depicts above process for master transmitter operation of I2C. Master Receiver S or Sr SLA+R SLA+W 0x86 ACK 0x87 DATA Rs Lost? 0x47 N LOST LOST& 0x0F 0x1D 0x1F Slave Receiver (0x1D) or Transmitter (0x1F) 0x22 STOP LOST Cont? 0x0E P 0x0E Y Y P LOST 0x46 ACK STOP Y STOP N 0x22 N Other master continues Y From master to slave / Master command or Data Write 0x0F From slave to master STOP 0x22 P 0xxx Value of Status Register ACK Interrupt, SCL1 line is held low P Interrupt after stop command LOST& Arbitration lost as master and addressed as slave Figure 11.94 Formats and States in the Master Transmitter Mode (USI1) PS029902-0212 PRELIMINARY 242 Z51F3220 Product Specification 11.13.20.2 USI1 I2C Master Receiver To operate I2C in master receiver, follow the recommended steps below. 10. Enable I2C by setting USI1MS[1:0] bits in USI1CR1 and USI1EN bit in USI1CR2. This provides main clock to the peripheral. 11. Load SLA1+R into the USI1DR where SLA is address of slave device and R is transfer direction from the viewpoint of the master. For master receiver, R is ‘1’. Note that USI1DR is used for both address and data. 12. Configure baud rate by writing desired value to both USI1SCLR and USI1SCHR for the Low and High period of SCL1 line. 13. Configure the USI1SDHR to decide when SDA1 changes value from falling edge of SCL1. If SDA1 should change in the middle of SCL1 LOW period, load half the value of USI1SCLR to the USI1SDHR. 14. Set the STARTC1 bit in USI1CR4. This transmits a START condition. And also configure how to handle interrupt and ACK signal. When the STARTC1 bit is set, 8-bit data in USI1DR is transmitted out according to the baud-rate. 15. This is ACK signal processing stage for address packet transmitted by master. When 7-bit address and 1-bit transfer direction is transmitted to target slave device, the master can know whether the slave th acknowledged or not in the 9 high period of SCL1. If the master gains bus mastership, I2C generates GCALL interrupt regardless of the reception of ACK from the slave device. When I2C loses bus mastership during arbitration process, the MLOST1 bit in USI1ST2 is set, and I2C waits in idle state or can be operate as an addressed slave. To operate as a slave when the MLOST1 bit in USI1ST2 is set, the ACK1EN bit in USI1CR4 must be set and the received 7-bit address must equal to the USI1SLA[6:0] bits in USI1SAR. In this case I2C operates as a slave transmitter or a slave receiver (go to appropriate section). In this stage, I2C holds the SCL1 LOW. This is because to decide whether I2C continues serial transfer or stops communication. The following steps continue assuming that I2C does not lose mastership during first data transfer. I2C (Master) can choose one of the following cases according to the reception of ACK signal from slave. 1) Master receives ACK signal from slave, so continues data transfer because slave can prepare and transmit more data to master. Configure ACK0EN bit in USI0CR4 to decide whether I2C ACKnowledges the next data to be received or not. 2) Master stops data transfer because it receives no ACK signal from slave. In this case, set the STOPC1 bit in USI1CR4. 3) Master transmits repeated START condition due to no ACK signal from slave. In this case, load SLA1+R/W into the USI1DR and set STARTC1 bit in USI1CR4. After doing one of the actions above, write arbitrary value to USI1ST2 to release SCL1 line. In case of 1), move to step 7. In case of 2), move to step 9 to handle STOP interrupt. In case of 3), move to step 6 after transmitting the data in USI1DR and if transfer direction bit is ‘0’ go to master transmitter section. 16. 1-Byte of data is being received. 17. This is ACK signal processing stage for data packet transmitted by slave. I2C holds the SCL1 LOW. When 1-Byte of data is received completely, I2C generates TEND1 interrupt. I2C can choose one of the following cases according to the RXACK1 flag in USI1ST2. 1) Master continues receiving data from slave. To do this, set ACK1EN bit in USI0CR4 to ACKnowledge the next data to be received. 2) Master wants to terminate data transfer when it receives next data by not generating ACK signal. This can be done by clearing ACK1EN bit in USI1CR4. 3) Because no ACK signal is detected, master terminates data transfer. In this case, set the STOPC1 bit in USI1CR4. 4) No ACK signal is detected, and master transmits repeated START condition. In this case, load SLA1+R/W into the USI1DR and set the STARTC1 bit in USI1CR4. After doing one of the actions above, write arbitrary value to USI1ST2 to release SCL1 line. In case of 1) and 2), move to step 7. In case of 3), move to step 9 to handle STOP interrupt. In case of 4), move to step 6 after transmitting the data in USI1DR, and if transfer direction bit is ‘0’ go to master transmitter section. PS029902-0212 PRELIMINARY 243 Z51F3220 Product Specification 18. This is the final step for master receiver function of I2C, handling STOP interrupt. The STOP bit indicates that data transfer between master and slave is over. To clear USI1ST2, write any value to USI1ST2. After this, I2C enters idle state. The processes described above for master receiver operation of I2C can be depicted as the following figure. Master Transmitter S or Sr SLA+W SLA+R 0x84 ACK 0x85 DATA 0x20 N STOP P 0x0C Y LOST Rs LOST LOST& 0x0D 0x1D 0x1F Slave Receiver (0x1D) or Transmitter (0x1F) 0x44 Sr 0x44 ACK 0x45 Y N 0x20 STOP LOST 0xxx P 0x0C Other master continues From master to slave / Master command or Data Write ACK From slave to master ACK Value of Status Register Interrupt, SCL1 line is held low P Interrupt after stop command LOST& Arbitration lost as master and addressed as slave Figure 11.95 Formats and States in the Master Receiver Mode (USI1) PS029902-0212 PRELIMINARY 244 Z51F3220 Product Specification 11.13.20.3 USI1 I2C Slave Transmitter To operate I2C in slave transmitter, follow the recommended steps below. 8. If the main operating clock (SCLK) of the system is slower than that of SCL1, load value 0x00 into USI1SDHR to make SDA1 change within one system clock period from the falling edge of SCL1. Note that the hold time of SDA1 is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from USI1SDHR. When the hold time of SDA1 is longer than the period of SCLK, I2C (slave) cannot transmit serial data properly. 9. Enable I2C by setting USI1MS[1:0] bits in USI1CR1 , IIC1IE bit in USI1CR4 and USI1EN bit in USI1CR2. This provides main clock to the peripheral. 10. When a START condition is detected, I2C receives one byte of data and compares it with USI1SLA[6:0] bits in USI1SAR. If the GCALL1 bit in USI1SAR is enabled, I2C compares the received data with value 0x00, the general call address. 11. If the received address does not equal to USI1SLA[6:0] bits in USI1SAR, I2C enters idle state ie, waits for another START condition. Else if the address equals to USI1SLA[6:0] bits and the ACK1EN bit is enabled, I2C generates SSEL1 interrupt and the SCL1 line is held LOW. Note that even if the address equals to USI1SLA[6:0] bits, when the ACK1EN bit is disabled, I2C enters idle state. When SSEL1 interrupt occurs, load transmit data to USI1DR and write arbitrary value to USI1ST2 to release SCL1 line. 12. 1-Byte of data is being transmitted. 13. In this step, I2C generates TEND1 interrupt and holds the SCL1 line LOW regardless of the reception of ACK signal from master. Slave can select one of the following cases. 1) No ACK signal is detected and I2C waits STOP or repeated START condition. 2) ACK signal from master is detected. Load data to transmit into USI1DR. After doing one of the actions above, write arbitrary value to USI1ST2 to release SCL1 line. In case of 1) move to step 7 to terminate communication. In case of 2) move to step 5. In either case, a repeated START condition can be detected. For that case, move step 4. 14. This is the final step for slave transmitter function of I2C, handling STOP interrupt. The STOPC1 bit indicates that data transfer between master and slave is over. To clear USI1ST2, write any value to USI1ST2. After this, I2C enters idle state. PS029902-0212 PRELIMINARY 245 Z51F3220 Product Specification The next figure shows flow chart for handling slave transmitter function of I2C. IDLE S or Sr SLA+R GCALL 0x97 0x1F ACK LOST& Y 0x17 DATA 0x22 Y 0x47 ACK Y N STOP P 0x46 IDLE From master to slave / Master command or Data Write From slave to master 0xxx Value of Status Register ACK Interrupt, SCL1 line is held low P Interrupt after stop command LOST& Arbitration lost as master and addressed as slave GCALL General Call Address Figure 11.96 Formats and States in the Slave Transmitter Mode (USI1) PS029902-0212 PRELIMINARY 246 Z51F3220 Product Specification 11.13.20.4 USI1 I2C Slave Receiver To operate I2C in slave receiver, follow the recommended steps below. 8. If the main operating clock (SCLK) of the system is slower than that of SCL1, load value 0x00 into USI1SDHR to make SDA1 change within one system clock period from the falling edge of SCL1. Note that the hold time of SDA1 is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from USI1SDHR. When the hold time of SDA1 is longer than the period of SCLK, I2C (slave) cannot transmit serial data properly. 9. Enable I2C by setting USI1MS[1:0] bits in USI1CR1, IIC1IE bit in USI1CR4 and USI1EN bit in USI1CR2. This provides main clock to the peripheral. 10. When a START condition is detected, I2C receives one byte of data and compares it with USI1SLA[6:0] bits in USI1SAR. If the GCALL1 bit in USI1SAR is enabled, I2C1 compares the received data with value 0x00, the general call address. 11. If the received address does not equal to SLA1 bits in USI1SAR, I2C enters idle state ie, waits for another START condition. Else if the address equals to SLA1 bits and the ACK1EN bit is enabled, I2C generates SSEL1 interrupt and the SCL1 line is held LOW. Note that even if the address equals to SLA1 bits, when the ACK1EN bit is disabled, I2C enters idle state. When SSEL1 interrupt occurs and I2C is ready to receive data, write arbitrary value to USI1ST2 to release SCL1 line. 12. 1-Byte of data is being received. 13. In this step, I2C generates TEND1 interrupt and holds the SCL1 line LOW regardless of the reception of ACK signal from master. Slave can select one of the following cases. 1) No ACK signal is detected (ACK1EN=0) and I2C waits STOP or repeated START condition. 2) ACK signal is detected (ACK1EN=1) and I2C can continue to receive data from master. After doing one of the actions above, write arbitrary value to USI1ST2 to release SCL1 line. In case of 1) move to step 7 to terminate communication. In case of 2) move to step 5. In either case, a repeated START condition can be detected. For that case, move step 4. 14. This is the final step for slave receiver function of I2C, handling STOP interrupt. The STOPC1 bit indicates that data transfer between master and slave is over. To clear USI1ST2, write any value to USI1ST2. After this, I2C enters idle state. PS029902-0212 PRELIMINARY 247 Z51F3220 Product Specification The process can be depicted as following figure when I2C operates in slave receiver mode. IDLE S or Sr SLA+W GCALL 0x95 0x1D ACK LOST& N Y 0x15 DATA 0x20 Y 0x45 ACK Y N STOP P 0x44 IDLE From master to slave / Master command or Data Write From slave to master 0xxx Value of Status Register ACK Interrupt, SCL1 line is held low P Interrupt after stop command LOST& Arbitration lost as master and addressed as slave GCALL General Call Address Figure 11.97 Formats and States in the Slave Receiver Mode (USI1) PS029902-0212 PRELIMINARY 248 Z51F3220 Product Specification 11.13.21 USI1 I2C Block Diagram IIC1IFR RXACK1, GCALL 1, TEND1, STOPD1, SSEL 1, MLOST1, BUSY1, TMODE1 Interrupt Generator To interrupt block Slave Address R egister USI1SAR IIC1IE General C all And Address D etector Receive Shift Register ( RXSR) SDA1 SDA1 I n/Out Controller N-ch VSS ACK Signal Generator USI1DR, (Rx) ACK1EN STOPC1 STOP /START Condition Generator SCL1 Out Controller SCL1 USI1DR, (Tx) SDA H old T ime R egister USI1SDHR Time Generator And Time C ontroller I N T E R N A L B U S STARTC1 Transmit Shift R egister (TXSR) USI1GCE L I N E SCL H igh Period R egister USI1SCHR SCL Low Period R egister USI1SCLR N-ch SCLK (fx: Sy stem c lock) VSS NOTE) When the USI1 block is an I2C mode and the corresponding port is an sub-function for SCL1/SDA1 pin, the SCL1/SDA1 pins are automatically set to the N-channel open-drain outputs and the input latch is read in the case of reading the pins. The corresponding pull-up resistor is determined by the control register. Figure 11.98 USI1 I2C Block Diagram PS029902-0212 PRELIMINARY 249 Z51F3220 Product Specification 11.13.22 Register Map Table 11-24 USI1 Register Map Name Address USI1BD F3H Dir R/W Default FFH Description USI1 Baud Rate Generation Register USI1DR F5H R/W 00H USI1 Data Register USI1SDHR F4H R/W 01H USI1 SDA Hold Time Register USI1SCHR F7H R/W 3FH USI1 SCL High Period Register USI1SCLR F6H R/W 3FH USI1 SCL Low Period Register USI1SAR EDH R/W 00H USI1 Slave Address Register USI1CR1 E9H R/W 00H USI1 Control Register 1 USI1CR2 EAH R/W 00H USI1 Control Register 2 USI1CR3 EBH R/W 00H USI1 Control Register 3 USI1CR4 ECH R/W 00H USI1 Control Register 4 USI1ST1 F1H R/W 80H USI1 Status Register 1 USI1ST2 F2H R 00H USI1 Status Register 2 11.13.23 USI1 Register Description USI1 module consists of USI1 baud rate generation register (USI1BD), USI1 data register (USI1DR), USI1 SDA hold time register (USI1SDHR), USI1 SCL high period register (USI1SCHR), USI1 SCL low period Register (USI1SCLR), USI1 slave address register (USI1SAR), USI1 control register 1/2/3/4 (USI1CR1/2/3/4), USI1 status register 1/2 (USI1ST1/2). 11.13.24 Register Description for USI1 USI1BD (USI1 Baud- Rate Generation Register: For UART and SPI mode) : F3H 7 6 5 4 3 2 1 0 USI1BD7 USI1BD 6 USI1BD 5 USI1BD 4 USI1BD 3 USI1BD 2 USI1BD 1 USI1BD 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : FFH USI1BD[7:0] The value in this register is used to generate internal baud rate in asynchronous mode or to g enerate S CK1 c lock in SPI m ode. To prevent malfunction, do not write ‘0’ in asynchronous mode and do not write ‘0’ or ‘1’ in SPI mode. NOTE) In co mmon with U SI1SAR register, USI1BD r egister i s used for slave address register when the USI1 I2C mode. PS029902-0212 PRELIMINARY 250 Z51F3220 Product Specification USI1DR (USI1 Data Register: For UART, SPI, and I2C mode) : F5H 7 6 5 4 3 2 1 0 USI1DR7 USI1DR 6 USI1DR 5 USI1DR 4 USI1DR 3 USI1DR 2 USI1DR 1 USI1DR 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 00H The USI1 transmit b uffer a nd r eceive buffer s hare the s ame I/O address with t his DAT A register. The t ransmit da ta buffer is th e destination for data written t o the USI 1DR register. Rea ding the USI1DR register returns the contents of the receive buffer. Write to this register only when the DRE1 flag is set. In SPI master mode, the SCK1 clock is generated when data are written to this register. USI1DR[7:0] USI1SDHR (USI1 SDA Hold Time Register: For I2C mode) : F4H 7 6 5 4 3 2 1 0 USI1SDHR7 USI1SDHR6 USI1SDHR5 USI1SDHR 4 USI1SDHR 3 USI1SDHR 2 USI1SDHR 1 USI1SDHR 0 R/W R/W R/W R/W R/W R/W R/W USI1SDHR[7:0] R/W Initial value : 00H The register is us ed to control SDA1 output timing from the falling edge of SCL1 in I2C mode. NOTE) That S DA1 is changed after tSCLK X ( USI1SDHR+2), in master SDA1 change in the middle of SCL1. In s lave mode, configure this reg ister r egarding the frequency of SCL1 from master. The SDA1 i s ch anged after t sclk X (USI1SDHR+2) in master mode. So, to insure operation in slave mode, the value tSCLK X (USI1SDHR +2) must be smaller than the period of SCL1. USI1SCHR (USI1 SCL High Period Register: For I2C mode) : F7H 7 6 5 4 3 2 1 0 USI1SCHR7 USI1SCHR6 USI1SCHR5 USI1SCHR 4 USI1SCHR 3 USI1SCHR 2 USI1SCHR 1 USI1SCHR 0 R/W R/W R/W R/W R/W R/W R/W USI1SCHR[7:0] R/W Initial value : 00H This register defines the high period of SCL1 when it operates in I2C master mode. The b ase c lock is S CLK, the s ystem c lock, and t he p eriod i s calculated by the formula: tSCLK X (4 X USI1SCHR +2) where tSCLK is the period of SCLK. So, the operating frequency of I2C master mode is calculated by the following equation. fI2C = PS029902-0212 1 tSCLK X (4 X (USI1SCLR + USI1SCHR + 4)) PRELIMINARY 251 Z51F3220 Product Specification USI1SCLR (USI1 SCL Low Period Register: For I2C mode) : F6H 7 6 5 4 3 2 1 0 USI1SCLR7 USI1SCLR6 USI1SCLR5 USI1SCLR 4 USI1SCLR 3 USI1SCLR 2 USI1SCLR 1 USI1SCLR 0 R/W R/W R/W R/W R/W R/W R/W USI1SCLR[7:0] R/W Initial value : 00H This register defines the high period of SCL1 when it operates in I2C master mode. The b ase c lock is S CLK, the s ystem c lock, and t he p eriod i s calculated by the formula: tSCLK X (4 X USI1SCLR +2) where tSCLK is the period of SCLK. USI1SAR (USI1 Slave Address Register: For I2C mode) : EDH 7 6 5 4 3 2 1 0 USI1SLA6 USI1SLA5 USI1SLA4 USI1SLA3 USI1SLA2 USI1SLA1 USI1SLA0 USI1GCE R/W R/W R/W R/W R/W R/W R/W PS029902-0212 R/W Initial value : 00H USI1SLA[6:0] These bits c onfigure the slave address of I2C when it operaties in I2C slave mode. UPM[1:0] This bi t dec ides whether I2 C allows general cal l ad dress o r not i n I2C slave mode. 0 Ignore general call address 1 Allow general call address PRELIMINARY 252 Z51F3220 Product Specification USI1CR1 (USI1 Control Register 1: For UART, SPI, and I2C mode) : E9H 7 6 5 4 3 2 1 0 USI1S0 CPHA1 CPOL1 R/W USI1MS1 USI1MS0 USI1PM1 USI1PM0 USI1S2 USI1S1 ORD1 R/W R/W R/W R/W R/W R/W USI1MS[1:0] USI1PM[1:0] USI1S[2:0] Selects operation mode of USI1 USI1MS1 USI 1MS0 Operation mode 00 Asynchronous Mode (UART) 01 Synchronous Mode 10 I2C mode 11 SPI mode Selects parity generation and check methods (only UART mode) USI1PM1 USI1PM0 Parity 00 No Parity 01 Reserved 10 Even Parity 11 Odd Parity When in asynchronous or synchronous mode of operation, selects the length of data bits in frame USI1S2 USI1 ORD1 USI1S0 Data Length 00 0 5 bit 00 1 6 bit 01 0 7 bit 01 1 8 bit 10 0 Reserved 10 1 Reserved S1 11 0 Reserved 11 1 9 bit This bit in the sa me bi t position w ith USI1S1. The M SB of the da ta byte is t ransmitted first when set to ‘1 ’ and t he LSB when s et t o ‘ 0’ (onl SPI mode) 0 LS B-first 1 MSBCPOL1 CPHA1 PS029902-0212 R/W Initial value : 00H first This bit determines the cl ock p olarity of A CK in s ynchronous or SP I mode. 0 TXD change@Rising Edge, RXD change@Falling Edge 1 TXD change@Falling Edge, RXD change@Rising Edge This bit is in the same bit position with USI1S0. This bit determines if data are sampled on t he le ading or trailing ed ge of SCK 1 (only SPI mode). CPOL1 CPHA1 Leading edge Trailing edge 0 0 Sample (Rising) Setup (Falling) 0 1 Setup (Rising) Sample (Falling) 1 0 Sample (Falling) Setup (Rising) 1 1 Setup (Falling) Sample (Rising) PRELIMINARY 253 Z51F3220 Product Specification USI1CR2 (USI1 Control Register 2: For UART, SPI, and I2C mode) : EAH 7 6 5 4 3 2 1 0 DRIE1 TXCIE1 RXCIE1 WAKEIE1 TXE1 RXE1 USI1EN DBLS1 R/W R/W R/W R/W R/W R/W R/W DRIE1 TXCIE1 RXCIE1 WAKEIE1 TXE1 RXE1 USI1EN DBLS1 PS029902-0212 R/W Initial value : 00H Interrupt enable bit for data register empty (only UART and SPI mode). 0 Interrupt from DRE1 is inhibited (use polling) 1 When DRE1 is set, request an interrupt Interrupt enable bit for transmit complete (only UART and SPI mode). 0 Interrupt from TXC1 is inhibited (use polling) 1 When TXC1 is set, request an interrupt Interrupt enable bit for receive complete (only UART and SPI mode). 0 Interrupt from RXC1 is inhibited (use polling) 1 When RXC1 is set, request an interrupt Interrupt enable bit for asynchronous wake in STOP mode. When device is in stop mode, if RXD1 goes to low level an interrupt can be requested to wake-up system. (o nly UAR T mode). At t hat time the DRIE1 b it and USI1ST1 register value should be set to ‘0b’ and “00H”, respectively. 0 Interrupt from Wake is inhibited 1 When WAKE1 is set, request an interrupt Enables the transmitter unit (only UART and SPI mode). 0 Tr ansmitter is disabled 1 Tr ansmitter is enabled Enables the receiver unit (only UART and SPI mode). 0 Receiv er is disabled 1 Receiv er is enabled Activate USI1 function block by supplying. 0 USI 1 is disabled 1 USI 1 is enabled This bit selects receiver sampling rate (only UART) 0 Normal asynchronous operation 1 Double Speed asynchronous operation PRELIMINARY 254 Z51F3220 Product Specification USI1CR3 (USI1 Control Register 3: For UART, SPI, and I2C mode) : EBH 7 6 5 4 3 2 1 0 MASTER1 LOOPS1 DISSCK1 USI1SSEN FXCH1 USI1SB USI1TX8 USI1RX8 R/W R/W R/W R/W R/W R/W R/W MASTER1 LOOPS1 DISSCK1 USI1SSEN Selects master or s lave in S PI a nd s ynchronous mode operation an d controls the direction of SCK1 pin 0 Slave mode operation (External clock for SCK1). 1 Master mode operation(Internal clock for SCK1). Controls the loop back mode of USI1 for test mode (only UART and SPI mode) 0 Nor mal operation 1 Loo p Back mode In synchronous mode of operation, selects the waveform of SCK1 output 0 ACK i s f ree-running while UART is en abled i n s ynchronous master mode 1 ACK is active while any frame is on transferring This bit controls the SS1 pin operation (only SPI mode) 0 Di sable 1 FXCH1 Enable (The SS1 pin should be a normal input) SPI port function exchange control bit (only SPI mode) 0 No effect 1 USI1SB USI1TX8 USI1RX8 PS029902-0212 R Initial value : 00H Exchange MOSI1 and MISO1 function Selects the length o f stop b it i n a synchronous o r synchronous mode of operation. 0 1 Stop Bit 1 2 Stop Bit The ninth bit of data frame in asynchronous or s ynchronous mode of operation. Write this bit first before loading the USI1DR register 0 MSB (9th bit) to be transmitted is ‘0’ 1 MSB (9th bit) to be transmitted is ‘1’ The ninth bit of data frame in asynchronous or s ynchronous mode of operation. Read this bit first before reading the receive buffer (only UART mode). 0 MSB (9th bit) received is ‘0’ 1 MSB (9th bit) received is ‘1’ PRELIMINARY 255 Z51F3220 Product Specification USI1CR4 (USI1 Control Register 4: For I2C mode) : ECH 7 6 5 4 3 2 1 0 IIC1IFR – TXDLYENB1 IIC1IE ACK1EN IMASTER1 STOPC1 STARTC1 R – R/W R/W R/W R R/W IIC1IFR TXDLYENB1 This is an interrupt flag bit for I2C mode. When an interrupt occurs, this bit becomes ‘1’. This bit is cleared when write any values in th USI1ST2. 0 I2C interrupt no generation 1 I2C interrupt generation USI1SDHR register control bit 0 Enab 1 IIC1IE ACK1EN R/W Initial value : 00H le USI1SDHR register Disable USI1SDHR register Interrupt Enable bit for I2C mode 0 Interrupt from I2C is inhibited (use polling) 1 Enable interrupt for I2C Controls ACK signal Generation at ninth SCL1 period. 0 No ACK signal is generated (SDA1 =1) 1 ACK signal is generated (SDA1 =0) NOTES) ACK signal is output (SDA1 =0) for the following 3 cases. 1. When received address packet equals to USI1SLA bits in USI1SAR. 2. When re ceived a ddress packet eq uals to value 0x0 0 with GC ALL1 enabled. 3. When I2C operates as a receiver (master or slave) IMASTER1 STOPC1 Represent operating mode of I2C 0 I2C is in slave mode 1 I2C is in master mode When I2C is master, STOP condition generation 0 No 1 STARTC1 When I2C is master, START condition generation 0 No 1 PS029902-0212 effect STOP condition is to be generated effect START or repeated START condition is to be generated PRELIMINARY 256 Z51F3220 Product Specification USI1ST1 (USI1 Status Register 1: For UART and SPI mode) : F1H 7 6 5 4 3 2 1 0 DRE1 TXC1 RXC1 WAKE1 USI1RST DOR1 FE1 PE1 R/W R/W R R/W R/W R R/W DRE1 TXC1 RXC1 WAKE1 USI1RST The DR E1 flag i ndicates if the t ransmit buffer (U SI1DR) i s rea dy to receive ne w da ta. If DRE1 is ‘ 1’, the buf fer i s em pty and re ady to be written. This flag can generate a DRE1 interrupt. 0 Transmit buffer is not empty. 1 Transmit buffer is empty. This flag i s s et when the entire f rame i n the transmit s hift reg ister has been s hifted out a nd ther e is no new data cu rrently present in the transmit b uffer. T his flag is automatically cleared when the i nterrupt service routine of a TXC1 interrupt is executed. This flag can generate a TXC1 interrupt. This bit is automatically cleared. 0 Transmission is ongoing. 1 Transmit buffer i s emp ty and th e dat a i n transmit sh ift reg ister are shifted out completely. This flag is s et when there are unread dat a i n the re ceive bu ffer and cleared when all the data in the receive buffer are read. The RXC1 flag can be used to generate a RXC1 interrupt. 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer This flag is set when the RXD1 pin is detected low while the CPU is in STOP mode. This flag can be used to generate a WAKE1 interrupt. This bit is set only when in asynchronous mode of operation. This bit should be cleared by program software. (only UART mode) 0 No WAKE interrupt is generated. 1 WAKE interrupt is generated This is an internal reset and only has effect on USI1. Writing ‘1’ to this bit initializes the internal logic of USI1 and this bit is automatically cleared to ‘0’. 0 No operation 1 Reset DOR1 No Data OverRun 1 Data PE1 OverRun detected This bit is set if the first stop bit of next character in the receive buffer is detected as ‘0’. This bit is v alid un til the rec eive buffer i s read. ( only UART mode) 0 No Frame Error 1 Frame Error detected This bit is set if the next character in the receive buffer has a Parity Error to be received while Parity Checking is enabled. This bit is valid until the receive buffer is read. (only UART mode) 0N o Parity Error 1 Parit PS029902-0212 USI1 This bit is set if a Data OverRun occurs. While this bit is set, the incoming data frame is ignored. This flag is valid until the receive buffer is read. 0 FE1 R/W Initial value : 80H y Error detected PRELIMINARY 257 Z51F3220 Product Specification USI1ST2 (USI1 Status Register 2: For I2C mode) : F2H 7 6 5 4 3 2 1 0 GCALL1 TEND1 STOPD1 SSEL1 MLOST1 BUSY1 TMODE1 RXACK1 R R/W R/W R/W R/W R/W R/W R/W Initial value : 00H GCALL1(NOTE) This bit has d ifferent m eaning depending on whether I 2C is ma ster o r slave. Wh en I2 C i s a ma ster, this bit represents whether it received AACK (address ACK) from slave. 0 No AACK is received (Master mode) 1 AACK is received (Master mode) When I2C is a slave, this bit is used to indicated general call. TEND1 (NOTE) 0 General call address is not detected (Slave mode) 1 General call address is detected (Slave mode) This bit is set when 1-byte of data is transferred completely 0 1 byte of data is not completely transferred 1 1 byte of data is completely transferred STOPD1(NOTE) This bit is set when a STOP condition is detected. SSEL1 (NOTE) MLOST1 (NOTE) BUSY1 TMODE1 RXACK1 0 No STOP condition is detected 1 STOP condition is detected This bit is set when I2C is addressed by other master. 0 I2C is not selected as a slave 1 I2C is addressed by other master and acts as a slave This bit represents the result of bus arbitration in master mode. 0I 2C maintains bus mastership 1 I2C maintains bus mastership during arbitration process This bit reflects bus status. 0 I2C bus is idle, so a master can issue a START condition 1 I2C bus is busy This bit is used to indicate whether I2C is transmitter or receiver. 0I 2C is a receiver 1 I2C is a transmitter This bit shows the state of ACK signal 0 No ACK is received 1 ACK is received at ninth SCL period NOTE) These bits can be source of interrupt. When an I2C interrupt oc curs e xcept f or S TOP mo de, t he S CL1 line is h old LOW. T o release SC L1, write r bitrary value to USI 1ST2. When USI1ST2 is written, the T END1, STOPD1, SSEL1, MLOST1, and RXACK1 bits are cleared. PS029902-0212 PRELIMINARY 258 Z51F3220 Product Specification 11.14.1 Baud Rate setting (example) Table 11-25 Examples of USI0BD and USI1BD Settings for Commonly Used Oscillator Frequencies = fx 1.00MHz f =x 1.8432MHz Baud Rate USI0BD/USI1BD ERROR US I0BD/USI1BD ERRO = fx 2.00MHz R US I0BD/USI1BD ERROR 2400 25 0.2% 47 0. 0% 51 4800 12 0.2% 23 0. 0% 25 0.2% 9600 6 -7.0% 11 0. 0% 12 0.2% 14.4k 3 8.5% 7 0.0% 8 -3.5% 19.2k 2 8.5% 5 0.0% 6 -7.0% 28.8k 1 8.5% 3 0.0% 3 38.4k 1 57.6k -18.6% 2 0.0% - - 1 -25. - 1 115.2k - ----- 230.4k - ----- 76.8k - 0.2% 8.5% 2 0% 1 0.0% 8.5% 8.5% 1 -18.6% (continued) = fx 3.6864MHz f =x 4.00MHz f Baud Rate USI0BD/USI1BD ERROR US I0BD/USI1BD ERRO 2400 95 0.0% 10 4800 47 0.0% 51 9600 23 14.4k 19.2k 3 =x 7.3728MHz R US I0BD/USI1BD ERROR 0.2% 191 0.0% 0. 2% 95 0.0% 0.0% 25 0. 2% 47 0.0% 15 0.0% 16 2. 1% 31 0.0% 11 0.0% 12 0. 2% 23 0.0% 28.8k 7 0.0% 8 -3.5% 15 38.4k 5 0.0% 6 -7.0% 11 0.0% 0.0% 57.6k 3 0.0% 3 8.5% 7 0.0% 0.0% 76.8k 2 0.0% 2 8.5% 5 115.2k 1 0.0% 1 8.5% 3 230.4k - --- 1 0.0% 250k - --- 1 -7.8% 0.5M - ----- 0.0% (continued) = fx 8.00MHz f Baud Rate USI0BD/USI1BD ERRO 2400 20 7 =x 11.0592MHz R 0.2% 4800 103 0. 2% 143 9600 51 0. 2% 14.4k 34 -0.8% USI0BD/USI1BD ERRO R - 0. 0% 71 0. 0% 47 0.0% 19.2k 25 0. 2% 35 0. 0% 28.8k 16 2. 1% 23 0. 0% 38.4k 12 0. 2% 17 0. 57.6k 8 -3.5% 0% 11 0.0% 76.8k 6 -7. 0% 8 0.0% 115.2k 3 8. 5% 5 0.0% 230.4k 1 8. 5% 2 0.0% 250k 1 0. 0% 2 -7.8% 0.5M - --- 1M - --- PS029902-0212 PRELIMINARY 259 Z51F3220 Product Specification 11.15 LCD Driver 11.15.1 Overview The LCD driver is controlled by the LCD Control Register (LCDCRH/L). The LCLK[1:0] determines the frequency of COM signal scanning of each segment output. A RESET clears the LCD control register LCDCRH and LCDCRL values to logic ‘0’. The LCD display can continue operating during IDLE and STOP modes if a sub-frequency clock is used as system clock source. PS029902-0212 PRELIMINARY 260 Z51F3220 Product Specification 11.15.2 LCD Display RAM Organization Display data are stored to the display data area in the external data memory. The display data which stored to the display external data area (address 0000H-001AH) are read automatically and sent to the LCD driver by the hardware. The LCD driver generates the segment signals and common signals in accordance with the display data and drive method. Therefore, display patterns can be changed by only overwriting the contents of the display external data area with a program. Figure 11-99 shows the correspondence between the display external data area and the COM/SEG pins. The LCD is turned on when the display data is “1” and turned off when “0”. SEG 26 001 AH SEG 25 0019 H SEG 24 0018 H SEG 23 0017 H SEG 22 0016 H SEG 7 0007 H SEG 6 0006 H SEG 5 0005 H SEG 4 0004 H SEG 3 0003 H SEG 2 0002 H SEG 1 0001 H SEG 0 0000 H bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 C O M 0 C O M 1 C O M 2 C O M 3 C O M 4 C O M 5 C O M 6 C O M 7 Figure 11.99 LCD Circuit Block Diagram PS029902-0212 PRELIMINARY 261 Z51F3220 Product Specification 11.15.3 LCD Signal Waveform COM0 0 1 0 1 VDD SEG0 VSS 1 Frame COM1 VLC0 VLC2(VLC1, VLC3) COM0 VSS SEG1 SEG2 SEG3 VLC0 COM1 VLC2(VLC1, VLC3) VSS VLC0 VLC2(VLC1, VLC3) SEG0 VSS VLC0 VLC2(VLC1, VLC3) SEG1 VSS +VLC0 +VLC2(VLC1, VLC3) COM0-SEG0 VSS -VLC2(VLC1, VLC3) -VLC0 Figure 11.100 LCD Signal Waveforms (1/2Duty, 1/2Bias) PS029902-0212 PRELIMINARY 262 Z51F3220 Product Specification SEG3 SEG2 SEG1 0 1 2 0 1 2 VDD VSS COM0 1 Frame VLC0 COM1 COM0 VLC1 VLC2(VLC3) VSS COM2 VLC0 COM1 VLC1 VLC2(VLC3) VSS VLC0 COM2 VLC1 VLC2(VLC3) VSS VLC0 SEG1 VLC1 VLC2(VLC3) VSS VLC0 SEG2 VLC1 VLC2(VLC3) VSS +VLC0 +VLC1 +VLC2(VLC3) COM0-SEG1 VSS -VLC2(VLC3) -VLC1 -VLC0 Figure 11.101 LCD Signal Waveforms (1/3Duty, 1/3Bias) PS029902-0212 PRELIMINARY 263 Z51F3220 Product Specification SEG3 SEG2 0 1 2 3 0 1 2 3 VDD VSS COM0 1 Frame COM1 COM2 VLC0 VLC1 COM0 VLC2(VLC3) VSS COM3 VLC0 VLC1 COM1 VLC2(VLC3) VSS VLC0 VLC1 COM2 VLC2(VLC3) VSS VLC0 VLC1 SEG2 VLC2(VLC3) VSS VLC0 VLC1 SEG3 VLC2(VLC3) VSS +VLC0 +VLC1 +VLC2(VLC3) COM0-SEG2 VSS -VLC2(VLC3) -VLC1 -VLC0 Figure 11.102 LCD Signal Waveforms (1/4Duty, 1/3Bias) PS029902-0212 PRELIMINARY 264 Z51F3220 Product Specification COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 VDD VSS 1 Frame S E G 6 S E G 7 S E G 8 S E G 9 S E G 1 0 COM0 VLC0 VLC1 VLC2 VLC3 VSS COM1 VLC0 VLC1 VLC2 VLC3 VSS COM2 VLC0 VLC1 VLC2 VLC3 VSS SEG6 VLC0 VLC1 VLC2 VLC3 VSS SEG7 VLC0 VLC1 VLC2 VLC3 VSS +VLC0 +VLC1 +VLC2 +VLC3 VSS -VLC3 -VLC2 -VLC1 -VLC0 COM0-SEG6 Figure 11.103 LCD Signal Waveforms (1/8Duty, 1/4Bias) PS029902-0212 PRELIMINARY 265 Z51F3220 Product Specification 11.15.4 LCD Voltage Dividing Resistor Connection ( 1/ 2 Bias , 160 K ohm) (1/ 2 Bias, 80K ohm ) VLCD R R R VLC0 VLC1 VLC2 VLC3 Contrast Cont roller Cont rast Controller R VLC0 VLC1 VLC2 (1/ 3 BIAS) VLC3 VSS DISP LCTEN VLC0 VLC1 VLC2 VLC3 VLC1 VLC2 VLC3 VLCD Contrast Controller Contrast Controller VLC2 VLC2 VSS VLC0 R VLC1 VLC1 (1/ 4 BIAS) R VLC0 R DISP LCTEN VLC3 VLCD R R VLC0 VSS DISP LCTEN VLCD R R R R VLC0 VLC1 VLC2 VLC3 VSS DISP LCTEN VLC3 VLC0 VLC1 VLC2 VLC3 NOTES) 1. The above figures are for the internal resistor bias connection. So, It is not needed an external connection. 2. When the internal resistors are selected, all the P40/VLC3, P41/VLC2, P42/VLC1 and P43/VLC0 pins can be used for normal I/O. Figure 11.104 Internal Resistor Bias Connection PS029902-0212 PRELIMINARY 266 Z51F3220 Product Specification (1/ 2 BI AS) VLCD Contrast Controller DISP LCTEN VLC0 VLC1 VLC2 R’ VLC3 R’ VSS (1/ 3 BIAS) (1/ 4 BIAS) VLCD VLCD Contrast Controller Contrast Controller DISP LCTEN DISP LCTEN VLC0 VLC1 VLC2 R’ R’ R’ VLC3 VLC0 VLC1 VLC2 VLC3 R’ R’ R’ R’ VSS VSS NOTES) 1. When the external resistor bias is selected, the internal resistors for bias are disconnected. 2. When the external resistor bias is selected, the dividing resistors should be connected like the above figure and the needed bias pins should be selected as the LCD bias function pins (VLC0, VLC1, VLC2, and VLC3) by P4FSR register. - When it is 1/2 bias, the P43/VLC0 and P41/VLC2 pins should be selected as VLC0 and VLC2 functions. The other pins can be used for normal I/O. - When it is 1/3 bias, the P43/VLC0, P42/VLC1, and P41/VLC2 pins should be selected as VLC0, VLC1, and VLC2 functions. Another pin can be used for normal I/O. - When it is 1/4 bias, the P43/VLC0, P42/VLC1, P41/VLC2, and P40/VLC3 pins should be selected as VLC0, VLC1, VLC2, and VLC3 functions Figure 11.105 External Resistor Bias Connection PS029902-0212 PRELIMINARY 267 Z51F3220 Product Specification 11.15.5 Block Diagram Port Latch SEG/Port Driver LCD Display RAM COM/Port Driver fLCD Timing Controller LCDCRL LCDCRH LCDCCR VLC0 LCD Bias Voltage Generator Contrast Controller VLC1 VLC2 VLC3 Figure 11.106 LCD Circuit Block Diagram 11.15.6 Register Map Table 11-26 LCD Register Map Name Address LCDCRH 9AH LCDCRL 99H LCDCCR 9BH Dir Default Description R/W 00H LCD Driver Control High Register R/W 00H LCD Driver Control Low Register R/W 00H LCD Contrast Control Register 11.15.7 LCD Driver Register Description LCD driver register has two control registers, LCD driver control high register (LCDCRH), LCD driver control low register (LCDCRL) and LCD contrast control register. PS029902-0212 PRELIMINARY 268 Z51F3220 Product Specification 11.15.8 Register Description for LCD Driver LCDCRH (LCD Driver Control High Register) : 9AH 7 6 5 4 3 2 1 0 – – – COMCHG – – LCDDR DISP – – – R/W – – R/W COMCHG R/W Initial value : 00H Common Signal Output Port Change Control 0 COM0 – COM3 signals are outputted through the P37-P34 1 COM0 – COM3 signals are outputted through the P33-P30 NOTES) 1. The COM0/COM1/COM2/COM3 signals can be outputted through the P33/P32/P31/P30, respectively. 2. For example, the COM0 signal may be outputted to P33 pin if the P3FSR.3 is “1b” and the COMCHG bit is “1b”. 3. Refer to the port3 function selection register (P3FSR). 4. Available only below the 1/4 duty. LCDDR DISP LCD Driving Resistor for Bias Select 0 Internal LCD driving resistors for bias 1 External lCD driving resistors for bias LCD Display Control 0 Dis 1 PS029902-0212 play off Normal display on PRELIMINARY 269 Z51F3220 Product Specification LCDCRL (LCD Driver Control Low Register) : 99H 7 6 5 4 3 2 1 0 – – DBS3 DBS2 DBS1 DBS0 LCLK1 LCK0 – – R./W R/W R/W R/W R/W DBS[3:0] LCD Duty and Bias Select (NOTE) DBS3 DBS2 DBS1 DBS0 Description 00 0 0 1/8Duty, 1/4Bias (60k ohm) 0 0 0 1 1/6Duty, 1/4Bias (60k ohm) 0 0 1 0 1/5Duty, 1/3Bias (60k ohm) 0 0 1 1 1/4Duty, 1/3Bias (60k ohm) 0 1 0 0 1/3Duty, 1/3Bias (60k ohm) 0 1 01 0 1 10 0 1 1/3Duty, 1/2Bias (60k ohm) 1 0 1/3Duty, 1/2Bias (120k ohm) 1 1 1/2Duty, 1/2Bias (60k ohm) 0 0 1/2Duty, 1/2Bias (120k ohm) Other values LCLK[1:0] R/W Initial value : 00H Not available LCD Clock Select (When fWCK(Watch timer clock)= 32.768 kHz) LCLK1 LCLK 0 Description 00 fLCD = 128Hz 01 fLCD = 256Hz 10 fLCD = 512Hz 11 fLCD = 1024Hz NOTE) Th e LC D clock i s generated by watch t imer cl ock (fWCK). S o the watch timer should be enabled when the LCD display is turned on. PS029902-0212 PRELIMINARY 270 Z51F3220 Product Specification LCDCCR (LCD Driver Contrast Control Low Register) : 9BH 7 6 5 4 3 2 1 0 LCTEN – – – VLCD3 VLCD VLCD1 VLCD0 R/W – – – R/W R/W R/W LCTEN VLCD[3:0] R/W Initial value : 00H Control LCD Driver Contrast 0 LCD Driver Contrast disable 1 LCD Driver Contrast enable VLC0 Voltage Control when the contrast is enabled VLCD3 VLCD 2 VLCD 1 VLCD 0 Description 0 0 00 V = LC0 VDD x 16/31 step 0 0 01 V = LC0 VDD x 16/30 step 0 0 10 V = LC0 VDD x 16/29 step 0 0 11 V = LC0 VDD x 16/28 step 0 1 00 V = LC0 VDD x 16/27 step 0 1 01 V = LC0 VDD x 16/26 step 0 1 10 V = LC0 VDD x 16/25 step 0 1 11 V = LC0 VDD x 16/24 step 1 0 00 V = LC0 VDD x 16/23 step 1 0 01 V = LC0 VDD x 16/22 step 1 0 10 V = LC0 VDD x 16/21 step 1 0 11 V = LC0 VDD x 16/20 step 1 1 00 V = LC0 VDD x 16/19 step 1 1 01 V = LC0 VDD x 16/18 step 1 1 10 V = LC0 VDD x 16/17 step 1 1 11 V = LC0 VDD x 16/16 step NOTES) The LCD contrast step is based on 1/4 bias. 1/4 bias : VDD x (16/31 – VLC[3:0]) 1/3 bias : VDD x (12/27 – VLC[3:0]) 1/2 bias : VDD x (8/23 – VLC[3:0]) PS029902-0212 PRELIMINARY 271 Z51F3220 Product Specification 12. Power Down Operation 12.1 Overview The Z51F3220 has two power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. The device provides three kinds of power saving functions, Main-IDLE, Sub-IDLE and STOP mode. In three modes, program is stopped. 12.2 Peripheral Operation in IDLE/STOP Mode Table 12-1 Peripheral Operation during Power Down Mode Peripheral ID CPU RAM R LE Mode ALL CPU Operation are Disable etain STOP Mode ALL CPU Operation are Disable Retain Basic Interval Timer Operates Continuously Watch Dog Timer Operates Continuously Stop Stop (Can be operated with WDTRC OSC) Watch Timer Operates Continuously Stop (Can be operated with sub clock) Timer0~4 O perates Continuously Halted (Only when the Event Counter Mode is Enabled, Timer operates Normally) ADC O perates Continuously Stop BUZ O SPI perates Continuously Stop Operates Continuously Only operate with external clock USI0/1 Operates Continuously Only operate with external clock LCD Controller Operates Continuously Stop (Can be operated with sub clock) Internal OSC (16MHz) Oscillation Stop when the system clock (fx) is fIRC WDTRC OSC (5kHz) Stop Can be operated with setting value Main OSC (0.4~12MHz) Oscillation Stop when fx = fXIN Sub OSC (32.768kHz) Oscillation Stop when fx = fSUB I/O Port Retain Retain Control Register Retain Retain Address Data Bus Retain Retain By RESET, Timer Interrupt (EC0, EC1, EC3), SPI (External clock), External Interrupt, UART by ACK, WT (sub clock), WDT Release Method PS029902-0212 By RESET, all Interrupts PRELIMINARY 272 Z51F3220 Product Specification 12.3 IDLE Mode The power control register is set to ‘01h’ to enter the IDLE Mode. In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally but CPU stops. It is released by reset or interrupt. To be released by interrupt, interrupt should be enabled before IDLE mode. If using reset, because the device becomes initialized state, the registers have reset value. OSC CPU Clock External Interrupt Release Normal Operation Stand-by Mode Normal Operation Figure 12.1 IDLE Mode Release Timing by External Interrupt PS029902-0212 PRELIMINARY 273 Z51F3220 Product Specification 12.4 STOP Mode The power control register is set to ‘03H’ to enter the STOP Mode. In the stop mode, the selected oscillator, system clock and peripheral clock is stopped, but watch timer can be continued to operate with sub clock. With the clock frozen, all functions are stopped, but the on-chip RAM and control registers are held. For example, If the internal RC oscillator (fIRC) is selected for the system clock and the sub clock (fSUB) is oscillated, the internal RC oscillator stops oscillation and the sub clock is continuously oscillated in stop mode. At that time, the watch timer and LCD controller can be operated with the sub clock. The source for exit from STOP mode is hardware reset and interrupts. The reset re-defines all the control registers. When exit from STOP mode, enough oscillation stabilization time is required to normal operation. Figure 12.2 shows the timing diagram. When released from STOP mode, the Basic interval timer is activated on wake-up. Therefore, before STOP instruction, user must be set its relevant prescale divide ratio to have long enough time. This guarantees that oscillator has started and stabilized. OSC CPU Clock Release External Interrupt STOP Instruction Execute BIT Counter n n+1 n+2 n+3 0 1 2 FE FF 0 1 Clear & Start By Software setting Normal Operation STOP Operation Normal Operation Before executed STOP instruction, BIT must be set properly by software to get stabilization. Figure 12.2 STOP Mode Release Timing by External Interrupt PS029902-0212 PRELIMINARY 274 Z51F3220 Product Specification 12.5 Release Operation of STOP Mode After STOP mode is released, the operation begins according to content of related interrupt register just before STOP mode start (Figure 12.3). If the global interrupt Enable Flag (IE.EA) is set to `1`, the STOP mode is released by the interrupt which each interrupt enable flag = `1` and the CPU jumps to the relevant interrupt service routine. Even if the IE.EA bit is cleared to ‘0’, the STOP mode is released by the interrupt of which the interrupt enable flag is set to ‘1’. SET PCON[7:0] SET IEx.b STOP Mode Interrupt Request Corresponding Interrupt Enable Bit(IE, IE1, IE2, IE3) N IEx.b==1 ? Y STOP Mode Release Interrupt Service Routine Next Instruction Figure 12.3 STOP Mode Release Flow PS029902-0212 PRELIMINARY 275 Z51F3220 Product Specification 12.5.1 Register Map Table 12-2 Power Down Operation Register Map Name Address Dir PCON 87H Default R/W Description 00H Power Control Register 12.5.2 Power Down Operation Register Description The power down operation register consists of the power control register (PCON). 12.5.3 Register Description for Power Down Operation PCON (Power Control Register) : 87H 7 6 5 4 3 2 1 0 PCON7 – – – PCON3 PCON2 PCON1 PCON0 R/W – – – R/W R/W R/W PCON[7:0] R/W Initial value : 00H Power Control 01H IDLE mode enable 03H ST OP mode enable Other Values Normal operation NOTES) 1. To enter IDLE mode, PCON must be set to ‘01H’. 2. To enter STOP mode, PCON must be set to ‘03H’. 3. The PCON register is automatically cleared by a release signal in STOP/IDLE mode. 4. Three or more NOP instructions must immediately follow the instruction that make the device enter STOP/IDLE mode. Refer to the following examples. Ex1) MOV NOP NOP NOP • • • PS029902-0212 PCON, #01H ; IDLE mode Ex2) PRELIMINARY MOV NOP NOP NOP • • • PCON, #03H ; STOP mode 276 Z51F3220 Product Specification 13. RESET 13.1 Overview The following is the hardware setting value. Table 13-1 Reset State On Chip Hardware Initial Value Program Counter (PC) 0000h Accumulator 00h Stack Pointer (SP) 07h Peripheral Clock On Control Register Refer to the Peripheral Registers 13.2 Reset Source The Z51F3220 has five types of reset sources. The following is the reset sources. - External RESETB - Power ON RESET (POR) - WDT Overflow Reset (In the case of WDTEN = `1`) - Low Voltage Reset (In the case of LVREN = `0 `) - OCD Reset 13.3 RESET Block Diagram Ext RESET Disable by FUSE RESET Noise Canceller LVR LVR Enable RESET Noise Canceller POR RST S WDT RST WDT RSTEN R Q Internal Reset IFBIT (BIT Overflow) OCD RST OCD RSTEN Figure 13.1 RESET Block Diagram PS029902-0212 PRELIMINARY 277 Z51F3220 Product Specification 13.4 RESET Noise Canceller The Figure 13.2 is the noise canceller diagram for noise cancellation of RESET. It has the noise cancellation value of about 2us (@VDD=5V) to the low input of system reset. t < TRNC t < TRNC A t > TRNC t > TRNC t > TRNC A’ Figure 13.2 Reset noise canceller timer diagram 13.5 Power on RESET When rising device power, the POR (Power On Reset) has a function to reset the device. If POR is used, it executes the device RESET function instead of the RESET IC or the RESET circuits. Fast VDD Rise Time VDD nPOR (Internal Signal) BIT Overflows BIT Starts Internal RESETB Oscillation Figure 13.3 Fast VDD Rising Time Slow VDD Rise Time, min. 0.15V/mS VPOR=1.4V (Typ) VDD nPOR (Internal Signal) BIT Overflows BIT Starts Internal RESETB Oscillation Figure 13.4 Internal RESET Release Timing On Power-Up PS029902-0212 PRELIMINARY 278 Z51F3220 Product Specification Counting for config read start after POR is released VDD Internal nPOR PAD RESETB “H” LVR_RESETB BIT (for Config) 00 01 02 03 BIT (for Reset) 00 00 .. 27 28 01 F1 02 01 00 04 03 05 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms RESET_SYSB INT-OSC (8MHz) INT-OSC 8MHz/8 INT-OSC 8MHz / 8 = 1MHz (1us) Figure 13.5 Configuration Timing when Power-on :VDD Input :Internal OSC ⑥ ④ Reset Release Config Read ② POR ① ③ ⑤ ⑦ Figure 13.6 Boot Process WaveForm PS029902-0212 PRELIMINARY 279 Z51F3220 Product Specification Table 13-2 Boot Process Description Process Description ① -No Operation ② -1st POR level Detection Remarks -about 1.4V - (INT-OSC 8MHz/8)x256x28h Delay section (=10ms) ③ -VDD input voltage must ris e over tha n fl ash operating voltage for Config read ④ - Config read point ⑤ - Rising section to Reset Release Level -Slew Rate 0.15V/ms -about 1.5V ~ 1.6V -Config V alue is Writing Option determined by -16ms point after POR or Ext_reset release - Reset Release section (BIT overflow) ⑥ i) after16ms, after External Reset Release (External reset) - BIT is used for Peripheral stability ii) 16ms point after POR (POR only) ⑦ -Normal operation PS029902-0212 PRELIMINARY 280 Z51F3220 Product Specification 13.6 External RESETB Input The External RESETB is the input to a Schmitt trigger. If RESETB pin is held with low for at least 10us over within the operating voltage range and stable oscillation, it is applied and the internal state is initialized. After reset state becomes ‘1’, it needs the stabilization time with 16ms and after the stable state, the internal RESET becomes ‘1’. The Reset process step needs 5 oscillator clocks. And the program execution starts at the vector address stored at address 0000H. 1 2 3 4 5 OSC RESETB Release Internal RESETB Release ADDRESS BUS ? ? CORE BUS ? Stabilization Time TST = 16.4ms 00 ? ? 02 01 02 ? ? ? ? RESET Process Step Main Program Figure 13.7 Timing Diagram after RESET PRESCALER COUNT START VDD OSC START TIMING Figure 13.8 Oscillator generating waveform example NOTE) As shown Figure 13.8, the stable generating time is not included in the start-up time. The RESETB pin has a Pull-up register by H/W. PS029902-0212 PRELIMINARY 281 Z51F3220 Product Specification 13.7 Brown Out Detector Processor The Z51F3220 has an On-chip brown-out detection circuit (BOD) for monitoring the VDD level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by LVRVS[3:0] bit to be 1.60V, 2.00V, 2.10V, 2.20V,2.32V, 2.44V, 2.59V, 2.75V, 2.93V, 3.14V, 3.38V, 3.67V, 4.00V, 4.40V. In the STOP mode, this will contribute significantly to the total current consumption. So to minimize the current consumption, the LVREN bit is set to off by software. External VDD LVRVS[3:0] Brown Out Detector (BOD) RESET_BODB LVREN CPU Write SCLK (System CLK) D Q LVRF (Low Voltage Reset Flag) CP r nPOR Figure 13.9 Block Diagram of BOD VDD VBODMAX VBODMIN 16ms Internal RESETB VDD VBODMAX VBODMIN t < 16ms 16ms Internal RESETB Figure 13.10 Internal Reset at the power fail situation PS029902-0212 PRELIMINARY 282 Z51F3220 Product Specification “H” VDD “H” Internal nPOR “H” PAD RESETB LVR_RESETB BIT (for Config) BIT (for Reset) .. 27 28 00 01 02 .. .. F1 00 01 F1 03 02 04 00 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms RESET_SYSB Main OSC Off INT-OSC (8MHz) INT-OSC 8MHz/8 INT-OSC 8MHz / 8 = 1MHz (1us) Figure 13.11 Configuration timing when BOD RESET 13.8 LVI Block Diagram VDD Reference Voltage Generator 2.00V 2.10V 2.20V 2.32V 2.44V 2.59V 2.75V 2.93V 3.14V 3.38V 3.67V 4.00V 4.40V M U X LVI C ircuit LVIF LVIEN LVIREF 4 LVILS[3:0 ] Figure 13.12 LVI Diagram PS029902-0212 PRELIMINARY 283 Z51F3220 Product Specification 13.8.1 Register Map Table 13-3 Reset Operation Register Map Name Address Dir RSTFR E8H LVRCR D LVICR Default R/W Description 80H Reset Flag Register 8H R/W 00H Low Voltage Reset Control Register 86H R/W 00H Low Voltage Indicator Control Register 13.8.2 Reset Operation Register Description The reset control register consists of the reset flag register (RSTFR), low voltage reset control register (LVRCR), and low voltage indicator control register (LVICR). 13.8.3 Register Description for Reset Operation RSTFR (Reset Flag Register) : E8H 7 6 5 4 3 2 1 0 PORF EXTRF WDTRF OCDRF LVRF – – – R/W R/W R/W R/W R/W – – PORF EXTRF WDTRF OCDRF LVRF – Initial value : 80H Power-On Reset flag bit. The bit is reset by writing ‘0’ to this bit. 0 No detection 1 Det ection External Reset (RESETB ) flag bit. The bit is reset by writing ‘0’ to this bit or by Power-On Reset. 0 No detection 1 De tection Watch Dog Reset f lag bit. The bit i s re set by writing ‘0’ t o t his bit or by Power-On Reset. 0 No detection 1 De tection On-Chip Debug Reset flag bit. The bit is reset by writing ‘0’ to this bit or by Power-On Reset. 0 No detection 1 De tection Low Voltage Reset flag bit. The bit is reset by writing ‘0’ to this bit or by Power-On Reset. 0 No detection 1 De tection NOTES) 1. When the Power-On Reset occurs, the PORF bit is only set to “1”, the other flag (WDTRF and OCDRF) bits are all cleared to “0”. 2. When the Power-On Reset occurs, the EXTRF bit is unknown, At that time, the EXTRF bit can be set to “1” when External Reset (RESETB) occurs. 3. When the Power-On Reset occurs, the LVRF bit is unknown, At that time, the LVRF bit can be set to “1” when LVR Reset occurs. 4. When a reset except the POR occurs, the corresponding flag bit is only set to “1”, the other flag bits are kept in the previous values. PS029902-0212 PRELIMINARY 284 Z51F3220 Product Specification LVRCR (Low Voltage Reset Control Register) : D8H 7 6 5 4 3 2 1 0 LVRST – – LVRVS3 LVRVS2 LVRVS1 LVRVS0 LVREN R/W – – R/W R/W R/W R/W LVRST R/W Initial value : 00H LVR Enable when Stop Release 0 Not effect at stop release 1 LVR enable at stop release NOTES) When this bit i s ‘ 1’, t he LVR EN bit is cleared to ‘0’ b y s top mode to release. (LVR enable) When t his bit is ‘0’, the L VREN bit i s not ef fect by s top mode to release. LVRVS[3:0] LVREN LVR Voltage Select LVRVS3 LVRVS2 LV RVS1 LVRVS0 Description 0 0 00 1 .60V 0 0 01 2 .00V 0 0 10 2 .10V 0 0 11 2 .20V 0 1 00 2 .32V 0 1 01 2 .44V 0 1 10 2 .59V 0 1 11 2 .75V 1 0 00 2 .93V 1 0 01 3 .14V 1 0 10 3 .38V 1 0 11 3 .67V 1 1 00 4 .00V 1 1 01 4 .40V 1 1 10 Not available 1 1 11 Not available LVR Operation 0 LVR Enable 1 LVR Disable NOTES) 1. The LVRVS[3:0] bits are cleared by a power-on reset but are retained by other reset signals. 2. The LVRVS[3:0] bits should be set to ‘0000b’ while LVREN bit is “1”. PS029902-0212 PRELIMINARY 285 Z51F3220 Product Specification LVICR (Low Voltage Indicator Control Register) : 86H 7 6 5 4 3 2 1 0 – – LVIF LVIEN LVILS3 LVILS2 LVILS1 LVILS0 – – R/W R/W R/W R/W R/W LVIF LVIEN LVILS[3:0] Low Voltage Indicator Flag Bit 0 No detection 1 De tection LVI Enable/Disable 0 Di sable 1 En able LVI Level Select LVILS3 LV ILS2 LVILS1 0 0 00 2 .00V 0 0 01 2 .10V 0 0 10 2 .20V 0 0 11 2 .32V 0 1 00 2 .44V 0 1 01 2 .59V 0 1 10 2 .75V 0 1 11 2 .93V 1 0 00 3 .14V 1 0 01 3 .38V 1 0 10 3 .67V 1 0 11 4 .00V 1 1 00 4 .40V Other Values PS029902-0212 R/W Initial value : 00H PRELIMINARY LVILS0 Description Not available 286 Z51F3220 Product Specification 14. On-chip Debug System 14.1 Overview 14.1.1 Description On-chip debug system (OCD) of Z51F3220 can be used for programming the non-volatile memories and onchip debugging. Detail descriptions for programming via the OCD interface can be found in the following chapter. Figure 14.1 shows a block diagram of the OCD interface and the On-chip Debug system. 14.1.2 Feature • Two-wire external interface: 1-wire serial clock input, 1-wire bi-directional serial data bus • Debugger Access to: − All Internal Peripheral Units − Internal data RAM − Program Counter − Flash and Data EEPROM Memories • Extensive On-chip Debug Support for Break Conditions, Including − Break Instruction − Single Step Break − Program Memory Break Points on Single Address − Programming of Flash, EEPROM, Fuses, and Lock Bits through the two-wire Interface ® − On-chip Debugging Supported by Dr.Choice • Operating frequency Supports the maximum frequency of the target MCU Target MCU internal circuit Format converter DSCL USB DSDA BDC CPU DBG Control DBG Register Address bus Internal data bus User I/O Code memory - SRAM - Flash - EEPROM PS029902-0212 PRELIMINARY Data memory Peripheral 287 Z51F3220 Product Specification Figure 14.1 Block Diagram of On-Chip Debug System 14.2 Two-Pin External Interface 14.2.1 Basic Transmission Packet • 10-bit packet transmission using two-pin interface. • 1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge. • Parity is even of ‘1’ for 8-bit data in transmitter. • Receiver generates acknowledge bit as ‘0’ when transmission for 8-bit data and its parity has no error. • When transmitter has no acknowledge (Acknowledge bit is ‘1’ at tenth clock), error process is executed in transmitter. • When acknowledge error is generated, host PC makes stop condition and transmits command which has error again. • Background debugger command is composed of a bundle of packet. • Start condition and stop condition notify the start and the stop of background debugger command respectively. Figure 14.2 10-bit Transmission Packet PS029902-0212 PRELIMINARY 288 Z51F3220 Product Specification 14.2.2 Packet Transmission Timing 14.2.2.1 Data Transfer DSDA LSB acknowledgement signal from receiver LSB acknowledgement signal from receiver DSCL St 1 1 10 ACK 10 Sp ACK STOP START Figure 14.3 Data Transfer on the Twin Bus 14.2.2.2 Bit Transfer DSDA DSCL data line stable: data valid except Start and Stop change of data allowed Figure 14.4 Bit Transfer on the Serial Bus PS029902-0212 PRELIMINARY 289 Z51F3220 Product Specification 14.2.2.3 Start and Stop Condition DSDA DSDA DSCL DSCL St Sp STOP condition START condition Figure 14.5 Start and Stop Condition 14.2.2.4 Acknowledge Bit Data output by transmitter no acknowledge Data output By receiver acknowledge DSCL from master 1 2 9 10 clock pulse for acknowledgement Figure 14.6 Acknowledge on the Serial Bus PS029902-0212 PRELIMINARY 290 Z51F3220 Product Specification Acknowledge bit transmission Acknowledge bit transmission Minimum 500ns wait HIGH start HIGH Host PC DSCL OUT Target Device DSCL OUT Start wait Maximum 5 TSCLK minimum 1 TSCLK for next byte transmission DSCL Internal Operation Figure 14.7 Clock Synchronization during Wait Procedure PS029902-0212 PRELIMINARY 291 Z51F3220 Product Specification 14.2.3 Connection of Transmission Two-pin interface connection uses open-drain (wire-AND bidirectional I/O). VDD pull -up resistors Rp Rp DSDA(Debugger Serial Data Line) DSCL(Debugger Serial Clock Line) VDD DSCL OUT DSCL IN DSDA OUT DSDA IN VDD DSCL OUT DSDA OUT DSDA IN DSCL IN Target Device(Slave) Host Machine(Master) Current source for DSCL to fast 0 to 1 transition in high speed mode Figure 14.8 Connection of Transmission PS029902-0212 PRELIMINARY 292 Z51F3220 Product Specification 15. Flash Memory 15.1 Overview 15.1.1 Description Z51F3220 incorporates flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory can be read by ‘MOVC’ instruction and it can be programmed in OCD, serial ISP mode or user program mode. • Flash Size : 32kbytes • Single power supply program and erase • Command interface for fast program and erase operation • Up to 100,000 program/erase cycles at typical voltage and temperature for flash memory PS029902-0212 PRELIMINARY 293 Z51F3220 Product Specification 15.1.2 Flash Program ROM Structure 07FFFH Sector 511 07FC0H 07FBFH 07FC0H Sector 510 07F80H 07F7FH 07F80H Sector 509 07F40H 07F3FH 07F40H Sector 508 Flash Sector Address ROM Address Sector 2 00080H 00080H 0007FH Sector 1 00040H 00040H 0003FH Sector 0 00000H 00000H 64bytes Accessed by MOVX instruction only Flash Page Buffer (External Data Memory, 64bytes) Flash Controller 803FH 8000H Page(Sector) Buffer Address FSADRH/M/L FIDR FMCR Figure 15.1 Flash Program ROM Structure PS029902-0212 PRELIMINARY 294 Z51F3220 Product Specification 15.1.3 Register Map Table 15-1Flash Memory Register Map Name Address Dir Default Description FSADRH FAH R/W 00H Flash Sector Address High Register FSADRM FBH R/W 00H Flash Sector Address Middle Register FSADRL FCH R/W 00H Flash Sector Address Low Register FIDR FDH R/W 00H Flash Identification Register FMCR FEH R/W 00H Flash Mode Control Register 15.1.4 Register Description for Flash Memory Control and Status Flash control register consists of the flash sector address high register (FSADRH), flash sector address middle register (FSADRM), flash sector address low register (FSADRL), flash identification register (FIDR), and flash mode control register (FMCR). They are mapped to SFR area and can be accessed only in programming mode. PS029902-0212 PRELIMINARY 295 Z51F3220 Product Specification 15.1.5 Register Description for Flash FSADRH (Flash Sector Address High Register) : FAH 7 6 5 4 3 2 1 0 – – – – FSADRH3 FSADRH 2 FSADRH1 FSADRH0 – – – – R/W R/W R/W FSADRH[3:0] R/W Initial value : 00H Flash Sector Address High FSADRM (Flash Sector Address Middle Register) : FBH 7 6 5 4 3 2 1 0 FSADRM7 FSADRM6 FSADRM5 FSADRM4 FSADRM3 FSADRM2 FSADRM1 FSADRM0 R/W R/W R/W R/W R/W R/W R/W FSADRM[7:0] R/W Initial value : 00H Flash Sector Address Middle FSADRL (Flash Sector Address Low Register) : FCH 7 6 5 4 3 2 1 0 FSADRL7 FSADRL6 FSADRL5 FSADRL4 FSADRL3 FSADRL2 FSADRL1 FSADRL0 R/W R/W R/W R/W R/W R/W R/W FSADRL[7:0] R/W Initial value : 00H Flash Sector Address Low FIDR (Flash Identification Register) : FDH 7 6 5 4 3 2 1 0 FIDR7 FIDR6 FIDR5 FIDR4 FIDR3 FIDR2 FIDR1 FIDR0 R/W R/W R/W R/W R/W R/W R/W FIDR[7:0] R/W Initial value : 00H Flash Identification Others No 10100101 identification value Identification value for a flash mode (These bits are automatically cleared to logic ‘00H’ immediately after one time operation) PS029902-0212 PRELIMINARY 296 Z51F3220 Product Specification FMCR (Flash Mode Control Register) : FEH 7 6 5 4 3 2 1 0 FMBUSY – – – – FMCR2 FMCR1 FMCR0 R – – – – R/W R/W R/W Initial value : 00H FMBUSY Flash Mode Busy Bit. This bit will be used for only debugger. 0 No effect when “1” is written 1 Bus FMCR[2:0] y Flash Mode Control Bits. During a flash mode operation, the CPU is hold and the global interrupt is on disable state regardless of the IE.7 (EA) bit. FMCR2 FM CR1 FMCR0 Description 0 0 1 Select flash page buffer reset mode and start regardless of the FIDR value (Clear all 64bytes to ‘0’) 0 1 0 Select flash sector erase mode and start operation when the FIDR=”10100101b’ 0 1 1 Select flash sector write mode and start operation when the FIDR=”10100101b’ 1 0 0 Select flash sector hard lock and start operation when the FIDR=”10100101b’ Others Values: No operation (These bits are automatically cleared to logic ‘00H’ immediately after one time operation) PS029902-0212 PRELIMINARY 297 Z51F3220 Product Specification 15.1.6 Serial In-System Program (ISP) Mode Serial in-system program uses the interface of debugger which uses two wires. Refer to chapter 14 in details about debugger 15.1.7 Protection Area (User program mode) Z51F3220 can program its own flash memory (protection area). The protection area can not be erased or programmed. The protection areas are available only when the PAEN bit is cleared to ‘0’, that is, enable protection area at the configure option 2 if it is needed. If the protection area isn’t enabled (PAEN =’1’), this area can be used as a normal program memory. The size of protection area can be varied by setting of configure option 2. Table 15-2 Protection Area size Protection Area Size Select PASS1 Size of Protection Area Address of Protection Area PASS0 0 0 3. 8k Bytes 0100H – 0FFFH 0 1 1. 7k Bytes 0100H – 07FFH 10 7 68 Bytes 0100H – 03FFH 11 2 56 Bytes 0100H – 01FFH NOTE) Refer to chapter 16 in configure option control. PS029902-0212 PRELIMINARY 298 Z51F3220 Product Specification 15.1.8 Erase Mode The sector erase program procedure in user program mode 1. Page buffer clear (FMCR=0x01) 2. Write ‘0’ to page buffer 3. Set flash sector address register (FSADRH/FSADRM/FSADRL). 4. Set flash identification register (FIDR). 5. Set flash mode control register (FMCR). 6. E rase verify Program Tip – sector erase MOV NOP NOP NOP M FMCR,#0x01 MOV A, #0 OV R0,#64 MOV DPH,#0x80 MOV DPL,#0 Pgbuf_clr: M OVX INC DJNZ @DPTR,A DPTR R0, Pgbuf_clr ;page buffer clear ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ; Sector size is 64bytes ; Write ‘0’ to all page buffer MOV FSADRH,#0x00 MOV FSADRM,#0x7F MOV FSADRL ,#0x40 MOV FI DR,#0xA5 MOV FMCR,#0x02 NOP NOP NOP M M OV OV MOV MOV MOV Erase_verify: MOVC SUBB JNZ INC DJNZ A,#0 R0,#64 R1,#0 DPH,#0x7F DPL,#0x40 ;Select sector 509 ;Identification value ;Start flash erase mode ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ; ; erase verify Sector size is 64bytes A,@A+DPTR A,R1 Verify_error DPTR R0, Erase_verify Verify_error: PS029902-0212 PRELIMINARY 299 Z51F3220 Product Specification The Byte erase program procedure in user program mode 1. Page buffer clear (FMCR=0x01) 2. Write ‘0’ to page buffer 3. Set flash sector address register (FSADRH/FSADRM/FSADRL). 4. Set flash identification register (FIDR). 5. Set flash mode control register (FMCR). 6. E rase verify Program Tip – byte erase MOV NOP NOP NOP FMCR,#0x01 ;page buffer clear ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. MOV A, #0 MOV DPH,#0x80 MOV DPL,#0 MOVX @ DPTR,A M SU SU MOV DPH,#0x80 MOV DPL,#0x05 MOVX @ DPTR,A ;Write ‘0’ to page buffer MOV FSADRH,#0x00 MOV FSADRM,#0x7F MOV FSADRL ,#0x40 MOV FI DR,#0xA5 MOV FMCR,#0x02 NOP NOP NOP ;Select sector 509 ;Identification value ;Start flash erase mode ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. OV MOV MOV MOV MOVC BB JNZ A,#0 R1,#0 DPH,#0x7F DPL,#0x40 A,@A+DPTR A,R1 Verify_error MOV A, MOV MOV MOV MOVC BB JNZ #0 R1,#0 DPH,#0x7F DPL,#0x45 A,@A+DPTR A,R1 Verify_error ; erase verify ; 0x7F40 = 0? ; 0x7F45 = 0? Verify_error: PS029902-0212 PRELIMINARY 300 Z51F3220 Product Specification 15.1.9 Write Mode The sector Write program procedure in user program mode 1. Page buffer clear (FMCR=0x01) 2. Write data to page buffer 3. Set flash sector address register (FSADRH/FSADRM/FSADRL). 4. Set flash identification register (FIDR). 5. Set flash mode control register (FMCR). 6. E rase verify Program Tip – sector write MOV NOP NOP NOP M FMCR,#0x01 MOV A, #0 OV R0,#64 MOV DPH,#0x80 MOV DPL,#0 Pgbuf_WR: M OVX INC INC DJNZ ;page buffer clear ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ; @DPTR,A A DPTR R0, Pgbuf_WR ;Write data to all page buffer MOV FSADRH,#0x00 MOV FSADRM,#0x7F MOV FSADRL ,#0x40 MOV FI DR,#0xA5 MOV FMCR,#0x03 NOP NOP NOP M M Write_verify: OV OV MOV MOV MOV A,#0 R0,#64 R1,#0 DPH,#0x7F DPL,#0x40 MOVC SUBB JNZ INC INC DJNZ A,@A+DPTR A,R1 Verify_error R1 DPTR R0, Write_verify Sector size is 64bytes ;Select sector 509 ;Identification value ;Start flash write mode ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;w ; rite verify Sector size is 64bytes Verify_error: PS029902-0212 PRELIMINARY 301 Z51F3220 Product Specification The Byte Write program procedure in user program mode 1. Page buffer clear (FMCR=0x01) 2. Write data to page buffer 3. Set flash sector address register (FSADRH/FSADRM/FSADRL). 4. Set flash identification register (FIDR). 5. Set flash mode control register (FMCR). 6. E rase verify Program Tip – byte write MOV NOP NOP NOP M SU SU FMCR,#0x01 ;page buffer clear ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. MOV A, #5 MOV DPH,#0x80 MOV DPL,#0 MOVX @DPTR,A ;Write data to page buffer MOV A, #6 MOV DPH,#0x80 MOV DPL,#0x05 MOVX @DPTR,A ;Write data to page buffer MOV FSADRH,#0x00 MOV FSADRM,#0x7F MOV FSADRL ,#0x40 MOV FI DR,#0xA5 MOV FMCR,#0x03 NOP NOP NOP ;Select sector 509 ;Identification value ;Start flash write mode ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. OV MOV MOV MOV MOVC BB JNZ A,#0 R1,#5 DPH,#0x7F DPL,#0x40 A,@A+DPTR A,R1 Verify_error MOV A, MOV MOV MOV MOVC BB JNZ #0 R1,#6 DPH,#0x7F DPL,#0x45 A,@A+DPTR A,R1 Verify_error ;w rite verify ; 0x7F40 = 5? ; 0x7F45 = 6? Verify_error: PS029902-0212 PRELIMINARY 302 Z51F3220 Product Specification 15.1.10 Read Mode The Reading program procedure in user program mode 1. Load receive data from flash memory on MOVC instruction by indirectly addressing mode. Program Tip – reading M MOV MOV OV A,#0 DPH,#0x7F DPL,#0x40 ; MOVC A,@A+DPTR flash memory address ;read data from flash memory 15.1.11 Hard Lock Mode The Reading program procedure in user program mode 1. Set flash identification register (FIDR). 2. Set flash mode control register (FMCR). Program Tip – reading MOV FI DR,#0xA5 MOV FMCR,#0x04 NOP NOP NOP PS029902-0212 ;Identification value ;Start flash hard lock mode ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. ;Dummy instruction, This instruction must be needed. PRELIMINARY 303 Z51F3220 Product Specification 16. Configure Option 16.1 Configure Option Control The data for configure option should be written in the configure option area (003EH – 003FH) by programmer (Writer tools). CONFIGURE OPTION 1 : ROM Address 003FH 7 6 5 4 3 2 1 R_P HL – – – – – 0 RSTS Initial value : 00H Read Protection R_P 0 Disa ble “Read protection” 1 Enab le “Read protection” Hard-Lock HL 0 Disa ble “Hard-lock” 1 Enab le “Hard-lock” RESETB Select RSTS 0 P55 port 1 RESETB port with a pull-up resistor CONFIGURE OPTION 2: ROM Address 003EH 7 6 5 4 3 2 1 0 – – – – – PAEN PASS1 PASS0 Initial value : 00H PAEN PASS [1:0] Protection Area Enable/Disable 0 Disable Protection (Erasable by instruction) 1 Enable Protection (Not erasable by instruction) Protection Area Size Select PASS1 PASS PS029902-0212 0 Description 0 0 3.8k Bytes (Address 0100H – 0FFFH) 0 1 1.7k Bytes (Address 0100H – 07FFH) 1 0 768 Bytes (Address 0100H – 03FFH) 1 1 256 Bytes (Address 0100H – 01FFH) PRELIMINARY 304 Z51F3220 Product Specification 17. APPENDIX A. Instruction Table Instructions are either 1, 2 or 3 bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles. Mnemonic ADD A,Rn ADD A,dir ADD A,@Ri ADD A,#data ADDC A,Rn ADDC A,dir ADDC A,@Ri ADDC A,#data SUBB A,Rn SUBB A,dir SUBB A,@Ri SUBB A,#data INC A INC Rn INC dir INC @Ri DEC A DEC Rn DEC dir DEC @Ri INC DPTR MUL AB DIV AB DA A Mnemonic ANL A,Rn ANL A,dir ANL A,@Ri ANL A,#data ANL dir,A ANL dir,#data ORL A,Rn ORL A,dir ORL A,@Ri ORL A,#data ORL dir,A ORL dir,#data XRL A,Rn XRL A,dir XRL A, @Ri PS029902-0212 ARITHMETIC Description Add register to A Add direct byte to A Add indirect memory to A Add immediate to A Add register to A with carry Add direct byte to A with carry Add indirect memory to A with carry Add immediate to A with carry Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect memory from A with borrow Subtract immediate from A with borrow Increment A Increment register Increment direct byte Increment indirect memory Decrement A Decrement register Decrement direct byte Decrement indirect memory Increment data pointer Multiply A by B Divide A by B Decimal Adjust A LOGICAL Description AND register to A AND direct byte to A AND indirect memory to A AND immediate to A AND A to direct byte AND immediate to direct byte OR register to A OR direct byte to A OR indirect memory to A OR immediate to A OR A to direct byte OR immediate to direct byte Exclusive-OR register to A Exclusive-OR direct byte to A Exclusive-OR indirect memory to A PRELIMINARY Bytes 11 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 Cycles Hex code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 28-2F 25 26-27 24 38-3F 35 36-37 34 98-9F 95 96-97 94 04 08-0F 05 06-07 14 18-1F 15 16-17 A3 A4 84 D4 Bytes 11 2 1 2 2 3 1 2 1 2 2 3 1 2 1 Cycles Hex code 1 1 1 1 2 1 1 1 1 1 2 1 1 1 58-5F 55 56-57 54 52 53 48-4F 45 46-47 44 42 43 68-6F 65 66-67 305 Z51F3220 Product Specification XRL A,#data XRL dir,A XRL dir,#data CLR A CPL A SWAP A RL A RLC A RR A RRC A Mnemonic MOV A,Rn MOV A,dir MOV A,@Ri MOV A,#data MOV Rn,A MOV Rn,dir MOV Rn,#data MOV dir,A MOV dir,Rn MOV dir,dir MOV dir,@Ri MOV dir,#data MOV @Ri,A MOV @Ri,dir MOV @Ri,#data MOV DPTR,#data MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri MOVX A,@DPTR MOVX @Ri,A MOVX @DPTR,A PUSH dir POP dir XCH A,Rn XCH A,dir XCH A,@Ri XCHD A,@Ri Mnemonic CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit PS029902-0212 Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR immediate to direct byte Clear A Complement A Swap Nibbles of A Rotate A left Rotate A left through carry Rotate A right Rotate A right through carry DATA TRANSFER Description Move register to A Move direct byte to A Move indirect memory to A Move immediate to A Move A to register Move direct byte to register Move immediate to register Move A to direct byte Move register to direct byte Move direct byte to direct byte Move indirect memory to direct byte Move immediate to direct byte Move A to indirect memory Move direct byte to indirect memory Move immediate to indirect memory Move immediate to data pointer Move code byte relative DPTR to A Move code byte relative PC to A Move external data(A8) to A Move external data(A16) to A Move A to external data(A8) Move A to external data(A16) Push direct byte onto stack Pop direct byte from stack Exchange A and register Exchange A and direct byte Exchange A and indirect memory Exchange A and indirect memory nibble BOOLEAN Description Clear carry Clear direct bit Set carry Set direct bit Complement carry Complement direct bit AND direct bit to carry AND direct bit inverse to carry PRELIMINARY 2 2 3 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 64 62 63 E4 F4 C4 23 33 03 13 Bytes 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 Cycles 1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 Hex code E8-EF E5 E6-E7 74 F8-FF A8-AF 78-7F F5 88-8F 85 86-87 75 F6-F7 A6-A7 76-77 90 93 83 E2-E3 E0 F2-F3 F0 C0 D0 C8-CF C5 C6-C7 D6-D7 Bytes 11 2 1 2 1 2 2 2 Cycles Hex code 1 1 1 1 1 2 2 C3 C2 D3 D2 B3 B2 82 B0 306 Z51F3220 Product Specification ORL C,bit ORL C,/bit MOV C,bit MOV bit,C OR direct bit to carry OR direct bit inverse to carry Move direct bit to carry Move carry to direct bit BRANCHING Description Mnemonic ACALL addr 11 LCALL addr 16 RET Return RETI Return AJMP addr 11 LJMP addr 16 SJMP rel JC rel JNC rel JB bit,rel JNB bit,rel JBC bit,rel JMP @A+DPTR JZ rel JNZ rel CJNE A,dir,rel CJNE A,#d,rel CJNE Rn,#d,rel CJNE @Ri,#d,rel DJNZ Rn,rel DJNZ dir,rel Absolute jump to subroutine Long jump to subroutine from subroutine from interrupt Absolute jump unconditional Long jump unconditional Short jump (relative address) Jump on carry = 1 Jump on carry = 0 Jump on direct bit = 1 Jump on direct bit = 0 Jump on direct bit = 1 and clear Jump indirect relative DPTR Jump on accumulator = 0 Jump on accumulator ≠ 0 Compare A,direct jne relative Compare A,immediate jne relative Compare register, immediate jne relative Compare indirect, immediate jne relative Decrement register, jnz relative Decrement direct byte, jnz relative MISCELLANEOUS Description Mnemonic NOP No Mnemonic MOVC @(DPTR++),A TRAP So operation 2 2 2 2 2 2 1 2 72 A0 A2 92 Bytes 22 3 1 1 2 3 2 2 2 3 3 3 1 2 2 3 3 3 3 3 3 Cycles Hex code 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 11→F1 12 22 32 01→E1 02 80 40 50 20 30 10 73 60 70 B5 B4 B8-BF B6-B7 D8-DF D5 Bytes 11 Cycles Hex code ADDITIONAL INSTRUCTIONS (selected through EO[7:4]) Description Bytes M8051W/M8051EW-specific instruction supporting 12 software download into program memory 11 ftware break command 00 Cycles Hex code A5 A5 In the above table, an entry such as E8-EF indicates a continuous block of hex opcodes used for 8 different registers, the register numbers of which are defined by the lowest three bits of the corresponding code. Noncontinuous blocks of codes, shown as 11→F1 (for example), are used for absolute jumps and calls, with the top 3 bits of the code being used to store the top three bits of the destination address. The CJNE instructions use the abbreviation #d for immediate data; other instructions use #data. PS029902-0212 PRELIMINARY 307 Z51F3220 Product Specification B. Instructions on how to use the input port.  Error occur status Using compare jump instructions with input port, it could cause error due to the timing conflict inside the MCU. Compare jump Instructions which cause potential error used with input port condition:   JB bit, rel ; jump on direct bit=1 JNB bit, rel ; jump on direct bit=0 JBC bit, rel ; jump on direct bit=1 and clear CJNE A, dir, rel ; compare A, direct jne relative DJNZ dir, rel It is only related with Input port. Internal parameters, SFRs and output bit ports don’t cause any error by using compare jump instructions. If input signal is fixed, there is no error in using compare jump instructions.    ; decrement direct byte, jnz relative Error status example while(1){ zzz: if (P00==1){ P10=1; } else { P10=0; } P11^=1; } 080.0, xxx ; it possible to be error 088.0 SJMP xxx: yyy: 088.0 MOV C,088.1 CPL C MOV 088.1,C SJMP zzz MOV { JB return !P00; yyy CLR unsigned char ret_bit_err(void) }  JNB SETB R7, #000 080.0, xxx ; it possible to be error MOV R7, #001 xxx: RET Preventative measures (2 cases) Do not use input bit port for bit operation but for byte operation. Using byte operation instead of bit oper ation will not cause any error in using compare jump instructions for input port.  while(1){ zzz: MOV A, 080 ; read as byte if ((P0&0x01)==0x01){ P10=1; } JNB 0E0.0, xxx ; compare else { P10=0; } SETB SJMP yyy xxx: CLR 088.0 yyy: MOV C,088.1 P11^=1; } PS029902-0212 088.0 CPL C MOV 088.1,C SJMP zzz PRELIMINARY 308 Z51F3220 Product Specification If you use input bit port for compare jump instruction, you have to copy the input port as internal paramet er or carry bit and then use compare jump instruction.  bit tt; zzz: while(1){ MOV C,080.0 ; input port use internal parameter MOV 020.0, C ; move tt=P00; JB if (tt==0){ P10=1;} SETB 088.0 else {P10=0;} SJMP yyy P11^=1; } PS029902-0212 020.0, xxx xxx: CLR 088.0 yyy: MOV C,088.1 CPL C MOV 088.1,C SJMP zzz PRELIMINARY ; compare 309 Z51F3220 Product Specification 310 Customer Support To share comments, get your technical questions answered, or report issues you may be experiencing with our products, please visit Zilog’s Technical Support page at  http://support.zilog.com. To learn more about this product, find additional documentation, or to discover other facets about Zilog product offerings, please visit the Zilog Knowledge Base or consider participating in the Zilog Forum. This publication is subject to replacement by a later edition. To determine whether a later edition exists, please visit the Zilog website at http://www.zilog.com. PS029902-0212 PRELIMINARY Customer Support