CMOS Z8 16K/32K EPROM MCUs
Z86E61/Z86E63
Microcontrollers
Product Specification
PS014404-0212
Copyright ©2012 Zilog®, Inc. All rights reserved.
www.zilog.com
Z86E61/Z86E63 Microcontrollers
Product Specification
ii
Warning: DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
LIFE SUPPORT POLICY
ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
©2012 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. Zilog, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. Zilog ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
Z8 is a registered trademark of Zilog, Inc. All other product or service names are the property of their
respective owners.
PS014404-0212
Z86E61/Z86E63 Microcontrollers
Product Specification
iii
Revision History
Each instance in the following revision history table reflects a change to this document
from its previous version. For more details, refer to the corresponding pages or appropriate
links provided in the table.
Date
Revision
Level
Description
Page
Feb
2012
04
Globally updated for style and content.
All
Oct
2008
03
Updated pin descriptions.
11
May
2008
02
Added LQFP pin diagram (Standard and Programming modes); replaced
44-pin QFP with 44-pin LQFP for CR #10886.
7, 8
Nov
2001
01
Original issue.
All
PS014404-0212
Revision History
Z86E61/Z86E63 Microcontrollers
Product Specification
iv
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .viii
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Counter/Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Z86E61/Z86E63 User Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Z86E63 Signal Description for EPROM Program/Read . . . . . . . . . . . . . . . . . . . . . 30
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Standby Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Z8 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Part Number Suffix Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
PS014404-0212
Table of Contents
Z86E61/Z86E63 Microcontrollers
Product Specification
v
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
PS014404-0212
Table of Contents
Z86E61/Z86E63 Microcontrollers
Product Specification
vi
List of Figures
Figure 1. Z86E61/Z86E63 MCU Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Z86E61/Z86E63 PDIP Pin Diagram, Standard Mode . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Z86E61/Z86E63 PDIP Pin Diagram, EPROM Programming Mode . . . . . . . . . 6
Figure 4. Z86E61/Z86E63 LQFP Pin Diagram, Standard Mode . . . . . . . . . . . . . . . . . . . 7
Figure 5. Z86E61/Z86E63 LQFP Pin Diagram, EPROM Programming Mode . . . . . . . . 8
Figure 6. Z86E61/Z86E63 PLCC Pin Diagram, Standard Mode . . . . . . . . . . . . . . . . . . . 9
Figure 7. Z86E61/Z86E63 PLCC Pin Diagram, EPROM Programming Mode . . . . . . . 10
Figure 8. Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Port 1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Serial Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Program Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. Data Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16. Register Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 17. Counter/Timers Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 18. Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 19. Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. EPROM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 21. EPROM Program and Verify Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 22. Programming EPROM and RAM Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 23. Intelligent Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 24. Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 25. Typical ICC vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 26. Typical ICC1 vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 27. External I/O or Memory Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 28. Input Handshake Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
PS014404-0212
List of Figures
Z86E61/Z86E63 Microcontrollers
Product Specification
vii
Figure 29. Output Handshake Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 30. Additional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 31. Serial I/O Register (F0H: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 32. Timer Mode Register (F1H: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 33. Counter/Timer 1 Register (F2H: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 34. Prescaler 1 Register (F3H: Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 35. Counter/Timer 0 Register (F4H: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 36. Prescaler 0 Register (F5H: Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 37. Port 2 Mode Register (F6H: Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 38. Port 3 Mode Register (F7H: Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 39. Port 0 and 1 Mode Register (F8H: Write Only) . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 40. Interrupt Priority Register (F9H: Write Only) . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 41. Interrupt Request Register (FAH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 42. Interrupt Mask Register (FBH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 43. Flag Register (FCH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 44. Register Pointer Register (FDH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 45. Stack Pointer Register (FEH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 46. Stack Pointer Register (FFH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 47. Instruction Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 48. Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PS014404-0212
List of Figures
Z86E61/Z86E63 Microcontrollers
Product Specification
viii
List of Tables
Table 1. Power Connection Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. Z86E61/Z86E63 PDIP Pin Description, Standard Mode. . . . . . . . . . . . . . . . . . . 4
Table 3. Z86E61/Z86E63 PDIP Pin Description, EPROM Programming Mode . . . . . . . 6
Table 4. Z86E61/Z86E63 LQFP Pin Description, Standard Mode . . . . . . . . . . . . . . . . . . 7
Table 5. Z86E61/Z86E63 LQFP Pin Description, EPROM Programming Mode . . . . . . . 8
Table 6. Z86E61/Z86E63 PLCC Pin Description, Standard Mode . . . . . . . . . . . . . . . . . . 9
Table 7. Z86E61/Z86E63 PLCC Pin Description, EPROM Programming Mode . . . . . . 10
Table 8. Port 3 Pin Assignments* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. OTP Programming1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 10. Timing of Programming Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 11. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 12. Direct Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 13. External I/O or Memory Read and Write Timing . . . . . . . . . . . . . . . . . . . . . . 38
Table 14. Clock-Dependent Formulas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. Handshake Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. Additional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 17. Instruction Set Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 18. Instruction Set Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 19. R252 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 20. R252 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 21. Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 22. Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 23. Z86E61/Z86E63 MCU Ordering Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
PS014404-0212
List of Tables
Z86E61/Z86E63 Microcontrollers
Product Specification
1
Overview
The Z86E61/Z86E63 microcontrollers are members of the Z8® single-chip microcontroller family with 16K/32 KB of EPROM and 236 bytes of general-purpose RAM.
Offered in 40-pin DIP, 44-pin PLCC or 44-pin LQFP package styles, these devices are
pin-compatible EPROM versions of the Z86C61/ 63. The ROMless pin option is available
on the 44-pin versions only.
With 16 KB/32 KB of ROM and 236 bytes of general-purpose RAM, the Z86E61/Z86E63
MCU offers fast execution, efficient use of memory, sophisticated interrupts, input/output
bit manipulation capabilities, and easy hardware/software system expansion.
For applications demanding powerful I/O capabilities, the Z86E61/Z86E63 MCU offers
32 pins dedicated to input and output. These lines are grouped into four ports. Each port
consists of eight lines, and is configurable under software control to provide timing, status
signals, serial or parallel I/O with or without handshake, and an address/data bus for interfacing external memory.
The Z86E61/Z86E63 MCU can address both external memory and preprogrammed ROM,
making it well suited for high-volume applications or where code flexibility is required.
There are three basic address spaces available to support this configuration:
•
•
•
Program memory
Data memory
236 General-purpose registers
Features
The Z86E61 and Z86E63 MCUs offer the following features:
•
•
•
•
•
•
•
•
•
PS014404-0212
8-Bit CMOS microcontroller
40-pin DIP, 44-pin PLCC and 44-pin LQFP packages
4.5 V to 5.5 V operating range
Clock speeds: 16 MHz and 20 MHz
Low power consumption: 275 mW (max)
Two Standby modes: STOP and HALT
32 Input/Output lines
Full-duplex UART
All digital inputs are TTL levels
Overview
Z86E61/Z86E63 Microcontrollers
Product Specification
2
•
•
•
•
Auto Latches
•
256-byte Register File:
– 236 bytes of General-Purpose RAM
– 16 bytes of Control and Status registers
– 4 bytes for ports
•
•
•
Two programmable 8-bit Counter/Timers, each with 6-bit programmable prescaler
High-voltage protection on high-voltage inputs
RAM and EPROM Protect
EPROM:
– 16 KB Z86E61
– 32 KB Z86E63
Six vectored priority interrupts from eight different sources
On-chip oscillator that accepts a crystal ceramic resonator, LC or external clock drive
To unburden the system from coping with real-time tasks such as counting/timing and
serial data communication, the Z86E61/Z86E63 MCU offers two on-chip counter/timers
with a large number of user selectable modes. See the block diagram in Figure 1.
PS014404-0212
Overview
Z86E61/Z86E63 Microcontrollers
Product Specification
3
Output Input
VCC
GND
DS
XTAL AS
R/W RESET
Machine Timing and
Instruction Control
Port 3
UART
ALU
Counter/
Timers
(2)
FLAGS
Prg. Memory
16K/32K
Register
Pointer
Interrupt
Control
Program
Counter
Register File
256 x 8-Bit
Port 0
Port 2
4
I/O
(Bit Programmable)
Port 1
4
8
Address or I/O
(Nibble Programmable)
Address/Data or I/O
(Byte Programmable)
Figure 1. Z86E61/Z86E63 MCU Functional Block Diagram
Power connections follow the conventional descriptions listed in Table 24.
Table 24. Power Connection Conventions
Connection
PS014404-0212
Circuit
Device
Power
VCC
VDD
Ground
GND
VSS
Overview
Z86E61/Z86E63 Microcontrollers
Product Specification
4
Pin Functions
The Z86E61/Z86E63 MCU is available in variety of package styles, programming modes
and pin configurations. This section describes the pin signals and configurations for each
of the 40-pin PDIP, 44-pin PLCC and 44-pin LQFP packages in both Standard and
EPROM Programming modes.
Pin Signals
Figure 2 shows the pin-outs for the 40-pin PDIP Standard Mode package; Table 25
describes each pin.
VCC
40
1
P36
XTAL2
P31
XTAL1
P27
P37
P26
P30
P25
RESET
R/W
DS
P24
P23
P22
Z86E61/E63
P21
AS
P35
PDIP
P20
GND
Standard
P33
P32
P34
Mode
P00
P17
P01
P16
P02
P03
P15
P14
P04
P13
P05
P12
P11
P06
P07
20
21
P10
Figure 2. Z86E61/Z86E63 PDIP Pin Diagram, Standard Mode
Table 25. Z86E61/Z86E63 PDIP Pin Description, Standard Mode
PS014404-0212
Pin Signal
Description
I/O
XTAL2
Crystal Oscillator Clock
Output
XTAL1
Crystal Oscillator Clock
Input
RESET
Reset
Input
R/W
Read/Write
Output
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
5
Table 25. Z86E61/Z86E63 PDIP Pin Description, Standard Mode (Continued)
PS014404-0212
Pin Signal
Description
I/O
DS
Data Strobe
Output
AS
Address Strobe
Output
P00–P07 Port 0
8-bit General I/O
Input/Output
P10–P17 Port 1
8-bit General I/O
Input/Output
P20–P27 Port 2
8-bit General I/O
Input/Output
P30–P33 Port 3
4-bit Input
Input
P34–P37 Port 3
4-bit Output
Output
R/RL
ROM/ROMless Control
Input
GND
Ground
Input
VCC
Power Supply
Input
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
6
Figure 3 shows the pin-outs for the 40-pin PDIP EPROM Programming Mode package;
Table 26 describes each pin.
VCC
40
1
NC
X TA L2
OE
X TA L1
NC
PGM
A14
CE
A13
RESET
NC
A12
A11
NC
Z86E61/E63
A10
NC
PDIP
A9
NC
A8
EPROM
GND
EPM
VPP
Programming
NC
Mode
D7
A0
A1
D6
A2
A3
D5
D4
A4
D3
A5
D2
D1
A6
A7
20
21
D0
Figure 3. Z86E61/Z86E63 PDIP Pin Diagram, EPROM Programming Mode
Table 26. Z86E61/Z86E63 PDIP Pin Description, EPROM Programming Mode
PS014404-0212
Pin Signal
Description
I/O
XTAL2
Crystal Oscillator Clock
Output
XTAL1
Crystal Oscillator Clock
Input
CE
Chip Enable
Input
RESET
Reset
Input
EPM
EPROM Programming Mode
Input
A0–A14
15-bit Address Bus
Input
D7–D0
8-bit Data Bus
Input/Output
VPP
Programming Voltage
Input
PGM
Programming Mode
Input
OE
Output Enable
Input
NC
Not Connected
Input
GND
Ground
Input
VCC
Power Supply
Input
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
7
RESET
P27
P26
P25
NC
P36
P31
XTAL1
XTAL2
VCC
P30
33
P37
Figure 4 shows the pin-outs for the 44-pin LQFP Standard Mode package; Table 27
describes each pin.
23
22
34
R/W
NC
P24
DS
P23
AS
P35
GND
Z86E61/E63
P22
LQFP
P21
Standard
P33
Mode
P34
P32
P00
P01
P20
P17
P02
P16
R/RL
P15
12
44
11
P14
P12
P13
P10
P11
P07
NC
P05
P06
P03
P04
1
Figure 4. Z86E61/Z86E63 LQFP Pin Diagram, Standard Mode
Table 27. Z86E61/Z86E63 LQFP Pin Description, Standard Mode
PS014404-0212
Pin Signal
Description
I/O
XTAL2
Crystal Oscillator Clock
Output
XTAL1
Crystal Oscillator Clock
Input
RESET
Reset
Input
R/W
Read/Write
Output
DS
Data Strobe
Output
AS
Address Strobe
Output
P00–P07 Port 0
8-bit General I/O
Input/Output
P10–P17 Port 1
8-bit General I/O
Input/Output
P20–P27 Port 2
8-bit General I/O
Input/Output
P30–P33 Port 3
4-bit Input
Input
P34–P37 Port 3
4-bit Output
Output
R/RL
ROM/ROMless Control
Input
GND
Ground
Input
VCC
Power Supply
Input
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
8
RESET
A13
PGM
A14
NC
OE
XTAL1
XTAL2
VCC
NC
CE
33
NC
Figure 5 shows the pin-outs for the 44-pin LQFP EPROM Programming Mode package;
Table 28 describes each pin.
23
22
34
NC
NC
A12
NC
A11
NC
Z86E61/E63
A10
GND
LQFP
A9
EPM
EPROM Programming
VPP
Mode
NC
NC
A0
A1
A8
D7
A2
D6
NC
D5
12
44
11
D3
D4
D1
D2
D0
A6
A7
NC
A5
A4
A3
1
Figure 5. Z86E61/Z86E63 LQFP Pin Diagram, EPROM Programming Mode
Table 28. Z86E61/Z86E63 LQFP Pin Description, EPROM Programming Mode
PS014404-0212
Pin Signal
Description
I/O
XTAL2
Crystal Oscillator Clock
Output
XTAL1
Crystal Oscillator Clock
Input
CE
Chip Enable
Input
RESET
Reset
Input
EPM
EPROM Programming Mode
Input
A0–A14
15-bit Address Bus
Input
D7–D0
8-bit Data Bus
Input/Output
VPP
Programming Voltage
Input
PGM
Programming Mode
Input
OE
Output Enable
Input
NC
Not Connected
Input
GND
Ground
Input
VCC
Power Supply
Input
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
9
P27
P26
P25
VCC
1
6
RESET
P36
P31
P37
XTAL1
XTAL2
NC
P30
Figure 6 shows the pin-outs for the 44-pin PLCC Standard Mode package; Table 29
describes each pin.
40
39
7
NC
P24
R/W
P23
DS
AS
Z86E61/E63
P22
P35
PLCC
P21
P32
Standard
P33
P00
Mode
P34
GND
P20
P17
P01
P16
P02
29
P15
P13
P14
NC
P11
P12
P07
P10
28
P06
P03
17
18
P04
P05
R/RL
Figure 6. Z86E61/Z86E63 PLCC Pin Diagram, Standard Mode
Table 29. Z86E61/Z86E63 PLCC Pin Description, Standard Mode
PS014404-0212
Pin Signal
Description
I/O
XTAL2
Crystal Oscillator Clock
Output
XTAL1
Crystal Oscillator Clock
Input
RESET
Reset
Input
R/W
Read/Write
Output
DS
Data Strobe
Output
AS
Address Strobe
Output
P00–P07 Port 0
8-bit General I/O
Input/Output
P10–P17 Port 1
8-bit General I/O
Input/Output
P20–P27 Port 2
8-bit General I/O
Input/Output
P30–P33 Port 3
4-bit Input
Input
P34–P37 Port 3
4-bit Output
Output
R/RL
ROM/ROMless Control
Input
GND
Ground
Input
VCC
Power Supply
Input
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
10
A14
A13
NC
1
6
RESET
OE
PGM
X T AL 2
VC C
NC
X T AL 1
NC
CE
Figure 7 shows the pin-outs for the 44-pin PLCC EPROM Programming Mode package;
Table 30 describes each pin.
40
39
7
NC
A12
NC
A11
NC
NC
Z86E61/E63
A10
NC
PLCC
A9
GND
A8
EPROM Programming
EPM
VPP
NC
Mode
A0
A1
D7
D6
A2
29
D5
NC
D3
D4
D1
D2
A7
D0
28
A5
A6
A3
17
18
A4
NC
Figure 7. Z86E61/Z86E63 PLCC Pin Diagram, EPROM Programming Mode
Table 30. Z86E61/Z86E63 PLCC Pin Description, EPROM Programming Mode
PS014404-0212
Pin Signal
Description
I/O
XTAL2
Crystal Oscillator Clock
Output
XTAL1
Crystal Oscillator Clock
Input
CE
Chip Enable
Input
RESET
Reset
Input
EPM
EPROM Programming Mode
Input
A0–A14
15-bit Address Bus
Input
D7–D0
8-bit Data Bus
Input/Output
VPP
Programming Voltage
Input
PGM
Programming Mode
Input
OE
Output Enable
Input
NC
Not Connected
Input
GND
Ground
Input
VCC
Power Supply
Input
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
11
Pin Descriptions
This section describes the major Z86E61/Z86E63 MCU pin signals and ports.
ROMless (Input, Active Low)
Connecting this pin to GND disables the internal ROM and forces the device to function
as a Z86C91 ROMless Z8 (see the Z86C91 product specification for more information).
When pulled High to VCC, the device functions as a normal Z86E61/Z86E63 EPROM
version. This pin is only available on the 44-pin versions of the Z86E61/Z86E63 MCU.
DS (Output, Active Low)
Data Strobe is activated once for each external memory transfer. For a READ operation,
data must be available prior to the trailing edge of DS. For WRITE operations, the falling
edge of DS indicates that output data is valid.
AS (Output, Active Low)
Address Strobe is pulsed once at the beginning of each machine cycle. Address output is
through Port 1 for all external programs. Memory address transfers are valid at the trailing
edge of AS. Under program control, AS can be placed in the high-impedance state along
with Ports 0 and 1, Data Strobe, and Read/Write.
XTAL2, XTAL1
Crystal 2, Crystal 1 (time-based input and output, respectively). These pins connect a parallel-resonant crystal, ceramic resonator, LC, or any external single-phase clock to the onchip oscillator and buffer.
R/W (Output, Write Low)
The Read/Write signal is Low when the MCU is writing to the external program or data
memory.
RESET (Input, Active Low)
To avoid asynchronous and noisy reset problems, the Z86E61/Z86E63 MCU is equipped
with a reset filter of four external clocks (4TpC). If the external RESET signal is less than
4TpC in duration, no reset occurs.
On the fifth clock after the RESET is detected, an internal RST signal is latched and held
for an internal register count of 18 external clocks, or for the duration of the external
RESET, whichever is longer. During the reset cycle, DS is held active Low while AS
cycles at a rate of TpC/2. When RESET is deactivated, program execution begins at location 000Ch. Power-up reset time must be held low for 50 ms, or until VCC is stable,
whichever is longer.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
12
Port 0 (P07–P00)
Port 0 is an 8-bit, nibble programmable, bidirectional, TTL compatible port. These eight I/
O lines can be configured under software control as a nibble I/O port, or as an address port
for interfacing external memory. When used as an I/O port, Port 0 may be placed under
handshake control. In this configuration, Port 3, lines P32 and P35 are used as the handshake control DAV0 and RDY0 (Data Available and Ready). Handshake signal assignment is dictated by the I/O direction of the upper nibble P07–P04. The lower nibble must
have the same direction as the upper nibble to be under handshake control.
For external memory references, Port 0 can provide address bits A11–A8 (lower nibble) or
A15–A8 (lower and upper nibbles) depending on the required address space. If the address
range requires 12 bits or less, the upper nibble of Port 0 can be programmed independently
as I/O while the lower nibble is used for addressing. If one or both nibbles are needed for
I/O operation, they must be configured by writing to the Port 0 Mode Register.
In ROMless Mode, after a hardware reset, the Port 0 lines are defined as address lines
A15–A8, and extended timing is set to accommodate slow memory access. The initialization routine can include reconfiguration to eliminate this extended timing mode; see
Figure 8.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
13
4
Z86E61/
Z86E63
4
Port 0 (I/O)
MCUs
Handshake controls
DAV0 and RDY0
(P32 and P35)
OEN
PAD
Out
TTL Level Shifter
In
Auto Latch
R = 500 kΩ
Figure 8. Port 0 Configuration
Port 1 (P17–P10)
Port 1 is an 8-bit, byte programmable, bidirectional, TTL compatible port. It has multiplexed Address (A7–A0) and Data (D7–D0) ports. For the Z86E61/Z86E63 MCU, these
eight I/O lines can be programmed as input or output lines or are configured under software control as an address/data port for interfacing external memory. When used as an I/O
port, Port 1 can be placed under handshake control. In this configuration, Port 3 lines, P33
and P34, are used as the handshake controls RDY1 and DAV1.
Memory locations greater than 16384 (Z86E61) or 32768 (Z86E63) are referenced
through Port 1. To interface external memory, Port 1 must be programmed for the multi-
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
14
plexed Address/ Data Mode. If more than 256 external locations are required, Port 0 must
output the additional address lines.
Port 1 can be placed in high-impedance state along with Port 0, AS, DS, and R/W, allowing the MCU to share common resources in multiprocessor and DMA applications. Data
transfers are controlled by assigning P33 as a Bus Acknowledge input, and P34 as a Bus
Request output; see Figure 9.
8
Port 1
(AD7-AD0)
Z86E61
Z86E63
MCU
Handshake controls
DAV1 and RDY1
(P33 and P34)
OEN
PAD
Out
TTL Level Shifter
In
Auto Latch
R = 500 kΩ
Figure 9. Port 1 Configuration
Port 2 (P27–P20)
Port 2 is an 8-bit, bit programmable, bi-directional, CM0S compatible port. Each of these
eight I/0 lines can be independently programmed as an input or output, or globally as an
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
15
open-drain output. Port 2 is always available for I/ 0 operation. When used as an I/0 port,
Port 2 can be placed under handshake control. In this configuration, Port 3 lines P31 and
P36 are used as the handshake control lines DAV2 and RDY2. The handshake signal
assignment for Port 3 lines, P31 and P36, is dictated by the direction (input or output)
assigned to P27; see Figure 10 and Table 31 on page 16).
Z86E61
Z86E63
MCU
Port 2 (I/O)
Handshake controls
DAV2 and RDY2
(P31 and P36)
Open-Drain
OEN
PAD
Out
TTL Level Shifter
In
Auto Latch
R = 500 kΩ
Figure 10. Port 2 Configuration
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
16
Port 3 (P37–P30)
Port 3 is an 8-bit, CMOS compatible four-fixed input and four-fixed output port. These
eight I/O lines have four-fixed (P33–P30) input and four-fixed (P37–P34) output ports.
Port 3, when used as serial I/O, is programmed as serial in and serial out, respectively; see
Figure 11.
Z86E61
Z86E63
MCU
Port 3
(I/O or Control)
Figure 11. Port 3 Configuration
Port 3 is configured under software control to provide the following control functions:
handshake for Ports 0 and 2 (DAV and RDY); four external interrupt request signals
(IRQ3–IRQ0); timer input and output signals (TIN and TOUT) Data Memory Select (DM)
and EPROM control signals (P30 = CE, P31 = OE, P32 = EPM and P33 = VPP).
Table 31 lists the pin assignments for Port 3.
Table 31. Port 3 Pin Assignments*
Pin
I/O
CTCI
Interrupt
P30
In
TIN
IRQ3
P31
In
TIN
IRQ2
P32
In
TIN
IRQ0
P33
In
TIN
IRQ1
P34
Out
TOUT
P35
Out
TOUT
P36
Out
TOUT
P37
Out
TOUT
P0 HS
P1 HS
P2 HS
UART
Ext
Serial In
EPROM
CE
D/R
OE
D/R
EPM
D/R
VPP
R/D
DM
R/D
R/D
Serial Out
T0
IRQ4
T1
IRQ5
Note: *HS = Handshake Signals; D = Data Available; R = Ready.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
17
UART Operation. Port 3 lines, P37 and P30, are programmed as serial I/0 lines for fullduplex serial asynchronous receiver/transmitter operation. The bit rate is controlled by
Counter/ Timer0.
The Z86E61/Z86E63 MCU automatically adds a start bit and two stop bits to transmitted
data; see Figure 12. Odd parity is also available as an option. Eight data bits are always
transmitted, regardless of parity selection. If parity is enabled, the eighth bit is the odd parity bit. An interrupt request (IRQ4) is generated on all transmitted characters.
Received data must have a start bit, eight data bits, and at least one stop bit. If parity is on,
bit 7 of the received data is replaced by a parity error flag. Received characters generate
the IRQ3 interrupt request.
Transmitted Data (No Parity)
Received Data (No Parity)
SP SP D7 D6 D5 D4 D3 D2 D1 D0 ST
SP D7 D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Start Bit
Eight Data Bits
Eight Data Bits
Two Stop Bits
One Stop Bit
Received Data (With Parity)
Transmitted Data (With Parity)
SP P D6 D5 D4 D3 D2 D1 D0 ST
SP SP P D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Start Bit
Seven Data Bits
Seven Data Bits
Odd Parity
Parity Error Flag
Two Stop Bits
One Stop Bit
Figure 12. Serial Data Formats
Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs that are not
externally driven. This reduces excessive supply current flow in the input buffer when it is
not driven by any source.
Note: P33–P30 inputs differ from the Z86C61/C63 in that there is no clamping diode to VCC
because of the EPROM high voltage detection circuits. Exceeding the VIH maximum specification during standard operating mode may cause the device to enter EPROM Mode.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
18
Address Space
This section describes the memory and addressing functions of the Z86E61/Z86E63
MCU.
Program Memory
The Z86E61/Z86E63 MCU can address 48 KB (Z86E61) or 32 KB (Z86E63) of external
program memory; see Figure 13. The first 12 bytes of program memory are reserved for
the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six
available interrupts. For EPROM Mode, byte 13 to byte 16383 (Z86E61) or 32767
(Z86E63) consists of on-chip EPROM. At addresses 16384 (Z86E61) or 32768 (Z86E63)
and above, the Z86E61/Z86E63 MCU executes external program memory fetches. In
ROMless Mode, the Z86E61/Z86E63 MCU can address up to 64 KB of program memory.
Program execution begins at external location 000C (HEX) after a reset.
65535
16384 (E61)
32768 (E63)
16383 (E61)
32767 (E63)
Location of
First Byte of
Instruction
Executed
After RESET
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
External
ROM and RAM
On-Chip PROM
12
11
IRQ5
10
IRQ5
9
IRQ4
8
IRQ4
7
IRQ3
6
IRQ3
5
IRQ2
4
IRQ2
3
IRQ1
2
IRQ1
1
IRQ0
0
IRQ0
Figure 13. Program Memory Configuration
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
19
Data Memory
The EPROM version can address up to 48 KB (Z86E61) or 32 KB (Z86E63) of external
data memory (DM) space beginning at location 16384 (Z86E61) or 32768 (Z86E63). The
ROMless version can address up to 64 KB of external data memory. External data memory
may be included with, or separated from, the external program memory space. DM, an
optional I/0 function that can be programmed to appear on pin P34, is used to distinguish
between data and program memory space; see Figure 14. The state of the DM signal is
controlled by the type instruction being executed. An LDC opcode references PROGRAM
(DM inactive) memory, and an LDE instruction references DATA (DM active Low) memory.
65535
External
Data
Memory
32768 (E63)
16384 (E61)
16383 (E61)
32767 (E63)
Not Addressable
0
Figure 14. Data Memory Configuration
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
20
Register File
The register file consists of four I/0 port registers, 236 general-purpose registers, and 16
control and status registers, as shown in Figure 15. The instructions can access registers
directly or indirectly through an 8-bit address field. The Z86E61/Z86E63 MCU also
allows short 4-bit register addressing using the Register Pointer, which is shown in
Figure 16. In 4-bit mode, the Register File is divided into 16 working register groups, each
occupying 16 continuous locations. The Register Pointer addresses the starting location of
the active working register group.
IDENTIFIERS
LOCATION
R255
Stack Pointer (Bits 7–0)
SPL
R254
Stack Pointer (Bits 15–8)
SPH
R253
Register Pointer
R252
Program Control Flags
R251
Interrupt Mask Register
IMR
R250
Interrupt Request Register
IRQ
R249
Interrupt Priority Register
IPR
RP
FLAGS
R248
Port 0–1 Mode
P01M
R247
Port 3 Mode
P3M
R246
Port 2 Mode
P2M
R245
T0 Prescaler
PRE0
R244
Timer/Counter0
R243
T1 Prescaler
R242
Timer/Counter1
R241
Timer Mode
TMR
R240
Serial I/O
SIO
T0
PRE1
T1
R239
General Purpose
Registers
R4
R3
Port 3
P3
R2
Port 2
P2
R1
Port 1
P1
R0
Port 0
P0
Figure 15. Register File
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
21
r7 r6 r5 r4
r3 r2 r1 r0
R253
(Register Pointer)
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
FF
R15 to R0
F0
Specified Working
Register Group
2F
20
1F
10
0F
00
The lower nibble of the register file
address provided by the instruction
points to the specified register.
Register Group 1
R15 to R0
Register Group 0
R15 to R4
I/O Ports
R3 to R0
Figure 16. Register Pointer
Stack
The Z86E61/Z86E63 MCU has a 16-bit Stack Pointer (R255–R254) used for external
stacks that reside anywhere in the data memory for the ROMless Mode, but only from
16384 (Z86E61) or 32768 (Z86E63) to 65535 in the EPROM Mode. An 8-bit Stack
Pointer (R255) is used for the internal stack that resides within the 236 general-purpose
registers (R239–R4). The high byte of the Stack Pointer (SPH Bits 15–8) can be use as a
general-purpose register when using internal stack only.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
22
Functional Description
This section describes the counter/timer, interrupt, clock and timer mode functions of the
Z86E61/Z86E63 MCU.
Counter/Timers
There are two 8-bit programmable counter/timers (T0–T1), each driven by its own 6-bit
programmable prescaler. The T1 prescaler is driven by internal or external clock sources;
however, the T0 prescaler is driven by the internal clock only, as shown in Figure 17.
Internal Data Bus
Write
Write
OSC
Read
PRE0
Initial Value
Register
T0
Initial Value
Register
6-Bit
Down
Counter
8-Bit
Down
Counter
T0
Current Value
Register
+2
+4
Internal
Clock
IRQ4
Serial I/O
Clock
+2
External Clock
T OUT
P36
Clock
Logic
+4
Internal Clock
Gated Clock
Triggered Clock
T IN P31
Write
6-Bit
Down
Counter
8-Bit
Down
Counter
PRE1
Initial Value
Register
T1
Initial Value
Register
Write
IRQ5
T1
Current Value
Register
Read
Internal Data Bus
Figure 17. Counter/Timers Block Diagram
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
23
The 6-bit prescalers can divide the input frequency of the clock source by any integer
number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to
256) that has been loaded into the counter. When both the counters and prescalers reach
the end of the count, a timer interrupt request, IRQ4 (T0) or IRQ5 (T1), is generated.
The counter is programmed to start, stop, restart to continue, or restart from the initial
value. The counters can also be programmed to stop upon reaching zero (Single Pass
Mode) or to automatically reload the initial value and continue counting (Modulo-n Continuous Mode).
The counter, but not the prescalers, are read at any time without disturbing their value or
count mode. The clock source for T1 is user-definable and is either the internal microprocessor clock divided-by-four, or an external signal input through Port 3. The Timer Mode
Register configures the external timer input (P31) as an external clock, a trigger input that
can be retriggerable or non-retriggerable, or as a gate input for the internal clock. Port 3
line P36 also serves as a timer output (TOUT) through which T0, T1, or the internal clock
can be output. The counter/timers are cascaded by connecting the T0 output to the input of
T1.
Interrupts
The Z86E61/Z86E63 MCU has six different interrupts from eight different sources. The
interrupts are maskable and prioritized. The eight sources are divided as follows: four
sources are claimed by Port 3 lines P33–P30, one in Serial Out, one in Serial In, and two in
the counter/timers; see Figure 18. The Interrupt Mask Register globally or individually
enables or disables the six interrupt requests. When more than one interrupt is pending,
priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority Register; see Figure 40 on page 48.
All Z86E61/Z86E63 MCU interrupts are vectored through locations in the program memory. When an interrupt machine cycle is activated, an interrupt request is granted. Thus,
this disables all of the subsequent interrupts, saves the Program Counter and Status Flags,
and then branches to the program memory vector location reserved for that interrupt. This
memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs are masked and the Interrupt
Request Register is polled to determine which of the interrupt requests need service. Software initialized interrupts are supported by setting the appropriate bit in the Interrupt
Request Register (IRQ).
Internal interrupt requests are sampled on the falling edge of the last cycle of every
instruction, and the interrupt request must be valid 5TpC before the falling edge of the last
clock cycle of the currently executing instruction.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
24
IRQ0–IRQ5
IRQ
IMR
6
Global
Interrupt
Enable
Interrupt
Request
IPR
PRIORITY
LOGIC
Vector Select
Figure 18. Interrupt Block Diagram
For the ROMless Mode, when the device samples a valid interrupt request, the next 48
(external) clock cycles are used to prioritize the interrupt, and push the two PC bytes and
the Flag Register on the stack. The following nine cycles are used to fetch the interrupt
vector from external memory. The first byte of the interrupt service routine is fetched
beginning on the 58th TpC cycle following the internal sample point, which corresponds
to the 63rd TpC cycle following the external interrupt sample point.
Clock
The Z86E61/Z86E63 MCU’s on-chip oscillator features a high gain, parallel resonant
amplifier for connection to a crystal, LC, ceramic resonator, or any suitable external clock
source (XTAL1 = Input, XTAL2 = Output). The crystal should be AT cut, 1 MHz to
20 MHz max; series resistance (RS) is less than or equal to 100 Ohms. The crystal should
be connected across XTAL1 and XTAL2 using the recommended capacitors (10 pF < CL <
100 pF) from each pin to ground; see Figure 19.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
25
XTAL1
C1
C1
Pin 11
Pin 11
XTAL1
XTAL1
XTAL2
XTAL2
L
XTAL2
C2
C2
Pin 11
Pin 11
Ceramic Resonator
or Crystal
LC Clock
External Clock
Figure 19. Oscillator Configuration
Note: The actual capacitor value is specified by the crystal manufacturer.
HALT
Turns off the internal CPU clock but not the XTAL oscillation. The counter/timers and
external interrupts IRQ0, IRQ1, IRQ2, and IRQ3 remain active. The devices are recovered
by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT.
STOP
This instruction turns off the internal clock and external crystal oscillation, and reduces the
standby current to 5 µA (typical) or less. The STOP Mode is terminated by a reset, which
causes the processor to restart the application program at address 000Ch.
To enter STOP (or HALT) Mode, it is necessary to first flush the instruction pipeline to
avoid suspending execution in mid-instruction. To do this, the user must execute a NOP
(opcode = 0FFH) immediately before the appropriate SLEEP instruction, as shown in the
following code segment.
FF
6F
or
FF
7F
PS014404-0212
NOP
STOP
; clear the pipeline
; enter STOP Mode
NOP
HALT
; clear the pipeline
; enter HALT Mode
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
26
Programming
This section describes the five user program modes available for programming the
Z86E61/Z86E63 MCU, including signal descriptions for programming or reading the
Z86E63 device.
Z86E61/Z86E63 User Modes
The Z86E61/Z86E63 MCU uses separate AC timing cycles for the different user modes
available. Table 32 shows the Z86E61/Z86E63 MCU’s user modes; Table 33 shows the
timing of the programming waveforms.
Table 32. OTP Programming1
Device Pins
User/Test Mode
Device Pin No.
P33
P32
P30
P31
P20
User Modes
VPP
EPM
CE
OE
PGM
ADDR
VCC
Port 1
Config
Data
3
4
VIL
VIH
Addr
5.0 V
Out
VIL
Addr
6.0 V
In
VIH
Addr
EPROM Read
Z
2
VH
VIL
VIH
VIL
VIH6
VIH
VIL
VIL
EPROM Protect
VPP5
VPP5
VPP5
VH
VH
VIH
RAM Protect
VPP
VIH
VH
VIH
Program
Program Verify
6.0 V
Out
VIL
X
7
6.0 V
X
VIL
X
6.0 V
X
Notes:
1. IPP during programming = 40 mA maximum; ICC during programming, verify or read = 40 mA maximum.
2. Z = VIL or VIH.
3. VH = 12.0 ± 0.5 V.
4. VIL = 0 V.
5. VPP = 12.0 ± 0.5 V.
6. VIH = 5 V.
7. X = Not used in this mode.
Table 33. Timing of Programming Waveforms
Parameters
Name
1
Address Setup Time
2
µs
2
Data Setup Time
2
µs
3
VPP Setup Time
2
µs
4
VCC Setup time
2
µs
5
Chip Enable Setup Time
2
µs
6
Program Pulse Width
0.95
µs
PS014404-0212
Min
Max
Unit
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
27
Table 33. Timing of Programming Waveforms (Continued)
Parameters
Name
Min
Max
Unit
7
Data Hold Time
2
µs
8
OE Setup Time
2
µs
9
Data Access Time
200
ns
10
Data Output Float Time
100
ns
11
Overprogram Pulse Width
12
2.85
ms
EPM Setup Time
2
µs
13
PGM Setup Time
2
µs
14
Address to OE Setup Time
2
µs
15
Option Program Pulse Width
78
ms
User MODE 1: EPROM Read
The Z86E61/Z86E63 EPROM read cycle is provided so that the user may read the
Z86E61/Z86E63 MCU as a standard 27128 (Z86E61) or 27256 (Z86E63) EPROM. This
is accomplished by driving the EPM pin (P32) to VH and activating CE and OE. PGM
remains inactive. This mode is not valid after execution of an EPROM protect cycle.
Timing for the EPROM read cycle is shown in Figure 20.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
28
VIH
Address
Address Stable
Address Stable
VIL
0 Min
VIH
Data
VIL
Invalid
Valid
Invalid
Valid
9
VIH
VPP
VIL
VH
EPM
VIL
12
VCC
5V
VIH
CE
VIL
0 Min
VIH
OE
VIL
VIH
PGM
VIL
3
Figure 20. EPROM Read Timing
User MODE 2: EPROM Program
The Z86E61/Z86E63 MCU’s Program function conforms to the Intelligent programming
algorithm. The device is programmed with VCC, at 6.0 V and VPP = 12.5 V. Programming
pulses are applied in 1 ms increments to a maximum of 25 pulses before proper verification. After verification, a programming pulse of three times the duration of the cycles necessary to program the device is issued to ensure proper programming. After all addresses
are programmed, a final data comparison is executed and the programming cycle is complete. Timing for the Z86E61/Z86E63 MCU programming cycle is shown in Figure 21.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
29
VIH
Address
Address Stable
VIL
1
VIH
Data
Data Out Valid
Data Stable
9
VIL
10
2
VH
VPP
VIL
3
VIH
EPM
VIL
6V
VCC
5V
7
4
VIH
CE
VIL
5
VIH
OE
VIL
VIH
PGM
8
VIL
6
11
Program Cycle
Verify Cycle
Figure 21. EPROM Program and Verify Timing
User Mode 3: PROM Verify
The Program Verify cycle is used as part of the intelligent programming algorithm to
insure data integrity under worst-case conditions. It differs from the EPROM Read cycle
in that VPP is active and VCC must be driven to 6.0 V. Timing is shown in Figure 21.
User Modes 4 and 5: EPROM and RAM Protect
To extend program security, EPROM and RAM protect cycles are provided for the
Z86E61/Z86E63 MCU. Execution of the EPROM protect cycle prohibits proper execution
of the EPROM Read, EPROM Verify, and EPROM programming cycles. Execution of the
RAM protect cycle disables accesses to the upper 128 bytes of register memory (excluding
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
30
mode and configuration registers), but first the user’s program must set bit 6 of the IMR
(R251). Timing is shown in Figure 22.
VIH
Address
VIL
VIH
Data
VIL
VH
VPP
VIH
VCC
3
6V
5V
4
VH
CE
VIH
5
VH
OE
VIH
VH
EPM VIH
VIL
VIH
12
12
VIH
PGM
VIL
15
ROM Protect
Programming
15
RAM Protect
Programming
Figure 22. Programming EPROM and RAM Protect
Z86E63 Signal Description for EPROM Program/Read
The following signals are required to correctly program or read the Z86E63 device.
ADDR
The address must remain stable throughout the program read cycle. On both the Z86E61
and Z86E63 MCUs, all A0–A14 address lines must be driven at all times.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
31
DATA
The I/O data bus must be stable during programming (OE High, PGM Low, VPP High).
During read the data bus outputs data.
XCLK
A clock is required to clock the RESET signal into the registers before programming. A
constant clock can be applied, or the XCLK input can be toggled a minimum of 12 cycles
before any programming or verify function begins. The maximum clock frequency to be
applied when in the EPROM Mode is 12 MHz.
RESET. The reset input can be held to a constant Low or High value throughout normal
programming. It must be held High to program the EPROM protect option bit. Also, any
time the RESET input changes state the XCLK must be clocked a minimum of 12 times to
clock the RESET through the reset filter.
OE. When the device is placed in EPROM Mode, the OE input also serves as the precharge for the sense amp. The precharge signal should be Low for the first half of the stable address and High for the second half. The PRECHG signal is inverted from the OE
signal so the OE should be High on the first half and Low on the second half, or stable
address. The EPROM output data should be sampled during the second half of stable
address.
The access time of the EPROM is defined in later sections. This two part calculation of
access time is required because this is a precharged sense amp with a precharge clock.
Programming Flow
Figure 23 shows the steps for programming the Z86E61/Z86E63 MCU.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
32
Start
Addr =
First Location
VCC = 6.0 V
VPP = 12.5 V
N=0
Program
1 ms Pulse
Increment N
Yes
N = 25?
No
Fail
Verify
One Byte
Verify Byte
Fail
Pass
Pass
Prog. One Pulse
3xN ms Duration
Increment
Address
No
Last Addr?
Yes
VCC=VPP=4.5V
Verify All
Bytes
Fail
Device Failed
VCC=VPP=5.5V
Verify All
Bytes
Pass
Fail
Device Passed
Figure 23. Intelligent Programming Flowchart
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
33
Absolute Maximum Ratings
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; operation of the device at any condition
above those indicated in the operational sections of these specifications is not implied.
Exposure to absolute maximum rating conditions for an extended period may affect device
reliability.
Table 34 lists the absolute maximum ratings of the Z86E61/Z86E63 MCU.
Table 34. Absolute Maximum Ratings
Symbol
Description
Voltage1
VCC
Supply
TSTG
Storage Temperature
TA
Operating Ambient Temperature
Min
Max
Unit
–0.3
+7.0
V
–65
+150
°C
See Note 2
°C
Notes:
1. Voltages on all pins with respect to GND.
2. See Ordering Information on page 60.
Standard Test Conditions
The characteristics described in this document apply to standard test conditions, as noted.
All voltages are referenced to GND, and positive current flows into the referenced pin; see
Figure 24.
From Output
Under Test
I
150 pF
Figure 24. Test Load Diagram
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
34
DC Characteristics
Table 35 lists voltage and direct current characteristics for the Z86E61/Z86E63 MCU
under differing conditions. Be advised that ICC2 requires loading TMR (F1Hh) with any
value prior to STOP execution. Use the following sequence:
LD TMR,#00
NOP
STOP
Table 35. Direct Current Characteristics
Symbol
Parameter
Min
Max Input Voltage
Max
Typical
@ 25°C
7
Units Conditions
V
IIN < 250 µA.
V
P33–P30 Only.
Max Input Voltage
13
VCH
Clock Input High Voltage
3.8
VCC + 0.3
V
Driven by External Clock
Generator.
VCL
Clock Input Low Voltage
–0.3
0.8
V
Driven by External Clock
Generator.
VIH
Input High Voltage
2.0
VCC + 0.3
V
VIL
Input Low Voltage
–0.3
0.8
V
VOH
Output High Voltage
2.4
VOL
Output Low Voltage
VRH
Reset Input High Voltage
VRL
V
IOH = –2.0 mA.
0.4
V
IOL = +2.0 mA.
3.8
VCC + 0.3
V
Reset Input Low Voltage
–0.3
0.8
V
IIL
Input Leakage
–10
10
µA
VIN = 0 V, 5.25 V.
IOL
Output Leakage
–10
10
µA
VIN = 0 V, 5.25 V.
IIR
Reset Input Current
–50
µA
VCC = +5.25 V; VRL = 0 V.
ICC
Supply Current
50
25
mA
@ 16 MHz.
60
35
mA
@ 20 MHz.
15
5
mA
HALT Mode @ 16 MHz;
VIN = 0 V, VCC
20
10
mA
HALT Mode @ 20 MHz;
VIN = 0 V, VCC
20
5
µA
STOP Mode
VIN = 0 V, VCC
ICC1
ICC2
Standby Current
Standby Current
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
35
Supply Current
Figure 25 shows the typical supply current values (in milliamps), for the Z86E61/Z86E63
MCU as a function of frequency (in megahertz).
ICC (mA)
40
A
B
30
C
20
10
0
2
4
6
8
10
12
14
16
18
20
Frequency (MHz)
Legend:
A – VCC = 5.6V
B – VCC = 5.0V
C – VCC = 4.4V
Figure 25. Typical ICC vs. Frequency
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
36
Standby Current
Figure 26 shows the typical standby current values (in milliamps), for the Z86E61/
Z86E63 MCU as a function of frequency (in megahertz).
I CC1 (mA)
12
A
10
B
C
8
6
4
2
0
2
4
6
8
10
12
14
16
18
20
Frequency (MHz)
Legend:
A – VCC = 5.6V
B – VCC = 5.0V
C – VCC = 4.4V
Figure 26. Typical ICC1 vs. Frequency
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
37
AC Characteristics
Figure 27 displays the timing characteristics for the Z86E61/Z86E63 MCU. The circled
numbers in this figure reference a description in Table 36 of each symbol, its parameter
and its frequency range for these 16 MHz and 20 MHz parts.
R/W
13
12
Port 0, DM
16
18
3
Port 1
D7–D0 IN
A7–A0
2
9
1
AS
8
11
4
6
DS
(Read)
17
10
Port 1
A7–A0
D7–D0 OUT
14
15
7
DS
(Write)
17
Figure 27. External I/O or Memory Read/Write Timing
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
38
Table 36 lists the alternating current characteristics for the Z86E61/Z86E63 MCU as they
relate to Figure 27. Formulas for each parameter are listed in Table 37.
Table 36. External I/O or Memory Read and Write Timing
TA = 0°C to +70°C
16 MHz1
Min
Max
20 MHz
Min
Max
No. Symbol
Parameter
1
TdA(AS)
Address Valid to AS Rise Delay
20
26
ns
2,3
2
TdAS(A)
AS Rise to Address Float Delay
30
28
ns
2,3
3
TdAS(DR)
AS Rise to Read Data Req’d
Valid
ns
2,3,4
4
TwAS
AS Low Width
35
36
ns
2,3
5
TdAZ(DS)
Address Float to DS Fall
0
0
ns
6
TwDSR
DS (Read) Low Width
135
130
ns
2,3,4
7
TwDSW
DS (Write) Low Width
80
75
ns
2,3,4
8
TdDSR(DR)
DS Fall to Read Data Req’d Valid
ns
2,3,4
9
ThDR(DS)
Read Data to DS Rise Hold Time
0
0
ns
2,3
10
TdDS(A)
DS Rise to Address Active Delay
35
48
ns
2,3
11
TdDS(AS)
DS Rise to AS Fall Delay
30
36
ns
2,3
12
TdR/W(AS)
R/W Valid to AS Rise Delay
20
32
ns
2,3
13
TdDS(R/W)
DS Rise to R//W Not Valid
30
36
ns
2,3
14
TdDW(DSW) Write Data Valid to DS Fall
(Write) Delay
TdDS(DW)
DS Rise to Write Data Not Valid
25
40
ns
2,3
30
40
ns
2,3
ns
2,3,4
15
180
160
75
100
Units Notes
Delay
16
TdA(DR)
17
18
200
200
TdAS(DS)
Address Valid to Read Data
Req’d Valid
AS Rise to DS Fall Delay
40
48
ns
2,3
TdDM(AS)
DM Valid to AS Fall Delay
30
36
ns
2,3
Notes:
1. All timing references use 2.0 V for a logic 1 and 0.8V for a logic 0.
2. Timing numbers given are for minimum TpC.
3. See Table 37.
4. When using extended memory timing, add 2 TpC.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
39
Table 37. Clock-Dependent Formulas
Number
Symbol
Formula
1
TdA(AS)
0.40 TpC + 0.32
2
TdAS(A)
0.59 TpC – 3.25
3
TdAS(DR)
2.83 TpC + 6.14
4
TwAS
0.66 TpC – 1.65
6
TwDSR
2.33 TpC – 10.56
7
TwDSW
1.27 TpC + 1.67
8
TdDSR(DR)
1.97 TpC – 42.5
10
TdDS(A)
0.8 TpC
11
TdDS(AS)
0.59 TpC – 3.14
12
TdR/W(AS)
0.4 TpC
13
TdDS(R/W)
0.8 TpC – 15
14
TdDW(DSW)
0.4 sTpC
15
TdDS(DW)
0.88 TpC – 19
16
TdA(DR)
4 TpC – 20
17
TdAS(DS)
0.91 TpC – 10.7
18
TdDM(AS)
0.9 TpC – 26.3
Input and output handshake timing characteristics are shown in Figures 28 and 29 and
described in Table 38.
Next Data In Valid
Data In Valid
Data In
2
1
DAV
(Input)
3
Delayed DAV
5
6
4
RDY
(Output)
Delayed RDY
Figure 28. Input Handshake Timing
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
40
Next Data Out Valid
Data Out Valid
Data Out
7
Delayed DAV
DAV
(Output)
8
9
11
10
RDY
(Input)
Delayed RDY
Figure 29. Output Handshake Timing
Table 38. Handshake Timing
TA = 0°C to +70°C
16 MHz
Max
Symbol
Parameter
1
TsDI(DAV)
Data In Setup Time
0
0
IN
2
ThDI(DAV)
Data In Hold Time
145
145
IN
3
TwDAV
Data Available Width
110
110
IN
4
TdDAVI(RDY)
DAV Fall to RDY Fall Delay
115
115
IN
5
TdDAVId(RDY)
DAV Rise to RDY Rise Delay
115
115
IN
6
TdRDY0(DAV)
RDY Rise to DAV Fall Delay
7
TdD0(DAV)
Data Out to DAV Fall Delay
8
TdDAV0(RDY)
DAV Fall to RDY Fall Delay
9
TdRDY0(DAV)
RDY Fall to DAV Rise Delay
10
TwRDY
RDY Width
11
TdRDY0d(DAV)
RDY Rise to DAV Fall Delay
0
Min
Max
Data
Direction
No.
PS014404-0212
Min
20 MHz
0
TpC
0
IN
TpC
0
115
110
OUT
115
110
115
OUT
OUT
OUT
115
OUT
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
41
Additional timing characteristics are shown in Figure 30 and described in Table 39.
3
1
Clock
2
2
3
7
7
TIN
5
4
6
IRQN
9
8
Figure 30. Additional Timing
Table 39. Additional Timing
TA = 0°C to +70°C
16 MHz1
20 MHz
No. Symbol
Parameter
Min
Max
Min
Max
1
TpC
Input Clock Period
62.5
1000
50
1000
ns
1
2
TrC,TfC
Clock Input Rise & Fall Times
15
ns
1
3
TwC
Input Clock Width
21
37
ns
1
4
TwTINL
Timer Input Low Width
50
75
ns
2
5
TwTINH
Timer Input High Width
5 TpC
5 TpC
2
6
TpTIN
Timer Input Period
8 TpC
8 TpC
2
7
TrTIN,TfTIN
Timer Input Rise & Fall times
100
100
10
Units Notes
ns
2
Notes:
1. Clock timing references use 3.8 V for a logic 1 and 0.8 V for a logic 0.
2. Timing references use 2.0 V for a logic 1 and 0.8 V for a logic 0.
3. Interrupt request through Port 3 (P33–P31).
4. Interrupt request through Port 30.
5. Interrupt references request through Port 3.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
42
Table 39. Additional Timing (Continued)
TA = 0°C to +70°C
16 MHz1
20 MHz
No. Symbol
Parameter
8A
TwIL
Interrupt Request Input Low
Times
70
50
8B
TwIL
Interrupt Request Input Low
Times
5 TpC
5 TpC
2,4
9
TwIH
Interrupt Request Input High
Times
5 TpC
5 TpC
2,5
Min
Max
Min
Max
Units Notes
ns
2,3
Notes:
1. Clock timing references use 3.8 V for a logic 1 and 0.8 V for a logic 0.
2. Timing references use 2.0 V for a logic 1 and 0.8 V for a logic 0.
3. Interrupt request through Port 3 (P33–P31).
4. Interrupt request through Port 30.
5. Interrupt references request through Port 3.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
43
Control Registers
Figures 31 through 46 provide brief bit descriptions of each of the Z86E61/Z86E63
MCU’s control registers.
R240 SIO
D7
D6
D5
D4
D3
D2
D1
D0
Serial Data (D0 = LSB)
Figure 31. Serial I/O Register (F0H: Read/Write)
R241 TMR
D7
D6
D5
D4
D3
D2
D1
D0
0: No function
1: Load T0
0: Disable T0 count
1: Enable T0 count
0: No function
1: Load T1
0: Disable T1 count
1: Enable T1 count
TIN Modes
00: External clock input
01: Gate input
10: Trigger input (nonretriggerable)
11: Trigger input (retriggerable)
TOUT Modes
00: Not used
01: T0 Out
10: T1 Out
11: Internal clock out
Figure 32. Timer Mode Register (F1H: Read/Write)
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
44
R242 T1
D7
D6
D5
D4
D3
D2
D1
D0
T1 Initial Value (when written)
Range: 1–256 decimal, 01–00 hex
Figure 33. Counter/Timer 1 Register (F2H: Read/Write)
R243 PRE1
D7
D6
D5
D4
D3
D2
D1
D0
Count Mode
0: T1 Single pass
1: T1 Modulo N
Clock Source
0: T1 Internal
1: T1 External timing input (TIN Mode)
Prescaler Modulo
Range: 1–64 decimal, 01–00 hex
Figure 34. Prescaler 1 Register (F3H: Write Only)
R244 T0
D7
D6
D5
D4
D3
D2
D1
D0
T0 Initial Value (when written)
Range: 1–256 decimal, 01–00 hex
T0 Current Value (when read)
Figure 35. Counter/Timer 0 Register (F4H: Read/Write)
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
45
R245 PRE0
D7
D6
D5
D4
D3
D2
D1
D0
Count Mode
0: T0 Single pass
1: T0 Modulo N
Reserved (must be 0)
Prescaler Modulo
Range: 1–64 decimal, 01–00 hex
Figure 36. Prescaler 0 Register (F5H: Write Only)
R246 P2M
D7
D6
D5
D4
D3
D2
D1
D0
P20–P27 I/O Definition
0: Defines bit as output
1: Defines bit as input
Figure 37. Port 2 Mode Register (F6H: Write Only)
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
46
R247 P3M
D7
D6
D5
D4
D3
D2
D1
D0
0: Port 2 pull-ups open drain
1: Port 3 pull-ups active
Reserved (must be 0)
0: P32 = Input; P35 = Output
1: P32 = DAV0/RDY0; P35 = RDY0/DAV0
00: P33 = Input; P34 = Output
01: P33 = Input
10: P34 = DM
11: P33 = DAV1/RDY1; P34 = RDY1/DAV1
0: P31 = Input (TIN); P36 = Output (TOUT )
1: P31 = DAV2/RDY2; P36= RDY2/DAV2
0: P30 = Input; P37 = Output
1: P30 = Serial in; P37 = Serial out
0: Parity off
1: Parity on
Figure 38. Port 3 Mode Register (F7H: Write Only)
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
47
R248 P01M
D7
D6
D5
D4
D3
D2
D1
D0
P00–P00 Mode
00: Output
01: Input
1x: A11–A8
Stack Selection
0: External
1: Internal
P17–P10 Mode
00: Byte output
01: Byte input
10: AD7–AD0
11: High-impedance AD7–DA0, AS, DS,
R/W, A11–A8, A15–A12, if selected
External Memory Timing
0: Normal
1: Extended
P07–P04 Mode
00: Output
01: Input
1x: A15–A12
Figure 39. Port 0 and 1 Mode Register (F8H: Write Only)
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
48
R249 IPR
D7
D6
D5
D4
D3
D2
D1
D0
Interrupt Group Priority
000 = Reserved
001 = C > A > B
010 = A > B > C
011 = A > C > B
100 = B > C > A
101 = C > B > A
110 = B > A > C
111 = Reserved
IRQ1, IRQ4 Priority (Group C)
0: IRQ1 > IRQ4
1: IRQ4 > IRQ1
IRQ0, IRQ2 Priority (Group B)
0: IRQ2 > IRQ0
1: IRQ0 > IRQ2
IRQ3, IRQ5 Priority (Group A)
0: IRQ5 > IRQ3
1: IRQ3 > IRQ5
Reserved (must be 0)
Figure 40. Interrupt Priority Register (F9H: Write Only)
R250 IRQ
D7
D6
D5
D4
D3
D2
D1
D0
IRQ0 = P32 input (D0 = IRQ0)
IRQ1 = P33 input
IRQ2 = P31 input
IRQ3 = P30 input, serial input
IRQ4 = T0 serial output
IRQ5 = T1
Reserved (must be 0)
Figure 41. Interrupt Request Register (FAH: Read/Write)
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
49
R251 IMR
D7
D6
D5
D4
D3
D2
D1
D0
1: Enables IRQ5–IRQ0
(D0 = IRQ0)
1: Enables RAM protect
1: Enables interrupts
Figure 42. Interrupt Mask Register (FBH: Read/Write)
R252 SPL Flags
D7
D6
D5
D4
D3
D2
D1
D0
User flag 1
User flag 2
Half Carry flag
Decimal Adjust flag
Overflow flag
Sign flag
Zero flag
Carry flag
Figure 43. Flag Register (FCH: Read/Write)
R253 SPL
D7
D6
D5
D4
D3
D2
D1
D0
0: Reserved (must be 0)
f4
r5
r6
r7
Figure 44. Register Pointer Register (FDH: Read/Write)
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
50
R254 SPL
D7
D6
D5
D4
D3
D2
D1
D0
Stack Pointer Low Byte
Byte (SP15–SP8)
Figure 45. Stack Pointer Register (FEH: Read/Write)
R255 SPH
D7
D6
D5
D4
D3
D2
D1
D0
Stack Pointer High Byte
Byte (SP7–SP0)
Figure 46. Stack Pointer Register (FFH: Read/Write)
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
51
Z8 Instruction Set
This section discusses the addressing modes, symbols, flags, condition codes and instruction formats that apply to the Z8 instruction set. A summary of the Z8 instruction set follows on page 55.
The notations listed in Table 40 are used to describe addressing modes and instruction
operations.
Table 40. Instruction Set Notation
Notation
Definition
IRR
Indirect register pair or indirect working register pair address.
Irr
Indirect working register pair only.
X
Indexed address.
DA
Direct address.
RA
Relative address.
IM
Immediate.
R
Register or working register address.
r
Working register address only.
IR
Indirect register or indirect working register address.
Ir
Indirect working register address only.
RR
Register pair or working register pair address.
The symbols listed in Table 41are used to describe the Z8 instruction set.
Table 41. Instruction Set Symbols
PS014404-0212
Symbol
Definition
dst
Destination location or contents.
src
Source location or contents.
cc
Condition code.
@
Indirect address prefix.
SP
Stack Pointer.
PC
Program Counter.
FLAGS
Flag Register (Control Register 252).
RP
Register Pointer (R253).
IMR
Interrupt Mask Register (R251).
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
52
Control Register R252 contains the six flags shown in Table 42.
Table 42. R252 Flags
Symbol
Definition
C
Carry flag.
Z
Zero flag.
S
Sign flag.
V
Overflow flag.
D
Decimal Adjust flag.
H
Half Carry flag.
The flags in Table 42 can be affected by the symbols defined in Table 43.
Table 43. R252 Flags
Symbol
Definition
0
Clear to zero.
1
Set to one.
*
Set to clear
according to
operation.
–
Unaffected.
x
Undefined.
Table 44 defines the flags that are set for each condition code value.
Table 44. Condition Codes
Value
Mnemonic
Definition
0000
F
Never True (Always False)
0001
LT
Less Than
(S XOR V) = 1
0010
LE
Less Than Or Equal To
[Z OR (S XOR V)] = 1
0011
ULE
Unsigned Less Than Or Equal
(C OR Z) = 1
0100
OV
Overflow
V=0
0101
MI
Minus
S=1
0110
EQ
Equal
Z=1
0110
Z
Zero
Z=1
0111
C
Carry
C=1
PS014404-0212
Flags Set
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
53
Table 44. Condition Codes (Continued)
Value
Mnemonic
Definition
Flags Set
0111
ULT
Unsigned Less Than
C=1
1000
Always True
1001
GE
Greater Than Or Equal To
(S XOR V) = 0
1010
GT
Greater Than
[Z OR (S XOR V)] = 0
1011
UGT
Unsigned Greater Than
(C = 0 AND Z = 0) = 1
1100
NOV
No Overflow
V=0
1101
PL
Plus
S=0
1110
NE
Not Equal
Z=0
1110
NZ
Not Zero
Z=0
1111
NC
No Carry
C=0
1111
UGE
Unsigned Greater Than Or Equal To C = 0
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
54
Instruction Formats
Figure 47 shows the one-, two- and three-byte formats used in the Z8 instruction set.
OPC
dst
CCF, DI, EI, IRET, NOP,
RCF, RET, SCF
OPC
One-Byte Instructions
OPC
MODE
dst/src
OR
1110
dst/src
OPC
CLR, CPL, DA, DEC,
DECW, INC, INCW,
POP, PUSH, RL, RLC,
RR, RRC, SRA, SWAP
OPC
MODE
src
OR
1110
src
dst
OR
1110
dst
OR
1110
dst
src
OR
1110
src
dst
OR
1110
dst
ADC, ADD, AND, CP
LD, OR, SBC, SUB,
TCM, TM, XOR
JP, CALL (Indirect)
dst
OR
1110
OPC
dst
MODE
dst
OPC
ADC, ADD, AND, CP
LD, OR, SBC, SUB,
TCM, TM, XOR
VALUE
SRP
VALUE
MODE
OPC
MODE
dst
src
MODE
OPC
dst/src
src/dst
OPC
ADC, ADD, AND, CP,
OR, SBC, SUB, TCM,
TM, XOR
LD, LDE, LDEI,
LDC, LDCI
MODE
OPC
dst/src
X
LD
LD
ADDRESS
OPC
dst/src
src/dst
LD
OR
1110
src
OPC
CC
JP
DAU
dst
DAL
OPC
LD
OPC
DJNZ, JR
VALUE
OPC
dst/CC
DAL
RA
FFH
6FH
CALL
DAU
STOP/HALT
7FH
Two-Byte Instructions
Three-Byte Instructions
Figure 47. Instruction Formats
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
55
Instruction Summary
Table 45 summarizes each Z8 instruction by its operation, addressing mode, operation
code, and the flag(s) each instruction affects.
Table 45. Instruction Summary
Address Mode
Instruction and Operation
dst
src
Flags Affected
Op Code Byte
(Hex)
C
Z
S
V
D
H
ADC dst, src
dst ← dst + src + C
See Note 1
1[]
*
*
*
*
0
*
ADD dst, src
dst ← dst + src
See Note 1
0[]
*
*
*
*
0
*
AND dst, src
dst ← dst AND src
See Note 1
5[]
–
*
*
0
–
–
DA
IRR
06
D4
–
–
–
–
–
–
EF
*
–
–
–
–
–
CALL dst
SP ← SP – 2 @ SP ← PC,
PC ← dst
CCF
C ← NOT C
CLR dst
dst ← 0
R
IR
B0
B11
–
–
–
–
–
–
COM dst
dst ← NOT dst
R
IR
60
61
–
*
*
0
–
–
See Note 1
A[]
*
*
*
*
–
–
DA dst
dst ← DA dst
R
IR
40
41
*
*
*
X
–
–
DEC dst
dst ← dst – 1
R
IR
00
01
–
*
*
*
–
–
DECW dst
dst ← dst – 1
R
IR
80
81
–
*
*
*
–
–
8F
–
–
–
–
–
–
CP dst, src
dst – src
DI
IMR(7) ← 0
Note: These instructions have an identical set of addressing modes, which are encoded for brevity. The first Op Code
nibble is found in this instruction set table. The second nibble is expressed symbolically by a ’[ ]’ in this table,
and its value is found on the left of the applicable addressing mode pair in the Op Code Map in Figure 48.
For example, the op code of an ADC instruction using the addressing modes r (destination) and Ir (source) is 13.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
56
Table 45. Instruction Summary (Continued)
Address Mode
Instruction and Operation
dst
DJNZ r, dst
r ← r – 1
if r ≠ 0
PC ← PC + dst
Range: +127, –128
RA
Flags Affected
C
Z
S
V
D
H
rA
r=0–F
–
–
–
–
–
–
EI
IRM(7) ← 1
BF
*
*
*
*
*
*
HALT
7F
–
–
–
–
–
–
–
*
*
*
–
–
R
IR
rE
r=0–F
20
21
RR
IR
A0
A1
–
*
*
*
–
–
BF
*
*
*
*
*
*
cD
c=0–F
30
–
–
–
–
–
–
cB
c=0–F
–
–
–
–
–
–
INC dst
dst ← dst + 1
INCW dst
dst ← dst + 1
r
IRET
FLAGS ← @SP;
SP ← SP + 1
PC ← @SP;
SP ← SP + 2;
IMR(7) ← 1
JP cc, dst
if cc is true,
PC ← dst
JR cc, dst
if cc is true,
PC ← PC + dst
Range: +127, –128
DA
IRR
RA
src
Op Code Byte
(Hex)
Note: These instructions have an identical set of addressing modes, which are encoded for brevity. The first Op Code
nibble is found in this instruction set table. The second nibble is expressed symbolically by a ’[ ]’ in this table,
and its value is found on the left of the applicable addressing mode pair in the Op Code Map in Figure 48.
For example, the op code of an ADC instruction using the addressing modes r (destination) and Ir (source) is 13.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
57
Table 45. Instruction Summary (Continued)
Address Mode
Instruction and Operation
dst
src
r
r
R
Im
R
r
r
X
r
Ir
R
R
R
IR
IR
LDC dst, src
dst ← src
LDCI dst, src
dst ← src
r ← r + 1;
rr ← rr + 1
Op Code Byte
(Hex)
Flags Affected
C
Z
S
V
D
H
–
–
–
–
–
–
X
r
Ir
r
R
IR
IM
IM
R
rC
r8
r9
r=0–F
C7
D7
E3
F3
E4
E5
E6
E7
F5
r
Irr
C2
–
–
–
–
–
–
Ir
Irr
C3
–
–
–
–
–
–
FF
–
–
–
–
–
–
See Note 1
4[ 1
–
*
*
0
–
–
POP
dst ← @SP;
SP ← SP + 1
R
IR
50
51
–
–
–
–
–
–
PUSH src
SP ← SP – 1;
@SP ← src
R
IR
70
71
–
–
–
–
–
–
RCF
C←0
CF
0
–
–
–
–
–
RET
PC ← @SP;
SP ← SP + 2
AF
–
–
–
–
–
–
90
91
*
*
*
*
–
–
LD dst, src
dst ← src
NOP
OR dst, src
dst ← dst OR src
RL dst
R
IR
Note: These instructions have an identical set of addressing modes, which are encoded for brevity. The first Op Code
nibble is found in this instruction set table. The second nibble is expressed symbolically by a ’[ ]’ in this table,
and its value is found on the left of the applicable addressing mode pair in the Op Code Map in Figure 48.
For example, the op code of an ADC instruction using the addressing modes r (destination) and Ir (source) is 13.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
58
Table 45. Instruction Summary (Continued)
Address Mode
Instruction and Operation
dst
RLC dst
R
IR
RR dst
RRC dst
SBC dst, src
dst ← dst ← src ← C
Flags Affected
C
Z
S
V
D
H
10
11
*
*
*
*
–
–
R
IR
E0
E1
*
*
*
*
–
–
R
IR
C0
C1
*
*
*
*
–
–
See Note 1
3[]
*
*
*
*
1
*
DF
1
–
–
–
–
–
SCF
C←1
src
Op Code Byte
(Hex)
SRA dst
R
IR
D0
D1
*
*
*
0
–
–
SRP dst
RP ← src
Im
31
–
–
–
–
–
–
6F
1
–
–
–
–
–
See Note 1
2[ ]
[
[
[
[
1
[
R
IR
F0
F1
X
*
*
X
–
–
TCM dst, src
(NOT dst)
AND src
See Note 1
6[ ]
–
*
*
0
–
–
TM dst, src
dst AND src
See Note 1
7[ ]
–
*
*
0
–
–
XOR dst, src
dst ← dst
XOR src
See Note 1
B[ ]
–
*
*
0
–
–
STOP
SUB dst, src
dst ← dst ← src
SWAP dst
Note: These instructions have an identical set of addressing modes, which are encoded for brevity. The first Op Code
nibble is found in this instruction set table. The second nibble is expressed symbolically by a ’[ ]’ in this table,
and its value is found on the left of the applicable addressing mode pair in the Op Code Map in Figure 48.
For example, the op code of an ADC instruction using the addressing modes r (destination) and Ir (source) is 13.
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
59
Op Code Map
Figure 48 shows a map of the Z86E61/Z86E63 MCU’s operational codes.
Lower Nibble (Hex)
0
0
1
2
3
4
Upper Nibble (Hex)
5
6
7
8
9
A
B
C
D
E
F
1
6.6
6.5
DEC
DEC
R1
IR1
6.5
6.5
RLC
RLC
R1
IR1
6.5
6.6
INC
WC
R1
IR1
6.5
6.1
JP
SRP
IRR1
1M
8.5
8.5
DA
DA
R1
IR1
10.5
10.5
POP
POP
R1
IR1
6.5
6.5
COM
COM
R1
IR1
10/12.1 10/12.1
PUSH
PUSH
R2
IR2
10.5
10.5
DECW DECW
RR1
IR1
6.5
6.5
RL
RL
R1
IR1
10.5
10.5
INCW
INCW
RR1
IR1
6.5
6.5
CLR
CLR
R1
IR1
6.5
6.5
RRC
RRC
R1
IR1
6.5
6.5
SRA
SRA
R1
IR1
6.5
6.5
RR
RR
R1
IR1
8.5
8.5
SWAP SWAP
R1
IR1
2
3
4
5
6
7
8
9
A
B
C
D
E
6.5
ADD
r1, r2
6.5
ADC
r1, r2
6.5
SUB
r1, r2
6.5
SBC
r1, r2
6.5
OR
r1, r2
6.5
AND
r1, r2
6.5
TCM
r1, r2
6.5
TM
r1, r2
12.0
LDE
r1, Irr2
12.0
LDE
r1, Irr2
6.5
CP
r1, r2
6.5
XOR
r1, r2
12.0
LDC
r1, Irr2
12.0
LDC
r1, Irr2
8.5
ADD
r1, Ir2
6.5
ADC
r1, Ir2
0.5
SUB
r1, Ir2
6.5
OR
r1, Ir2
6.5
OR
r1, Ir2
6.5
AND
r1, Ir2
6.5
TCM
r1, Ir2
6.5
TM
r1, Ir2
18.0
LDEI
r1, Irr2
18.0
LDEI
r1, Irr2
6.5
CP
r1, Ir2
6.5
XOR
r1, Ir2
18.0
LDC
Ir1, Irr2
18.0
LDCI
Ir1, Irr2
6.5
LD
r1, IR2
6.5
LD
Ir1, r2
10.5
ADD
R2,R1
10.5
ADC
R2, R1
10.5
SUB
R2, R1
10.5
SBC
R2, R1
10.5
OR
R2, R1
10.5
AND
R2, R1
10.5
TCM
R2, R1
10.5
TM
R2, R1
10.5
ADD
IR2, R1
10.5
ADC
IR2, R1
10.5
SUB
IR2, R1
10.5
SBC
IR2, R1
10.5
OR
IR2, R1
10.5
AND
IR2, R1
10.5
TCM
IR2, R1
10.5
TM
IR2, R1
10.5
ADD
R1, 1M
10.5
ADC
R1, 1M
10.5
SUB
R2, 1M
10.5
SBC
R1, 1M
10.5
OR
R1, 1M
10.5
AND
R1, 1M
10.5
TCM
R1, 1M
10.5
TM
R1, 1M
10.5
ADD
R1, 1M
10.5
ADC
R1, 1M
10.5
BUB
IR1, 1M
10.5
SBC
IR1, 1M
6.5
LD
r1, R2
6.5
LD
r2, R1
12/10.5
DJNZ
r1, RA
12/0.0
JA
cc, RA
6.5
LD
r1, 1M
12/10.0
JP
cc, DA
6.5
INC
r1
10.5
CP
R2, R1
10.5
XOR
R2, R1
20.0
CALL*
IRR1
10.5
LD
R2, R1
10.5
CP
IR2, R1
10.5
XOR
R2, R1
First
Operand
10.5
CP
R1, R2
7.0
HALT
10.5
10.5
CP
CP
R1, 1M IR1, 1M
10.5
10.5
XOR
XOR
R1, 1M IR1, 1M
10.5
LD
r1, x, R2
20.0
10.5
CALL
LD
DA
42, x, R1
10.5
10.5
LD
LD
R1, 1M IR1, 1M
10.5
LD
IR2, R1
10.5
LD
R2, IR1
Lower
Op Code
Nibble
A
6.0
STOP
6.1
EI
Pipeline
Cycles
Mnemonic
14.0
RET
16.0
IRET
6.5
RCF
6.5
SCF
6.5
CCF
6.0
NOP
3
4
Upper
Op Code
Nibble
10.5
TCM
IR1, 1M
10.5
TCM
IR1, 1M
10.5
TM
IR1, 1M
6.1
DI
2
Execution
Cycles
F
2
3
1
Bytes per instruction
Legend:
R = 8-bit address
r = 4-bit address
R1 or r1 = dst address
R2 or r2 = src address
Sequence:
Op code, first operand, second operand
Note: *The 2-byte instruction appears as a 3-byte instruction; blank
areas are not defined.
Second
Operand
Figure 48. Op Code Map
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
60
Packaging
Zilog’s Z86E61 and Z86E63 MCUs are available in the following packages:
•
•
•
40-pin Plastic Dual Inline Package (PDIP)
44-pin Low-Profile Quad Flat Package (LQFP)
44-pin Plastic Chip Carrier (PLCC)
Current diagrams for each of these packages are published in Zilog’s Packaging Product
Specification (PS0072), which is available free for download from the Zilog website.
Ordering Information
Order your Z86E61/Z86E63 MCU products from Zilog using the part numbers shown in
Table 46. For more information about ordering, please consult your local Zilog sales
office. The Sales Location page on the Zilog website lists all regional offices.
Table 46. Z86E61/Z86E63 MCU Ordering Matrix
Frequency Package
Temperature
Range
Z86E6116PSG
16 MHz
40-pin PDIP
0°C to +70°C
Z86E6116VSG
16 MHz
44-pin PLCC
0°C to +70°C
Z86E6116ASG
16 MHz
44-pin LQFP
0°C to +70°C
Z86E6120PSG
20 MHz
40-pin PDIP
0°C to +70°C
Z86E6120VSG
20 MHz
44-pin PLCC
0°C to +70°C
Z86E6120ASG
20 MHz
44-pin LQFP
0°C to +70°C
Z86E6316PSG
16 MHz
40-pin PDIP
0°C to +70°C
Z86E6316VSG
16 MHz
44-pin PLCC
0°C to +70°C
Z86E6316ASG
16 MHz
44-pin LQFP
0°C to +70°C
Z86E6320PSG
20 MHz
40-pin PDIP
0°C to +70°C
Z86E6320VSG
20 MHz
44-pin PLCC
0°C to +70°C
Z86E6320ASG
20 MHz
44-pin LQFP
0°C to +70°C
Part Number
Z86E61 MCU
Z86E63 MCU
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
61
Part Number Suffix Designations
Zilog part numbers consist of a number of components. For the Z86E61/Z86E63 MCU,
these components are:
Environmental Flow
G = Lead-Free Packaging
Temperature Range
S = 0ºC to +70ºC
Package
P = 40-pin Plastic DIP (PDIP)
V = 44-pin Plastic Chip Carrier (PLCC)
A = 44-pin Low-Profile Quad Flat Package (LQFP)
Frequency
16 = 16 MHz
20 = 20 MHz
Memory Type
E = One-Time-Programmable EPROM
Example. Part number Z86E6116PSC is an 8-bit Z8-powered MCU operating at a
16 MHz frequency in a 40-pin PDIP package, operating within a 0ºC to +70ºC temperature
range and built using lead-free solder.
Z86
E
61
16
P
S
G
Environmental Flow
G = Lead-Free Packaging
Temperature Range
S = Standard, 0°C to +70°C
Package
P = 40-pin PDIP
Frequency
16 = 16 MHz
Unique Zilog Device Type
Memory Type
E = One-Time-Programmable EPROM
Device Family
Z86 = Zilog’s 8-bit Z8 MCU
PS014404-0212
Pin Functions
Z86E61/Z86E63 Microcontrollers
Product Specification
62
Customer Support
To share comments, get your technical questions answered, or report issues you may be
experiencing with our products, please visit Zilog’s Technical Support page at
http://support.zilog.com.
To learn more about this product, find additional documentation, or to discover other facets about Zilog product offerings, please visit the Zilog Knowledge Base at http://
zilog.com/kb or consider participating in the Zilog Forum at http://zilog.com/forum.
This publication is subject to replacement by a later edition. To determine whether a later
edition exists, please visit the Zilog website at http://www.zilog.com.
PS014404-0212
Pin Functions