74HC30D,652

74HC30; 74HCT30 8-input NAND gate Rev. 7 — 2 December 2015 Product data sheet 1. General description The 74HC30; 74HCT30 is an 8-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits  Complies with JEDEC standard JESD7A  Input levels:  For 74HC30: CMOS level  For 74HCT30: TTL level  ESD protection:  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V  Multiple package options  Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number 74HC30D Package Temperature range Name Description Version 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74HCT30D 74HC30DB 74HCT30DB 74HC30PW 74HCT30PW 74HC30; 74HCT30 Nexperia 8-input NAND gate 4. Functional diagram  $  %  &  '  (  )  *  +     <      PQD Fig 1.  PQD Logic symbol Fig 2. IEC logic symbol $ % & ' < ( PQD ) * + Fig 3. Logic diagram 74HC_HCT30 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 December 2015 © Nexperia B.V. 2017. All rights reserved 2 of 15 74HC30; 74HCT30 Nexperia 8-input NAND gate 5. Pinning information 5.1 Pinning +& +&7 $  %   9&&  QF &   + '   * (   QF )   QF *1'   < DDO Fig 4. Pin configuration SO14 and (T)SSOP14 5.2 Pin description Table 2. Pin description Symbol Pin Description A 1 data input B 2 data input C 3 data input D 4 data input E 5 data input F 6 data input GND 7 ground (0 V) Y 8 data output n.c. 9 not connected n.c. 10 not connected G 11 data input H 12 data input n.c. 13 not connected VCC 14 supply voltage 74HC_HCT30 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 December 2015 © Nexperia B.V. 2017. All rights reserved 3 of 15 74HC30; 74HCT30 Nexperia 8-input NAND gate 6. Functional description Table 3. Function table[1] Input Output A B C D E F G H Y L X X X X X X X H X L X X X X X X H X X L X X X X X H X X X L X X X X H X X X X L X X X H X X X X X L X X H X X X X X X L X H X X X X X X X L H H H H H H H H H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V IO output current 0.5 V < VO < VCC + 0.5 V ICC supply current IGND ground current Tstg storage temperature total power dissipation Ptot Conditions SO14, (T)SSOP14 packages Min Max 0.5 +7 V [1] - 20 mA [1] - 20 mA - 25 mA - 50 mA 50 - mA 65 +150 C - 500 mW [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. Unit For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. 74HC_HCT30 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 December 2015 © Nexperia B.V. 2017. All rights reserved 4 of 15 74HC30; 74HCT30 Nexperia 8-input NAND gate 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC30 Min Typ 74HCT30 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 - +125 40 - +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V 74HC30 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 2.0 - 20 - 40 A 74HC_HCT30 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 December 2015 © Nexperia B.V. 2017. All rights reserved 5 of 15 74HC30; 74HCT30 Nexperia 8-input NAND gate Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter CI 25 C Conditions input capacitance 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 3.5 - - - - - pF 74HCT30 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V VOL II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 A ICC additional supply current per input pin; VI = VCC  2.4 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V - 60 216 - 275 - 294 A CI input capacitance - 3.5 - - - - - pF 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for test circuit see Figure 6. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) VCC = 2.0 V - 41 130 165 195 ns VCC = 4.5 V - 15 26 33 39 ns VCC = 5.0 V; CL = 15 pF - 12 - - - ns - 12 22 28 33 ns VCC = 2.0 V - 19 75 95 110 ns VCC = 4.5 V - 7 15 19 22 ns VCC = 6.0 V - 6 13 16 19 ns 74HC30 tpd propagation delay A, B, C, D, E, F, G, H to Y; see Figure 5 [1] VCC = 6.0 V tt transition time 74HC_HCT30 Product data sheet see Figure 5 [2] All information provided in this document is subject to legal disclaimers. Rev. 7 — 2 December 2015 © Nexperia B.V. 2017. All rights reserved 6 of 15 74HC30; 74HCT30 Nexperia 8-input NAND gate Table 7. Dynamic characteristics …continued GND = 0 V; CL = 50 pF; for test circuit see Figure 6. Symbol Parameter CPD 25 C Conditions power dissipation capacitance [3] per package; VI = GND to VCC 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) - 15 - - - pF - 16 28 35 42 ns 74HCT30 [1] propagation delay A, B, C, D, E, F, G, H to Y; see Figure 5 tpd VCC = 4.5 V VCC = 5.0 V; CL = 15 pF transition time tt power dissipation capacitance CPD [1] - 12 - - - ns VCC = 4.5 V; see Figure 5 [2] - 7 15 19 22 ns per package; VI = GND to VCC  1.5 V [3] - 15 - - - pF tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD  VCC2  fi  N +  (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching;  (CL  VCC2  fo) = sum of outputs. 11. Waveforms 9, $%&' ()*+ LQSXW *1' 90 W3+/ 92+ W3/+ 9< 90 Q