74LVC2G02DC-Q100H

74LVC2G02-Q100 Dual 2-input NOR gate Rev. 2 — 13 December 2016 Product data sheet 1. General description The 74LVC2G02-Q100 provides a 2-input NOR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Wide supply voltage range from 1.65 V to 5.5 V  5 V tolerant outputs for interfacing with 5 V logic  High noise immunity  24 mA output drive (VCC = 3.0 V)  CMOS low power consumption  Complies with JEDEC standard:  JESD8-7 (1.65 V to 1.95 V)  JESD8-5 (2.3 V to 2.7 V)  JESD8-B/JESD36 (2.7 V to 3.6 V)  Latch-up performance exceeds 250 mA  Direct interface with TTL levels  Inputs accept voltages up to 5 V  ESD protection:  MIL-STD-883, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )  Multiple package options 74LVC2G02-Q100 Nexperia Dual 2-input NOR gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC2G02DP-Q100 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC2G02DC-Q100 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 4. Marking Table 2. Marking codes Type number Marking code[1] 74LVC2G02DP-Q100 V02 74LVC2G02DC-Q100 V02 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram  $ < % % $  < % < $ DDK Fig 1. Logic symbol PQD DDK Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 6. Pinning information 6.1 Pinning /9&*4 $   9&& %   < <   % *1'   $ DDD Fig 4. Pin configuration SOT505-2 and SOT765-1 74LVC2G02_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 December 2016 © Nexperia B.V. 2017. All rights reserved 2 of 13 74LVC2G02-Q100 Nexperia Dual 2-input NOR gate 6.2 Pin description Table 3. Pin description Symbol Pin Description 1A, 2A 1, 5 data input 1B, 2B 2, 6 data input GND 4 ground (0 V) 1Y, 2Y 7, 3 data output VCC 8 supply voltage 7. Functional description Table 4. Function table[1] Input Output nA nB nY L L H X H L H X L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage [1] output voltage VO Conditions Min Max Unit 0.5 +6.5 V 0.5 +6.5 V [1] 0.5 VCC + 0.5 V [1][2] 0.5 +6.5 V Active mode Power-down mode IIK input clamping current VI < 0 V 50 - mA IOK output clamping current VO < 0 V or VO > VCC - 50 mA IO output current VO = 0 V to VCC - 50 mA ICC supply current - 100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 300 mW Tamb = 40 C to +125 C [3] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal condition. [3] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K. 74LVC2G02_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 December 2016 © Nexperia B.V. 2017. All rights reserved 3 of 13 74LVC2G02-Q100 Nexperia Dual 2-input NOR gate 9. Recommended operating conditions Table 6. Operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Tamb ambient temperature t/V input transition rise and fall rate Min Max Unit 1.65 5.5 V 0 5.5 V Active mode 0 VCC V Power-down mode 0 5.5 V 40 +125 C VCC = 1.65 V to 2.7 V - 20 ns/V VCC = 2.7 V to 5.5 V - 10 ns/V 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max 0.65  VCC - - V Unit Tamb = 40 C to +85 C VIH VIL VOH HIGH-level input voltage LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7  VCC - - V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3  VCC V HIGH-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V VOL 0.35  VCC V LOW-level output voltage VCC  0.1 - - V IO = 4 mA; VCC = 1.65 V 1.2 1.53 - V IO = 8 mA; VCC = 2.3 V 1.9 2.13 - V IO = 12 mA; VCC = 2.7 V 2.2 2.50 - V IO = 24 mA; VCC = 3.0 V 2.3 2.60 - V IO = 32 mA; VCC = 4.5 V 3.8 4.10 - V - - 0.1 V VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V 74LVC2G02_Q100 Product data sheet IO = 4 mA; VCC = 1.65 V - 0.08 0.45 V IO = 8 mA; VCC = 2.3 V - 0.14 0.3 V IO = 12 mA; VCC = 2.7 V - 0.19 0.4 V IO = 24 mA; VCC = 3.0 V - 0.37 0.55 V IO = 32 mA; VCC = 4.5 V - 0.43 0.55 V All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 December 2016 © Nexperia B.V. 2017. All rights reserved 4 of 13 74LVC2G02-Q100 Nexperia Dual 2-input NOR gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Min Typ[1] Max VI = 5.5 V or GND; VCC = 0 V to 5.5 V - 0.1 1 A power-off leakage current VI or VO = 5.5 V; VCC = 0 V - 0.1 2 A ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - 0.1 4 A ICC additional supply current per pin; VI = VCC  0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 A CI input capacitance - 2.5 - pF 0.65  VCC - - V 1.7 - - V Symbol Parameter Conditions II input leakage current IOFF Unit Tamb = 40 C to +125 C HIGH-level input voltage VIH VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V LOW-level input voltage VIL VOH VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7  VCC - - V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3  VCC V VCC  0.1 - - V 0.7 V HIGH-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V LOW-level output voltage VOL 0.35  VCC V IO = 4 mA; VCC = 1.65 V 0.95 - - V IO = 8 mA; VCC = 2.3 V 1.7 - - V IO = 12 mA; VCC = 2.7 V 1.9 - - V IO = 24 mA; VCC = 3.0 V 2.0 - - V IO = 32 mA; VCC = 4.5 V 3.4 - - V IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.1 V IO = 4 mA; VCC = 1.65 V - - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.80 V IO = 32 mA; VCC = 4.5 V - - 0.80 V VI = VIH or VIL II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V - - 1 A IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - 2 A ICC supply current VI = 5.5 V or GND; VCC = 1.65 V to 5.5 V; IO = 0 A - - 4 A ICC additional supply current per pin; VI = VCC  0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - - 500 A [1] All typical values are measured at Tamb = 25 C. 74LVC2G02_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 13 December 2016 © Nexperia B.V. 2017. All rights reserved 5 of 13 74LVC2G02-Q100 Nexperia Dual 2-input NOR gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground 0 V); for test circuit see Figure 6. Symbol Parameter 40 C to +85 C Conditions Min Max Min Max VCC = 1.65 V to 1.95 V 1.2 3.8 8.9 1.2 11.2 ns VCC = 2.3 V to 2.7 V 0.8 2.4 5.4 0.8 6.8 ns VCC = 2.7 V 0.8 3.2 6.0 0.8 7.5 ns VCC = 3.0 V to 3.6 V 0.6 2.4 4.9 0.6 6.2 ns VCC = 4.5 V to 5.5 V 0.6 1.8 4.3 0.6 5.5 ns - 14 - - - pF [2] propagation delay nA, nB to nY; see Figure 5 tpd power dissipation capacitance CPD [3] per gate; VI = GND to VCC [1] Typical values are measured at nominal VCC and at Tamb = 25 C. [2] tpd is the same as tPLH and tPHL. [3] 40 C to +125 C Unit Typ[1] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL  VCC2  fo) = sum of outputs. 12. Waveforms 9, 90 Q$Q%LQSXW *1' W 3+/ W 3/+ 92+ Q