XD74LS165

XD74LS165 DIP-16 XL74LS165 SOP16 D D D D Complementary Outputs Direct Overriding Load (Data) Inputs Gated Clock Inputs Parallel-to-Serial Data Conversion TYPE 74LS165 TYPICAL MAXIMUM CLOCK FREQUENCY 35 MHz 74LS165 (TOP VIEW) TYPICAL POWER DISSIPATION SH/LD CLK E F G H QH GND 90 mW description 74LS165 are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. These registers also feature gated clock (CLK) inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design. Clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with SH/LD high enables the other clock input. Clock inhibit (CLK INH) should be changed to the high level only while CLK is high. Parallel loading is inhibited as long as SH/LD is high. Data at the parallel inputs are loaded directly into the register while SH/LD is low, independently of the levels of CLK, CLK INH, or serial (SER) inputs. 1 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC CLK INH D C B A SER QH XD74LS165 DIP-16 XL74LS165 SOP16 ORDERING INFORMATION ORDERABLE PART NUMBER PACKAGE† TA DIP 0°C to 70°C SOP Tube XD74LS165 Tube XL74LS165 Tape and reel XL74LS165 TOP-SIDE MARKING XD74LS165 XL74LS165 FUNCTION TABLE INTERNAL OUTPUTS INPUTS SH/LD CLK INH CLK SER PARALLEL A...H QA QB OUTPUT QH L X X X a...h a b h H L L X X QA0 QB0 QH0 H L ↑ H X H QAn QGn H L ↑ L X L QAn QGn H H X X X QA0 QB0 QH0 schematics of inputs and outputs 74LS165 EQUIVALENT OF PARALLEL INPUTS AND SERIAL INPUT EQUIVALENT OF ALL OTHER INPUTS VCC Req TYPICAL OF BOTH OUTPUTS VCC 120 Ω NOM 24 kΩ NOM Input Input Output CLK, CLK INH: Req = 10 kΩ NOM SH/LD: Req = 13 kΩ NOM 2 XD74LS165 DIP-16 XL74LS165 SOP16 logic diagram (positive logic) A SH/LD CLK INH CLK SER B 11 1 C 12 D 13 E 14 G F 3 4 H 5 6 15 2 S C1 1D R 10 QA S C1 1D R QB S C1 1D R QC S C1 1D R QD S C1 1D R QE S C1 1D R S C1 1D R QF Pin numbers shown are for D, J, N, NS, and W packages. typical shift, load, and inhibit sequences CLK CLK INH SER L SH/LD Data Inputs A H B L C H D L E H F L G H H H Output QH H H L H L H L H Output QH L L H L H L H L Inhibit Serial Shift Load 3 QG S C1 1D R 9 7 QH QH XD74LS165 DIP-16 XL74LS165 SOP16 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI: 74LS165 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Interemitter voltage (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Package thermal impedance θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values, except interemitter voltage, are with respect to network ground terminal. 2. This is the voltage between two emitters of a multiple-emitter transistor. This rating applies for the ’165 to the SH/LD input in conjunction with the CLK INH input. 3. The package thermal impedance is calculated in accordance with JESD 51-7. 4 XD74LS165 DIP-16 XL74LS165 SOP16 recommended operating conditions 74LS165 MIN NOM MAX 4.75 5 5.25 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage IOL fclock Low-level output current tw(clock) ( l k) Width of clock input pulse tw(load) (l d) Width of load input pulse tsu tsu Clock-enable setup time 30 ns Parallel input setup time 10 ns tsu tsu Serial input setup time 20 ns Shift setup time 45 ns th TA Hold time at any input 0 Operating free-air temperature 0 High-level input voltage 2 V High-level output current Clock frequency 0 Clock high 15 Clock low 25 Clock high 25 Clock low 17 V 0.8 V –0.4 mA 8 mA 25 MHz ns ns ns 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) 74LS165 TEST CONDITIONS† PARAMETER MIN TYP‡ 2.7 3.5 MAX VIK VOH VCC = MIN, VCC = MIN, II = –18 mA VIH = 2 V, VIL = MAX, VOL VCC = MIN MIN, VIH = 2 V, V II IIH VCC = MAX, VCC = MAX, VI = 7 V VI = 2.7 V 0.1 20 µA IIL IOS§ VCC = MAX, VCC = MAX VI = 0.4 V –0.4 mA –100 mA VIL = MAX –1.5 UNIT IOH = –0.4 mA IOL = 4 mA IOL = 8 mA –20 V V 0.25 0.4 0.35 0.5 V mA ICC VCC = MAX, 18 30 mA NOTE 4. With the outputs open, CLK INH and CLK at 4.5 V, and a clock pulse applied to SH/LD, ICC is measured first with the parallel inputs at 4.5 V, then with the parallel inputs grounded. † For conditions shown as MIN or MAX, use the appropriate values specified under recommended operating conditions. ‡ All typical values are at VCC = 5 V, TA = 25°C. § Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. 5 XD74LS165 DIP-16 XL74LS165 SOP16 74LS165 switching characteristics, V CC = 5 V, TA = 25°C PARAMETER† fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP 25 35 MAX UNIT MHz LD Any RL = 2 kW, CL = 15 pF 21 35 26 35 CLK Any RL = 2 kW, CL = 15 pF 14 25 16 25 H QH RL = 2 kW, CL = 15 pF 13 25 24 30 H QH RL = 2 kW, CL = 15 pF 19 30 17 25 ns ns ns ns † fmax = maximum clock frequency, tPLH = propagation delay time, low-to-high-level output, tPHL = propagation delay time, high-to-low-level output 6 XD74LS165 DIP-16 XL74LS165 SOP16 PARAMETER MEASUREMENT INFORMATION VCC Test Point VCC RL (see Note B) From Output Under Test CL (see Note A) LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS High-Level Pulse 1.5 V 1 kΩ Test Point S2 LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.5 V S1 (see Note B) CL (see Note A) RL CL (see Note A) RL From Output Under Test VCC From Output Under Test Test Point 1.5 V 0V tw Low-Level Pulse 1.5 V tsu Data Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATIONS 1.5 V 0V In-Phase Output (see Note D) 1.5 V 1.5 V tPLZ VOL tPZH Waveform 2 (see Notes C and D) VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ≈1.5 V 1.5 V VOL tPLH 1.5 V 0V Waveform 1 (see Notes C and D) VOH tPHL Out-of-Phase Output (see Note D) 0V tPZL tPHL 1.5 V 1.5 V 3V Output Control (low-level enabling) 1.5 V tPLH 3V 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input th VOL + 0.5 V tPHZ VOH 1.5 V VOH – 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series 74LS165 devices and tr and tf ≤ 2.5 ns for Series 74LS165 devices. F. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 7 XD74LS165 DIP-16 XL74LS165 SOP16 PARAMETER MEASUREMENT INFORMATION VCC Test Point VCC RL From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS High-Level Pulse 1.3 V S1 (see Note B) CL (see Note A) RL (see Note B) RL From Output Under Test VCC From Output Under Test Test Point 5 kΩ Test Point S2 LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V Timing Input 1.3 V 1.3 V 0V tw Low-Level Pulse 1.3 V tsu Data Input 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS 1.3 V 1.3 V Output Control (low-level enabling) 0V tPLH In-Phase Output (see Note D) 1.3 V 0V 3V 1.3 V 1.3 V 0V tPZL tPLZ tPHL VOH 1.3 V 1.3 V Waveform 1 (see Notes C and D) VOL tPZH tPLH VOH 1.3 V 1.3 V VOL Waveform 2 (see Notes C and D) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ≈1.5 V 1.3 V VOL tPHL Out-of-Phase Output (see Note D) 3V 1.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input th VOL + 0.5 V tPHZ VOH 1.3 V VOH – 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time with one input transition per measurement. Figure 2. Load Circuits and Voltage Waveforms 8 XD74LS165 DIP-16 XL74LS165 SOP16 DIP 89 XD74LS165 DIP-16 XL74LS165 SOP16 SOP 10