XD232

XL232Z SOP窄体16 XL232K SOP宽体16 XD232 DIP-16 1 Features 3 Description • The XD232 device is a dual driver/receiver that includes a capacitive voltage generator to supply TIA/EIA-232-F voltage levels from a single 5-V supply. Each receiver converts TIA/EIA-232-F inputs to 5-V TTL/CMOS levels. These receivers have a typical threshold of 1.3 V, a typical hysteresis of 0.5 V, and can accept ±30-V inputs. Each driver converts TTL/CMOS input levels into TIA/EIA-232-F levels. 1 • • • • • • • Meets or Exceeds TIA/EIA-232-F and ITU Recommendation V.28 Operates From a Single 5-V Power Supply With 1.0-µF Charge-Pump Capacitors Operates up to 120 kbit/s Two Drivers and Two Receivers ±30-V Input Levels Low Supply Current: 8 mA Typical ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) Upgrade With Improved ESD (15-kV HBM) and 0.1-µF Charge-Pump Capacitors is Available With the 202 Device 5 Device Information(1) ORDER NUMBER XD/L232x 2 Applications • • • • • TIA/EIA-232-F Battery-Powered Systems Terminals Modems Computers 4 Simplified Schematic 5V POWER 2 2 TOUT RS232 2 RIN RS232 TX TIN 2 ROUT RX 1 1 PACKAGE (PIN) BODY SIZE SOP窄体16 9.90 mm × 3.91 mm SOP宽体16 10.30 mm × 7.50 mm DIP16 19.30 mm × 6.35 mm XL232Z SOP窄体16 XL232K SOP宽体16 XD232 DIP-16 6 Pin Configuration and Functions C1+ VS+ C1− C2+ C2− VS− T2OUT R2IN 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC GND T1OUT R1IN R1OUT T1IN T2IN R2OUT Pin Functions PIN NAME NO. C1+ 1 VS+ C1- TYPE DESCRIPTION — Positive lead of C1 capacitor 2 O Positive charge pump output for storage capacitor only 3 — Negative lead of C1 capacitor C2+ 4 — Positive lead of C2 capacitor C2- 5 — Negative lead of C2 capacitor VS- 6 O Negative charge pump output for storage capacitor only T2OUT, T1OUT 7, 14 O RS232 line data output (to remote RS232 system) R2IN, R1IN 8, 13 I RS232 line data input (from remote RS232 system) R2OUT, R1OUT 9, 12 O Logic data output (to UART) T2IN, T1IN 10, 11 I Logic data input (from UART) GND 15 — Ground VCC 16 — Supply Voltage, Connect to external 5V power supply 2 XL232Z SOP窄体16 XL232K SOP宽体16 XD232 DIP-16 7 Specifications 7.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC Input Supply voltage range (2) VS+ Positive output supply voltage range VS– Negative output supply voltage range VI Input voltage range VO Output voltage range (1) (2) MAX 6 V VCC – 0.3 15 V –0.3 –15 V –0.3 VCC + 0.3 T1IN, T2IN R1IN, R2IN Short-circuit duration TJ MIN –0.3 UNIT V ±30 T1OUT, T2OUT VS– – 0.3 VS+ + 0.3 R1OUT, R2OUT –0.3 VCC + 0.3 T1OUT, T2OUT V Unlimited Operating virtual junction temperature 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to network GND. 7.2 Handling Ratings Tstg V(ESD) (1) (2) MIN MAX UNIT -65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 0 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 0 1000 Storage temperature range Electrostatic discharge V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions MIN NOM MAX 4.5 5 5.5 UNIT VCC Supply voltage VIH High-level input voltage (T1IN,T2IN) VIL Low-level input voltage (T1IN, T2IN) 0.8 V R1IN, R2IN Receiver input voltage ±30 V TA Operating free-air temperature 2 V V XD232 0 70 XL232 –40 85 °C 7.4 Electrical Characteristics –– Device over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 6) TEST CONDITIONS (1) PARAMETER ICC (1) (2) Supply current VCC = 5.5V, all outputs open, TA = 25°C Test conditions are C1–C4 = 1 μF at VCC = 5 V ± 0.5 V All typical values are at VCC = 5 V, and TA = 25°C. 3 MIN TYP (2) MAX 8 10 UNIT mA XL232Z SOP窄体16 XL232K SOP宽体16 XD232 DIP-16 7.5 Electrical Characteristics –– Driver over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS (1) PARAMETER VOH High-level output voltage T1OUT, T2OUT RL = 3 kΩ to GND VOL Low-level output voltage (3) T1OUT, T2OUT RL = 3 kΩ to GND rO Output resistance T1OUT, T2OUT VS+ = VS– = 0, VO = ±2 V IOS (4) Short-circuit output current T1OUT, T2OUT VCC = 5.5 V, VO = 0 V IIS Short-circuit input current T1IN, T2IN VI = 0 (1) (2) (3) (4) MIN TYP (2) 5 MAX 7 –7 UNIT V –5 V Ω 300 ±10 mA 200 µA Test conditions are C1–C4 = 1 μF at VCC = 5 V ± 0.5 V All typical values are at VCC = 5 V, TA = 25°C. The algebraic convention, in which the least-positive (most negative) value is designated minimum, is used in this data sheet for logic voltage levels only. Not more than one output should be shorted at a time. 7.6 Electrical Characteristics –– Receiver over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP (2) MAX High-level output voltage R1OUT, R2OUT IOH = –1 mA VOL Low-level output voltage (3) R1OUT, R2OUT IOL = 3.2 mA VIT+ Receiver positive-going input threshold voltage R1IN, R2IN VCC = 5 V, TA = 25°C VIT– Receiver negative-going input threshold R1IN, R2IN voltage VCC = 5 V, TA = 25°C 0.8 1.2 Vhys Input hysteresis voltage R1IN, R2IN VCC = 5 V 0.2 0.5 1 V rI Receiver input resistance R1IN, R2IN VCC = 5 V, TA = 25°C 3 5 7 kΩ (1) (2) (3) 3.5 UNIT VOH V 1.7 0.4 V 2.4 V V Test conditions are C1–C4 = 1 μF at VCC = 5 V ± 0.5 V. All typical values are at VCC = 5 V, TA = 25°C. The algebraic convention, in which the least-positive (most negative) value is designated minimum, is used in this data sheet for logic voltage levels only. 7.7 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS (1) PARAMETER SR Driver slew rate RL = 3 kΩ to 7 kΩ, see Figure 4 SR(t) Driver transition region slew rate see Figure 5 Data rate tPLH®) tPHL®) (1) MIN TYP (1) MAX UNIT 30 V/μs 3 V/μs One TOUT switching 120 kbit/s Receiver propagation delay time, low- to high-level output TTL load, see Figure 3 500 ns Receiver propagation delay time, high- to low-level output TTL load, see Figure 3 500 ns Test conditions are C1–C4 = 1 μF at VCC = 5 V ± 0.5 V. 4 XL232Z SOP窄体16 XL232K SOP宽体16 XD232 DIP-16 10 9 8 7 6 5 4 3 2 1 0 ±1 ±2 ±3 ±4 ±5 ±6 ±7 ±8 ±9 ±10 ±11 ±12 Voltage (V) Voltage (V) 7.8 Typical Characteristics VOL VOH 1 2 3 4 5 Load resistance (k ) 6 7 12 11 10 9 8 7 6 5 4 3 2 1 0 ±1 ±2 ±3 ±4 ±5 ±6 ±7 ±8 TIN TOUT (to RIN) ROUT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Time (s) C001 Figure 1. TOUT VOH & VOL vs Load Resistance, Both Drivers Loaded C001 Figure 2. Driver to Receiver Loopback Timing Waveform 5 XL232Z SOP窄体16 XL232K SOP宽体16 XD232 DIP-16 8 Parameter Measurement Information VCC Pulse Generator (see Note A) RL = 1.3 kΩ R1OUT or R2OUT R1IN or R2IN See Note C CL = 50 pF (see Note B) TEST CIRCUIT ≤10 ns ≤10 ns Input 10% 90% 50% 90% 50% 3V 10% 0V 500 ns tPLH tPHL VOH Output 1.5 V 1.5 V VOL WAVEFORMS A. The pulse generator has the following characteristics: ZO = 50 Ω, duty cycle ≤ 50%. B. CL includes probe and jig capacitance. C. All diodes are 1N3064 or equivalent. Figure 3. Receiver Test Circuit and Waveforms for tPHL and tPLH Measurements 6 XL232Z SOP窄体16 XL232K SOP宽体16 XD232 DIP-16 Parameter Measurement Information (continued) T1IN or T2IN Pulse Generator (see Note A) T1OUT or T2OUT EIA-232 Output CL = 10 pF (see Note B) RL TEST CIRCUIT ≤10 ns ≤10 ns 90% 50% Input 10% 3V 90% 50% 10% 0V 5 µs tPLH tPHL 90% Output 90% 10% 10% VOH VOL tTLH tTHL 0.8 (V SR = –V ) 0.8 (V –V ) OH OL OL OH or t t TLH THL WAVEFORMS A. The pulse generator has the following characteristics: ZO = 50 Ω, duty cycle ≤ 50%. B. CL includes probe and jig capacitance. Figure 4. Driver Test Circuit and Waveforms for tPHL and tPLH Measurements (5-μs Input) Pulse Generator (see Note A) EIA-232 Output 3 kΩ CL = 2.5 nF TEST CIRCUIT ≤10 ns ≤10 ns Input 90% 1.5 V 10% 90% 1.5 V 10% 20 µs tTLH tTHL Output 3V 3V −3 V −3 V SR = t THL 6V or t VOH VOL TLH WAVEFORMS A. The pulse generator has the following characteristics: ZO = 50 Ω, duty cycle ≤ 50%. Figure 5. Test Circuit and Waveforms for tTHL and tTLH Measurements (20-μs Input) 7 XL232Z SOP窄体16 XL232K SOP宽体16 XD232 DIP-16 9 Detailed Description 9.1 Overview The XD232 device is a dual driver/receiver that includes a capacitive voltage generator using four capacitors to supply TIA/EIA-232-F voltage levels from a single 5-V supply. Each receiver converts TIA/EIA-232-F inputs to 5V TTL/CMOS levels. These receivers have a typical threshold of 1.3 V, a typical hysteresis of 0.5 V, and can accept ±30-V inputs. Each driver converts TTL/CMOS input levels into TIA/EIA-232-F levels. The driver, receiver, and voltage-generator functions are available as cells in the Texas Instruments LinASIC™ library. Outputs are protected against shorts to ground. 9.2 Functional Block Diagram 5V POWER 2 2 TOUT RS232 2 RIN RS232 TX TIN 2 ROUT RX 9.3 Feature Description 9.3.1 Power The power block increases and inverts the 5V supply for the RS232 driver using a charge pump that requires four 1-µF external capacitors. 9.3.2 RS232 Driver Two drivers interface standard logic level to RS232 levels. Internal pull up resistors on TIN inputs ensures a high input when the line is high impedance. 9.3.3 RS232 Receiver Two receivers interface RS232 levels to standard logic levels. An open input will result in a high output on ROUT. 9.4 Device Functional Modes 9.4.1 VCC powered by 5V The device will be in normal operation. 9.4.2 VCC unpowered When XD232 is unpowered, it can be safely connected to an active remote RS232 device. Table 1. Function Table Each Driver (1) (1) INPUT OUTPUT TIN TOUT L H H L H = high level, L = low level, X = irrelevant, Z = high impedance 8 XL232Z SOP窄体16 XL232K SOP宽体16 XD232 DIP-16 Table 2. Function Table Each Receiver (1) (1) INPUTS OUTPUT RIN ROUT L H H L Open H H = high level, L = low level, X = irrelevant, Z = high impedance (off), Open = disconnected input or connected driver off 10 Application and Implementation 10.1 Application Information For proper operation add capacitors as shown in Figure 6. Pins 9 through 12 connect to UART or general purpose logic lines. EIA-232 lines will connect to a connector or cable. 10.2 Typical Application 5V + CBYPASS = 1 µF − 16 1 C1 1 µF 3 4 C2 1 µF 5 From CMOS or TTL To CMOS or TTL C3† VCC C1+ 8.5 V VS+ C1− VS− C2+ 1 µF 2 6 −8.5 V C4 + C2− 11 14 10 7 12 13 9 8 0V 1 µF EIA-232 Output EIA-232 Output EIA-232 Input EIA-232 Input 15 GND † C3 can be connected to VCC or GND. NOTES: A. Resistor values shown are nominal. B. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be e 202 can operate with 0.1-µF capacitors. connected as shown. In addition to the 1-µF capacitors shown, the MAX202 can operate with 0.1-µF capacitors. Figure 6. Typical Operating Circuit 10.2.1 Design Requirements • • VCC minimum is 4.5 V and maximum is 5.5 V. Maximum recommended bit rate is 120 kbps. 10.2.2 Detailed Design Procedure Use 1 uF tantalum or ceramic capacitors. 9 XL232Z SOP窄体16 XL232K SOP宽体16 XD232 DIP-16 Typical Application (continued) 10 9 8 7 6 5 4 3 2 1 0 ±1 ±2 ±3 ±4 ±5 ±6 ±7 ±8 ±9 ±10 ±11 ±12 Voltage (V) Voltage (V) 10.2.3 Application Curves VOL VOH 1 2 3 4 5 6 7 Load resistance (k ) 12 11 10 9 8 7 6 5 4 3 2 1 0 ±1 ±2 ±3 ±4 ±5 ±6 ±7 ±8 TIN TOUT (to RIN) ROUT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Time (s) C001 Figure 7. TOUT VOH & VOL vs Load Resistance, Both Drivers Loaded C001 Figure 8. Driver to Receiver Loopback Timing Waveform 11 Power Supply Recommendations The VCC voltage should be connected to the same power source used for logic device connected to TIN pins. VCC should be between 4.5V and 5.5V. 12 Layout 12.1 Layout Guidelines Keep the external capacitor traces short. This is more important on C1 and C2 nodes that have the fastest rise and fall times. 12.2 Layout Example Ground 1 C1+ VCC 16 1 µF 1 µF 2 VS+ GND 15 3 C1- T1OUT 14 4 C2+ R1IN 13 5 C2- R1OUT 12 6 VS- T1IN 11 7 T2OUT T2IN 10 1 µF Ground 1 µF 8 R2IN R2OUT 9 Figure 9. Layout Schematic 10 VCC 1 µF Ground XL232Z SOP窄体16 XL232K SOP宽体16 XD232 DIP-16 11 10 XL232Z SOP窄体16 XL232K SOP宽体16 XD232 DIP-16 12 10 XL232Z SOP窄体16 XL232K SOP宽体16 XD232 DIP-16 13 10