XD8574P

XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 1. General description The 8574A/PT provides general-purpose remote I/O expansion via the two-wire bidirectional I2C-bus (serial clock (SCL), serial data (SDA)). The devices consist of eight quasi-bidirectional ports, 100 kHz I2C-bus interface, three hardware address inputs and interrupt output operating between 2.5 V and 6 V. The quasi-bidirectional port can be independently assigned as an input to monitor interrupt status or keypads, or as an output to activate indicator devices such as LEDs. System master can read from the input port or write to the output port through a single register. The low current consumption of 2.5 A (typical, static) is great for mobile applications and the latched output ports directly drive LEDs. The 8574A/PT are identical, except for the different fixed portion of the slave address. The three hardware address pins allow eight of each device to be on the same I2C-bus, so there can be up to 16 of these I/O expanders 8574A/PT together on the same I2C-bus, supporting up to 128 I/Os (for example, 128 LEDs). The active LOW open-drain interrupt output (INT) can be connected to the interrupt logic of the microcontroller and is activated when any input state differs from its corresponding input port register state. It is used to indicate to the microcontroller that an input state has changed and the device needs to be interrogated without the microcontroller continuously polling the input register via the I2C-bus. The internal Power-On Reset (POR) initializes the I/Os as inputs with a weak internal pull-up 100 A current source. 2. Features and benefits  I2C-bus to parallel port expander  100 kHz I2C-bus interface (Standard-mode I2C-bus)  Operating supply voltage 2.5 V to 6 V with non-overvoltage tolerant I/O held to VDD with 100 A current source  8-bit remote I/O pins that default to inputs at power-up  Latched outputs directly drive LEDs  Total package sink capability of 80 mA  Active LOW open-drain interrupt output  Eight programmable slave addresses using three address pins  Low standby current (2.5 A typical)  40 C to +85 C operation  ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per 1 XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16  Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA  Packages offered: DIP16, SOP16 3. Applications           LED signs and displays Servers Key pads Industrial control Medical equipment PLC Cellular telephones Mobile devices Gaming machines Instrumentation and test measurement 4. Ordering options Table 1. Ordering options Type number Package Packing method Temperature range XD8574P DIP16 Standard marking * IC’s tube - DSC bulk pack T amb = 40 C to +85 C XD8574AP DIP16 Standard marking * IC’s tube - DSC bulk pack T amb = 40 C to +85 C XL8574T SO16 Standard marking * tube dry pack T amb = 40 C to +85 C SO16 Reel 13” Q1/T1 *standard mark SMD dry pack T amb = 40 C to +85 C SO16 Standard marking * tube dry pack T amb = 40 C to +85 C SO16 Reel 13” Q1/T1 *standard mark SMD dry pack T amb = 40 C to +85 C XL8574AT 2 XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 5. Block diagram 8574A/PT INTERRUPT LOGIC LP FILTER INT A0 A1 A2 SCL SDA I2C-BUS CONTROL INPUT FILTER SHIFT REGISTER 8 bits P0 P1 P2 P3 P4 P5 P6 P7 I/O PORT write pulse read pulse POWER-ON RESET VDD VSS Fig 1. Block diagram write pulse 100 μA IOH VDD Itrt(pu) data from Shift Register D Q FF IOL CI P0 to P7 S power-on reset VSS D Q FF CI read pulse S to interrupt logic data to Shift Register Fig 2. Simplified schematic diagram of P0 to P7 3 XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 6. Pinning information 6.1 Pinning A0 1 16 VDD A1 2 15 SDA A2 3 14 SCL P0 4 P1 5 8574P 8574AP 13 INT 12 P7 P2 6 11 P6 P3 7 10 P5 VSS 8 Fig 3. 9 A0 1 16 VDD A1 2 15 SDA A2 3 P0 4 P1 5 P2 6 11 P6 P3 7 10 P5 VSS 8 9 14 SCL 8574T 8574AT 12 P7 P4 P4 Pin configuration for DIP16 Fig 4. Pin configuration for SO16 6.2 Pin description Table 2. 13 INT Pin description Symbol Pin Description A0 1 6 address input 0 A1 2 7 address input 1 A2 3 9 address input 2 P0 4 10 quasi-bidirectional I/O 0 P1 5 11 quasi-bidirectional I/O 1 P2 6 12 quasi-bidirectional I/O 2 P3 7 14 quasi-bidirectional I/O 3 DIP16, SO16 VSS 8 15 supply ground P4 9 16 quasi-bidirectional I/O 4 P5 10 17 quasi-bidirectional I/O 5 P6 11 19 quasi-bidirectional I/O 6 P7 12 20 quasi-bidirectional I/O 7 INT 13 1 interrupt output (active LOW) SCL 14 2 serial clock line SDA 15 4 serial data line VDD 16 5 supply voltage n.c. - 3, 8, 13, 18 not connected 4 XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 7. Functional description Refer to Figure 1 “Block diagram”. 7.1 Device address Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address format of the 8574A/PT is shown in Figure5 . Slave address pins A2, A1 and A0 are held HIGH or LOW to choose one of eight slave addresses. To conserve power, no internal pull-up resistors are incorporated on A2, A1 or A0, so they must be externally held HIGH or LOW. The address pins (A2, A1, A0) can connect to VDD or VSS directly or through resistors. R/W slave address 0 1 0 0 fixed A2 A1 A0 0 0 hardware selectable 1 1 fixed a. XD8574AP Fig 5. R/W slave address 1 A2 A1 A0 0 hardware selectable b.XD8574P 8574A/PT slave addresses The last bit of the first byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation (write operation is shown in Figure 5). 7.1.1 Address maps The 8574A/PT are functionally the same, but have a different fixed portion (A6 to A3) of the slave address. This allows eight of the XD8574AP and eight of the XD8574P to be on the same I 2C-bus without address conflict. Table 3. 8574A/PT address map Pin connectivity Address of PCF8574 Address byte value Write Read 7-bit hexadecimal address without R/W - 40h 41h 20h 1 - 42h 43h 21h 1 0 - 44h 45h 22h 1 1 - 46h 47h 23h 1 0 0 - 48h 49h 24h 0 1 0 1 - 4Ah 4Bh 25h 0 1 1 0 - 4Ch 4Dh 26h 0 1 1 1 - 4Eh 4Fh 27h A2 A1 A0 A6 A5 A4 A3 A2 A1 VSS VSS VSS 0 1 0 0 0 0 0 VSS VSS VDD 0 1 0 0 0 0 VSS VDD VSS 0 1 0 0 0 VSS VDD VDD 0 1 0 0 0 VDD VSS VSS 0 1 0 0 VDD VSS VDD 0 1 0 VDD VDD VSS 0 1 0 VDD VDD VDD 0 1 0 5 A0 R/W XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 Table 4. 8574A/PT address map Pin connectivity Address of PCF8574A Address byte value Write Read 7-bit hexadecimal address without R/W - 70h 71h 38h 1 - 72h 73h 39h 1 0 - 74h 75h 3Ah 1 1 - 76h 77h 3Bh 1 0 0 - 78h 79h 3Ch 1 1 0 1 - 7Ah 7Bh 3Dh 1 1 1 1 0 - 7Ch 7Dh 3Eh 1 1 1 1 1 - 7Eh 7Fh 3Fh A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 R/W VSS VSS VSS 0 1 1 1 0 0 0 VSS VSS VDD 0 1 1 1 0 0 VSS VDD VSS 0 1 1 1 0 VSS VDD VDD 0 1 1 1 0 VDD VSS VSS 0 1 1 1 VDD VSS VDD 0 1 1 VDD VDD VSS 0 1 VDD VDD VDD 0 1 8. I/O programming 8.1 Quasi-bidirectional I/Os A quasi-bidirectional I/O is an input or output port without using a direction control register. Whenever the master reads the register, the value returned to master depends on the actual voltage or status of the pin. At power on, all the ports are HIGH with a weak 100 A internal pull-up to VDD, but can be driven LOW by an internal transistor, or an external signal. The I/O ports are entirely independent of each other, but each I/O octal is controlled by the same read or write data byte. Advantages of the quasi-bidirectional I/O over totem pole I/O include: • Better for driving LEDs since the p-channel (transistor to VDD) is small, which saves die size and therefore cost. LED drive only requires an internal transistor to ground, while the LED is connected to VDD through a current-limiting resistor. Totem pole I/O have both n-channel and p-channel transistors, which allow solid HIGH and LOW output levels without a pull-up resistor — good for logic levels. • Simpler architecture — only a single register and the I/O can be both input and output at the same time. Totem pole I/O have a direction register that specifies the port pin direction and it is always in that configuration unless the direction is explicitly changed. • Does not require a command byte. The simplicity of one register (no need for the pointer register or, technically, the command byte) is an advantage in some embedded systems where every byte counts because of memory or bandwidth limitations. 6 XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 There is only one register to control four possibilities of the port pin: Input HIGH, input LOW, output HIGH, or output LOW. Input HIGH: The master needs to write 1 to the register to set the port as an input mode if the device is not in the default power-on condition. The master reads the register to check the input status. If the external source pulls the port pin up to VDD or drives logic 1, then the master will read the value of 1. Input LOW: The master needs to write 1 to the register to set the port to input mode if the device is not in the default power-on condition. The master reads the register to check the input status. If the external source pulls the port pin down to VSS or drives logic 0, which sinks the weak 100 A current source, then the master will read the value of 0. Output HIGH: The master writes 1 to the register. There is an additional ‘accelerator’ or strong pull-up current when the master sets the port HIGH. The additional strong pull-up is only active during the HIGH time of the acknowledge clock cycle. This accelerator current helps the port’s 100 A current source make a faster rising edge into a heavily loaded output, but only at the start of the acknowledge clock cycle to avoid bus contention if an external signal is pulling the port LOW to VSS/driving the port with logic 0 at the same time. After the half clock cycle there is only the 100 A current source to hold the port HIGH. Output LOW: The master writes 0 to the register. There is a strong current sink transistor that holds the port pin LOW. A large current may flow into the port, which could potentially damage the part if the master writes a 0 to the register and an external source is pulling the port HIGH at the same time. VDD input HIGH weak 100 µA current source (inactive when output LOW) pull-up with resistor to VDD or external drive HIGH P port P7 - P0 output HIGH accelerator pull-up pull-down with resistor to VSS or external drive LOW output LOW input LOW VSS Fig 6. Simple quasi-bidirectional I/O 7 XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 8.2 Writing to the port (Output mode) The master (microcontroller) sends the START condition and slave address setting the last bit of the address byte to logic 0 for the write mode. The 8574A/PT acknowledges and the master then sends the data byte for P7 to P0 to the port register. As the clock line goes HIGH, the 8-bit data is presented on the port lines after it has been acknowledged by the 8574A/PT. If a LOW is written, the strong pull-down turns on and stays on. If a HIGH is written, the strong pull-up turns on for 1⁄2 of the clock cycle, then the line is held HIGH by the weak current source. The master can then send a STOP or ReSTART condition or continue sending data. The number of data bytes that can be sent successively is not limited and the previous data is overwritten every time a data byte has been sent and acknowledged. Ensure a logic 1 is written for any port that is being used as an input to ensure the strong external pull-down is turned off. SCL 1 2 3 4 5 6 7 8 9 slave address data 1 SDA S A6 A5 A4 A3 A2 A1 A0 0 START condition R/W data 2 A P7 P6 1 P4 P3 P2 P1 P0 A P7 P6 0 P4 P3 P2 P1 P0 A P5 acknowledge from slave P5 acknowledge from slave acknowledge from slave write to port tv(Q) data output from port tv(Q) DATA 1 VALID DATA 2 VALID P5 output voltage Itrt(pu) P5 pull-up output current IOH INT td(rst) Fig 7. Write mode (output) Simple code WRITE mode: ... Remark: Bold type = generated by slave device. 8 XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 8.3 Reading from a port (Input mode) The port must have been previously written to logic 1, which is the condition after power-on reset. To enter the Read mode the master (microcontroller) addresses the slave device and sets the last bit of the address byte to logic 1 (address byte read). The slave will acknowledge and then send the data byte to the master. The master will NACK and then send the STOP condition or ACK and read the input register again. The read of any pin being used as an output will indicate HIGH or LOW depending on the actual state of the pin. If the data on the input port changes faster than the master can read, this data may be lost. The DATA 2 and DATA3 are lost because these data did not meet the setup time and hold time (see Figure 8). slave address data from port SDA S A6 A5 A4 A3 A2 A1 A0 1 START condition R/W A DATA 1 data from port A acknowledge from slave DATA 4 acknowledge from master no acknowledge from master 1 P STOP condition read from port DATA 2 data at port DATA 1 DATA 3 th(D) DATA 4 tsu(D) INT tv(INT) trst(INT) trst(INT) A LOW-to-HIGH transition of SDA while SCL is HIGH is defined as the STOP condition (P). Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost. Fig 8. Read mode (input) Simple code for Read mode: ... Remark: Bold type = generated by slave device. 8.4 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the 8574A/PT in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the 8574A/PT registers and I 2C-bus/SMBus state machine will initialize to their default states of all I/Os to inputs with weak current source to VDD. Thereafter VDD must be lowered below VPOR and back up to the operation voltage for power-on reset cycle. 9 XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 8.5 Interrupt output (INT) The 8574A/PT provides an open-drain output (INT ) which can be fed to a corresponding input of the microcontroller (see Figure 9 ). As soon as a port input is changed, the INT will be active (LOW) and notify the microcontroller. An interrupt is generated at any rising or falling edge of the port inputs. After time tv(Q), the signal INT is valid. The interrupt will reset to HIGH when data on the port is changed to the original setting or data is read or written by the master. In the Write mode, the interrupt may be reset (HIGH) on the rising edge of the acknowledge bit of the address byte and also on the rising edge of the write to port pulse. The interrupt will always be reset (HIGH) on the falling edge of the write to port pulse (see Figure 7). The interrupt is reset (HIGH) in the Read mode on the rising edge of the read from port pulse (see Figure8 ). During the interrupt reset, any I/O change close to the read or write pulse may not generate an interrupt, or the interrupt will have a very short pulse. After the interrupt is reset, any change in I/Os will be detected and transmitted as an INT. At power-on reset all ports are in Input mode and the initial state of the ports is HIGH, therefore, for any port pin that is pulled LOW or driven LOW by external source, the interrupt output will be active (output LOW). VDD device 1 device 2 device 16 XD8574AP XD8574AP XD8574P INT INT INT MICROCONTROLLER INT Fig 9. Application of multiple 8574A/PT with interrupt 10 XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 9. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-wire communication between different ICs or modules. The two wires are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 9.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure10 ). SDA SCL change of data allowed data line stable; data valid Fig 10. Bit transfer 9.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 11). SDA SCL S P START condition STOP condition Fig 11. Definition of START and STOP conditions 9.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 12). 11 XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER MASTER TRANSMITTER/ RECEIVER MASTER TRANSMITTER I2C-BUS MULTIPLEXER SLAVE Fig 12. System configuration 9.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit (see Figure 13). The acknowledge bit is an active LOW level (generated by the receiving device) that indicates to the transmitter that the data transfer was successful. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that wants to issue an acknowledge bit has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge bit related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 S 8 clock pulse for acknowledgement START condition Fig 13. Acknowledgement on the I2C-bus 12 9 XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 10. Application design-in information 10.1 Bidirectional I/O expander applications In the 8-bit I/O expander application shown in Figure 14, P0 and P1 are inputs, and P2 to P7 are outputs. When used in this configuration, during a write, the input (P0 and P1) must be written as HIGH so the external devices fully control the input ports. The desired HIGH or LOW logic levels may be written to the ports used as outputs (P2 to P7). If 10 A internal output HIGH is not enough current source, the port needs external pull-up resistor. During a read, the logic levels of the external devices driving the input ports (P0 and P1) and the previous written logic level to the output ports (P2 to P7) will be read. The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O informs the microprocessor that there has been a change of data on its ports without having to communicate via the I2C-bus. VDD VDD CORE PROCESSOR VDD SDA SCL INT A0 A1 A2 P0 P1 P2 P3 P4 P5 P6 P7 temperature sensor battery status control for latch control for switch control for audio control for camera control for MP3 Fig 14. Bidirectional I/O expander application 10.2 How to read and write to I/O expander (example) In the application example of 8574A/PT shown in Figure 14, the microcontroller wants to control the P3 switch ON and the P7 LED ON when the temperature sensor P0 changes. 1. When the system power on: Core Processor needs to issue an initial command to set P0 and P1 as inputs and P[7:2] as outputs with value 1010 00 (LED off, MP3 off, camera on, audio off, switch off and latch off). 2. Operation: When the temperature changes above the threshold, the temperature sensor signal will toggle from HIGH to LOW. The INT will be activated and notifies the ‘core processor’ that there have been changes on the input pins. Read the input register. If P0 = 0 (temperature sensor has changed), then turn on LED and turn on switch. 3. Software code: //System Power on // write to 8574A/PT with data 1010 0011b to set P[7:2] outputs and P[1:0] inputs //Initial setting for 9574 13 XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 while (INT == 1); //Monitor the interrupt pin. If INT = 1 do nothing //When INT = 0 then read input ports //Read 8574A/PT data If (P0 == 0) //Temperature sensor activated { // write to 8574A/PT with data 0010 1011b to turn on LED (P7), on Switch (P3) and keep P[1:0] as input ports. // Write to 8574A/PT } 10.3 High current-drive load applications The GPIO has a minimum guaranteed sinking current of 10 mA per bit at 5 V. In applications requiring additional drive, two port pins may be connected together to sink up to 20 mA current. Both bits must then always be turned on or off together. Up to five pins can be connected together to drive 80 mA, which is the device recommended total limit. Each pin needs its own limiting resistor as shown in Figure 15 to prevent damage to the device should all ports not be turned on at the same time. VDD VDD SDA SCL INT CORE PROCESSOR A0 A1 A2 VDD P0 P1 P2 P3 P4 P5 P6 P7 LOAD Fig 15. High current-drive load application 10.4 Migration path NXP offers newer, more capable drop-in replacements for the 8574A/PT in newer space-saving packages. Table 5. Migration path Type number I2C-bus frequency Voltage range Number of addresses per device Interrupt Reset Total package sink current 8574A/PT 100 kHz 2.5 V to 6 V 8 yes no 80 mA 8574A/PT 400 kHz 2.3 V to 5.5 V 8 yes no 200 mA 9674/74A 1 MHz Fm+ 2.3 V to 5.5 V 64 yes 14 no 200 mA XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 11. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IDD ISS Conditions Min Max Unit 0.5 +7 V supply current - 100 mA ground supply current - 100 mA VI input voltage VSS  0.5 VDD + 0.5 V II input current - 20 mA IO output current - 25 mA Ptot total power dissipation - 400 mW P/out power dissipation per output - 100 mW Tj(max) maximum junction temperature - 125 C Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +85 C operating 12. Thermal characteristics Table 7. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient SO16 package 115 C/W SSOP20 package 136 C/W 15 XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 13. Static characteristics Table 8. Static characteristics VDD = 2.5 V to 6 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supply VDD supply voltage 2.5 - 6.0 V IDD supply current operating mode; VDD = 6 V; no load; VI = VDD or VSS; fSCL = 100 kHz - 40 100 A Istb standby current standby mode; VDD = 6 V; no load; VI = VDD or VSS - 2.5 10 A VPOR power-on reset voltage VDD = 6 V; no load; VI = VDD or VSS - 1.3 2.4 V 0.5 - +0.3VDD V [1] Input SCL; input/output SDA VIL LOW-level input voltage VIH HIGH-level input voltage 0.7VDD - VDD + 0.5 V IOL LOW-level output current VOL = 0.4 V 3 - - mA IL leakage current VI = VDD or VSS 1 - +1 A Ci input capacitance VI = VSS - - 7 pF I/Os; P0 to P7 VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - VDD + 0.5 V IIHL(max) maximum allowed input current through protection diode VI  VDD or VI  VSS - - 400 A IOL LOW-level output current VOL = 1 V; VDD = 5 V 10 25 - mA IOH HIGH-level output current VOH = VSS 30 - 300 A Itrt(pu) transient boosted pull-up current HIGH during acknowledge (see Figure7 ); VOH = VSS; VDD = 2.5 V - 1 - mA Ci input capacitance - - 10 pF Co output capacitance - - 10 pF Interrupt INT (see Figure7 ) IOL LOW-level output current VOL = 0.4 V 1.6 - - mA IL leakage current VI = VDD or VSS 1 - +1 A 0.5 - +0.3VDD V Select inputs A0, A1, A2 VIL LOW-level input voltage VIH HIGH-level input voltage ILI input leakage current [1] pin at VDD or VSS 0.7VDD - VDD + 0.5 V 250 - +250 nA The power-on reset circuit resets the I2C-bus logic at VDD < VPOR and sets all I/Os to logic 1 (with current source to VDD). 16 XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 14. Dynamic characteristics Table 9. Dynamic characteristics VDD = 2.5 V to 6 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol I2C-bus Parameter timing[1] Conditions Min Typ Max Unit (see Figure 16) fSCL SCL clock frequency - - 100 kHz tBUF bus free time between a STOP and START condition 4.7 - - s tHD;STA hold time (repeated) START condition 4 - - s tSU;STA set-up time for a repeated START condition 4.7 - - s tSU;STO set-up time for STOP condition 4 - - s tHD;DAT data hold time 0 - - ns tVD;DAT data valid time - - 3.4 s tSU;DAT data set-up time 250 - - ns tLOW LOW period of the SCL clock 4.7 - - s tHIGH HIGH period of the SCL clock 4 - - s tr rise time of both SDA and SCL signals - - 1 s tf fall time of both SDA and SCL signals - - 0.3 s Port timing (see Figure7 and Figure8 ) tv(Q) data output valid time CL  100 pF - - 4 s tsu(D) data input set-up time CL  100 pF 0 - - s th(D) data input hold time CL  100 pF 4 - - s Interrupt INT timing (see Figure8 ) tv(INT) valid time on pin INT from port to INT; CL  100 pF - - 4 s trst(INT) reset time on pin INT from SCL to INT; CL  100 pF - - 4 s [1] All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSS to VDD. protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW bit 6 (A6) tHIGH bit 0 (R/W) acknowledge (A) STOP condition (P) 1 / fSCL 0.7 × VDD SCL 0.3 × VDD tBUF tr tf 0.7 × VDD SDA 0.3 × VDD tHD;STA tSU;DAT tHD;DAT Rise and fall times refer to VIL and VIH. Fig 16. I2C-bus timing diagram 17 tVD;DAT tVD;ACK tSU;STO XD8574AP DIP-16 XD8574P DIP-16 XL8574AT SOP16 XL8574T SOP16 17 18