XL3525Z

XD3525 DIP16 XL3525Z SOP16窄体 XL3525K SOP16宽体 .. .. .. .. . . 8 TO 35 V OPERATION 5.1 V REFERENCE TRIMMED TO ± 1 % 100 Hz TO 500 KHz OSCILLATOR RANGE SEPARATE OSCILLATOR SYNC TERMINAL ADJUSTABLE DEADTIME CONTROL INTERNAL SOFT-START PULSE-BY-PULSE SHUTDOWN INPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS LATCHING PWM TO PREVENT MULTIPLE PULSES DUAL SOURCE/SINK OUTPUT DRIVERS DESCRIPTION The XD3525 series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip + 5.1 V reference is trimmed to ± 1 % and the input common-mode range of the error amplifier includes the reference voltage eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CT and the discharge terminals provide a wide range of dead time ad- justment. These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuity and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500 mV of hysteresis for jitterfree operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulses has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The XD3525 output stage features NOR logic, giving a LOW output for an OFF state. 型号 封装 尺寸 XD3525 DIP16 18.70mm*6.23mm XL3525Z SOP16窄体 9.97mm*3.93mm XL3525K SOP16宽体 10.28mm*7.39mm XD3525 1 1 XD3525 DIP16/XL3525Z SOP16窄体/XL3525K SOP16宽体 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vi Supply Voltage 40 V VC Collector Supply Voltage 40 V IOSC 5 mA Io Output Current, Source or Sink 500 mA IR Reference Output Current 50 mA IT Current through CT Terminal Logic Inputs Analog Inputs Total Power Dissipation at Tamb = 70 °C 5 – 0.3 to + 5.5 – 0.3 to Vi 1000 mA V V mW Junction Temperature Range – 55 to 150 °C Storage Temperature Range Operating Ambient Temperature : XD3525 XL3525Z – 65 to 150 – 25 to 85 0 to 70 °C °C °C Ptot Tj Tstg Top Oscillator Charging Current THERMAL DATA Symbol Rth j-pins Rth j-amb Rth j-alumina Parameter SO16 Thermal Resistance Junction-pins Thermal Resistance Junction-ambient Thermal Resistance Junction-alumina (*) Max Max Max 50 DIP16 Unit 50 80 °C/W °C/W °C/W * Thermal resistance junction-alumina with the device soldered on the middle of an alumina supporting substrate measuring 15 × 20 mm ; 0.65 mm thickness with infinite heatsink. BLOCK DIAGRAM XD3525 XD3525 OUTPUT STAGE 2 2 XD3525 DIP16/XL3525Z SOP16窄体/XL3525K SOP16宽体 ELECTRICAL CHARACTERISTICS (V# i = 20 V, and over operating temperature, unless otherwise specified) Symbol Parameter XD3525 Test Conditions XL3525Z/K Unit Min. Typ. Max. Min. Typ. Max. 5.05 5.1 5.15 5 5.1 5.2 REFERENCE SECTION Tj = 25 °C VREF Output Voltage ∆VREF Line Regulation Vi = 8 to 35 V 10 20 10 20 mV ∆VREF Load Regulation IL = 0 to 20 mA 20 50 20 50 mV Over Operating Range 20 50 20 50 mV 5.25 V ∆VREF/∆T* Temp. Stability * * ∆VREF* 5 5.2 4.95 V Total Output Variation Line, Load and Temperature Short Circuit Current VREF = 0 Tj = 25 °C 80 100 80 100 mA Output Noise Voltage 10 Hz ≤f ≤ 10 kHz, Tj = 25 °C 40 200 40 200 µVrms Long Term Stability Tj = 125 °C, 1000 hrs 20 50 20 50 mV OSCILLATOR SECTION * * *, • Initial Accuracy Tj = 25 °C *, • Voltage Stability Vi = 8 to 35 V ∆f/∆T* Temperature Stability Over Operating Range fMIN Minimum Frequency RT = 200 KΩ CT = 0.1 µF fMAX Maximum Frequency RT = 2 KΩ CT = 470 pF 400 Current Mirror IRT = 2 mA 1.7 2 3 3.5 0.3 0.5 1.2 2 1 2.5 *, • Clock Amplitude *, • Clock Width Tj = 25 °C Sync Threshold Sync Input Current ±2 ±6 ±2 ±6 % ± 0.3 ±1 ±1 ±2 % ±6 ±3 ±3 120 Sync Voltage = 3.5 V ±6 % 120 Hz 400 2.2 KHz 1.7 2 2.2 mA 3 3.5 1 0.3 0.5 1 µs 2.8 1.2 2 2.8 V 1 2.5 mA V ERROR AMPLIFIER SECTION (VCM = 5.1 V) VOS Input Offset Voltage Ib Input Bias Current Ios Input Offset Current * *, ❚ 0.5 5 2 10 mV 1 10 1 10 µA 1 µA 1 DC Open Loop Gain RL ≥ 10 MΩ Gain Bandwidth Product Gv = 0 dB DC Transconduct. 30 KΩ ≤ RL ≤ 1 MΩ Tj = 25 °C T j = 25 °C 60 75 60 75 dB 1 2 1 2 MHz 1.1 1.5 1.1 1.5 ms Output Low Level 0.2 Output High Level 0.5 0.2 0.5 V 3.8 5.6 3.8 5.6 V CMR Comm. Mode Reject. VCM = 1.5 to 5.2 V 60 75 60 75 dB PSR Supply Voltage Rejection Vi = 8 to 35 V 50 60 50 60 dB 3 3 XD3525 DIP16/XL3525Z SOP16窄体/XL3525K SOP16宽体 ELECTRICAL CHARACTERISTICS (continued) Symbol Parameter XD3525 Test Conditions Min. Typ. XL3525Z/K Max. Min. Typ. Unit Max. PWM COMPARATOR Minimum Duty-cycle • Maximum Duty-cycle • Input Threshold * Input Bias Current 0 Zero Duty-cycle 0 % 45 49 45 49 % 0.7 0.9 0.7 0.9 V Maximum Duty-cycle 3.3 3.6 3.3 3.6 V 0.05 1 0.05 1 µA 50 80 50 80 µA 0.4 0.7 0.4 0.7 V 0.8 1 0.8 1 V SHUTDOWN SECTION Soft Start Current VSD = 0 V, VSS = 0 V Soft Start Low Level VSD = 2.5 V Shutdown Threshold To outputs, VSS = 5.1 V Tj = 25 °C 25 0.6 Shutdown Input Current VSD = 2.5 V * Shutdown Delay VSD = 2.5 V Tj = 25 °C 25 0.6 0.4 1 0.4 1 mA 0.2 0.5 0.2 0.5 µs 0.2 0.4 0.2 0.4 V 1 2 1 2 OUTPUT DRIVERS (each output) (VC = 20 V) Output Low Level Isink = 20 mA Output High Level Isource = 20 mA 18 19 Isource = 100 mA 17 18 Under-Voltage Lockout Vcomp and Vss = High 6 7 Isink = 100 mA 8 18 19 17 18 6 7 V V V 8 V IC Collector Leakage VC = 35 V 200 µA tr* Rise Time CL = 1 nF, Tj = 25 °C 100 600 100 600 ns tf* Fall Time CL = 1 nF, Tj = 25 °C 50 300 50 300 ns 14 20 14 20 mA 200 TOTAL STANDBY CURRENT Is Supply Current Vi = 35 V * These parameters, although guaranteed over the recommended operating conditions, are not 100 % tested in production. Tested at fosc = 40 KHz (RT = 3.6 KΩ, CT = 10nF, RD = 0 Ω). Approximate oscillator frequency is defined by : • f= 1 CT (0.7 RT + 3 RD) . DC transconductance (gM) relates to DC open-loop voltage gain (Gv) according to the following equation : Gv = gM RL where RL is the resistance from pin 9 to ground. The minimum gM specification is used to calculate minimum Gv when the error amplifier output is loaded. 4 4 XD3525 DIP16/XL3525Z SOP16窄体/XL3525K SOP16宽体 TEST CIRCUIT 5 5 XD3525 DIP16/XL3525Z SOP16窄体/XL3525K SOP16宽体 RECOMMENDED OPERATING CONDITIONS (•) Parameter Value Input Voltage (Vi) 8 to 35 V Collector Supply Voltage (VC) 4.5 to 35 V Sink/Source Load Current (steady state) 0 to 100 mA Sink/Source Load Current (peak) Reference Load Current 0 to 400 mA 0 to 20 mA Oscillator Frequency Range 100 Hz to 400 KHz Oscillator Timing Resistor 2 KΩ to 150 KΩ Oscillator Timing Capacitor 0.001 µF to 0.1 µF Dead Time Resistor Range 0 to 500 Ω ⋅ ( ) Range over which the device is functional and parameter limits are guaranteed. • Figure 1 : Oscillator Charge Time vs. R T and C T . Figure 2 : Oscillator Discharge Time vs. R D and C T . Figure 3 : Output Saturation Characteristics. Figure 4 : Error Amplifier Voltage Gain and Phase vs. Frequency. 6 6 XD3525 DIP16/XL3525Z SOP16窄体/XL3525K SOP16宽体 Figure 5 : Error Amplifier. PRINCIPLES OF OPERATION ately set providing the fastest turn-off signal to the outputs ; and a 150 µA current sink begins to discharge the external soft-start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft-start capacitor, thus, allowing, for example, a convenient implementation of pulse-by-pulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn-on upon release. SHUTDOWN OPTIONS (see Block Diagram) Since both the compensation and soft-start terminals (Pins 9 and 8) have current source pull-ups, either can readily accept a pull-down signal which only has to sink a maximum of 100 µA to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions : the PWM latch is immedi- Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation. 7 7 XD3525 DIP16/XL3525Z SOP16窄体/XL3525K SOP16宽体 Figure 6 : Oscillator Schematic. Figure 7 : Output Circuit (1/2 circuit shown). XD3525 8 8 XD3525 DIP16/XL3525Z SOP16窄体/XL3525K SOP16宽体 Figure 8. Figure 9. For single-ended supplies, the driver outputs are grounded. The VC terminal is switched to ground by the totem-pole source transistors on alternate oscillator cycles. In conventional push-pull bipolar designs, forward base drive is controlled by R1 - R3. Rapid turn-off times for the power devices are achieved with speed-up capacitors C1 and C2. Figure 10. Figure 11. The low source impedance of the output drivers provides rapid charging of Power Mos input capacitance while minimizing external components. Low power transformers can be driven directly. Automatic reset occurs during dead time, when both ends of the primary winding are switched to ground. 9 XD3525 DIP16/XL3525Z SOP16窄体/XL3525K SOP16宽体 DIP SOP16宽体 910 XD3525 DIP16/XL3525Z SOP16窄体/XL3525K SOP16宽体 SOP16窄体 911