XD74HC245

XL74HC245 SOP-20 XD74HC245 DIP-20 1 Features 3 Description • • • • These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. 1 3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce DC Loading on Bus Lines Hysteresis at Bus Inputs Improves Noise Margins Typical Propagation Delay Times Port to Port, 8 ns The 74HC245 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the directioncontrol (DIR) input. The output-enable (OE) input can disable the device so that the buses are effectively isolated. 2 Applications • • • • Building Automation Electronic Point of Sale Factory Automation and Control Test and Measurement 4 Logic Diagram (Positive Logic) DIR 1 19 A1 OE 2 18 To Seven Other Channels 1 1 B1 XL74HC245 SOP-20 XD74HC245 DIP-20 5 Device Comparison Table TYPE IOL (SINK CURRENT) IOH (SOURCE CURRENT) 24 mA –15 mA 74HC245 6 Pin Configuration and Functions SOP/DIP DIR 1 20 VCC A1 2 19 OE A2 3 18 B1 A3 4 17 B2 A4 5 16 B3 A5 6 15 B4 A6 7 14 B5 A7 8 13 B6 A8 9 12 B7 10 11 B8 GND Pin Functions PIN NO. NAME I/O DESCRIPTION 1 DIR I 2 A1 I/O Controls signal direction; Low = Bx to Ax, High = Ax to Bx Channel 1, A side 3 A2 I/O Channel 2, A side 4 A3 I/O Channel 3, A side 5 A4 I/O Channel 4, A side 6 A5 I/O Channel 5, A side 7 A6 I/O Channel 6, A side 8 A7 I/O Channel 7, A side 9 A8 I/O Channel 8, A side 10 GND — Ground 11 B8 O/I Channel 8, B side 12 B7 O/I Channel 7, B side 13 B6 O/I Channel 6, B side 14 B5 O/I Channel 5, B side 15 B4 O/I Channel 4, B side 16 B3 O/I Channel 3, B side 17 B2 O/I Channel 2, B side 18 B1 O/I Channel 1, B side 19 OE I 20 VCC — Active low output enable; Low = all channels active, High = all channels disabled (high impedance) Power supply 2 XL74HC245 SOP-20 XD74HC245 DIP-20 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) MIN VCC UNIT 7 V (1) VI Input voltage TJ Operating virtual junction temperature Tstg Storage temperature (1) MAX Supply voltage –65 7 V 150 °C 150 °C All voltage values are with respect to GND. 7.2 ESD Ratings VALUE V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1500 UNIT V 7.5 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) TEST CONDITIONS (1) PARAMETER VIH High-level input voltage VIL Low-level input voltage VIK Input clamp voltage Hysteresis (VT+ – VT–) MIN TYP (1) MAX 2 V 74HC245 VCC = MIN, A or B II = –18 mA VCC = MIN UNIT 0.2 0.4 2.4 3.4 0.8 V –1.5 V V High-level output voltage VCC = MIN, VIL = VIL(max) VIH = 2 V, IOH = –3 mA VOH Low-level output voltage VCC = MIN, VIH = 2 V, VIL = VIL(max) IOL = 12 mA VOL IOZH Off-state output current, high-level voltage applied VCC = MAX, OE at 2 V VO = 2.7 V 20 µA IOZL Off-state output current, low-level voltage applied VCC = MAX, OE at 2 V VO = 0.4 V –200 µA II Input current at maximum input voltage IIH High-level input current IIL IOS A or B IOH = MAX IOL = 24 mA 0.5 V 0.1 VI = 7 V 0.1 VCC = MAX, VIH = 2.7 V 20 µA Low-level input current VCC = MAX, VIL = 0.4 V –0.2 mA Short-circuit output current (2) VCC = MAX –225 mA VCC = MAX –40 Supply current Total, outputs low VCC = MAX Outputs open Outputs at high Z (1) (2) 0.4 74HC245 VI = 5.5 V DIR or OE Total, outputs high ICC V 2 48 70 62 90 64 95 All typical values are at VCC = 5 V, TA = 25°C. Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second. 3 mA mA XL74HC245 SOP-20 XD74HC245 DIP-20 7.6 Switching Characteristics VCC = 5 V, TA = 25°C (see Figure 2) PARAMETER TEST CONDITIONS tPLH Propagation delay time, low- to high-level output tPHL Propagation delay time, high- to low-level output tPZL Output enable time to low level tPZH Output enable time to high level tPLZ Output disable time from low level tPHZ Output disable time from high level MIN CL = 45 pF, RL = 667 Ω CL = 45 pF, RL = 667 Ω CL = 5 pF, RL = 667 Ω 7.7 Typical Characteristics VCC = 5 V, TA = 25°C, CL = 45 pF, RL = 667 Ω 5.5 4.5 Voltage (V) 3.5 2.5 1.5 0.5 Input Output -0.5 0 5 10 Time (ns) 15 20 D001 Figure 1. Simulated Propagation Delay From Input to Output 4 TYP MAX 8 12 8 12 27 40 25 40 15 25 15 28 UNIT ns ns ns XL74HC245 SOP-20 XD74HC245 DIP-20 8 Parameter Measurement Information VCC Test Point VCC RL From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS High-Level Pulse 1.3 V S1 (see Note B) CL (see Note A) RL (see Note B) RL From Output Under Test VCC From Output Under Test Test Point 5 kΩ Test Point S2 LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3V Timing Input 1.3 V 1.3 V 0V tw Low-Level Pulse 1.3 V tsu Data Input 1.3 V VOLTAGE WAVEFORMS PULSE DURATIONS 1.3 V Output Control (low-level enabling) 1.3 V 0V tPLH In-Phase Output (see Note D) 1.3 V 0V 3V 1.3 V 1.3 V 0V tPZL tPLZ tPHL VOH 1.3 V 1.3 V Waveform 1 (see Notes C and D) VOL + 0.5 V VOL VOH 1.3 V tPHZ tPZH tPLH 1.3 V VOL Waveform 2 (see Notes C and D) ≈1.5 V 1.3 V VOL tPHL Out-of-Phase Output (see Note D) 3V 1.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input th VOH 1.3 V VOH – 0.5 V ≈1.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time with one input transition per measurement. Figure 2. Load Circuits and Voltage Waveforms 5 XL74HC245 SOP-20 XD74HC245 DIP-20 9 Detailed Description 9.1 Overview The 74HC245 uses Schottky transistor logic to perform the standard '245 transceiver function. This standard logic function has a common pinout, direction select pin, and active-low output enable. When the outputs are disabled, the A and B sides of the device are effectively isolated. 9.2 Functional Block Diagram DIR 1 19 A1 OE 2 18 B1 To Seven Other Channels Figure 3. Logic Diagram (Positive Logic) 9.3 Feature Description 9.3.1 3-State outputs The 3-state outputs can drive bus lines directly. All outputs can be put into high impedance mode through the OE pin. 9.3.2 PNP Inputs This device has PNP inputs which reduce dc loading on bus lines. 9.3.3 Hysteresis on Bus Inputs The bus inputs have built-in hysteresis that improves noise margins. 9.4 Device Functional Modes The 74HC245 performs the standard '245 logic function. Data can be transmitted from A to B or from B to A depending on the DIR pin value, or the A and B sides can be isolated from one another by setting the OE pin HIGH. 6 XL74HC245 SOP-20 XD74HC245 DIP-20 Table 1. Function Table INPUTS OE OPERATION DIR L L B data to A bus L H A data to B bus H X Isolation EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC VCC 50 Ω NOM 9 kΩ NOM Input Output Figure 4. Schematics of Inputs and Outputs 7 XL74HC245 SOP-20 XD74HC245 DIP-20 DIP 78 XL74HC245 SOP-20 XD74HC245 DIP-20 SOP 79