S-93C46B/56B/66B
3-WIRE SERIAL E2PROM
www.ablicinc.com
Rev.8.1_02
© ABLIC Inc., 2002-2015
The S-93C46B/56B/66B is a high speed, low current consumption, 3-wire serial E2PROM with a wide operating voltage
range. The S-93C46B/56B/66B has the capacity of 1 K-bit, 2 K-bit and 4 K-bit, and the organization is 64-word 16-bit,
128-word 16-bit and 256-word 16-bit. It is capable of sequential read, at which time addresses are automatically
incremented in 16-bit blocks.
The communication method is by the Microwire bus.
Features
Operating voltage range:
Read
1.8 V to 5.5 V
Write
2.7 V to 5.5 V
2.0 MHz (VCC = 4.5 V to 5.5 V)
8.0 ms max.
Operation frequency:
Write time:
Sequential read capable
Write protect function during the low power supply voltage
Function to protect against write due to erroneous instruction recognition
6
*1
Endurance:
10 cycles / word (Ta = 85 C)
Data retention:
100 years (Ta = 25 C)
20 years (Ta = 85 C)
Memory capacity:
S-93C46B 1 K-bit
S-93C56B 2 K-bit
S-93C66B 4 K-bit
Initial delivery state:
FFFFh
Operation temperature range:
Ta = 40°C to 85 C
Lead-free, Sn 100%, halogen-free*2
*1. For each address (Word: 16-bit)
*2. Refer to “
Product Name Structure” for details.
Packages
8-Pin SOP (JEDEC)
8-Pin TSSOP
TMSOP-8
SNT-8A
Caution This product is intended to use in general electronic devices such as consumer electronics, office
equipment, and communications devices. Before using the product in medical equipment or
automobile equipment including car audio, keyless entry and engine control unit, contact to ABLIC
Inc. is indispensable.
1
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
Pin Configurations
1. 8-Pin SOP (JEDEC)
Table 1
8-Pin SOP (JEDEC)
Top view
1
8
2
7
3
6
4
5
Figure 1
Pin No.
Symbol
Description
1
CS
Chip select input
2
SK
Serial clock input
3
DI
Serial data input
4
DO
Serial data output
5
GND
Ground
*1
6
TEST
Test
7
NC
No connection
8
VCC
Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long
as the absolute maximum rating is not exceeded.
S-93C46BD0I-J8T1x
S-93C56BD0I-J8T1x
S-93C66BD0I-J8T1x
8-Pin SOP (JEDEC) (Rotated)
Top view
1
8
2
7
3
6
4
5
Figure 2
S-93C46BR0I-J8T1x
S-93C56BR0I-J8T1x
S-93C66BR0I-J8T1x
Table 2
Pin No.
Symbol
Description
1
NC
No connection
2
VCC
Power supply
3
CS
Chip select input
4
SK
Serial clock input
5
DI
Serial data input
6
DO
Serial data output
7
GND
Ground
8
TEST*1
Test
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long
as the absolute maximum rating is not exceeded.
Remark 1. Refer to the “package drawings” for the details.
2. x: G or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
2
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
2. 8-Pin TSSOP
Table 3
8-Pin TSSOP
Top view
8
7
6
5
1
2
3
4
Figure 3
S-93C46BD0I-T8T1x
S-93C56BD0I-T8T1x
S-93C66BD0I-T8T1x
3.
Pin No.
1
2
3
4
5
6
7
8
Symbol
CS
SK
DI
DO
GND
*1
TEST
NC
VCC
Description
Chip select input
Serial clock input
Serial data input
Serial data output
Ground
Test
No connection
Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long
as the absolute maximum rating is not exceeded.
TMSOP-8
Table 4
TMSOP-8
Top view
8
7
6
5
1
2
3
4
Figure 4
S-93C46BD0I-K8T3U
S-93C56BD0I-K8T3U
S-93C66BD0I-K8T3U
Pin No.
Symbol
Description
1
CS
Chip select input
2
SK
Serial clock input
3
DI
Serial data input
4
DO
Serial data output
5
GND
Ground
6
TEST*1
Test
7
NC
No connection
8
VCC
Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long
as the absolute maximum rating is not exceeded.
Remark 1. Refer to the “package drawings” for the details.
2. x: G or U
3. Please select products of environmental code = U for Sn 100%, halogen-free products.
3
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
4.
Rev.8.1_02
SNT-8A
Table 5
SNT-8A
Top view
1
2
3
4
8
7
6
5
Figure 5
S-93C46BD0I-I8T1U
S-93C56BD0I-I8T1U
S-93C66BD0I-I8T1U
Pin No.
Symbol
Description
1
CS
Chip select input
2
SK
Serial clock input
3
DI
Serial data input
4
DO
Serial data output
5
GND
Ground
6
TEST*1
Test
7
NC
No connection
8
VCC
Power supply
*1. Connect to GND or VCC.
Even if this pin is not connected, performance is not affected so long as
the absolute maximum rating is not exceeded.
Remark Refer to the “package drawings” for the details.
4
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
Block Diagram
Memory array
VCC
Address
decoder
Data register
GND
Output buffer
DO
DI
Mode decode logic
CS
'PSGOTYPWI
QSRMXSVMRKGMVGYMX
SK
Voltage detector
Clock generator
Figure 6
5
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
Instruction Sets
1. S-93C46B
Table 6
Instruction
SK input clock
Start Bit
Address
Data
4
5
6
7
8
9
READ (Read data)
WRITE (Write data)
ERASE (Erase data)
1
1
1
1
0
1
0
1
1
A5
A5
A5
A4
A4
A4
A3
A3
A3
A2
A2
A2
A1
A1
A1
A0
A0
A0
WRAL (Write all)
ERAL (Erase all)
1
0
0
0
1
x
x
x
x
1
0
0
1
0
x
x
x
x
EWEN (Write enable)
1
0
0
1
1
x
x
x
x
EWDS (Write disable)
1
0
0
0
0
x
x
x
x
*1.
1
Operation
Code
2
3
10 to 25
D15 to D0 Output*1
D15 to D0 Input
D15 to D0 Input
When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x: Don’t care
2. S-93C56B
Table 7
Instruction
SK input clock
Start Bit
Address
Data
READ (Read data)
WRITE (Write data)
ERASE (Erase data)
1
1
1
1
0
1
0
1
1
4
x
x
x
5
A6
A6
A6
6
A5
A5
A5
7
A4
A4
A4
8
A3
A3
A3
9
A2
A2
A2
10
A1
A1
A1
WRAL (Write all)
ERAL (Erase all)
1
1
0
0
0
0
0
1
1
0
x
x
x
x
x
x
x
x
x
x
x
x
EWEN (Write enable)
1
0
0
1
1
x
x
x
x
x
x
0
x
x
x
x
x
x
EWDS (Write disable)
*1.
1
Operation
Code
2
3
1
0
0
0
11
12 to 27
A0 D15 to D0 Output*1
A0 D15 to D0 Input
A0
D15 to D0 Input
When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x: Don’t care
3. S-93C66B
Table 8
Instruction
SK input clock
Start Bit
Address
Data
READ (Read data)
WRITE (Write data)
ERASE (Erase data)
1
1
1
1
0
1
0
1
1
4
A7
A7
A7
5
A6
A6
A6
6
A5
A5
A5
7
A4
A4
A4
8
A3
A3
A3
9
A2
A2
A2
10
A1
A1
A1
11
A0
A0
A0
WRAL (Write all)
ERAL (Erase all)
1
1
0
0
0
0
0
1
1
0
x
x
x
x
x
x
x
x
x
x
x
x
EWEN (Write enable)
1
0
0
1
1
x
x
x
x
x
x
EWDS (Write disable)
1
0
0
0
0
x
x
x
x
x
x
*1.
12 to 27
D15 to D0 Output
D15 to D0 Input
D15 to D0 Input
When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark x: Don’t care
6
1
Operation
Code
2
3
*1
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
Absolute Maximum Ratings
Table 9
Item
Symbol
Ratings
Unit
Power supply voltage
VCC
0.3 to 7.0
V
Input voltage
VIN
0.3 to VCC 0.3
V
Output voltage
VOUT
0.3 to VCC
V
Operation ambient temperature Topr
40 to 105
C
Storage temperature
Tstg
65 to 150
C
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Recommended Operating Conditions
Table 10
Item
Symbol
Power supply voltage
VCC
High level input voltage
VIH
Low level input voltage
VIL
Ta = 40 C to 85 C
Min.
Max.
1.8
5.5
Conditions
READ, EWDS
WRITE, ERASE,
WRAL, ERAL, EWEN
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
VCC = 1.8 V to 2.7 V
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
VCC = 1.8 V to 2.7 V
Unit
V
2.7
5.5
V
2.0
0.8 VCC
0.8 VCC
0.0
0.0
0.0
VCC
VCC
VCC
0.8
0.2 VCC
0.15 VCC
V
V
V
V
V
V
Pin Capacitance
Table 11
Item
Input Capacitance
Output Capacitance
Symbol
CIN
COUT
Conditions
VIN = 0 V
VOUT = 0 V
(Ta = 25 C, f = 1.0 MHz, VCC = 5.0 V)
Min.
Max.
Unit
8
pF
10
pF
Endurance
Table 12
Item
Symbol
Operation Ambient Temperature
Endurance
NW
Ta = 40 C to 85 C
*1. For each address (Word: 16-bit)
Min.
106
Max.
Unit
cycles / word*1
Min.
100
20
Max.
Unit
year
year
Data Retention
Table 13
Item
Data retention
Symbol
Operation Ambient Temperature
Ta = 25°C
Ta = 40 C to 85°C
7
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
DC Electrical Characteristics
Table 14
Item
Current consumption
(READ)
Symbol
ICC1
Conditions
VCC =
4.5 V to 5.5 V
Min.
Max.
DO no load
Ta = 40 C to 85 C
VCC =
2.5 V to 4.5 V
Min.
Max.
0.8
VCC =
1.8 V to 2.5 V
Min.
Max.
0.5
0.4
Unit
mA
Table 15
Item
Current consumption
(WRITE)
Symbol
ICC2
Conditions
Ta = 40 C to 85 C
VCC = 4.5 V to 5.5 V
VCC = 2.7 V to 4.5 V
Min.
Max.
Min.
Max.
DO no load
2.0
Unit
1.5
mA
Table 16
Item
Standby current
consumption
Input leakage current
Output leakage
current
Low level output
voltage
8
Symbol
Conditions
Ta = 40 C to 85 C
VCC =
VCC =
VCC =
4.5 V to 5.5 V 2.5 V to 4.5 V 1.8 V to 2.5 V
Min. Max. Min. Max. Min. Max.
ILI
CS = GND, DO = Open,
Other inputs to VCC or GND
VIN = GND to VCC
ILO
VOUT = GND to VCC
1.0
1.0
1.0
IOL = 2.1 mA
IOL = 100 A
IOH = 400 A
IOH = 100 A
IOH = 10 A
0.4
0.1
0.1
0.1
ISB
VOL
High level output
voltage
VOH
Data hold voltage
of write enable latch
VDH
Only program disable mode
Unit
1.5
1.5
1.5
A
1.0
1.0
1.0
A
A
2.4
VCC 0.3
VCC 0.2
VCC 0.3
VCC 0.2
VCC 0.2
V
V
V
V
V
1.5
1.5
1.5
V
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
AC Electrical Characteristics
Table 17
Measurement Conditions
Input pulse voltage
0.1
Output reference voltage
VCC to 0.9
0.5
Output load
VCC
VCC
100 pF
Table 18
Ta = 40 C to 85 C
Item
Symbol
VCC = 4.5 V to 5.5 V VCC = 2.5 V to 4.5 V VCC = 1.8 V to 2.5 V
Min.
Max.
Min.
Max.
Min.
Unit
Max.
CS setup time
tCSS
0.2
0.4
1.0
s
CS hold time
tCSH
0
0
0
s
CS deselect time
tCDS
0.2
0.2
0.4
s
Data setup time
tDS
0.1
0.2
0.4
s
Data hold time
tDH
0.1
0.2
0.4
s
Output delay time
tPD
0.4
0.8
2.0
s
*1
Clock frequency
fSK
0
2.0
0
0.5
0
0.25
MHz
SK clock time “L”*1
tSKL
0.1
0.5
1.0
s
SK clock time “H”*1
tSKH
0.1
0.5
1.0
s
Output disable time
tHZ1, tHZ2
0
0.15
0
0.5
0
1.0
s
Output enable time
tSV
0
0.15
0
0.5
0
1.0
s
*1. The clock cycle of the SK clock (frequency: fSK) is 1 / fSK s. This clock cycle is determined by a
combination of several AC characteristics, so be aware that even if the SK clock cycle time is minimized,
the clock cycle (1 / fSK) cannot be made equal to tSKL (min.) tSKH (min.).
Table 19
Item
Symbol
Min.
Write time
tPR
Ta = 40 C to 85 C
VCC = 2.7 V to 5.5 V
Typ.
4.0
Unit
Max.
8.0
ms
9
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
1 / fSK
tCSS
*2
tCDS
CS
tSKH
tCSH
tSKL
SK
tDS
DI
tDH
Valid data
tPD
High-Z*1
(READ)
DO
tDH
Valid data
tPD
DO
tDS
High-Z
tSV
tHZ2
tHZ1
High-Z
High-Z
(VERIFY)
*1.
*2.
Indicates high impedance.
1 / fSK is the SK clock cycle. This clock cycle is determined by a combination of several AC
characteristics, so be aware that even if the SK clock cycle time is minimized, the clock cycle (1 / fSK)
cannot be made equal to tSKL (min.) tSKH (min.).
Figure 7 Timing Chart
10
Rev.8.1_02
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Initial Delivery State
Initial delivery state of all addresses is “FFFFh”.
Operation
All instructions are executed by inputting DI in synchronization with the rising edge of SK after CS goes high. An
instruction set is input in the order of start bit, instruction, address, and data.
Instruction input finishes when CS goes low. A low level must be input to CS between commands during tCDS.
While a low level is being input to CS, the S-93C46B/56B/66B is in standby mode, so the SK and DI inputs are
invalid and no instructions are allowed.
Start Bit
A start bit is recognized when the DI pin goes high at the rise of SK after CS goes high. After CS goes high, a start
bit is not recognized even if the SK pulse is input as long as the DI pin is low.
1.
Dummy clock
SK clocks input while the DI pin is low before a start bit is input are called dummy clocks. Dummy clocks are
effective when aligning the number of instruction sets (clocks) sent by the CPU with those required for serial
memory operation. For example, when a CPU instruction set is 16 bits, the number of instruction set clocks
can be adjusted by inserting a 7-bit dummy clock for the S-93C46B and a 5-bit dummy clock for the S93C56B/66B.
2.
Start bit input failure
When the output status of the DO pin is high during the verify period after a write operation, if a high level is
input to the DI pin at the rising edge of SK, the S-93C46B/56B/66B recognizes that a start bit has been input.
To prevent this failure, input a low level to the DI pin during the verify operation period (refer to “4. 1 Verify
operation”).
When a 3-wire interface is configured by connecting the DI input pin and DO output pin, a period in which the
data output from the CPU and the serial memory collide may be generated, preventing successful input of the
start bit. Take the measures described in “ 3-Wire Interface (Direct Connection between DI and DO)”.
11
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
3.
Rev.8.1_02
Reading (READ)
The READ instruction reads data from a specified address.
After CS has gone high, input an instruction in the order of the start bit, read instruction, and address. Since
the last input address (A0) has been latched, the output status of the DO pin changes from high impedance
(High-Z) to low, which is held until the next rise of SK. 16-bit data starts to be output in synchronization with
the next rise of SK.
3. 1
Sequential read
After the 16-bit data at the specified address has been output, inputting SK while CS is high automatically
increments the address, and causes the 16-bit data at the next address to be output sequentially. The
above method makes it possible to read the data in the whole memory space. The last address (An
A1 A0 = 1
1 1) rolls over to the top address (An
A1 A0 = 0
0 0).
CS
SK
1
DI
2
1
3
0
4
A5
5
A4
6
A3
7
A2
8
A1
9
11
12
23
24
25
26
27
39
28
40
41
42
43
44
A0
High-Z
DO
10
0
D15
D14
D13
D2
D1
D0
D15
D14
D13
D2
D1
ADRINC
D0
D15
D14
D13
High-Z
ADRINC
Figure 8 Read Timing (S-93C46B)
CS
SK
DI
DO
1
2
1
3
0
4
5
A6
High-Z
6
7
A5
A4
8
A3
9
A2
10
A1
11
12
13
14
24
25 26
27
28
29
41 42
43
44
45
A0
x : S-93C56B
A7: S-93C66B
0
D15 D14 D13
D2
D1
D0 D15 D14 D13
ADRINC
Figure 9 Read Timing (S-93C56B, S-93C66B)
12
40
D2
D1
D0 D15 D14 D13
ADRINC
High-Z
Rev.8.1_02
4.
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Writing (WRITE, ERASE, WRAL, ERAL)
A write operation includes four write instructions: data write (WRITE), data erase (ERASE), chip write (WRAL),
and chip erase (ERAL).
A write instruction (WRITE, ERASE, WRAL, ERAL) starts a write operation to the memory cell when a low level
is input to CS after a specified number of clocks have been input. The SK and DI inputs are invalid during the
write period, so do not input an instruction.
Input an instruction while the output status of the DO pin is high or high impedance (High-Z).
A write operation is valid only in program enable mode (refer to “5. Write enable (EWEN) and write disable
(EWDS)”).
4. 1 Verify operation
A write operation executed by any instruction is completed within 8 ms (write time tPR: typically 4 ms), so if
the completion of the write operation is recognized, the write cycle can be minimized. A sequential
operation to confirm the status of a write operation is called a verify operation.
4. 1. 1 Operation
After the write operation has started (CS = low), the status of the write operation can be verified by
confirming the output status of the DO pin by inputting a high level to CS again. This sequence is
called a verify operation, and the period that a high level is input to the CS pin after the write operation
has started is called the verify operation period.
The relationship between the output status of the DO pin and the write operation during the verify
operation period is as follows.
DO pin = low: Writing in progress (busy)
DO pin = high: Writing completed (ready)
4. 1. 2 Operation example
There are two methods to perform a verify operation: Waiting for a change in the output status of the
DO pin while keeping CS high, or suspending the verify operation (CS = low) once and then performing
it again to verify the output status of the DO pin. The latter method allows the CPU to perform other
processing during the wait period, allowing an efficient system to be designed.
Caution 1. Input a low level to the DI pin during a verify operation.
2. If a high level is input to the DI pin at the rise of SK when the output status of the DO pin is
high, the S-93C46B/56B/66B latches the instruction assuming that a start bit has been input.
In this case, note that the DO pin immediately enters a high-impedance (High-Z) state.
13
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
4. 2 Writing data (WRITE)
To write 16-bit data to a specified address, change CS to high and then input the WRITE instruction,
address, and 16-bit data following the start bit. The write operation starts when CS goes low. There is no
need to set the data to 1 before writing. If the clocks more than the specified number have been input, the
clock pulse monitoring circuit cancels the WRITE instruction. For details of the clock pulse monitoring
circuit, refer to “ Function to Protect Against Write due to Erroneous Instruction Recognition”.
tCDS
CS
Standby
Verify
SK
1
2
DI
3
0
1
4
5
6
7
8
9
10
A5
A4
A3
A2
A1
A0
D15
25
D0
DO
tHZ1
tSV
High-Z
busy
ready
tPR
Figure 10
High-Z
Data Write Timing (S-93C46B)
tCDS
CS
SK
DI
1
2
0
3
1
4
5
6
7
8
9
10
11
12
27
A6
A5
A4
A3
A2
A1
A0
D15
D0
High-Z
DO
tSV
x : S-93C56B
A7: S-93C66B
Figure 11
14
Standby
Verify
Data Write Timing (S-93C56B, S-93C66B)
tHZ1
busy
tPR
ready
High-Z
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
4. 3
Erasing data (ERASE)
To erase 16-bit data at a specified address, set all 16 bits of the data to 1, change CS to high, and then
input the ERASE instruction and address following the start bit. There is no need to input data. The data
erase operation starts when CS goes low. If the clocks more than the specified number have been input,
the clock pulse monitoring circuit cancels the ERASE instruction. For details of the clock pulse monitoring
circuit, refer to “ Function to Protect Against Write due to Erroneous Instruction Recognition”.
tCDS
CS
Standby
Verify
SK
1
2
DI
3
1
1
4
5
6
7
8
A5
A4
A3
A2
A1
9
A0
tSV
High-Z
DO
busy
tHZ1
ready
High-Z
tPR
Figure 12 Data Erase Timing (S-93C46B)
tCDS
CS
SK
DI
DO
Standby
Verify
1
2
1
3
1
4
5
6
7
8
9
A6
A5
A4
A3
A2
High-Z
x : S-93C56B
A7: S-93C66B
10
A1
11
A0
tSV
busy
tPR
tHZ1
ready
High-Z
Figure 13 Data Erase Timing (S-93C56B, S-93C66B)
15
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
4. 4
Rev.8.1_02
Writing to chip (WRAL)
To write the same 16-bit data to the entire memory address space, change CS to high, and then input the
WRAL instruction, an address, and 16-bit data following the start bit. Any address can be input. The
write operation starts when CS goes low. There is no need to set the data to 1 before writing. If the clocks
more than the specified number have been input, the clock pulse monitoring circuit cancels the WRAL
instruction. For details of the clock pulse monitoring circuit, refer to “ Function to Protect Against
Write due to Erroneous Instruction Recognition”.
tCDS
CS
Standby
Verify
SK
1
2
DI
3
0
4
0
5
0
6
7
9
1
10
25
D0
D15
4Xs
High-Z
DO
8
tSV
busy
tHZ1
ready
High-Z
tPR
Figure 14
Chip Write Timing (S-93C46B)
tCDS
CS
SK
DI
DO
1
2
0
3
0
4
0
5
6
7
8
1
High-Z
6Xs
9
10
11
12
27
D15
D0
tSV
tHZ1
busy
tPR
Figure 15
16
Standby
Verify
Chip Write Timing (S-93C56B, S-93C66B)
ready
High-Z
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
4. 5 Erasing chip (ERAL)
To erase the data of the entire memory address space, set all the data to 1, change CS to high, and then
input the ERAL instruction and an address following the start bit. Any address can be input. There is no
need to input data. The chips erase operation starts when CS goes low. If the clocks more than the
specified number have been input, the clock pulse monitoring circuit cancels the ERAL instruction. For
details of the clock pulse monitoring circuit, refer to “ Function to Protect Against Write due to
Erroneous Instruction Recognition”.
CS
SK
1
DI
2
3
4
0
0
1
5
6
7
8
9
0
4Xs
tSV
High-Z
DO
Standby
Verify
tCDS
tHZ1
busy
ready
High-Z
tPR
Figure 16
Chip Erase Timing (S-93C46B)
CS
SK
DI
DO
1
2
3
4
0
0
1
5
6
7
8
9
10
Standby
Verify
tCDS
11
0
High-Z
6Xs
tSV
tHZ1
busy
ready
High-Z
tPR
Figure 17
Chip Erase Timing (S-93C56B, S-93C66B)
17
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
5.
Rev.8.1_02
Write enable (EWEN) and write disable (EWDS)
The EWEN instruction is an instruction that enables a write operation. The status in which a write operation is
enabled is called the program enable mode.
The EWDS instruction is an instruction that disables a write operation. The status in which a write operation is
disabled is called the program disable mode.
After CS goes high, input an instruction in the order of the start bit, EWEN or EWDS instruction, and address
(optional). Each mode becomes valid by inputting a low level to CS after the last address (optional) has been
input.
CS
Standby
SK
1
2
3
0
DI
4
5
6
7
8
9
0
4Xs
11 = EWEN
00 = EWDS
Figure 18
Write Enable / Disable Timing (S-93C46B)
CS
SK
DI
Standby
1
2
0
3
4
5
7
8
9
10
11
0
11 = EWEN
00 = EWDS
Figure 19
6
6Xs
Write Enable / Disable Timing (S-93C56B, S-93C66B)
5. 1 Recommendation for write operation disable instruction
It is recommended to implement a design that prevents an incorrect write operation when a write instruction
is erroneously recognized by executing the write operation disable instruction when executing instructions
other than write instruction, and immediately after power-on and before power off.
18
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
Write Protect Function during the Low Power Supply Voltage
The S-93C46B/56B/66B provides a built-in detector. When the power supply voltage is low or at power application,
the write instructions (WRITE, ERASE, WRAL, ERAL) are cancelled, and the write disable state (EWDS) is
automatically set. The detection voltage is 1.75 V typ., the release voltage is 2.05 V typ., and there is a hysteresis of
about 0.3 V (refer to Figure 20). Therefore, when a write operation is performed after the power supply voltage has
dropped and then risen again up to the level at which writing is possible, a write enable instruction (EWEN) must be
sent before a write instruction (WRITE, ERASE, WRAL, ERAL) is executed.
When the power supply voltage drops during a write operation, the data being written to an address at that time is
not guaranteed.
Power supply voltage
Detection voltage ( VDET)
1.75 V typ.
Hysteresis
About 0.3 V
Release voltage ( VDET)
2.05 V typ.
Write instruction cancelled
Write disable state (EWDS) automatically set
Figure 20 Operation during Low Power Supply Voltage
19
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
Function to Protect Against Write due to Erroneous Instruction Recognition
The S-93C46B/56B/66B provides a built-in clock pulse monitoring circuit which is used to prevent an erroneous
write operation by canceling write instructions (WRITE, ERASE, WRAL, ERAL) recognized erroneously due to an
erroneous clock count caused by the application of noise pulses or double counting of clocks.
Instructions are cancelled if a clock pulse more or less than specified number decided by each write operation
(WRITE, ERASE, WRAL, ERAL) is detected.
Erroneous recognition of program disable instruction (EWDS) as erase instruction (ERASE)
Example of S-93C46B
Noise pulse
CS
1
2
3
4
5
6
7
8
9
SK
DI
Input EWDS instruction
Erroneous recognition as
ERASE instruction due to
1
0
0
0
0
0
0
0
0
1 1 10
0
0
00
0
0
0
0
noise pulse
In products that do not include a clock pulse monitoring circuit, FFFF is mistakenly written
on address 00h. However the S-93C46B detects the overcount and cancels the instruction
without performing a write operation.
Figure 21 Example of Clock Pulse Monitoring Circuit Operation
20
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
3-Wire Interface (Direct Connection between DI and DO)
There are two types of serial interface configurations: a 4-wire interface configured using the CS, SK, DI, and DO
pins, and a 3-wire interface that connects the DI input pin and DO output pin.
When the 3-wire interface is employed, a period in which the data output from the CPU and the data output from the
serial memory collide may occur, causing a malfunction. To prevent such a malfunction, connect the DI and DO
pins of the S-93C46B/56B/66B via a resistor (10 k to 100 k ) so that the data output from the CPU takes
precedence in being input to the DI pin (refer to “Figure 22 Connection of 3-Wire Interface”).
CPU
S-93C46B/56B/66B
SIO
DI
DO
R : 10 k
Figure 22
to 100 k
Connection of 3-Wire Interface
Input Pin and Output Pin
1.
Connection of input pins
All the input pins of the S-93C46B/56B/66B employ a CMOS structure, so design the equipment so that high
impedance will not be input while the S-93C46B/56B/66B is operating. Especially, deselect the CS input (a low
level) when turning on / off power and during standby. When the CS pin is deselected (a low level), incorrect
data writing will not occur. Connect the CS pin to GND via a resistor (10 k to 100 k pull-down resistor).
To prevent malfunction, it is recommended to use equivalent pull-down resistors for pins other than the CS pin.
2.
Equivalent circuit of input pin and output pin
The following shows the equivalent circuits of input pins of the S-93C46B/56B/66B. None of the input pins
incorporate pull-up and pull-down elements, so special care must be taken when designing to prevent a floating
status.
Output pins are high-level / low-level / high-impedance tri-state outputs. The TEST pin is disconnected from
the internal circuit by a switching transistor during normal operation. As long as the absolute maximum rating
is satisfied, the TEST pin and internal circuit will never be connected.
21
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
2. 1 Input pin
CS
Figure 23 CS Pin
SK, DI
Figure 24 SK, DI Pin
TEST
Figure 25 TEST Pin
22
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
2. 2 Output pin
VCC
DO
Figure 26 DO Pin
3.
Input pin noise elimination time
The S-93C46B/56B/66B includes a built-in low-pass filter to eliminate noise at the SK, DI, and CS pins. This
means that if the supply voltage is 5.0 V (at room temperature), noise with a pulse width of 20 ns or less can be
eliminated.
Note, therefore, the noise with a pulse width of more than 20 ns will be recognized as a pulse if the voltage
exceeds VIH / VIL.
Precaution
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
ABLIC Inc. claims no responsibility for any and all disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
23
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
Characteristics (Typical Data)
1.
DC Characteristics
1. 1 Current consumption (READ) ICC1
vs. ambient temperature Ta
1. 2 Current consumption (READ) ICC1
vs. ambient temperature Ta
VCC = 3.3 V
fSK = 500 kHz
DATA = 0101
VCC ! 5.5 V
fSK ! 2 MHz
DATA ! 0101
0.4
0.4
ICC1
(mA)
ICC1
(mA)
0.2
0.2
0
40
0
85
0
40
Ta ( C)
1. 4 Current consumption (READ) ICC1
vs. power supply voltage VCC
Ta = 25 C
fSK = 1 MHz, 500 kHz
DATA = 0101
VCC ! 1.8 V
fSK ! 10 kHz
DATA ! 0101
0.4
0.4
ICC1
(mA)
ICC1
(mA)
0.2
1 MHz
0.2
500 kHz
40
0
0
85
2
Ta ( C)
ICC1
(mA)
100 kHz
5 6
VCC (V)
24
0.2
0
10 kHz
4
6
0.4
0.2
3
5
VCC = 5.0 V
Ta = 25 C
0.4
2
4
1. 6 Current consumption (READ) ICC1
vs. Clock frequency fSK
Ta = 25 C
fSK = 100 kHz, 10 kHz
DATA = 0101
ICC1
(mA)
3
VCC (V)
1. 5 Current consumption (READ) ICC1
vs. power supply voltage VCC
0
85
Ta ( C)
1. 3 Current consumption (READ) ICC1
vs. ambient temperature Ta
0
0
7
10 k
100 k
1 M 2M 10M
fSK (Hz)
7
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
1. 7 Current consumption (WRITE) ICC2
vs. ambient temperature Ta
1. 8 Current consumption (WRITE) ICC2
vs. ambient temperature Ta
VCC = 3.3 V
VCC ! 5.5 V
1.0
1.0
ICC2
(mA)
ICC2
(mA)
0.5
0.5
0
0
40
0
85
40
0
Ta ( C)
Ta ( C)
1. 9 Current consumption (WRITE) ICC2
vs. ambient temperature Ta
85
1. 10 Current consumption (WRITE) ICC2
vs. power supply voltage VCC
VCC ! 2.7 V
Ta ! 25 C
1.0
1.0
ICC2
(mA)
ICC2
(mA)
0.5
0.5
0
40
0
0
85
2
3
Ta ( C)
1. 11 Current consumption in standby mode ISB
vs. ambient temperature Ta
5 6
7
1. 12 Current consumption in standby mode ISB
vs. power supply voltage VCC
Ta = 25 C
CS = GND
VCC = 5.5 V
CS = GND
1.0
ISB
( A)
ISB
( A)
1.0
0.5
0.5
0
4
VCC (V)
40
0
Ta (°C)
85
0
2
3
4
5 6
7
VCC (V)
25
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
1. 13 Input leakage current ILI
vs. ambient temperature Ta
1. 14 Input leakage current ILI
vs. ambient temperature Ta
VCC ! 5.5 V
CS, SK, DI,
TEST ! 5.5 V
VCC = 5.5 V
CS, SK, DI,
TEST = 0 V
1.0
1.0
ILI
( A)
lLI
( A)
0.5
0.5
0
0
-40
0
85
40
1. 16 Output leakage current ILO
vs. ambient temperature Ta
VCC = 5.5 V
DO = 5.5 V
VCC ! 5.5 V
DO ! 0 V
1.0
1.0
ILO
( A)
ILO
( A)
0.5
0
0.5
40
0
0
85
40
Ta ( C)
85
1. 18 High-level output voltage VOH
vs. ambient temperature Ta
VCC ! 2.7 V
IOH ! 100 A
2.7
VOH
(V)
4.4
2.6
2.5
4.2
40
0
Ta ( C)
26
0
Ta (°C)
1. 17 High-level output voltage VOH
vs. ambient temperature Ta
VCC = 4.5 V
IOH = 400 A
4.6
VOH
(V)
85
Ta ( C)
Ta ( C)
1. 15 Output leakage current ILO
vs. ambient temperature Ta
0
85
40
0
Ta ( C)
85
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
1. 19 High-level output voltage VOH
vs. ambient temperature Ta
2.5
VOH
(V)
1. 20 High-level output voltage VOH
vs. ambient temperature Ta
VCC ! 2.5 V
IOH ! 100 A
1.9
VOH
(V)
2.4
VCC = 1.8 V
IOH = 10 A
1.8
1.7
2.3
40
0
40
85
1. 21 Low-level output voltage VOL
vs. ambient temperature Ta
VOL
(V)
1. 22 Low-level output voltage VOL
vs. ambient temperature Ta
VCC ! 4.5 V
IOL ! 2.1 mA
0.03
0.2
VOL 0.02
(V)
0.1
0.01
40
0
85
Ta ( C)
Ta ( C)
0.3
0
85
VCC ! 1.8 V
IOL ! 100 A
40
0
85
Ta ( C)
Ta ( C)
1. 23 High-level output current IOH
vs. ambient temperature Ta
VCC ! 4.5 V
VOH ! 2.4 V
1. 24 High-level output current IOH
vs. ambient temperature Ta
VCC = 2.7 V
VOH = 2.4 V
20.0
2
IOH
(mA)
IOH
(mA)
10.0
0
1
40
0
Ta ( C)
85
0
40
0
85
Ta ( C)
27
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
1. 25 High-level output current IOH
vs. ambient temperature Ta
1. 26 High-level output current IOH
vs. ambient temperature Ta
VCC ! 2.5 V
VOH ! 2.2 V
VCC ! 1.8 V
VOH ! 1.6 V
2
1.0
IOH
(mA)
IOH
(mA)
1
0.5
0
0
40
0
85
40
Ta ( C)
85
Ta ( C)
1. 27 Low-level output current IOL
vs. ambient temperature Ta
1. 28 Low-level output current IOL
vs. ambient temperature Ta
VCC = 1.8 V
VOL = 0.1 V
VCC = 4.5 V
VOL = 0.4 V
1.0
20
IOL
(mA)
IOL
(mA)
0.5
10
0
0
Ta ( C)
40
0
85
1. 29 Input inverted voltage VINV
vs. power supply voltage VCC
40
0
Ta ( C)
85
1. 30 Input inverted voltage VINV
vs. ambient temperature Ta
VCC = 5.0 V
CS, SK, DI
Ta ! 25 C
CS, SK, DI
3.0
3.0
VINV
(V)
VINV
(V)
1.5
0
2.0
1
2
3
4 5
VCC (V)
28
0
6 7
0
40
0
Ta ( C)
85
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
2.0
2.0
VDET
(V)
VDET
(V)
1.0
0
1.0
40
0
Ta ( C)
85
0
40
0
85
Ta ( C)
29
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
2.
Rev.8.1_02
AC Characteristics
2. 1 Maximum operating frequency fMAX.
vs. power supply voltage VCC
2. 2 Write time tPR
vs. power supply voltage VCC
Ta ! 25 C
fMAX.
,^
Ta ! 25 C
2M
1M
4
tPR
(ms)
100k
2
10k
1
2
3
4
5
1
2
3
VCC (V)
2. 3 Write time tPR
vs. ambient temperature Ta
VCC = 3.0 V
6
tPR
(ms)
6
4
4
2
2
40
0
85
40
Ta ( C)
0
85
Ta ( C)
2. 5 Write time tPR
vs. ambient temperature Ta
2. 6 Data output delay time tPD
vs. ambient temperature Ta
VCC ! 2.7 V
VCC ! 4.5 V
tPR
(ms)
6
tPD
( s)
4
0.3
0.2
2
0.1
40
0
Ta ( C)
30
5 6
2. 4 Write time tPR
vs. ambient temperature Ta
VCC ! 5.0 V
tPR
(ms)
4
VCC (V)
85
40
0
Ta ( C)
85
7
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
2. 7 Data output delay time tPD
vs. ambient temperature Ta
2. 8 Data output delay time tPD
vs. ambient temperature Ta
VCC ! 2.7 V
tPD
( s)
VCC ! 1.8 V
0.6
tPD
( s)
1.5
0.4
1.0
0.2
0.5
40
0
Ta ( C)
85
40
0
85
Ta ( C)
31
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
Product Name Structure
1. Product name
1. 1 8-Pin SOP (JEDEC), 8-Pin TSSOP
S-93CxxB
x
0
I
-
xxxx
x
Environmental code
U:
Lead-free (Sn 100%), halogen-free
G:
Lead-free (for details, please contact our sales office)
Package name (abbreviation) and IC packing specifications
J8T1: 8-Pin SOP (JEDEC), Tape
T8T1: 8-Pin TSSOP, Tape
Operation temperature
40 C to 85 C
I:
Fixed
Pin assignment
D:
8-Pin SOP (JEDEC)
8-Pin TSSOP
R:
8-Pin SOP (JEDEC) (Rotated)
Product name
S-93C46B :
S-93C56B :
S-93C66B :
1 K-bit
2 K-bit
4 K-bit
1. 2 TMSOP-8, SNT-8A
S-93CxxB
D0
I
-
xxxx
U
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package name (abbreviation) and IC packing specifications
K8T3: TMSOP-8, Tape
I8T1: SNT-8A, Tape
Operation temperature
40 C to 85 C
I:
Fixed
Product name
S-93C46B :
S-93C56B :
S-93C66B :
32
1 K-bit
2 K-bit
4 K-bit
3-WIRE SERIAL E2PROM
S-93C46B/56B/66B
Rev.8.1_02
2.
Packages
Package Name
8-Pin SOP
(JEDEC)
8-Pin TSSOP
TMSOP-8
SNT-8A
Environmental code = G
Environmental code = U
Environmental code = G
Environmental code = U
Package
FJ008-A-P-SD
FJ008-A-P-SD
FT008-A-P-SD
FT008-A-P-SD
FM008-A-P-SD
PH008-A-P-SD
Drawing Code
Tape
Reel
FJ008-D-C-SD FJ008-D-R-SD
FJ008-D-C-SD FJ008-D-R-S1
FT008-E-C-SD FT008-E-R-SD
FT008-E-C-SD FT008-E-R-S1
FM008-A-C-SD FM008-A-R-SD
PH008-A-C-SD PH008-A-R-SD
Land
PH008-A-L-SD
33
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and application
circuit examples, etc.) is current as of publishing date of this document and is subject to change without notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein
(hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use
of the information described herein.
3.
ABLIC Inc. is not responsible for damages caused by the incorrect information described herein.
4.
Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings,
operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the
products outside their specified ranges.
5.
When using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products must not be used or provided (exported) for the purposes of the development of weapons of mass
destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to
develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do
not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc.
Especially, the products cannot be used for life support devices, devices implanted in the human body and devices
that directly affect human life, etc.
Prior consultation with our sales office is required when considering the above uses.
ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products.
9.
Semiconductor products may fail or malfunction with some probability.
The user of the products should therefore take responsibility to give thorough consideration to safety design including
redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or
death, fires and social damage, etc. that may ensue from the products' failure or malfunction.
The entire system must be sufficiently evaluated and applied on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc.
The information described herein does not convey any license under any intellectual property rights or any other
rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any
part of this document described herein for the purpose of disclosing it to a third-party without the express permission
of ABLIC Inc. is strictly prohibited.
14. For more details on the information described herein, contact our sales office.
2.0-2018.01
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