HI5960IB

HI5960 ® Data Sheet March 31, 2005 14-Bit, 130MSPS, High Speed D/A Converter FN4655.6 Features • Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 130MSPS The HI5960 is a 14-bit, 130MSPS (Mega Samples Per Second), high speed, low power, D/A converter which is implemented in an advanced CMOS process. Operating from a single +3V to +5V supply, the converter provides 20mA of full scale output current and includes edgetriggered CMOS input data latches. Low glitch energy and excellent frequency domain performance are achieved using a segmented current source architecture. • Low Power (at 100MSPS) at 5V . . . . . . . . . . . . . .175mW at 3V. . . . . . . . . . . . . . . .32mW • Adjustable Full Scale Output Current. . . . . 2mA to 20mA • Internal 1.2V Bandgap Voltage Reference • Single Power Supply from +5V to +3V • Power Down Mode This device complements the HI5x60 and HI5x28 family of high speed converters, which includes 8, 10, 12, and 14-bit devices. • CMOS Compatible Inputs Ordering Information • Excellent Multitone Intermodulation Distortion PART NUMBER TEMP. RANGE (oC) • Excellent Spurious Free Dynamic Range (77dBc, f S = 50MSPS, fOUT = 2.51MHz) • Pb-Free Available (RoHS Compliant) PACKAGE PKG. DWG. # CLOCK SPEED Applications HI5960IB -40 to 85 28 Ld SOIC M28.3 130MHz • Cellular Basestations HI5960IBZ (See Note) -40 to 85 28 Ld SOIC (Pb-free) M28.3 130MHz • WLL, Basestation and Subscriber Units HI5960IA -40 to 85 28 Ld TSSOP M28.173 130MHz HI5960IAZ (See Note) -40 to 85 28 Ld TSSOP M28.173 (Pb-free) 130MHz HI5960IA-T -40 to 85 28 Ld TSSOP M28.173 Tape and Reel 130MHz HI5960IAZ-T (See Note) -40 to 85 28 Ld TSSOP M28.173 Tape and Reel (Pb-free) 130MHz HI5960SOICEVAL1 25 Evaluation Platform • Wireless Communications Systems • Direct Digital Frequency Synthesis • High Resolution Imaging Systems • Arbitrary Waveform Generators Pinout 130MHz NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 • Medical/Test Instrumentation HI5960 (SOIC, TSSOP) TOP VIEW D13 (MSB) 1 28 CLK D12 2 27 DVDD D11 3 26 DCOM D10 4 25 ACOM D9 5 24 AVDD D8 6 23 COMP2 D7 7 22 IOUTA D6 8 21 IOUTB D5 9 20 ACOM D4 10 19 COMP1 D3 11 18 FSADJ D2 12 17 REFIO D1 13 16 REFLO D0 (LSB) 14 15 SLEEP CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003, 2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. HI5960 Typical Applications Circuit HI5960 D13 D13 (1) (25) ACOM D12 D12 (2) D11 D11 (3) (15) SLEEP (16) REFLO D10 D10 (4) D9 D9 (5) D8 D8 (6) D7 D7 (7) D6 D6 (8) D5 D5 (9) 0.1µF (18) FSADJ D4 (10) D3 D3 (11) D2 D2 (12) D1 D1 (13) D0 D0 (LSB) (14) (23) COMP2 CLK (28) (19) COMP1 10µH 10µF 1.91kΩ RSET (22) IOUTA D/A OUT 50Ω 50Ω (21) IOUTB DCOM (26) (20) ACOM DVDD (27) (24) AVDD BEAD + DCOM (17) REFIO D4 50Ω ACOM D/A OUT 0.1µF 0.1µF FERRITE BEAD + 10µH 0.1µF 0.1µF +5V OR +3V (VDD) 10µF Functional Block Diagram IOUTA IOUTB (LSB) D0 CASCODE D1 CURRENT SOURCE D2 D3 D4 LATCH D5 40 D6 LATCH SWITCH MATRIX D7 40 9 LSBs + 31 MSB SEGMENTS D8 D9 D10 D11 UPPER 5-BIT D12 DECODER 31 (MSB) D13 COMP2 COMP1 CLK AVDD ACOM DVDD 2 DCOM INT/EXT INT/EXT VOLTAGE REFERENCE SELECT REFERENCE REFLO REFIO BIAS GENERATION FSADJ SLEEP HI5960 Pin Descriptions PIN NO. PIN NAME DESCRIPTION 1-14 D13 (MSB) Through D0 (LSB) 15 SLEEP Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin has internal 20µA active pulldown current. 16 REFLO Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable internal reference. 17 REFIO Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled. Use 0.1µF cap to ground when internal reference is enabled. 18 FSADJ Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current = 32 x VFSADJ/RSET. 19 COMP1 For use in reducing bandwidth/noise. Recommended: connect 0.1µF to AVDD . 21 IOUTB The complimentary current output of the device. Full scale output current is achieved when all input bits are set to binary 0. 22 IOUTA Current output of the device. Full scale output current is achieved when all input bits are set to binary 1. 23 COMP2 Connect 0.1µF capacitor to ACOM. 24 AVDD Analog Supply (+3V to +5V). 20, 25 ACOM Connect to Analog Ground. 26 DCOM Connect to Digital Ground. 27 DVDD Digital Supply (+3V to +5V). 28 CLK Digital Data Bit 13, (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit). Clock Input. Input data to the DAC passes through the “master” latches when the clock is low and is latched into the “master” latches when the clock is high. Data presented to the “slave” latch passes through when the clock is logic high and is latched into the “slave” latches when the clock is logic low. Adequate setup time must be allowed for the MSBs to pass through the thermometer decoder before the clock goes high. This master-slave arrangement comprises an edge-triggered flip-flop, with the DAC being updated on the rising clock edge. It is recommended that the clock edge be skewed such that setup time is larger than the hold time. 3 HI5960 Absolute Maximum Ratings Thermal Information Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V Analog Supply Voltage AVDD to ACOM . . . . . . . . . . . . . . . . . +5.5V Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . DVDD + 0.3V Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA Thermal Resistance (Typical, Note 1) θJA(oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions HI5960IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 14 - - Bits SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL “Best Fit” Straight Line (Note 8) -5 ±2.5 +5 LSB Differential Linearity Error, DNL (Note 8) -3 ±1.5 +3 LSB Offset Error, IOS (Note 8) -0.025 +0.025 % FSR Offset Drift Coefficient (Note 8) - 0.1 - ppm FSR/oΧ Full Scale Gain Error, FSE With External Reference (Notes 2, 8) -10 ±2 +10 % FSR With Internal Reference (Notes 2, 8) -10 ±1 +10 % FSR With External Reference (Note 8) - ±50 - ppm FSR/οΧ With Internal Reference (Note 8) - ±100 - ppm FSR/οΧ 2 - 20 mA (Note 3, 8) -0.3 - 1.25 V Maximum Clock Rate, fCLK (Note 3) 130 - - MHz Output Settling Time, (tSETT) ±0.05% (±8 LSB) (Note 8) - 35 - ns Singlet Glitch Area (Peak Glitch) RL = 25Ω (Note 8) - 5 - pV•s Output Rise Time Full Scale Step - 2.5 - ns Output Fall Time Full Scale Step - 2.5 - ns - 10 - pF IOUTFS = 20mA - 50 - pA/√Hz IOUTFS = 2mA - 30 - pA/√Hz fCLK = 100MSPS, fOUT = 20.2MHz, 30MHz Span (Notes 4, 8) - 77 - dBc fCLK = 100MSPS, fOUT = 5.04MHz, 8MHz Span (Notes 4, 8) - 97 - dBc fCLK = 50MSPS, fOUT = 5.02MHz, 8MHz Span (Notes 4, 8) - 97 - dBc Full Scale Gain Drift Full Scale Output Current, IFS Output Voltage Compliance Range DYNAMIC CHARACTERISTICS Output Capacitance Output Noise AC CHARACTERISTICS +5V Power Supply Spurious Free Dynamic Range, SFDR Within a Window 4 HI5960 AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) Electrical Specifications PARAMETER TEST CONDITIONS +5V Power Supply Total Harmonic Distortion (THD) to Nyquist +5V Power Supply Spurious Free Dynamic Range, SFDR to Nyquist (fCLK/2) +5V Power Supply Multitone Power Ratio +3V Power Supply Spurious Free Dynamic Range, SFDR Within a Window +3V Power Supply Total Harmonic Distortion (THD) to Nyquist 5 MIN TYP MAX UNITS fCLK = 100MSPS, fOUT = 4.0MHz (Notes 4, 8) - -71 - dBc fCLK = 50MSPS, fOUT = 2.0MHz (Notes 4, 8) - -75 - dBc fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8) - -77 - dBc fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 8) - 56 - dBc fCLK = 130MSPS, fOUT = 10.1MHz (Notes 4, 8) - 67 - dBc fCLK = 130MSPS, fOUT = 5.02MHz, T = 25oC (Notes 4, 8) 68 74 - dBc fCLK = 130MSPS, fOUT = 5.02MHz, T = Min to Max (Notes 4, 8) 66 - - dBc fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 8) - 55 - dBc fCLK = 100MSPS, fOUT = 20.2MHz (Notes 4, 8) - 63 - dBc fCLK = 100MSPS, fOUT = 5.04MHz, T = 25oC (Notes 4, 8) 68 74 - dBc fCLK = 100MSPS, fOUT = 5.04MHz, T = Min to Max (Notes 4, 8) 66 - fCLK = 100MSPS, fOUT = 2.51MHz (Notes 4, 8) - 76 - dBc fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 8) - 65 - dBc fCLK = 50MSPS, fOUT = 5.02MHz, T = 25oC (Notes 4, 8) 68 74 - dBc fCLK = 50MSPS, fOUT = 5.02MHz, T = Min to Max (Notes 4, 8) 66 - - dBc fCLK = 50MSPS, fOUT = 2.51MHz (Notes 4, 8) - 77 - dBc fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 8) - 79 - dBc fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8) - 79 - dBc fCLK = 20MSPS, fOUT = 2.0MHz to 2.99MHz, 8 Tones at 110kHz Spacing (Notes 4, 8) - 76 - dBc fCLK = 100MSPS, fOUT = 10MHz to 14.95MHz, 8 Tones at 530kHz Spacing (Notes 4, 8) - 76 - dBc fCLK = 100MSPS, fOUT = 20.2MHz, 30MHz Span (Notes 4, 8) - 80 - dBc fCLK = 100MSPS, fOUT = 5.04MHz, 8MHz Span (Notes 4, 8) - 95 - dBc fCLK = 50MSPS, fOUT = 5.02MHz, 8MHz Span (Notes 4, 8) - 95 - dBc fCLK = 100MSPS, fOUT = 4.0MHz (Notes 4, 8) - -70 - dBc fCLK = 50MSPS, fOUT = 2.0MHz (Notes 4, 8) - -74 - dBc fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8) - -76 - dBc dBc HI5960 AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 8) - 48 - dBc fCLK = 130MSPS, fOUT = 10.1MHz (Notes 4, 8) - 66 - dBc fCLK = 130MSPS, fOUT = 5.02MHz (Notes 4, 8) - 74 - dBc fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 8) - 49 - dBc fCLK = 100MSPS, fOUT = 20.2MHz (Notes 4, 8) - 59 - dBc fCLK = 100MSPS, fOUT = 5.04MHz (Notes 4, 8) - 72 - dBc fCLK = 100MSPS, fOUT = 2.51MHz (Notes 4, 8) - 77 - dBc fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 8) - 56 - dBc fCLK = 50MSPS, fOUT = 5.02MHz, T = 25oC (Notes 4, 8) 68 73 - dBc fCLK = 50MSPS, fOUT = 5.02MHz, T = Min to Max (Notes 4, 8) 66 - - dBc fCLK = 50MSPS, fOUT = 2.51MHz (Notes 4, 8) - 76 - dBc fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 8) - 79 - dBc fCLK = 25MSPS, fOUT = 1.0MHz (Notes 4, 8) - 78 - dBc fCLK = 20MSPS, fOUT = 2.0MHz to 2.99MHz, 8 Tones at 110kHz Spacing (Notes 4, 8) - 75 - dBc fCLK = 100MSPS, fOUT = 10MHz to 14.95MHz, 8 Tones at 530kHz Spacing (Notes 4, 8) - 77 - dBc 1.13 1.2 1.28 V Internal Reference Voltage Drift - ±60 - ppm/οΧ Internal Reference Output Current Sink/Source Capability - ±50 - µA Reference Input Impedance - 1 - MΩ Reference Input Multiplying Bandwidth (Note 8) - 1.4 - MHz +3V Power Supply Spurious Free Dynamic Range, SFDR to Nyquist (fCLK/2) +3V Power Supply Multitone Power Ratio VOLTAGE REFERENCE Internal Reference Voltage, VFSADJ DIGITAL INPUTS Pin 18 Voltage with Internal Reference D11-D0, CLK Input Logic High Voltage with 5V Supply, VIH (Note 3) 3.5 5 - V Input Logic High Voltage with 3V Supply, VIH (Note 3) 2.1 3 - V Input Logic Low Voltage with 5V Supply, VIL (Note 3) - 0 1.3 V Input Logic Low Voltage with 3V Supply, VIL (Note 3) - 0 0.9 V Sleep Input Current, IIH -25 - +25 µA Input Logic Current, IIH -20 - +20 µA Input Logic Current, IIL -10 - +10 µA - 5 - pF Digital Input Capacitance, CIN TIMING CHARACTERISTICS Data Setup Time, tSU See Figure 4 (Note 3) - 1.5 - ns Data Hold Time, tHLD See Figure 4 (Note 3) - 1.2 - ns Propagation Delay Time, tPD See Figure 4 - 2.5 - ns CLK Pulse Width, tPW1 , tPW2 See Figure 4 (Note 3) 4 - - ns 6 HI5960 AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values (Continued) Electrical Specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNITS POWER SUPPLY CHARACTERISTICS AVDD Power Supply (Notes 9) 2.7 5.0 5.5 V DVDD Power Supply (Notes 9) 2.7 5.0 5.5 V Analog Supply Current (IAVDD) 5V or 3V, IOUTFS = 20mA - 23 - mA 5V or 3V, IOUTFS = 2mA - 5 - mA 5V (Note 5) - 7 - mA 5V (Note 6) - 13 - mA 5V (Note 7) - 10 - mA 3V (Note 5) - 2 - mA 3V (Note 6) - 6 - mA 3V (Note 7) - 5 - mA Supply Current (IAVDD) Sleep Mode 5V or 3V, IOUTFS = Don’t Care - 2.7 - mA Power Dissipation 5V, IOUTFS = 20mA (Note 5) - 150 - mW 5V, IOUTFS = 20mA (Note 6) - 180 200 mW 5V, IOUTFS = 20mA (Note 7) - 165 - mW 5V, IOUTFS = 2mA (Note 6) - 80 - mW 3V, IOUTFS = 20mA (Note 5) - 75 - mW 3V, IOUTFS = 20mA (Note 6) - 87 100 mW 3V, IOUTFS = 20mA (Note 7) - 84 - mW 3V, IOUTFS = 2mA (Note 6) - 32 - mW -0.2 - +0.2 % FSR/V Digital Supply Current (IDVDD) Power Supply Rejection Single Supply (Note 8) NOTES: 2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625µA). Ideally the ratio should be 32. 3. Parameter guaranteed by design or characterization and not production tested. 4. Spectral measurements made with differential transformer coupled output and no external filtering. 5. Measured with the clock at 50MSPS and the output frequency at 10MHz. 6. Measured with the clock at 100MSPS and the output frequency at 40MHz. 7. Measured with the clock at 130MSPS and the output frequency at 10MHz. 8. See “Definition of Specifications”. 9. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DVDD and AVDD do not have to be equal. 7 HI5960 Definition of Specifications Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. Full Scale Gain Drift, is measured by setting the data inputs to be all logic high (all 1s) and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (full scale range) per oC. Full Scale Gain Error, is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through RSET). Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Internal Reference Voltage Drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm per oC. Offset Drift, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (full scale range) per degree oC. Offset Error, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage through a known resistance. Offset error is defined as the maximum deviation of the output current from a value of 0mA. Output Settling Time, is the time required for the output voltage to settle to within a specified error band measured from the beginning of the output transition. The measurement is done by switching quarter scale. Termination impedance was 25Ω due to the parallel resistance of the 50Ω loading on the output and the oscilloscope’s 50Ω input. This also aids the ability to resolve the specified error band without overdriving the oscilloscope. Output Voltage Compliance Range, is the voltage limit imposed on the output. The output impedance should be chosen such that the voltage developed does not violate the compliance range. Power Supply Rejection, is measured using a single power supply. The supply’s nominal +5V is varied ±10% and the change in the DAC full scale output is noted. Reference Input Multiplying Bandwidth, is defined as the 3dB bandwidth of the voltage reference input. It is measured 8 by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. The frequency is increased until the amplitude of the output waveform is 0.707 (-3dB) of its original value. Singlet Glitch Area, is the switching transient appearing on the output during a code transition. It is measured as the area under the overshoot portion of the curve and is expressed as a Volt-Time specification. This is tested using a single code transition across a major current source. Spurious Free Dynamic Range, SFDR, is the amplitude difference from the fundamental signal to the largest harmonically or non-harmonically related spur within the specified frequency window. Total Harmonic Distortion, THD, is the ratio of the RMS value of the fundamental output signal to the RMS sum of the first five harmonic components. Detailed Description The HI5960 is a 14-bit, current out, CMOS, digital to analog converter. Its maximum update rate is 130MSPS and can be powered by either single or dual power supplies in the recommended range of +3V to +5V. Operation with clock rates higher than 130MSPS is possible; please contact the factory for more information. It consumes less than 180mW of power when using a +5V supply with the data switching at 130MSPS. The architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. In previous architectures that contained all binary weighted current sources or a binary weighted resistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worst-case transition points such as midscale and quarter scale transitions. By greatly reducing the amount of current switching at certain “major” transitions, the overall glitch of the converter is dramatically reduced, improving settling time, transient problems, and accuracy. Digital Inputs and Termination The HI5960 digital inputs are guaranteed to CMOS levels. However, TTL compatibility can be achieved by lowering the supply voltage to 3V due to the digital threshold of the input buffer being approximately half of the supply voltage. The internal register is updated on the rising edge of the clock. To minimize reflections, proper termination should be implemented. If the lines driving the clock and the digital inputs are long 50Ω lines, then 50Ω termination resistors should be placed as close to the converter inputs as possible connected to the digital ground plane (if separate grounds are used). These termination resistors are not likely needed as long as the digital waveform source is within a few inches of the DAC. Ground Planes Separate digital and analog ground planes should be used. All of the digital functions of the device and their HI5960 corresponding components should be located over the digital ground plane and terminated to the digital ground plane. The same is true for the analog components and the analog ground plane. Consult Application Note 9853. Noise Reduction To minimize power supply noise, 0.1µF capacitors should be placed as close as possible to the converter’s power supply pins, AVDD and DVDD . Also, the layout should be designed using separate digital and analog ground planes and these capacitors should be terminated to the digital ground for DVDD and to the analog ground for AVDD . Additional filtering of the power supplies on the board is recommended. Voltage Reference The internal voltage reference of the device has a nominal value of +1.2V with a ±60ppm/ oC drift coefficient over the full temperature range of the converter. It is recommended that a 0.1µF capacitor be placed as close as possible to the REFIO pin, connected to the analog ground. The REFLO pin (16) selects the reference. The internal reference can be selected if pin 16 is tied low (ground). If an external reference is desired, then pin 16 should be tied high (the analog supply voltage) and the external reference driven into REFIO, pin 17. The full scale output current of the converter is a function of the voltage reference used and the value of RSET . IOUT should be within the 2mA to 20mA range, though operation below 2mA is possible, with performance degradation. If the internal reference is used, VFSADJ will equal approximately 1.2V (pin 18). If an external reference is used, VFSADJ will equal the external reference. The calculation for IOUT (Full Scale) is: IOUT(Full Scale) = (VFSADJ/RSET) X 32. If the full scale output current is set to 20mA by using the internal voltage reference (1.2V) and a 1.91kΩ RSET resistor, then the input coding to output current will resemble the following: TABLE 1. INPUT CODING vs OUTPUT CURRENT INPUT CODE (D13-D0) IOUTA (mA) IOUTB (mA) 1111 11111 11111 20 0 1000 00000 00000 10 10 0000 00000 00000 0 20 Outputs IOUTA and IOUTB are complementary current outputs. The sum of the two currents is always equal to the full scale output current minus one LSB. If single ended use is desired, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be either grounded or equally terminated. The voltage developed at the output must not violate the output voltage compliance range of -0.3V to 1.25V. RLOAD (the impedance 9 loading each current output) should be chosen so that the desired output voltage is produced in conjunction with the output full scale current. If a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. The output voltage equation is: VOUT = IOUT X RLOAD . These outputs can be used in a differential-to-single-ended arrangement to achieve better harmonic rejection. The SFDR measurements in this data sheet were performed with a 1:1 transformer on the output of the DAC (see Figure 1). With the center tap grounded, the output swing of pins 21 and 22 will be biased at zero volts. The loading as shown in Figure 1 will result in a 500mV signal at the output of the transformer if the full scale output current of the DAC is set to 20mA. REQ IS THE IMPEDANCE LOADING EACH OUTPUT 50Ω VOUT = (2 x IOUT x REQ)V IOUTB PIN 21 100Ω PIN 22 HI5960 50Ω IOUTA 50Ω 50Ω REPRESENTS THE SPECTRUM ANALYZER FIGURE 1. VOUT = 2 x IOUT x REQ, where REQ is ~12.5Ω. Allowing the center tap to float will result in identical transformer output, however the output pins of the DAC will have positive DC offset. Since the DAC’s output voltage compliance range is 0.3V to +1.25V, the center tap may need to be left floating or DC offset in order to increase the amount of signal swing available. The 50Ω load on the output of the transformer represents the spectrum analyzer’s input impedance. HI5960 Timing Diagrams 50% CLK D13-D0 GLITCH AREA = 1/2 (H x W) V HEIGHT (H) ERROR BAND IOUT t(ps) WIDTH (W) tSETT tPD FIGURE 2. OUTPUT SETTLING TIME DIAGRAM tPW1 FIGURE 3. PEAK GLITCH AREA (SINGLET) MEASUREMENT METHOD tPW2 50% CLK tSU tSU tHLD tSU tHLD tHLD D13-D0 tPD tSETT IOUT tPD tSETT tPD tSETT FIGURE 4. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 10 HI5960 Small Outline Plastic Packages (SOIC) M28.3 (JEDEC MS-013-AE ISSUE C) N 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B- 1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M B S 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 11 MILLIMETERS MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 0.05 BSC 10.00 h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 8o 0o 28 0o 10.65 - 0.394 N 0.419 1.27 BSC H α NOTES: MAX A1 e α MIN 28 - 7 8o Rev. 0 12/93 HI5960 Thin Shrink Small Outline Plastic Packages (TSSOP) M28.173 N INDEX AREA E 0.25(0.010) M E1 2 INCHES GAUGE PLANE -B1 28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE B M 3 L 0.05(0.002) -A- 0.25 0.010 SEATING PLANE A D -C- α e A2 A1 b c 0.10(0.004) 0.10(0.004) M C A M B S SYMBOL MIN MAX MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.378 0.386 9.60 9.80 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC E 0.246 L 0.0177 N α NOTES: MILLIMETERS 0.65 BSC 0.256 6.25 0.0295 0.45 28 0o - 0.75 6 28 8o 0o - 6.50 7 8o 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AE, Issue E. Rev. 0 6/98 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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