LS8297CT-S

LSI/CSI UL ® LS8297 LS8297CT LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 A3800 STEPPER MOTOR CONTROLLER The LS8297 Stepper Motor Controller generates four phase drive signal outputs for controlling two phase Bipolar and four phase Unipolar motors. The outputs are used to drive two H-bridges for the two motor windings in the Bipolar motor or the four driver transistors for the two center- tapped windings in the Unipolar motor. The motor can be driven in full step mode either in normal drive (two-phase-on) or wave drive (one-phase-on) and half step mode. The LS8297 provides two inhibit outputs which are used to control the driver stages of each of the motor phases. The circuit uses STEP, FRD/REV and HALF/FULL inputs in a translator to generate controls for the output stages. A dual PWM chopper circuit using an on-chip oscillator, latches and voltage comparators are used to regulate the current in the motor windings. For each pair of phase driver outputs (PHA, PHB, and PHC, PHD) each pulse of the common internal oscillator sets the latch and enables the output. If the current in the motor winding causes the voltage across a sense resistor to exceed the reference voltage, VREF, at the comparator inputs, the latch is reset disabling the output until the next oscillator pulse. The CONTROL input determines whether the chopper acts on the phase driver outputs or the inhibit outputs. When the phase lines are chopped, the non-active phase line of each pair (PHA, PHB or PHC, PHD) is activated rather than de-activating the active line to reduce dissipation in the load sensing resistors. Refer to Figure 5B for Bipolar motors. If PHA is high and PHB is low, current flows through Q1, motor winding, Q4 and sense resistor Rs. When chopping occurs, PHB is brought high and circulating current flows through Q1 and D3 and not through Rs resulting in less power dissipation in Rs. Current decay is slow using this method. When the Control input is brought low, chopping occurs by bringing INH1 low. In this case circulating current flows through D2, motor winding and D3 and through the power supply to ground causing the current to decay rapidly. For Unipolar motors, only inhibit chopping is used. Refer to Figure 6. When INH1 is brought low 8297-042009-1 20 RESET 2 19 HALF/FULL HOME 3 18 STEP PHA 4 17 FWD/REV INH1 5 16 OSC 15 VREF SYNC 1 V SS LS8297 LS8297CT DESCRIPTION: PIN ASSIGNMENT TOP VIEW LSI FEATURES: • Controls Bipolar and Unipolar Motors • Cost-effective, low current, pin compatible replacement for L297 • Torque ripple compensated half-steps - LS8297CT • Half and full step modes • Normal/wave drive • Direction control • Reset input • Step control input • Enable input • PWM chopper circuit for current control • Two over current sensor comparators with external references input • All inputs and outputs TTL/CMOS compatible (TTL for 5V operation) • Supply current < 400uA • 4.75 to 7V Operation (VDD – VSS). • LS8297 (DIP), LS8297-S (SOIC), LS8297-TS (TSSOP) LS8297CT (DIP), LS8297CT-S (SOIC), LS8297CT-TS (TSSOP) – See Figure 1 – April 2009 PHB 6 PHC 7 14 SENSE1 INH2 8 13 SENSE2 PHD 9 12 V DD ENABLE 10 11 CONTROL FIGURE 1 current in either half of the center tapped motor winding recirculates through the diode across it. LS8297CT is the torque ripple compensated version of the LS8297. Torque imbalance resulting from alternating “onephase on”, “two-phase on” sequence of the half-step mode (see Figure 4) is eliminated in the LS8297CT by switching the sense reference voltage between 100% and 70.7% in alternate steps. INPUT/OUTPUT DESCRIPTION: OSC Input An RC input with the resistor connected to VDD and the capacitor connected to ground determines the oscillator chopper rate. When connected as an oscillator, the oscillator output appears as a negative-going pulse at the Sync pin. If the Oscillator pin is tied to ground, the Sync pin becomes an input. Osc frequency, fosc = 1/0.69RC SYNC As an output the Sync can be used to drive Sync pins of other LS8297s. This eliminates the need for RC components for any other LS8297 controllers used in the system. As an input the Sync can be driven by the LS8297 that has the RC oscillator components or by any other system external clock. PHA/PHB/PHC/PHD Phase drive output signals for power stages. In a Bipolar motor PHA and PHB are used for one H-bridge while PHC and PHD are used for the other. STEP Input An active low pulse on this input causes the motor to advance one step. The step occurs on the rising edge of the step signal. INH1/INH2 Outputs These outputs are active low inhibit controls for motor drive outputs. INH1 controls driver stage using PHA and PHB signals while INH2 control driver stage using PHC and PHD signals. When the Control input is low, these outputs are chopped using the internal oscillator for current regulating. FRD/REV Input A logic 1 on this input causes the motor to advance through the stepping sequence of Fig. 4. A logic 0 on this input cause the motor to reverse the sequence. CONTROL Input When high, the phase outputs, PHA, PHB, PHC and PHD are chopped. When low, INH1 and INH2 are chopped. Normally, inhibit outputs are chopped. Phase chopping might be used with a Bipolar motor that does not store much energy to prevent fast current decay and a low useful torque. ENABLE Input When Enable input is low, INH1, INH2, PHA, PHB, PHC and PHD are brought low. HOME Output An open drain output that indicates when the LS8297 is in its initial state with PHA, PHB, PHC, PHD = logic states 0101 respectively. Refer to Figure 4. In the active state the open drain device is off. VDD 12 VSS RESET Input An active low on this input cause the motor to be restored to the home position (0101). HALF/FULL Input When high, half-step operation is selected. When low, fullstep operation is selected. One-phase on full step is selected by selecting full when stepping sequence is at an even state. Two-phase on full step operation is selected when stepping sequence is at an odd state. Refer to Figure 4. SENSE1/ SENSE2 Inputs Inputs for load current sense voltages from power stages using PHA and PHB drive signals or PHC and PHD drive signals, respectively. VREF Reference voltage for chopper circuit which determines the peak load current. PHA INH1 PHB PHC INH2 2 4 5 6 7 8 PHD 9 +V HALF/FULL 19 RESET 20 FWD/REV 17 STEP TRANSLATOR Q S FF1 R 11 CONTROL 18 + - 3 S Q FF2 R 1 + OSC MUX 15 14 13 16 VREF SENSE1 SENSE2 OSC FIGURE 2. LS8297/LS8297CT BLOCK DIAGRAM 8297-091608-2 ENABLE OUTPUT LOGIC x0.707 HOME 10 SYNC ABSOLUTE MAXIMUM RATINGS Symbol VS Vi TSTG, TJ Parameter Value Supply Voltage Input Signals Storage and Junction Temperatures Unit 10 7 -40 to +150 V V °C ELECTRICAL CHARACTERISTICS: (Refer to Block Diagram, Figure 2, and Timing Diagram, Figure 3) TA = +25°C, VDD = +5V unless otherwise specified. Parameter Symbol Minimum Typical Maximum Unit Condition (Pin 12) Supply Voltage Quiscent Supply Current VDD IDD 4.75 - 300 7 400 V uA Outputs floating (Pins 11, 17, 18, 19, 20) Input Voltage Low Input Voltage High Input Current Input Current VIL VIH II II 0 2 - - 0.75 VDD 50 50 V V nA nA VI = VIL VI = VIH (Pin 10) Enable Input Voltage Low Enable Input Voltage High Enable Input Current Enable Input Current VENL VENH IEN IEN 0 2 - - 1.3 VDD 50 50 V V nA nA VEN = VENL VEN = VENH (Pins 4, 6, 7, 9) Phase Output Voltage Low VOL Phase Output Voltage High VOH 4.0 - 0.5 - V V IO = -10mA IO = 5mA (Pins 5, 8) Inhibit Output Voltage Low VInhL Inhibit Output Voltage High VInhH 4.0 - 0.5 - V V IO = -10mA IO = 5mA (Pin 3) Leakage Current Saturation Voltage - - 1 0.4 uA V VO = VDO = 7V I = 5mA 100 5 - 10 mV uA VREF = 1V - VREF IREF 0 - - 3 8 V uA VREF = 3V Clock Time Step Pulse Width tstp 0.5 - - us - Set up time tS 1 - - us - Hold time tH 4 - - us - Reset time tR 1 - - us - Reset to Step delay tRStp 1 - - us - (Pin 16) Oscillator: Sawtooth Low VSOL - 2.1 - V - Sawtooth High VSOH - 3.65 - V - Frequency fOSC - 30 - kHz R = 22kΩ, C = 3.3nF ILeak VSat (Pins 13, 14, 15) Comparators Offset Voltage VOff Comparator Bias Current IO (Pin 15) Input Reference Voltage Input Current 8297-040109-3 - Parameter Symbol Minimum Typical Maximum Unit Condition (Pin 1) Sync: Sync Output Voltage Low Sync Output Voltage High VSyncL VSyncH 3.0 - 0.8 - V V IO = -5mA IO = 5mA Sync Input Pulse Width TSPW - 3.3 - us R = 22kΩ, C = 3.3nF Sync Input Switching Point TSSP - 2.0 - V Pin 16 < 1.0V Sync Input Current IIS - -425 - uA Pin 16 < 1.0V, VIN = VDD STEP t STP FWD/REV HALF/FULL tS tH RESET tR t RSTP FIGURE 3. Input Timing Diagram 8297-040109-4 1001 4 3 1 STEP 1000 5 2 3 4 5 6 7 8 1 2 3 4 5 1010 A B 2 0001 6 0010 C 0101 1 7 8 HOME 0110 D INH1 0100 INH2 FIGURE 4A. HALF-STEP MODE STEP 1001 1 3 5 7 1 3 5 7 1 3 5 7 1010 3 4 5 A B 2 6 C 0101 HOME 1 8 D 7 0110 INH1 0 INH2 0 FIGURE 4B. NORMAL DRIVE MODE (TWO-PHASE-ON) STEP 1000 3 0001 4 2 5 6 2 4 6 8 2 4 6 8 2 4 6 8 A 0010 B C D 1 8 7 0100 INH1 INH2 FIGURE 4C. WAVE DRIVE MODE (ONE-PHASE-ON) FIGURE 4. MOTOR DRIVING SEQUENCES The LS8297 generates phase sequences for half-step mode, normal drive mode and wave drive mode. Advancing occurs on the positive edge of the STEP input signal. HOME is defined as PHA, PHB, PHC, PHD being 0101, respectively. The State Diagrams showing the phase output polarities for all states are shown above for clockwise rotation. For counter clockwise rotation, the sequences are reversed. RESET restores the phases to 0101 and State 1. 7297-081208-5 5V VM V DD 19 20 CONTROL RESET 18 MCU INH1 HALF/FULL 11 17 10 INH2 PHA STEP FRD/REV PHB ENABLE PHC PHD V DD 22k 16 4 9 12 5 6 8 11 4 5 6 7 7 10 9 12 V DD INH1 VS 2 OUT1 INH2 PHA OUT2 PHB OUT3 3 13 STEPPER MOTOR WINDINGS PHC 14 OUT4 PHD LS8297 LS8297CT L298 OSC 3.3nF SENSE1 SENSE2 VREF SENSEB V SS SENSEA 2 14 1 13 15 R VSS 15 8 R Note: The SENSE resistors on L298 should be chosen so that IMAX = V REF/R, where IMAX is the maximum motor winding current. See Note FIGURE 5A. Typical Application Schematic for a Two-Phase Bipolar Motor Using a Single Motor Driver IC VM PHA INH1 Q1 D1 D3 Q3 Q2 D2 D4 Q4 SENSE1 R FIGURE 5B. One half of L298 Drive Stage 8297-040309-6 PHB 5V VM 12 19 11 20 18 MCU 17 10 V DD PHA HALF/FULL PHB INH1 CONTROL 4 6 4 5 STEP SENSE1 Q1 3 2 5 RESET FRD/REV 1 74HC08 6 Q2 14 ENABLE R 22k V DD 16 LS8297 LS8297CT OSC 3.3nF VM PHC PHD INH2 7 9 8 9 10 12 13 8 Q3 74HC08 11 Q4 2 SENSE2 V SS VREF 13 15 NOTE: Q1, Q2, Q3, Q4 are MOSFET Power Transistors suitable for 5V Gate Drive Typical P/Ns = IRLZ44N and IRF3708 FIGURE 6. TYPICAL APPLICATION SCHEMATIC FOR A FOUR-PHASE UNIPOLAR MOTOR USING DISCRETE MOSFET TRANSISTORS 7297-090908-7 R +V R 16 1 1 1 SYNC SYNC SYNC LS8297 LS8297CT LS8297 LS8297CT LS8297 LS8297CT OSC 16 OSC 16 C FIGURE 7. Synchronizing Multiple LS8297s The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. 7297-041309-8 OSC