S-576Z B Series
www.ablic.com
125°C OPERATION,
HIGH-WITHSTAND VOLTAGE, HIGH-SPEED,
ZCLTM HALL EFFECT IC
Rev.1.1_00
© ABLIC Inc., 2019-2020
This IC, developed by CMOS technology, is a high-accuracy Hall effect IC that operates with high temperature and
high-withstand voltage.
The IC switches output voltage level when the IC detects magnetic flux density (magnetic field) polarity changes. The ZCL
(Zero Crossing Latch) detection method realizes polarity changes detection with the higher accuracy than the conventional
bipolar latch method. Using this IC with a magnet makes it possible to detect the rotation status in various devices.
ABLIC Inc. offers a "magnetic simulation service" that provides the ideal combination of magnets and our Hall effect ICs
for customer systems. Our magnetic simulation service will reduce prototype production, development period and
development costs. In addition, it will contribute to optimization of parts to realize high cost performance.
For more information regarding our magnetic simulation service, contact our sales representatives.
Features
• Uses a thin (t0.80 mm max.) TSOT-23-3S or ultra-thin (t0.50 mm max.) HSNT-6(2025) package, allowing for device
miniaturization
• Contributes to reduction of mechanism operation dispersion through high accuracy detection of magnetic flux density
(magnetic field) polarity changes
• Contributes to device safe design with a built-in output current limit circuit
Specifications
• Pole detection:
• Output logic*1:
• Output form*1:
• Zero crossing latch point:
• Release point (S pole)*1:
Applications
ZCL detection
VOUT = "L" at S pole detection
VOUT = "H" at S pole detection
Nch open-drain output
Nch driver + built-in pull-up resistor (1.2 kΩ typ.)
BZ = 0.0 mT typ.
BRS = 3.0 mT typ.
BRS = 6.0 mT typ.
fC = 500 kHz typ.
tD = 8.0 μs typ.
VDD = 2.7 V to 26.0 V
• Chopping frequency:
• Output delay time:
• Power supply voltage range*2:
• Built-in regulator
• Built-in output current limit circuit
• Operation temperature range:
Ta = −40°C to +125°C
• Lead-free (Sn 100%), halogen-free
• DC brushless motor
• Home appliance
• Housing equipment
• Industrial equipment
Packages
• TSOT-23-3S
• HSNT-6(2025)
*1. The option can be selected.
*2. VDD = 2.7 V to 5.5 V when output form is Nch driver + built-in pull-up resistor (1.2 kΩ typ.)
1
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
S-576Z B Series
Rev.1.1_00
Block Diagrams
1.
Nch open-drain output product
VDD
Regulator
Chopper
stabilized
amplifier
*1
OUT
Output current limit circuit
VSS
*1. Parasitic diode
Figure 1
2.
Nch driver + built-in pull-up resistor product
VDD
Regulator
OUT
Chopper
stabilized
amplifier
*1
Output current limit circuit
VSS
*1. Parasitic diode
Figure 2
2
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
Rev.1.1_00
S-576Z B Series
Product Name Structure
1.
Product name
S-576Z
x
x x B - xxxx U
Environmental code
U: Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
L3T2: TSOT-23-3S, Tape
A6T8: HSNT-6(2025), Tape
Operation temperature
B: Ta = −40°C to +125°C
Release point (S pole)
1: BRS = 3.0 mT typ.
2: BRS = 6.0 mT typ.
Output logic
L: VOUT = "L" at S pole detection
H: VOUT = "H" at S pole detection
Output form
N: Nch open-drain output
1: Nch driver + built-in pull-up resistor (1.2 kΩ typ.)
*1. Refer to the tape drawing.
2.
Packages
Table 1
Package Name
TSOT-23-3S
HSNT-6(2025)
Dimension
MP003-E-P-SD
PJ006-B-P-SD
Package Drawing Codes
Tape
MP003-E-C-SD
PJ006-B-C-SD
Reel
MP003-E-R-SD
PJ006-B-R-SD
Land
−
PJ006-B-LM-SD
Stencil Opening
−
PJ006-B-LM-SD
3
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
S-576Z B Series
Rev.1.1_00
3.
Product name list
3. 1
TSOT-23-3S
Table 2
Output Form
Product Name
Power Supply
Voltage Range
S-576ZNL1B-L3T2U
Nch open-drain output
S-576Z1L1B-L3T2U
Nch driver + built-in pull-up resistor
VDD = 2.7 V to 5.5 V
(1.2 kΩ typ.)
Remark
3. 2
VDD = 2.7 V to 26.0 V
Output Logic
VOUT = "L" at
S pole detection
VOUT = "L" at
S pole detection
Release Point (S pole)
(BRS)
3.0 mT typ.
3.0 mT typ.
Please contact our sales representatives for products other than the above.
HSNT-6(2025)
Table 3
Product Name
Output Form
S-576ZNL1B-A6T8U Nch open-drain output
S-576Z1L1B-A6T8U
Remark
4
Power Supply
Voltage Range
VDD = 2.7 V to 26.0 V
Nch driver + built-in pull-up resistor
VDD = 2.7 V to 5.5 V
(1.2 kΩ typ.)
Output Logic
VOUT = "L" at
S pole detection
VOUT = "L" at
S pole detection
Please contact our sales representatives for products other than the above.
Release Point (S pole)
(BRS)
3.0 mT typ.
3.0 mT typ.
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
Rev.1.1_00
S-576Z B Series
Pin Configurations
1.
TSOT-23-3S
Top view
Table 4
1
Pin No.
1
2
3
2
Symbol
Description
GND pin
Power supply pin
Output pin
VSS
VDD
OUT
3
Figure 3
2.
HSNT-6(2025)
Top view
1
2
3
Table 5
6
5
4
Bottom view
6
5
4
1
2
3
Pin No.
1
2
3
4
5
6
Symbol
VDD
NC*2
OUT
NC*2
VSS
NC*2
Description
Power supply pin
No connection
Output pin
No connection
GND pin
No connection
*1
Figure 4
*1. Connect the heatsink of backside at shadowed area to the board, and set electric potential open or GND.
However, do not use it as the function of electrode.
*2. The NC pin is electrically open.
The NC pin can be connected to the VDD pin or the VSS pin.
5
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
S-576Z B Series
Rev.1.1_00
Absolute Maximum Ratings
Table 6
Item
Power supply voltage
Symbol
Nch open-drain output product
Nch driver + built-in pull-up resistor
(1.2 kΩ typ.) product
VDD
Power supply current
Output current
IDD
IOUT
Nch open-drain output product
Output voltage
Nch driver + built-in pull-up resistor
(1.2 kΩ typ.) product
Operation ambient temperature
Storage temperature
Caution
VOUT
Topr
Tstg
Absolute Maximum Rating
VSS − 0.3 to VSS + 28.0
Unit
VSS − 0.3 to VSS + 9.0
V
±10
±10
VSS − 0.3 to VSS + 28.0
mA
mA
V
VSS − 0.3 to VDD + 0.3
V
−40 to +125
−40 to +150
°C
°C
V
The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
Thermal Resistance Value
Table 7
Item
Symbol
Condition
TSOT-23-3S
Junction-to-ambient thermal resistance*1 θJA
HSNT-6(2025)
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A
Remark
6
Refer to " Power Dissipation" and "Test Board" for details.
Board A
Board B
Board C
Board D
Board E
Board A
Board B
Board C
Board D
Board E
Min.
−
−
−
−
−
−
−
−
−
−
Typ.
225
190
−
−
−
180
128
43
44
36
Max.
−
−
−
−
−
−
−
−
−
−
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
Rev.1.1_00
S-576Z B Series
Electrical Characteristics
1.
Nch open-drain output product
Table 8
(Ta = +25°C, VDD = 12.0 V, VSS = 0 V unless otherwise specified)
Item
Power supply voltage
Current consumption
Low level output voltage
Leakage current
Output limit current
Output delay time*1
Chopping frequency*1
Start up time*1
Output rise time*1
Output fall time*1
*1.
2.
Symbol
VDD
IDD
VOL
ILEAK
IOM
tD
fC
tPON
tR
tF
Condition
Min.
Typ.
Max.
Unit
−
−
2.7
−
−
−
11
−
250
−
−
−
12.0
4.0
−
−
−
8
500
25
−
−
26.0
4.5
0.4
1.0
35
16
−
40
1.0
1.0
V
mA
V
μA
mA
μs
kHz
μs
μs
μs
IOUT = 5 mA, VOUT = "L"
VOUT = "H"
VOUT = 12.0 V
−
−
−
C = 20 pF, R = 820 Ω
C = 20 pF, R = 820 Ω
Test
Circuit
−
1
2
3
3
−
−
4
5
5
This item is guaranteed by design.
Nch driver + built-in pull-up resistor (1.2 kΩ typ.) product
Table 9
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Item
Power supply voltage
Current consumption
Low level output voltage
High level output voltage
Output limit current
Output delay time*1
Chopping frequency*1
Start up time*1
Output rise time*1
Output fall time*1
Pull-up resistor
*1.
Symbol
VDD
IDD
VOL
VOH
IOM
tD
fC
tPON
tR
tF
RL
Condition
−
VOUT = "H"
IOUT = 0 mA, VOUT = "L"
IOUT = 0 mA, VOUT = "H"
VDD = VOUT = 5.0 V
−
−
−
C = 20 pF
C = 20 pF
−
Min.
Typ.
Max.
Unit
2.7
−
−
VDD × 0.9
11
−
250
−
−
−
0.9
5.0
4.0
−
−
−
8
500
25
−
−
1.2
5.5
4.5
0.4
−
35
16
−
40
1.0
1.0
1.5
V
mA
V
V
mA
μs
kHz
μs
μs
μs
kΩ
Test
Circuit
−
1
2
2
3
−
−
4
5
5
−
This item is guaranteed by design.
7
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
S-576Z B Series
Rev.1.1_00
S pole
Magnetic flux
density applied
to this IC (B)
BRS
BZ (0)
BRN
N pole
tD
tD
tF
Output voltage
(VOUT)
(Product with
VOUT = "L"
at S pole
detection)
90%
10%
tD
tD
tR
Output voltage
(VOUT)
(Product with
VOUT = "H"
at S pole
detection)
90%
10%
Figure 5 Operation Timing
8
tR
tF
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
Rev.1.1_00
S-576Z B Series
Magnetic Characteristics
1.
TSOT-23-3S
1. 1
Product with BRS = 3.0 mT typ.
Table 10
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Item
Zero crossing latch point
S pole
Release point
N pole
1. 2
Symbol
BZ*1
BRS*2
BRN*3
Condition
−
−
−
Min.
−1.15
1.9
−4.1
Typ.
0.0
3.0
−3.0
Max.
1.15
4.1
−1.9
Unit
mT
mT
mT
Test Circuit
4
4
4
Product with BRS = 6.0 mT typ.
Table 11
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Item
Zero crossing latch point
S pole
Release point
N pole
2.
Symbol
BZ*1
BRS*2
BRN*3
Condition
−
−
−
Min.
−1.35
4.0
−8.0
Typ.
0.0
6.0
−6.0
Max.
1.35
8.0
−4.0
Unit
mT
mT
mT
Test Circuit
4
4
4
HSNT-6(2025)
2. 1
Product with BRS = 3.0 mT typ.
Table 12
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Item
Zero crossing latch point
S pole
Release point
N pole
2. 2
Symbol
BZ*1
BRS*2
BRN*3
Condition
−
−
−
Min.
−1.65
1.0
−5.0
Typ.
0.0
3.0
−3.0
Max.
1.65
5.0
−1.0
Unit
mT
mT
mT
Test Circuit
4
4
4
Product with BRS = 6.0 mT typ.
Table 13
(Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified)
Item
Zero crossing latch point
S pole
Release point
N pole
Symbol
BZ*1
BRS*2
BRN*3
Condition
−
−
−
Min.
−1.75
3.5
−8.5
Typ.
0.0
6.0
−6.0
Max.
1.75
8.5
−3.5
Unit
mT
mT
mT
Test Circuit
4
4
4
*1.
BZ: Zero crossing latch point
BZ is the value of magnetic flux density at which polarity changes are detected according to the magnetic flux
density applied to this IC.
*2. BRS: Release point (S pole)
BRS is the value of magnetic flux density of release point (S pole).
This IC releases the Hold status of the output voltage (VOUT) when the magnetic flux density applied to this IC
exceeds BRS (by moving the magnet (S pole) closer).
*3. BRN: Release point (N pole)
BRN is the value of magnetic flux density of release point (N pole).
This IC releases the Hold status of the output voltage (VOUT) when the magnetic flux density applied to this IC
exceeds BRN (by moving the magnet (N pole) closer).
Remark
The unit of magnetic density mT can be converted by using the formula 1 mT = 10 Gauss.
9
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
S-576Z B Series
Rev.1.1_00
Test Circuits
A
R*1
820 Ω
VDD
VDD
OUT
OUT
VSS
V
VSS
*1.
Resistor (R) is unnecessary for Nch driver +
built-in pull-up resistor product.
Figure 6
Figure 7
Test Circuit 1
VSS
VSS
V
*1.
Test Circuit 3
OUT
VSS
V
Resistor (R) is unnecessary for Nch driver +
built-in pull-up resistor product.
Figure 10
10
C
20 pF
Test Circuit 5
V
Resistor (R) is unnecessary for Nch driver +
built-in pull-up resistor product.
Figure 9
R*1
820 Ω
VDD
R*1
820 Ω
OUT
A
OUT
Figure 8
Test Circuit 2
VDD
VDD
*1.
A
Test Circuit 4
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
Rev.1.1_00
S-576Z B Series
Standard Circuit
VDD
CIN
0.1 μF
*1.
R*1
820 Ω
OUT
VSS
Resistor (R) is unnecessary for Nch driver + built-in pull-up resistor product.
Figure 11
Caution The above connection diagram and constants will not guarantee successful operation. Perform
thorough evaluation using the actual application to set the constants.
11
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
S-576Z B Series
Rev.1.1_00
Operation
1.
Direction of applied magnetic flux
This IC detects the magnetic flux density which is perpendicular to the package marking surface. A magnetic field is
defined as positive when marking side of the package is the S pole, and negative when it is the N pole.
Figure 12 and Figure 13 show polarity in a magnetic field and direction in which magnetic flux is being applied.
1. 1
TSOT-23-3S
1. 2
HSNT-6(2025)
N
S
N
S
Marking surface
Marking surface
Figure 12
2.
Figure 13
Position of Hall sensor
Figure 14 and Figure 15 show the position of Hall sensor.
The center of this Hall sensor is located in the area indicated by a circle, which is in the center of a package as
described below.
The following also shows the distance (typ. value) between the marking surface and the chip surface of a package.
2. 1
TSOT-23-3S
2. 2
HSNT-6(2025)
Top view
2
The center of Hall
sensor, in this φ0.3 mm
1
6
2
5
3
4
3
0.22 mm (typ.)
Figure 14
12
Top view
The center of Hall sensor,
in this φ0.3 mm
1
0.16 mm (typ.)
Figure 15
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
Rev.1.1_00
S-576Z B Series
3.
Basic operation
This IC switches output voltage level (VOUT) when the IC detects magnetic flux density (magnetic field) polarity
changes by using ZCL technology. ZCL technology realizes polarity changes detection and hold operation (Hold
status) of VOUT. This is different from the conventional bipolar latch method. ZCL detection method has no
hysteresis width of the magnetic sensitivity to switch VOUT. Instead, the ZCL detection method can switch VOUT
without chattering by using the Hold status.
3. 1
ZCL basic operation
This IC switches VOUT after the output delay time (tD) from when the magnetic flux density applied to this IC
crosses BZ (from B > BRS to B < BZ or from B < BRN to B > BZ). When VOUT is switched, this IC starts the Hold
status. In the Hold status of VOUT, when the magnetic flux density applied to this IC exceeds BRS or BRN, this IC
releases the Hold status (from B < BZ to B < BRN or from B > BZ to B > BRS).
Figure 16 and Figure 17 show the VOUT operation timing when sine wave magnetic flux density is applied to this
IC.
(1)
(2)
(3)
(4)
B > BRS → B < BZ, and after tD, VOUT = "L" → "H", and Hold status starts
B < BZ → B < BRN, and after tD, Hold status is released, and VOUT = "H" continues
B < BRN → B > BZ, and after tD, VOUT = "H" → "L", and Hold status starts
B > BZ → B > BRS, and after tD, Hold status is released, and VOUT = "L" continues
(1)
Magnetic flux
density applied
to this IC (B)
(2)
(4)
(3)
S pole
BRS
BZ (0)
)
BRN
N pole
tD
tD
Hold
status
Output voltage (VOUT)
tD
tD
Hold
status
H
L
t
Figure 16
Product with VOUT = "L" at S pole detection
13
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
S-576Z B Series
Rev.1.1_00
(1)
(2)
(3)
(4)
B > BRS → B < BZ, and after tD, VOUT = "H" → "L", and Hold status starts
B < BZ → B < BRN, and after tD, Hold status is released, and VOUT = "L" continues
B < BRN → B > BZ, and after tD, VOUT = "L" → "H", and Hold status starts
B > BZ → B > BRS, and after tD, Hold status is released, and VOUT = "H" continues
(1)
Magnetic flux
density applied
to this IC (B)
(2)
(3)
(4)
S pole
BRS
BZ (0)
)
BRN
N pole
tD
tD
Hold
status
Output voltage (VOUT)
tD
tD
Hold
status
H
L
t
Figure 17
14
Product with VOUT = "H" at S pole detection
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
Rev.1.1_00
S-576Z B Series
3. 2
Prevention of VOUT chattering by Hold status
By the Hold status, this IC can switch VOUT without chattering even under an influence of external mechanical
vibrations, electrical noise, or magnetic noise.
Figure 18 and Figure 19 show the VOUT operation when the magnetic flux density applied to this IC changes near
the zero crossing latch point (BZ) and BZ is crossed multiple times.
(1) In the Hold status, the IC retains VOUT when the magnetic flux density applied to this IC crosses BZ.
(1)
(1)
S pole
BRS
Magnetic flux
density applied
to this IC (B)
BZ (0)
)
BRN
N pole
tD
tD
tD
tD
H
Hold
status
Hold
status
Output voltage (VOUT)
L
t
Figure 18 Product with VOUT = "L" at S pole detection
(1)
(1)
S pole
BRS
Magnetic flux
density applied
to this IC (B)
BZ (0)
)
BRN
N pole
tD
tD
tD
tD
H
Output voltage (VOUT)
Hold
status
Hold
status
L
t
Figure 19 Product with VOUT = "H" at S pole detection
15
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
S-576Z B Series
Rev.1.1_00
3. 3
Operation when polarity changes direction is inverted in the Hold status
In the Hold status, when the polarity changes direction is inverted, this IC release the Hold status at the opposite
release point and switches VOUT.
Figure 20 and Figure 21 show the VOUT operation timing when the polarity change direction is inverted.
(1)
(2)
(3)
(4)
(5)
(6)
B > BZ → B < BZ, and after tD, VOUT = "L" → "H", and Hold status starts
During Hold status, even after B < BZ → B > BZ, VOUT = "H" is retained
B > BZ → B > BRS, and after tD, Hold status is released, and VOUT = "H" → "L"
B < BZ → B > BZ, and after tD, VOUT = "H" → "L", and Hold status starts
During Hold status, even after B > BZ → B < BZ, VOUT = "L" is retained
B < BZ → B < BRN, and after tD, Hold status is released, and VOUT = "L" → "H"
(1) (2)
(3)
(4) (5)
(6)
S pole
BRS
Magnetic flux
density applied
to this IC (B)
・・・
・・・
BZ (0)
)
BRN
N pole
tD
tD
tD
tD
H
Output voltage (VOUT)
Hold
status
Hold
status
L
t
Figure 20 Product with VOUT = "L" at S pole detection
16
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
Rev.1.1_00
S-576Z B Series
(1)
(2)
(3)
(4)
(5)
(6)
B > BZ → B < BZ, and after tD, VOUT = "H" → "L", and Hold status starts
During Hold status, even after B < BZ → B > BZ, VOUT = "L" is retained
B > BZ → B > BRS, and after tD, Hold status is released, and VOUT = "L" → "H"
B < BZ → B > BZ, and after tD, VOUT = "L" → "H", and Hold status starts
During Hold status, even after B > BZ → B < BZ, VOUT = "H" is retained
B < BZ → B < BRN, and after tD, Hold status is released, and VOUT = "H" → "L"
(1) (2)
(3)
(4) (5)
(6)
S pole
BRS
Magnetic flux
density applied
to this IC (B)
BZ (0)
・・・
・・・
)
BRN
N pole
tD
tD
tD
tD
H
Output voltage (VOUT)
Hold
status
Hold
status
L
t
Figure 21 Product with VOUT = "H" at S pole detection
17
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
S-576Z B Series
Rev.1.1_00
4.
Power-on operation
This IC requires start up time (tPON) during the time immediately after power-on until VOUT switches. During the
tPON period, VOUT is "H". After tPON, when B > BRS or B < BRN is detected, polarity changes can be detected.
4. 1
B > BRS or B < BRN
When the magnetic flux density applied to this IC at power-on is B > BRS or B < BRN, after tPON, VOUT switches
according to the output logic at the S pole detection, and polarity changes can be detected.
Figure 22 and Figure 23 show VOUT operation immediately after power-on when B > BRS or B < BRN.
S pole
Magnetic flux
density applied
to this IC (B)
B > BRS
BRS
Bz (0)
BRN
B < BRN
N pole
Power supply voltage
(VDD)
tPON
Output voltage (VOUT)
when B > BRS
"H"
Output voltage (VOUT)
when B < BRN
"H"
"L"
"L"
t
Figure 22 Product with VOUT = "L" at S pole detection
S pole
Magnetic flux
density applied
to this IC (B)
B > BRS
BRS
Bz (0)
BRN
B < BRN
N pole
Power supply voltage
(VDD)
tPON
Output voltage (VOUT)
when B > BRS
"H"
Output voltage (VOUT)
when B < BRN
"H"
"L"
"L"
t
Figure 23 Product with VOUT = "H" at S pole detection
18
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
Rev.1.1_00
S-576Z B Series
4. 2
BRN < B < BRS
When the magnetic flux density applied to this IC at power-on is BRN < B < BRS, after tPON, VOUT continues "H".
Thereafter, when the magnetic flux density changes to B > BRS or B < BRN, after tD, VOUT switches according to the
output logic at the S pole detection and magnetic flux density, and polarity changes can be detected.
Figure 24 and Figure 25 show VOUT operation when change of BRN < B < BRS → B > BRS or B < BRN occurs after
tPON.
S pole
Magnetic flux
density applied
to this IC (B)
BRS
B < BRS → B > BRS
0 (BZ)
B > BRN → B < BRN
BRN
N pole
Power supply voltage
(VDD)
tPON
tD
Output voltage (VOUT)
when B < BRS → B > BRS
"H"
Output voltage (VOUT)
when B > BRN → B < BRN
"H"
"L"
"L"
t
Figure 24 Product with VOUT = "L" at S pole detection
S pole
Magnetic flux
density applied
to this IC (B)
BRS
B < BRS → B > BRS
0 (BZ)
B > BRN → B < BRN
BRN
N pole
Power supply voltage
(VDD)
tPON
tD
Output voltage (VOUT)
when B < BRS → B > BRS
"H"
Output voltage (VOUT)
when B > BRN → B < BRN
"H"
"L"
"L"
t
Figure 25 Product with VOUT = "H" at S pole detection
19
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
S-576Z B Series
Rev.1.1_00
Precautions
• If the impedance of the power supply is high, the IC may malfunction due to a supply voltage drop caused by
feed-through current. Take care with the pattern wiring to ensure that the impedance of the power supply is low.
• Note that the IC may malfunction if the power supply voltage rapidly changes. When the IC is used under the
environment where the power supply voltage rapidly changes, it is recommended to judge the output voltage of
the IC by reading it multiple times.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• Although this IC has a built-in output current limit circuit, it may suffer physical damage such as product
deterioration under the environment where the absolute maximum ratings are exceeded.
• The application conditions for the power supply voltage, the pull-up voltage, and the pull-up resistor should not
exceed the power dissipation.
• Large stress on this IC may affect the magnetic characteristics. Avoid large stress which is caused by the
handling during or after mounting the IC on a board.
• Since the package heat radiation differs according to the conditions of the application, perform thorough
evaluation with actual applications to confirm no problems occur.
• ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
20
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
Rev.1.1_00
S-576Z B Series
Characteristics (Typical Data)
Electrical Characteristics
S-576ZxxxB
Current consumption (IDD)
vs. Temperature (Ta)
1. 1. 2
VOUT = "H"
6.0
IDD [mA]
5.0
VDD = 5.5 V
4.0
3.0
VDD = 2.7 V
VDD = 12.0 V
1.0
0.0
−40 −25
1. 1. 3
20
25
50
Ta [°C]
Output delay time (tD)
vs. Temperature (Ta)
tD [μs]
2.0
100
0.0
125
0
1. 1. 4
20
25
50
Ta [°C]
75
15
20
25
VDD [V]
Output delay time (tD)
vs. Power supply voltage (VDD)
10
30
Ta = −40°C
5
100
5
10
VDD = 12.0 V
0
Ta = +125°C
Ta = +125°C
Ta = +25°C
0
125
0
5
10
15
20
VDD [V]
25
30
VDD = 2.7 V to 5.5 V when output form is Nch driver + built-in pull-up resistor (1.2 kΩ typ.).
Comply with power supply voltage range and do not exceed absolute maximum ratings.
S-576ZNxxB
1. 2. 1
Low level output voltage (VOL)
vs. Temperature (Ta)
1. 2. 2
IOUT = 5 mA
0.6
0.4
0.3
Low level output voltage (VOL)
vs. Power supply voltage (VDD)
IOUT = 5 mA
0.6
0.5
VOL [V]
3.0
VDD = 2.7 V
Caution
1. 2
75
VDD = 5.5 V
10
0
−40 −25
Ta = +25°C
4.0
15
VDD = 26.0 V
5
Ta = −40°C
1.0
0
15
VOUT = "H"
5.0
VDD = 26.0 V
2.0
Current consumption (IDD)
vs. Power supply voltage (VDD)
6.0
IDD [mA]
1. 1. 1
tD [μs]
1. 1
0.5
VDD = 2.7 V
VDD = 5.5 V
VDD = 12.0 V
VOL [V]
1.
0.2
0.1
0.0
−40 −25
25
50
Ta [°C]
75
100
Ta = +25°C
0.3
125
Ta = +125°C
0.2
0.1
VDD = 26.0 V
0
0.4
Ta = −40°C
0.0
0
5
10
15
20
VDD [V]
25
30
21
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
S-576Z B Series
Rev.1.1_00
1. 3
S-576Z1xxB
1. 3. 1
Low level output voltage (VOL)
vs. Temperature (Ta)
1. 3. 2
IOUT = 0 mA
0.6
0.2
0.5
VOL [V]
VOL [V]
0.3
VDD = 5.5 V
VDD = 5.0 V
VDD = 2.7 V
0.1
0
25
50
Ta [°C]
100
Ta = +125°C
Ta = +25°C
Ta = −40°C
0.3
0.2
0.0
125
2
1. 3. 4
IOUT = 0 mA
5.0
5.0
4.0
4.0
VDD = 5.0 V VDD = 5.5 V
3.0
2.0
1.0
0.0
−40 −25
25
50
Ta [°C]
4
VDD [V]
5
6
High level output voltage (VOH)
vs. Power supply voltage (VDD)
IOUT = 0 mA
Ta = +125°C
3.0
Ta = +25°C
Ta = −40°C
2.0
1.0
VDD = 2.7 V
0
3
6.0
VOH [V]
VOH [V]
75
High level output voltage (VOH)
vs. Temperature (Ta)
6.0
22
0.4
0.1
0.0
−40 −25
1. 3. 3
IOUT = 0 mA
0.6
0.5
0.4
Low level output voltage (VOL)
vs. Power supply voltage (VDD)
75
100
125
0.0
2
3
4
VDD [V]
5
6
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
Rev.1.1_00
S-576Z B Series
Magnetic Characteristics
S-576Zxx1B-L3T2U
Zero crossing latch point (BZ)
vs. Temperature (Ta)
N pole → S pole
8.0
6.0
VDD = 12.0 V
4.0
VDD = 26.0 V
2.0
0.0
−2.0
−4.0
VDD = 5.5 V VDD = 2.7 V
−6.0
−8.0
−40 −25
0
25
50
75 100 125
Ta [°C]
2. 1. 5
Release point (BRS, BRN)
vs. Temperature (Ta)
8.0
BRS
VDD = 26.0 V
6.0
VDD = 5.5 V VDD = 12.0 V
4.0
2.0
VDD = 26.0 V
0.0
VDD = 2.7 V
−2.0
−4.0
VDD = 2.7 V VDD = 5.5 V
−6.0 BRN
VDD = 12.0 V
−8.0
−40 −25
0
25
50
75 100 125
Ta [°C]
Caution
2. 1. 2 Zero crossing latch point (BZ)
vs. Power supply voltage (VDD)
S pole → N pole
BZ [mT]
S pole → N pole
8.0
6.0
VDD = 12.0 V
VDD = 26.0 V
4.0
2.0
0.0
−2.0
VDD = 2.7 V
−4.0
VDD = 5.5 V
−6.0
−8.0
−40 −25
0
25
50
75 100 125
Ta [°C]
2. 1. 3
BZ [mT]
Zero crossing latch point (BZ)
vs. Temperature (Ta)
8.0
6.0
4.0
2.0
0.0
−2.0
−4.0
−6.0
−8.0
Ta = +125°C
Ta = +25°C
Ta = −40°C
0
5
10
15
20
VDD [V]
25
30
2. 1. 4 Zero crossing latch point (BZ)
vs. Power supply voltage (VDD)
N pole → S pole
BZ [mT]
BZ [mT]
2. 1. 1
8.0
6.0
4.0
2.0
0.0
−2.0
−4.0
−6.0
−8.0
Ta = −40°C
Ta = +25°C
Ta = +125°C
0
5
10
15
20
VDD [V]
25
30
2. 1. 6 Release point (BRS, BRN)
vs. Power supply voltage (VDD)
8.0
Ta = −40°C
6.0 BRS Ta = +25°C
4.0
2.0
Ta = +125°C
0.0
Ta = +125°C
−2.0
−4.0
Ta = −40°C
−6.0 BRN Ta = +25°C
−8.0
0
30
5
10
15
20
25
VDD [V]
BRS, BRN [mT]
2. 1
BRS, BRN [mT]
2.
VDD = 2.7 V to 5.5 V when output form is Nch driver + built-in pull-up resistor (1.2 kΩ typ.).
Comply with power supply voltage range and do not exceed absolute maximum ratings.
23
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
S-576Z B Series
Rev.1.1_00
S-576Zxx2B-L3T2U
2. 2. 2 Zero crossing latch point (BZ)
vs. Power supply voltage (VDD)
Zero crossing latch point (BZ)
vs. Temperature (Ta)
BRS, BRN [mT]
2. 2. 5
Release point (BRS, BRN)
vs. Temperature (Ta)
8.0
BRS
6.0
4.0
VDD = 26.0 V
VDD = 5.5 V
2.0 VDD = 2.7 V
VDD = 12.0 V
0.0
VDD = 26.0 V
VDD = 5.5 V
−2.0
DD = 12.0 V
V
VDD = 2.7 V
−4.0
Caution
24
0
25
50
Ta [°C]
75
8.0
6.0
4.0
2.0
0.0
−2.0
−4.0
−6.0
−8.0
Ta = +125°C
Ta = +25°C
Ta = −40°C
0
5
10
15
20
VDD [V]
25
30
2. 2. 4 Zero crossing latch point (BZ)
vs. Power supply voltage (VDD)
N pole → S pole
8.0
6.0
VDD = 12.0 V
4.0
VDD = 26.0 V
2.0
0.0
−2.0
−4.0
VDD = 5.5 V VDD = 2.7 V
−6.0
−8.0
−40 −25
0
25
50
75 100 125
Ta [°C]
−6.0
BRN
−8.0
−40 −25
S pole → N pole
BZ [mT]
S pole → N pole
8.0
6.0
VDD = 12.0 V
4.0
VDD = 26.0 V
2.0
0.0
−2.0
−4.0
VDD = 5.5 V VDD = 2.7 V
−6.0
−8.0
−40 −25
0
25
50
75 100 125
Ta [°C]
2. 2. 3
BZ [mT]
Zero crossing latch point (BZ)
vs. Temperature (Ta)
100
125
N pole → S pole
BZ [mT]
BZ [mT]
2. 2. 1
8.0
6.0
4.0
2.0
0.0
−2.0
−4.0
−6.0
−8.0
Ta = +25°C
Ta = −40°C
Ta = +125°C
0
5
10
15
20
VDD [V]
25
30
2. 2. 6 Release point (BRS, BRN)
vs. Power supply voltage (VDD)
8.0
BRS
6.0
4.0
Ta = −40°C
Ta = +25°C
2.0
Ta = +125°C
0.0
Ta = −40°C
−2.0
Ta = 25 C
−4.0 Ta = +125°C
−6.0
BRN
−8.0
0
30
5
10
15
20
25
VDD [V]
BRS, BRN [mT]
2. 2
VDD = 2.7 V to 5.5 V when output form is Nch driver + built-in pull-up resistor (1.2 kΩ typ.).
Comply with power supply voltage range and do not exceed absolute maximum ratings.
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
Rev.1.1_00
S-576Z B Series
S-576Zxx1B-A6T8U
BZ [mT]
Zero crossing latch point (BZ)
vs. Temperature (Ta)
N pole → S pole
8.0
6.0
VDD = 12.0 V
4.0
VDD = 26.0 V
2.0
0.0
−2.0
−4.0
VDD = 5.5 V VDD = 2.7 V
−6.0
−8.0
−40 −25
0
25
50
75 100 125
Ta [°C]
2. 3. 5
Release point (BRS, BRN)
vs. Temperature (Ta)
8.0
BRS
VDD = 26.0 V
6.0
VDD = 5.5 V VDD = 12.0 V
4.0
2.0
VDD = 26.0 V
0.0
VDD = 2.7 V
−2.0
−4.0
VDD = 2.7 V VDD = 5.5 V
−6.0 BRN
VDD = 12.0 V
−8.0
−40 −25
0
25
50
75 100 125
Ta [°C]
Caution
2. 3. 2 Zero crossing latch point (BZ)
vs. Power supply voltage (VDD)
S pole → N pole
BZ [mT]
S pole → N pole
8.0
6.0
VDD = 12.0 V
VDD = 26.0 V
4.0
2.0
0.0
−2.0
VDD = 2.7 V
−4.0
VDD = 5.5 V
−6.0
−8.0
−40 −25
0
25
50
75 100 125
Ta [°C]
2. 3. 3
BRS, BRN [mT]
Zero crossing latch point (BZ)
vs. Temperature (Ta)
8.0
6.0
4.0
2.0
0.0
−2.0
−4.0
−6.0
−8.0
Ta = +125°C
Ta = +25°C
Ta = −40°C
0
5
10
15
20
VDD [V]
25
30
2. 3. 4 Zero crossing latch point (BZ)
vs. Power supply voltage (VDD)
N pole → S pole
BZ [mT]
BZ [mT]
2. 3. 1
8.0
6.0
4.0
2.0
0.0
−2.0
−4.0
−6.0
−8.0
Ta = −40°C
Ta = +25°C
Ta = +125°C
0
5
10
15
20
VDD [V]
25
30
2. 3. 6 Release point (BRS, BRN)
vs. Power supply voltage (VDD)
8.0
Ta = +125°C
6.0 BRS Ta = +25°C
4.0
2.0
Ta = +125°C
0.0
Ta = −40°C
−2.0
−4.0
Ta = −40°C
−6.0 BRN Ta = +25°C
−8.0
5
10
15
20
25
0
30
VDD [V]
BRS, BRN [mT]
2. 3
VDD = 2.7 V to 5.5 V when output form is Nch driver + built-in pull-up resistor (1.2 kΩ typ.).
Comply with power supply voltage range and do not exceed absolute maximum ratings.
25
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
S-576Z B Series
Rev.1.1_00
S-576Zxx2B-A6T8U
BZ [mT]
N pole → S pole
8.0
6.0
VDD = 12.0 V
4.0
VDD = 26.0 V
2.0
0.0
−2.0
−4.0
VDD = 5.5 V VDD = 2.7 V
−6.0
−8.0
−40 −25
0
25
50
75 100 125
Ta [°C]
2. 4. 5
BRS, BRN [mT]
Zero crossing latch point (BZ)
vs. Temperature (Ta)
Release point (BRS, BRN)
vs. Temperature (Ta)
8.0
BRS
6.0
4.0
VDD = 26.0 V
VDD = 5.5 V
2.0 VDD = 2.7 V
VDD = 12.0 V
0.0
VDD = 26.0 V
VDD = 5.5 V
−2.0
VDD = 12.0 V
V
DD = 2.7 V
−4.0
−6.0
BRN
−8.0
−40 −25
0
25
50
75 100 125
Ta [°C]
Caution
2. 4. 2 Zero crossing latch point (BZ)
vs. Power supply voltage (VDD)
S pole → N pole
BZ [mT]
S pole → N pole
8.0
6.0
VDD = 12.0 V
4.0
VDD = 26.0 V
2.0
0.0
−2.0
−4.0
VDD = 5.5 V VDD = 2.7 V
−6.0
−8.0
−40 −25
0
25
50
75 100 125
Ta [°C]
2. 4. 3
26
Zero crossing latch point (BZ)
vs. Temperature (Ta)
8.0
6.0
4.0
2.0
0.0
−2.0
−4.0
−6.0
−8.0
Ta = +125°C
Ta = +25°C
Ta = −40°C
0
5
10
15
20
VDD [V]
25
30
2. 4. 4 Zero crossing latch point (BZ)
vs. Power supply voltage (VDD)
N pole → S pole
BZ [mT]
BZ [mT]
2. 4. 1
8.0
6.0
4.0
2.0
0.0
−2.0
−4.0
−6.0
−8.0
Ta = −40°C
Ta = +25°C
Ta = +125°C
0
5
10
15
20
VDD [V]
25
30
2. 4. 6 Release point (BRS, BRN)
vs. Power supply voltage (VDD)
8.0
BRS
6.0
4.0
Ta = −40°C
Ta = +25°C
2.0
Ta = +125°C
0.0
−2.0
Ta = +25°C Ta = −40°C
Ta
=
+125°C
−4.0
−6.0
BRN
−8.0
5
10
15
20
25
0
30
VDD [V]
BRS, BRN [mT]
2. 4
VDD = 2.7 V to 5.5 V when output form is Nch driver + built-in pull-up resistor (1.2 kΩ typ.).
Comply with power supply voltage range and do not exceed absolute maximum ratings.
125°C OPERATION, HIGH-WITHSTAND VOLTAGE, HIGH-SPEED, ZCLTM HALL EFFECT IC
Rev.1.1_00
S-576Z B Series
Power Dissipation
TSOT-23-3S
HSNT-6(2025)
Tj = +150°C max.
4
3
2
1 B
Tj = +150°C max.
5
Power dissipation (PD) [W]
Power dissipation (PD) [W]
5
4
E
C
3
D
2
B
1
A
0
0
A
25
50
75
100
125
150
175
0
0
25
Ambient temperature (Ta) [°C]
Board
Power Dissipation (PD)
A
B
C
D
E
0.56 W
0.66 W
−
−
−
50
75
100
125
150
175
Ambient temperature (Ta) [°C]
Board
A
B
C
D
E
Power Dissipation (PD)
0.69 W
0.98 W
2.91 W
2.84 W
3.47 W
27
TSOT-23-3S Test Board
IC Mount Area
(1) Board A
Item
Size [mm]
Material
Number of copper foil layer
Copper foil layer [mm]
1
2
3
4
Thermal via
Specification
114.3 x 76.2 x t1.6
FR-4
2
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.070
-
(2) Board B
Item
Size [mm]
Material
Number of copper foil layer
Copper foil layer [mm]
Thermal via
1
2
3
4
Specification
114.3 x 76.2 x t1.6
FR-4
4
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070
-
No. TSOT23x-A-Board-SD-1.0
ABLIC Inc.
HSNT-6(2025) Test Board
IC Mount Area
(1) Board A
Item
Size [mm]
Material
Number of copper foil layer
Copper foil layer [mm]
1
2
3
4
Thermal via
Specification
114.3 x 76.2 x t1.6
FR-4
2
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.070
-
(2) Board B
Item
Size [mm]
Material
Number of copper foil layer
Copper foil layer [mm]
1
2
3
4
Thermal via
Specification
114.3 x 76.2 x t1.6
FR-4
4
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070
-
(3) Board C
Item
Size [mm]
Material
Number of copper foil layer
Copper foil layer [mm]
Thermal via
1
2
3
4
Specification
114.3 x 76.2 x t1.6
FR-4
4
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070
Number: 4
Diameter: 0.3 mm
No. HSNT6-B-Board-SD-1.0
enlarged view
ABLIC Inc.
HSNT-6(2025) Test Board
IC Mount Area
(4) Board D
Item
Size [mm]
Material
Number of copper foil layer
Copper foil layer [mm]
1
2
3
4
Thermal via
Specification
114.3 x 76.2 x t1.6
FR-4
4
2
Pattern for heat radiation: 2000mm t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070
-
enlarged view
(5) Board E
Item
Size [mm]
Material
Number of copper foil layer
Copper foil layer [mm]
Thermal via
1
2
3
4
Specification
114.3 x 76.2 x t1.6
FR-4
4
2
Pattern for heat radiation: 2000mm t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070
Number: 4
Diameter: 0.3 mm
enlarged view
No. HSNT6-B-Board-SD-1.0
ABLIC Inc.
2.9±0.2
1
2
3
0.16
0.95±0.1
+0.1
-0.06
1.9±0.2
0.42±0.1
No. MP003-E-P-SD-1.0
TITLE
TSOT233S-A-PKG Dimensions
No.
MP003-E-P-SD-1.0
ANGLE
UNIT
mm
ABLIC Inc.
ø1.5
+0.1
-0
4.0±0.1
2.0±0.05
ø1.0
+0.1
-0
0.25±0.1
(0.4)
4.0±0.1
0.95±0.2
3.23±0.2
(1.0)
1
2
3
Feed direction
No. MP003-E-C-SD-1.0
TITLE
TSOT233S-A-Carrier Tape
No.
MP003-E-C-SD-1.0
ANGLE
UNIT
mm
ABLIC Inc.
9.0
+1.0
- 0.0
11.4±1.0
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. MP003-E-R-SD-1.0
TITLE
TSOT233S-A-Reel
No.
MP003-E-R-SD-1.0
ANGLE
QTY.
UNIT
mm
ABLIC Inc.
3,000
1.96±0.05
1.78±0.1
6
5
0.5
1
4
2
3
0.5
0.5
0.12±0.04
0.48±0.02
0.22±0.05
The heat sink of back side has different electric
potential depending on the product.
Confirm specifications of each product.
Do not use it as the function of electrode.
No. PJ006-B-P-SD-1.0
TITLE
HSNT-6-C-PKG Dimensions
No.
PJ006-B-P-SD-1.0
ANGLE
UNIT
mm
ABLIC Inc.
ø1.5
+0.1
-0
2.0±0.05
4.0±0.1
ø0.5±0.1
0.25±0.05
0.65±0.05
4.0±0.1
2.25±0.05
3 21
0.5
0.5
0.5
0.5
0.5
0.5
4 5 6
Feed direction
No. PJ006-B-C-SD-1.0
TITLE
HSNT-6-C-Carrier Tape
No.
PJ006-B-C-SD-1.0
ANGLE
UNIT
mm
ABLIC Inc.
9.0
+1.0
- 0.0
11.4±1.0
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PJ006-B-R-SD-1.0
TITLE
HSNT-6-C-Reel
No.
PJ006-B-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
5,000
Land Recommendation
0.50
0.35
0.50
1.44
1.78
2.10
Caution It is recommended to solder the heat sink to a board in order to ensure the heat radiation.
PKG
Stencil Opening
1.40
0.50
0.50
No. PJ006-B-LM-SD-1.0
0.35
Caution
Mask aperture ratio of the lead mounting part is 100~120%.
Mask aperture ratio of the heat sink mounting part is 30%.
Mask thickness: t0.12 mm
Reflow atmosphere: Nitrogen atmosphere is recommended.
(Oxygen concentration: 1000ppm or less)
100~120%
30%
t0.12 mm
TITLE
HSNT-6-C
-Land &Stencil Opening
PJ006-B-LM-SD-1.0
No.
ANGLE
UNIT
mm
1000ppm
ABLIC Inc.
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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