HI1178JCQ

® oH S nd R a e e -Fr Sheet PbData Co October 25, 2005 Triple 8-Bit, 40MSPS, RGB, 3-Channel D/A Converter The HI1178 is a triple 8-bit, high-speed, CMOS D/A converter designed for video band use. It has three separate, 8-bit, pixel inputs, one each for red, green, and blue video data. A single 5.0V power supply and pixel clock input is all that is required to make the device operational. A bias voltage generator is internal. Each channel clock input can be controlled individually, or connected together as one. The HI1178 also has BLANK video control signal. Features • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 8-Bit • Maximum Conversion Speed . . . . . . . . . . . . . . . . . 40MHz • RGB 3-Channel Input/Output • Differential Linearity Error . . . . . . . . . . . . . . . . . +0.3 LSB • Low Power Consumption . . . . . . . . . . . . . . . . . . . .240mW (200Ω Load for 2VP-P Output) • Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . .+5V • Direct Replacement for Sony CXD1178 TEMP. RANGE (oC) HI1178JCQ FN4115.4 • Low Glitch Noise Ordering Information PART NUMBER HI1178 ant mpli -40 to 85 PACKAGE 48 Ld MQFP PKG. NO. Q48.12x12-S Applications • Digital TV • Graphics Display Pinout • High Resolution Color Graphics • Video Reconstruction RO GO GO BO • Instrumentation VG BO AVDD AVDD AVDD AVDD DVDD DVDD HI1178 (MQFP) TOP VIEW • Image Processing • I/Q Modulation R0 1 48 47 46 45 44 43 42 41 40 39 38 37 36 R1 2 35 IREF R2 R3 3 34 VREF 4 33 R4 R5 5 32 6 7 31 AVSS VB DVSS 30 DVSS 8 29 9 28 BCK GCK 10 27 RCK 11 12 26 CE 1 Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” BLK B7 B6 B4 B5 B2 B3 25 13 14 15 16 17 18 19 20 21 22 23 24 B1 G3 B0 G2 G6 G7 G0 G1 G5 R7 G4 R6 RO CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HI1178 Functional Block Diagram (LSB) R0 1 R1 2 R2 3 R3 4 R4 5 R5 6 R6 7 R7 8 (LSB) G0 9 G1 10 G2 11 G3 12 2 LSBs CURRENT CELLS DECODER LATCHES 13 G5 14 G6 15 G7 16 (LSB) B0 17 B1 18 B2 19 B3 20 B4 21 B5 22 B6 23 B7 DVDD 48 DVDD 36 R0 37 R0 27 RCK 43 AVSS 44 AVDD 45 AVDD 46 AVDD 38 G0 39 G0 28 GCK 33 AVSS 30 DVSS 31 DVSS 40 B0 41 B0 29 BCK 42 VG 34 VREF CURRENT CELLS (FOR FULL SCALE) 35 IREF BIAS VOLTAGE GENERATOR 32 VB 6 MSBs CURRENT CELLS DECODER CLOCK GENERATOR 2 LSBs CURRENT CELLS DECODER LATCHES G4 47 6 MSBs CURRENT CELLS DECODER CLOCK GENERATOR 2 LSBs CURRENT CELLS DECODER LATCHES 6 MSBs CURRENT CELLS DECODER CLOCK GENERATOR 24 - + BLK 25 CE 26 2 HI1178 Pin Descriptions PIN NO. SYMBOL 1 to 8 R0 to R7 9 to 16 G0 to G7 17 to 24 B0 to B7 EQUIVALENT CIRCUIT DESCRIPTION Digital input. DVDD 1 24 DVSS 25 BLK Blanking pin. No signal at “H” (Output 0V). Output condition at “L”. DVDD 25 DVSS 32 VB DVDD Connect a capacitor of about 0.1µF. DVDD + 32 - DVSS 27 RCK 28 CLK 29 BCK DVDD Clock pin. Moreover all input pins are TTL-CMOS compatible. 27 28 29 DVSS 30, 31 DVSS Digital GND. 33 AVSS Analog GND. 26 CE DVDD 26 DVSS 3 Chip enable pin. No signal (Output 0V) at “H” and minimizes power consumption. HI1178 Pin Descriptions PIN NO. SYMBOL 35 IREF (Continued) EQUIVALENT CIRCUIT AVDD 34 DESCRIPTION AVDD VREF Connect a resistance 16 times “16R” that of output resistance value “R”. Set full scale output value. + 42 VG Connect a capacitor of about 0.1µF. 35 AVDD AVSS 34 AVDD 42 AVSS AVSS 43 to 46 AVDD 37 RO 39 GO 41 BO 36 RO 38 GO 40 BO Analog VDD . AVDD Current output pin. Voltage output can be obtained by connecting a resistance. 37 39 Inverted current output pin. Normally dropped to analog GND. 41 AVSS AVDD 36 38 40 AVSS 47, 48 DVDD Digital VDD . 4 HI1178 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Input Voltage (VIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Digital Input Voltage (CLK) . . . . . . . . . . . . . . . . . . . . . 0mA to 15mA (Every Each Channel) Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Maximum Storage Temperature Range (TSTG) . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (MQFP - Lead Tips Only) Operating Conditions Temperature Range (TOPR) . . . . . . . . . . . . . . . . . . . -40oC to 85oC Supply Voltage AVDD , AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V DVDD , DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V Reference Input Voltage (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . .2V Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5ns (Min) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. fCLK = 40MHz, VDD = 5V, ROUT = 200Ω, VREF = 2.0V, TA = 25oC Electrical Specifications PARAMETER SYMBOL MIN TYP MAX UNITS n - 8 - bit fMAX 40 - - MSPS Linearity Error EL -2.5 - 2.5 LSB Differential Linearity Error ED -0.3 - 0.3 LSB Full Scale Output Voltage VFS 1.8 2.0 2.2 V Full Scale Output Ratio (Note 1) FSR 0 1.5 3 % Full Scale Output Current IFS - 10 15 mA Offset Output Voltage VOS - - 1 mV Power Supply Current IDD - - 48 mA Resolution Maximum Conversion Speed TEST CONDITIONS 14.3MHz, at Color Bar Data Input H Level IIH - - 5 µA L Level IIL -5 - - µA Set Up Time tS 5 - - ns Hold Time tH 10 - - ns Propagation Delay Time tPD - 10 - ns Glitch Energy GE ROUT = 75Ω - 30 - pV/s Crosstalk CT 1MHz Sine Wave Output - 57 - dB Digital Input Current NOTE: Full Scale Voltage of Channel 1. Full scale output ratio = ------------------------------------------------------------------------------------------------------------------------------------ – 1 x 100(%) Average of the Full Scale Voltage of the Channels 5 HI1178 I/O Chart (When Full Scale Output Voltage at 2.00V) INPUT CODE MSB 1 1 1 1 OUTPUT CODE 1 1 1 LSB 1 0 0 0 0 1.0V 0 0 0 0 0V 2.0V • • • 1 0 0 0 • • • 0 0 0 0 Timing Diagram tPW0 tPW1 CLK tS tS tS tHL tHL tHL DATA tPD 100% D/AOUT 50% tPD tPD 0% FIGURE 1. Test Circuits R0 ~ R7 1~8 G0 ~ G7 9 ~ 18 B0 ~ B7 17 ~ 24 8-BIT COUNTER WITH LATCH R0 37 200 AVSS OSCILLOSCOPE G0 39 200 AVSS 25 26 32 B0 41 BLK CE HI1178 200 AVSS VB AVDD 0.1µ DVSS 27 RCK CLK 40MHz SQUARE WAVE 28 GCK VG 42 0.1µ VREF 34 1K 29 BCK IREF 35 3.3K AVSS FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT 6 HI1178 Test Circuits (Continued) R0 ~ R7 1~8 8-BIT COUNTER R0 37 75 G0 ~ G7 9 ~ 18 WITH LATCH G0 39 B0 ~ B7 17 ~ 24 OSCILLOSCOPE AVSS 75 AVSS B0 41 25 BLK DELAY CONTROLLER 26 CE 75 HI1178 AVSS 0.1µ 32 VB AVDD DVSS VG 42 0.1µ 27 RCK CLK 1MHz SQUARE WAVE DELAY CONTROLLER 28 GCK VREF 34 29 BCK IREF 35 1K 1.2K AVSS FIGURE 3. SETUP HOLD TIME AND GLITCH ENERGY TEST CIRCUIT R0 ~ R7 1~8 R0 37 G0 39 B0 41 ALL “1” DIGITAL WAVEFORM GENERATOR G0 ~ G7 9 ~ 16 B0 ~ B7 17 ~ 24 AVSS SPECTRUM ANALYZER AVSS 25 BLK 26 CE HI1178 AVSS 0.1µ 32 VB DVSS AVDD VG 42 0.1µ 27 RCK CLK 40MHz SQUARE WAVE 28 GCK VREF 34 29 BCK IREF 35 1K AVSS FIGURE 4. CROSSTALK TEST CIRCUIT 7 HI1178 Test Circuits (Continued) R0 37 R0 ~ R7 1~8 200 G0 ~ G7 9 ~ 16 CONTROLLER AVSS DVM G0 39 B0 ~ B7 17 ~ 24 200 AVSS B0 41 25 BLK 0.1µ HI1178 200 26 CE AVSS 32 VB AVDD DVSS VG 42 27 RCK CLK 40MHz SQUARE WAVE 0.1µ 28 GCK VREF 34 29 BCK IREF 35 1K 3.3K AVSS FIGURE 5. DC CHARACTERISTICS TEST CIRCUIT R0 ~ R7 1~8 R0 37 200 G0 ~ G7 9 ~ 16 FREQUENCY DEMULTIPLIER AVSS G0 39 B0 ~ B7 17 ~ 24 OSCILLOSCOPE 200 AVSS B0 41 25 BLK 26 CE 200 HI1178 AVSS 0.1µ 32 VB DVSS 0.1µ AVDD VG 42 27 RCK CLK 10MHz SQUARE WAVE 28 GCK 29 BCK 1K VREF 34 IREF 35 3.3K FIGURE 6. PROPAGATION DELAY TIME TEST CIRCUIT 8 AVSS HI1178 VFS , OUTPUT FULL SCALE VOLTAGE (V) Typical Performance Curves 200 2.0 100 1.0 VDD = 5.0V R = 200Ω 16R = 3.3kΩ TA = 25oC 1.0 2.0 VREF , REFERENCE VOLTAGE (V) 100 OUTPUT RESISTANCE (Ω) FIGURE 8. GLITCH ENERGY vs OUTPUT RESISTANCE 60 2.0 CROSSTALK (dB) OUTPUT FULL SCALE VOLTAGE (V) FIGURE 7. OUTPUT FULL SCALE VOLTAGE vs REFERENCE VOLTAGE 200 1.9 VDD = 5.0V VREF = 2.0V R = 200Ω 16R = 3.3kΩ 50 40 0 -25 0 25 50 75 100 AMBIENT TEMPERATURE (oC) FIGURE 9. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE 9 100K 1M OUTPUT FREQUENCY (Hz) 10M FIGURE 10. CROSSTALK vs OUTPUT FREQUENCY HI1178 Application Circuit B(BLUE)OUT 200 AVSS G(GREEN)OUT 200 DVDD AVSS AVDD R(RED)OUT 0.1µ 200 48 47 46 45 44 43 42 41 40 39 38 37 AVSS (LSB) 1 36 2 35 3 34 4 33 5 32 R(RED)IN 6 (MSB) (LSB) AVDD 2V 3.3K 1K AVSS AVSS 0.1µ 31 HI1178 7 30 8 (BCK) 29 9 (GCK) 28 10 (RCK) 27 11 26 DVSS CLOCK IN 25 12 DVSS (MSB) G(GREEN)IN (LSB) (MSB) 13 14 15 16 17 18 19 20 21 22 23 24 B(BLUE)IN FIGURE 11. Notes On Operation • How to select the output resistance The HI1178 is a current-output D/A converter. To obtain the output voltage, connect the resistance to IO pin (RO, GO, BO). For specifications we have: Output Full Scale Voltage VFS = less than 2.0 [V] Output Full Scale Current IFS = less than 15 [mA] Calculate the output resistance value from the relation of VFS = IFS X R. Also, 16 times resistance of the output resistance is connected to reference current pin IREF . In some cases, however, this turns out to be a value that does not actually exist. In such a case a value close to it can be used as a substitute. Here please note that VFS becomes VFS = VREF X 16R/R'. R is the resistance connected to IO while R' is connected to IREF . Increasing the resistance value can curb power consumption. On the other hand glitch energy and data settling time will inversely increase. Set the most suitable value according to the desired application. • Phase Relation Between Data and Clock 10 To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. Be sure to satisfy the provisions of the set up time (tS) and hold time (tH) as stipulated in the Electrical Characteristics. • VDD , VSS To reduce noise effects separate analog and digital systems in the device periphery. For VDD pins, both digital and analog, bypass respective GNDs by using a ceramic capacitor of 0.1µF, as close as possible to the pin. HI1178 Metric Plastic Quad Flatpack Packages (MQFP/PQFP) Q48.12x12-S D 48 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE D1 INCHES SYMBOL E E1 e MIN MAX MILLIMETERS MIN MAX NOTES A 0.081 0.100 2.05 2.55 - A1 0.000 0.011 0.00 0.30 - B 0.008 0.017 0.20 0.45 5 D 0.587 0.618 14.90 15.70 2 D1 0.469 0.488 11.90 12.40 3, 4 E 0.587 0.618 14.90 15.70 2 E1 0.469 0.488 11.90 12.40 3, 4 L 0.028 0.043 0.70 1.10 - N 48 48 6 e 0.032 BSC 0.80 BSC Rev. 0 2/96 PIN 1 NOTES: -H- A SEATING PLANE 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. Dimensions D and E to be determined at seating plane -C- . 0.24 0.15 3. Dimensions D1 and E1 to be determined at datum plane -H- . 0.006 4. Dimensions D1 and E1 do not include mold protrusion. -C- M 5. Dimension B does not include dambar protrusion. 6. “N” is the number of terminal positions. B A1 0o-10o L 0.10/0.25 0.004/0.010 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 11