S-8215A Series
www.ablic.com
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK
(SECONDARY PROTECTION)
© ABLIC Inc., 2010-2019
Rev.2.6_00
The S-8215A Series is used for secondary protection of lithium-ion rechargeable batteries, and incorporates high-accuracy
voltage detection circuits and delay circuits.
Short-circuiting between cells makes it possible for serial connection of three cells to five cells.
Features
•
•
•
•
•
•
•
•
•
High-accuracy voltage detection circuit for each cell
Overcharge detection voltage n (n = 1 to 5)
3.600 V to 4.700 V (50 mV step)
Accuracy ±25 mV (Ta = +25°C)
Accuracy ±30 mV (Ta = −5°C to +55°C)
Overcharge hysteresis voltage n (n = 1 to 5)
0.0 mV to −550 mV (50 mV step)
−300 mV to −550 mV
Accuracy ±20%
−100 mV to −250 mV
Accuracy ±50 mV
0.0 mV to −50 mV
Accuracy ±25 mV
Delay times for overcharge detection can be set by an internal circuit only (External capacitors are unnecessary).
Output form is selectable:
CMOS output, Nch open-drain output, Pch open-drain output
Output logic is selectable:
Active "H", active "L"
High-withstand voltage:
Absolute maximum rating 28 V
Wide operation voltage range:
3.6 V to 26 V
Wide operation temperature range:
Ta = −40°C to +85°C
Low current consumption
At VCUn − 1.0 V for each cell:
3.0 μA max. (Ta = +25°C)
At 2.3 V for each cell:
1.7 μA max. (Ta = +25°C)
Lead-free (Sn 100%), halogen-free
Application
•
Lithium-ion rechargeable battery pack (for secondary protection)
Packages
•
•
TMSOP-8
SNT-8A
1
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8215A Series
Rev.2.6_00
Block Diagram
VDD
Overcharge
detection
comparator 1
VC1
+
−
Reference voltage 1
Overcharge
detection
comparator 2
VC2
Oscillator
+
Overcharge
detection / release
delay circuit
−
Reference voltage 2
Overcharge
detection
comparator 3
VC3
+
Control
circuit
−
Reference voltage 3
Overcharge
detection
comparator 4
VC4
+
−
Reference voltage 4
VC5
Overcharge
detection
comparator 5
+
−
Reference voltage 5
VSS
*1. The CO pin is connected only to Nch transistor in the case of Nch open-drain output.
The CO pin is connected only to Pch transistor in the case of Pch open-drain output.
Remark
The diodes in the figure are parasitic diodes.
Figure 1
2
CO*1
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.2.6_00
S-8215A Series
Product Name Structure
1. Product name
S-8215A xx
-
xxxx
U
Environmental code
U:
Lead-free (Sn 100%), halogen-free
Package abbreviation and IC packing specifications*1
K8T2: TMSOP-8, Tape
I8T1: SNT-8A, Tape
Serial code*2
Sequentially set from AA to AZ
*1. Refer to the tape drawing.
*2. Refer to "3. Product name list".
2. Packages
Table 1 Package Drawing Codes
Package Name
TMSOP-8
SNT-8A
Dimension
FM008-A-P-SD
PH008-A-P-SD
Tape
FM008-A-C-SD
PH008-A-C-SD
Reel
FM008-A-R-SD
PH008-A-R-SD
Land
−
PH008-A-L-SD
3
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8215A Series
Rev.2.6_00
3. Product name list
3. 1 TMSOP-8
Table 2
Product Name
Overcharge
Detection
Voltage
[VCU]
4.300 V
4.275 V
4.150 V
4.350 V
4.325 V
4.220 V
4.325 V
4.250 V
4.400 V
4.150 V
4.150 V
4.150 V
4.150 V
4.350 V
4.275 V
4.275 V
4.500 V
4.275 V
4.275 V
3.750 V
4.300 V
4.325 V
4.325 V
4.325 V
4.275 V
Overcharge
Hysteresis
Voltage
[VHC]
−0.300 V
−0.050 V
−0.250 V
−0.250 V
−0.050 V
−0.100 V
−0.300 V
−0.250 V
−0.100 V
−0.050 V
−0.500 V
−0.050 V
−0.500 V
−0.250 V
−0.500 V
−0.050 V
−0.100 V
−0.200 V
−0.050 V
−0.100 V
−0.300 V
−0.050 V
−0.300 V
−0.400 V
−0.050 V
Overcharge
Detection
Delay Time
[tCU]
4.0 s
2.0 s
1.0 s
2.0 s
1.0 s
1.0 s
1.0 s
1.0 s
2.0 s
2.0 s
2.0 s
2.0 s
2.0 s
4.0 s
1.0 s
1.0 s
4.0 s
2.0 s
2.0 s
1.0 s
1.0 s
8.0 s
8.0 s
8.0 s
1.0 s
Output Form
S-8215AAA-K8T2U
CMOS output
S-8215AAB-K8T2U
Nch open-drain output
S-8215AAC-K8T2U
CMOS output
S-8215AAD-K8T2U
CMOS output
S-8215AAE-K8T2U
Nch open-drain output
S-8215AAF-K8T2U
CMOS output
S-8215AAH-K8T2U
Nch open-drain output
S-8215AAI-K8T2U
CMOS output
S-8215AAJ-K8T2U
CMOS output
S-8215AAK-K8T2U
Nch open-drain output
S-8215AAL-K8T2U
Nch open-drain output
S-8215AAM-K8T2U
CMOS output
S-8215AAN-K8T2U
CMOS output
S-8215AAO-K8T2U
CMOS output
S-8215AAP-K8T2U
CMOS output
S-8215AAQ-K8T2U
CMOS output
S-8215AAR-K8T2U
CMOS output
S-8215AAS-K8T2U
CMOS output
S-8215AAT-K8T2U
CMOS output
S-8215AAU-K8T2U
CMOS output
S-8215AAV-K8T2U
CMOS output
S-8215AAW-K8T2U
CMOS output
S-8215AAX-K8T2U
CMOS output
S-8215AAY-K8T2U
CMOS output
S-8215AAZ-K8T2U
Nch open-drain output
Remark
Please contact our sales office for products other than the above.
Output Logic
Active "H"
Active "L"
Active "H"
Active "H"
Active "L"
Active "H"
Active "L"
Active "H"
Active "H"
Active "L"
Active "L"
Active "L"
Active "L"
Active "H"
Active "H"
Active "H"
Active "H"
Active "L"
Active "L"
Active "H"
Active "H"
Active "H"
Active "H"
Active "H"
Active "L"
3. 2 SNT-8A
Table 3
Product Name
S-8215AAA-I8T1U
S-8215AAG-I8T1U
S-8215AAV-I8T1U
Remark
4
Overcharge
Detection
Voltage
[VCU]
4.300 V
4.220 V
4.300 V
Overcharge
Hysteresis
Voltage
[VHC]
−0.300 V
−0.050 V
−0.300 V
Overcharge
Detection
Delay Time
[tCU]
4.0 s
1.0 s
1.0 s
Output Form
CMOS output
CMOS output
CMOS output
Please contact our sales office for products other than the above.
Output Logic
Active "H"
Active "H"
Active "H"
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.2.6_00
S-8215A Series
Pin Configurations
1. TMSOP-8
Table 4
Pin No. Symbol
1
VDD
2
VC1
Top view
1
2
3
4
8
7
6
5
Figure 2
3
VC2
4
VC3
5
VC4
6
VC5
7
VSS
8
CO
Description
Input pin for positive power supply
Positive voltage connection pin of battery 1
Negative voltage connection pin of battery 1
Positive voltage connection pin of battery 2
Negative voltage connection pin of battery 2
Positive voltage connection pin of battery 3
Negative voltage connection pin of battery 3
Positive voltage connection pin of battery 4
Negative voltage connection pin of battery 4
Positive voltage connection pin of battery 5
Input pin for negative power supply
Negative voltage connection pin of battery 5
FET gate connection pin for charge control
2. SNT-8A
Table 5
Pin No.
Top view
1
2
3
4
8
7
6
5
Figure 3
Symbol
1
2
VDD
VC1
3
VC2
4
VC3
5
VC4
6
VC5
7
VSS
8
CO
Description
Input pin for positive power supply
Positive voltage connection pin of battery 1
Negative voltage connection pin of battery 1
Positive voltage connection pin of battery 2
Negative voltage connection pin of battery 2
Positive voltage connection pin of battery 3
Negative voltage connection pin of battery 3
Positive voltage connection pin of battery 4
Negative voltage connection pin of battery 4
Positive voltage connection pin of battery 5
Input pin for negative power supply
Negative voltage connection pin of battery 5
FET gate connection pin for charge control
5
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8215A Series
Rev.2.6_00
Absolute Maximum Ratings
Table 6
(Ta = +25°C unless otherwise specified)
Item
Symbol
Applied Pin
Absolute Maximum Rating
VSS − 0.3 to VSS + 28
Input voltage between VDD pin and VSS pin
VDS
VDD
Input pin voltage
VIN
VC1, VC2, VC3, VC4, VC5 VSS − 0.3 to VDD + 0.3
VSS − 0.3 to VDD + 0.3
CMOS output product
CO pin
VSS − 0.3 to VSS + 28
Nch open-drain output product VCO
CO
output voltage
VDD − 28 to VDD + 0.3
Pch open-drain output product
650*1
TMSOP-8
Power
−
PD
dissipation
SNT-8A
450*1
−
−40 to +85
Operation ambient temperature
Topr
Storage temperature
Tstg
−
Unit
V
V
V
V
V
mW
mW
°C
−40 to +125
*1. When mounted on board
[Mounted board]
(1) Board size:
114.3 mm × 76.2 mm × t1.6 mm
(2) Name:
JEDEC STANDARD51-7
Caution
The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Power Dissipation (PD) [mW]
800
TMSOP-8
600
SNT-8A
400
200
0
0
150
100
50
Ambient Temperature (Ta) [°C]
Figure 4 Power Dissipation of Package (When Mounted on Board)
6
°C
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.2.6_00
S-8215A Series
Electrical Characteristics
Table 7
Item
Symbol
Condition
(Ta = +25°C unless otherwise specified)
Test
Min.
Typ.
Max.
Unit
Circuit
Detection Voltage
Overcharge detection
voltage n (n = 1, 2, 3, 4, 5)
VCUn
−
Ta = −5°C to +55°C*1
−550 mV ≤ VHC ≤ −300 mV
Overcharge hysteresis
voltage n (n = 1, 2, 3, 4, 5)
VHCn
−250 mV ≤ VHC ≤ −100 mV
VHC = −50 mV, 0 mV
VCU
− 0.025
VCU
− 0.030
VHC × 0.8
VHC
− 0.050
VHC
− 0.025
Input Voltage
Operation voltage between
VDSOP
3.6
−
VDD pin and VSS pin
Input Current
Current consumption during
IOPE
V1 = V2 = V3 = V4 = V5 = VCU − 1.0 V
−
operation
Current consumption during
V1 = V2 = V3 = V4 = V5 = 2.3 V
IOPED
−
overdischarge
VC1 pin current
IVC1
V1 = V2 = V3 = V4 = V5 = VCU − 1.0 V
−
VCn pin current
IVCn
V1 = V2 = V3 = V4 = V5 = VCU − 1.0 V
−0.3
(n = 2, 3, 4, 5)
Output Current (CMOS Output Product)
CO pin sink current
ICOL
0.4
−
CO pin source current
20
ICOH
−
Output Current (Nch Open-drain Output Product)
CO pin sink current
ICOL
0.4
−
CO pin leakage current "L"
ICOLL
−
−
Output Current (Pch Open-drain Output Product)
CO pin source current
ICOH
20
−
CO pin leakage current "H" ICOLH
−
−
Delay Time
Overcharge detection delay
tCU
−
tCU × 0.8
time
Overcharge timer reset
6
tTR
−
delay time
Transition time to test mode tTST
−
−
VCU
+ 0.025
VCU
+ 0.030
VHC × 1.2
VHC
+ 0.050
VHC
+ 0.025
−
VCU
V
1
V
1
V
1
V
1
V
1
26
V
−
1.6
3.0
μA
3
0.8
1.7
μA
3
0.2
0.4
μA
4
0
0.3
μA
4
−
−
−
−
mA
μA
5
5
−
−
−
0.1
mA
μA
5
5
−
−
−
0.1
μA
μA
5
5
tCU
tCU × 1.2
s
1
12
20
ms
1
−
80
ms
2
VCU
VHC
VHC
VHC
*1. Since products are not screened at high and low temperature, the specification for this temperature range is guaranteed
by design, not tested in production.
7
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8215A Series
Rev.2.6_00
Test Circuits
1. Overcharge detection voltage, overcharge hysteresis voltage
(Test circuit 1)
1. 1 Overcharge detection voltage n (VCUn)
Set V1 = V2 = V3 = V4 = V5 = VCU − 0.05 V. The overcharge detection voltage 1 (VCU1) is the V1 voltage when the CO
pin’s output changes after the voltage of V1 has been gradually increased.
Overcharge detection voltage (VCUn) (n = 2 to 5) can be determined in the same way as when n = 1.
1. 2 Overcharge hysteresis voltage n (VHCn)
Set V1 = VCU + 0.05 V, V2 = V3 = V4 = V5 = 2.5 V. The overcharge hysteresis voltage 1 (VHC1) is the difference
between V1 voltage and VCU1 when the CO pin's output changes after the V1 voltage has been gradually decreased.
Overcharge hysteresis voltage (VHCn) (n = 2 to 5) can be determined in the same way as when n = 1.
2. Output current
(Test circuit 5)
2. 1 Output current of CMOS output product
Set SW1 and SW2 to OFF.
2. 1. 1 Active "H"
(1) CO pin source current (ICOH)
Set SW1 to ON after setting V1 = 5.5 V, V2 to V5 = 3.0 V, V6 = 0.5 V. I1 is the CO pin source current (ICOH) at
that time.
(2) CO pin sink current (ICOL)
Set SW2 to ON after setting V1 to V5 = 3.5 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time.
2. 1. 2 Active "L"
(1) CO pin source current (ICOH)
Set SW1 to ON after setting V1 to V5 = 3.5 V, V6 = 0.5 V. I1 is the CO pin source current (ICOH) at that time.
(2) CO pin sink current (ICOL)
Set SW2 to ON after setting V1 = 5.5 V, V2 to V5 = 3.0 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that
time.
2. 2 Output current of Nch open-drain output product
Set SW1 and SW2 to OFF.
2. 2. 1 Active "H"
(1) CO pin leakage current "L" (ICOLL)
Set SW2 to ON after setting V1 = 5.5 V, V2 to V5 = 3.0 V, V7 = 17.5 V. I2 is the CO pin leakage current "L"
(ICOLL) at that time.
(2) CO pin sink current (ICOL)
Set V1 to V5 = 3.5 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time.
2. 2. 2 Active "L"
(1) CO pin leakage current "L" (ICOLL)
Set SW2 to ON after setting V1 to V5 = 3.5 V, V7 = 17.5 V. I2 is the CO pin leakage current "L" (ICOLL) at that
time.
(2) CO pin sink current (ICOL)
Set V1 = 5.5 V, V2 to V5 = 3.0 V, V7 = 0.5 V. I2 is the CO pin sink current (ICOL) at that time.
8
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.2.6_00
S-8215A Series
2. 3 Output current of Pch open-drain output product
Set SW1 and SW2 to OFF.
2. 3. 1 Active "H"
(1) CO pin source current (ICOH)
Set SW1 to ON after setting V1 = 5.5 V, V2 to V5 = 3.0 V, V6 = 0.5 V. I1 is the CO pin source current (ICOH) at
that time.
(2) CO pin leakage current "H" (ICOLH)
Set V1 to V5 = 3.5 V, V6 = 17.5 V. I1 is the CO pin leakage current "H" (ICOLH) at that time.
2. 3. 2 Active "L"
(1) CO pin source current (ICOH)
Set SW1 to ON after setting V1 to V5 = 3.5 V, V6 = 0.5 V. I1 is the CO pin source current (ICOH) at that time.
(2) CO pin leakage current "H" (ICOLH)
Set V1 = 5.5 V, V2 to V5 = 3.0 V, V6 = 17.5 V. I1 is the CO pin leakage current "H" (ICOLH) at that time.
3. Overcharge detection delay time (tCU)
(Test circuit 1)
Increase V1 up to 5.0 V after setting V1 = V2 = V3 = V4 = V5 = 3.5 V. The overcharge detection delay time (tCU) is the
time period until the CO pin output changes.
4. Overcharge timer reset delay time (tTR)
(Test circuit 1)
Increase V1 up to 5.0 V (first rise), and decrease V1 down to 3.5 V within tCU after setting V1 = V2 = V3 = V4 = V5 =
3.5 V. After that, increase V1 up to 5.0 V again (second rise), and detect the time period till the CO pin output changes.
When the period from when V1 has fallen to the second rise is short, CO pin output changes after tCU has elapsed since
the first rise. If the period is gradually made longer, CO pin output changes after tCU has elapsed since the second rise.
The overcharge timer reset delay time (tTR) is the period from V1 fall till the second rise at that time.
5. Transition time to test mode (tTST)
(Test circuit 2)
Increase V6 up to 5.0 V, and decrease V6 again to 0 V after setting V1 = V2 = V3 = V4 = V5 = 3.5 V, and V6 = 0 V.
When the period from when V6 was raised to when it has fallen is short, if an overcharge detection operation is
performed subsequently, the delay time is tCU. However, when the period from when V6 is raised to when it has fallen is
gradually made longer, the delay time during the subsequent overcharge detection operation is shorter than tCU. The
transition time to test mode (tTST) is the period from when V6 was raised to when it has fallen at that time.
9
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8215A Series
Rev.2.6_00
S-8215A Series
VDD
S-8215A Series
CO
VC1
VC1
VC5
V2
VC3
V5
V1
V4
V2
VC2
VC5
VC3
VC4
V4
V3
Figure 5 Test Circuit 1
IOPE
IOPED
Figure 6 Test Circuit 2
S-8215A Series
S-8215A Series
VDD
CO
VDD
CO
VC1
VSS
A
IVC2
VC1
VSS
A
VC2
VC5
IVC5
A
VC4
IVC4
A
IVC1
A
V5
V1
VC2
VC5
VC3
V1
V4
V2
V2
IVC3
A
VC4
V3
VC3
V3
Figure 7 Test Circuit 3
Figure 8 Test Circuit 4
V6
A I1
SW1
S-8215A Series
VDD
CO
VC1
VSS
VC2
VC5
VC3
VC4
V1
SW2
V5
V2
V4
V3
Figure 9 Test Circuit 5
10
VSS
V5
VC4
V3
CO
V
VSS
V1
VC2
VDD
V6
V
A I2
V7
V
V5
V4
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.2.6_00
S-8215A Series
Operation
Remark Refer to " Battery Protection IC Connection Examples".
1. Normal status
If the voltage of each of the batteries is lower than "the overcharge detection voltage n (VCUn) + the overcharge
hysteresis voltage n (VHCn)", the CO pin output changes to "L" (Active "H") or "H" (Active L"). This is called normal
status.
2. Overcharge status
When the voltage of one of the batteries exceeds VCUn during charging under normal status and the status is retained
for the overcharge detection delay time (tCU) or longer, the CO pin output changes. This is called overcharge status.
Connecting FET to the CO pin provides charge control and a second protection.
If the voltage of each of the batteries is lower than VCUn + VHCn and the status is retained for 2.0 ms typ. or longer, the
S-8215A Series returns to normal status.
3. Overcharge timer reset function
When an overcharge release noise that forces the voltage of one of the batteries temporarily below VCUn is input during
tCU from when VCUn is exceeded to when charging is stopped, tCU is continuously counted if the time the overcharge
release noise persists is shorter than the overcharge timer reset delay time (tTR). Under the same conditions, if the time
the overcharge release noise persists is tTR or longer, counting of tCU is reset once. After that, when VCUn has been
exceeded, counting tCU resumes.
11
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8215A Series
Rev.2.6_00
4. Test mode
The overcharge detection delay time (tCU) can be shortened by entering the test mode.
The test mode can be set by retaining the VDD pin voltage 5.0 V or more higher than the VC1 pin voltage for the
transition time to test mode (tTST) or longer. The status is retained by the internal latch and the test mode is retained
even if the VDD pin voltage is decreased to the same voltage as that of the VC1 pin voltage.
After that, the latch for retaining the test mode is reset and the S-8215A Series exits from test mode under the
overcharge status.
VDD pin voltage
VC1 pin voltage
5.0 V or
more
Pin voltage
VCUn
VHCn
Battery voltage
(n = 1 to 5)
Test mode
tTST = 80 ms max.
CO pin
(Active "H")
CO pin
(Active "L")
32 ms typ.
2.0 ms typ.
Figure 10
Caution
12
1. When the VDD pin voltage is decreased to lower than the UVLO voltage of 2 V typ., the
S-8215A Series exits from test mode.
2. Set the test mode when no batteries are overcharged.
3. The overcharge timer reset delay time (tTR) is not shortened in the test mode.
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.2.6_00
S-8215A Series
Timing Charts
1. Overcharge detection operation
VHCn
VCUn
Battery voltage
(n = 1 to 5)
tTR or longer
CO pin
(Active "H")
tTR or shorter
tCU or shorter
CO pin
(Active "L")
tCU
2.0 ms typ.
Figure 11
13
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8215A Series
Rev.2.6_00
2. Overcharge timer reset operation
VHCn
tTR or shorter
tTR or longer
tTR or shorter
VCUn
Battery voltage
(n = 1 to 5)
tTR
CO pin
(Active "H")
tCU or shorter
Timer reset
tCU
CO pin
(Active "L")
Figure 12
14
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.2.6_00
S-8215A Series
Battery Protection IC Connection Examples
1. 5-serial cell
SCP
EB+
VDD
RVDD
CVDD
VC1
R1
BAT1
C1
VC2
R2
BAT2
S-8215A
Series
C2
VC3
R3
BAT3
VC4
R4
BAT4
FET
C3
CO
DP
C4
VC5
R5
BAT5
C5
VSS
EB−
Figure 13
Table 8 Constants for External Components
No.
1
2
3
Caution
Part
R1 to R5
C1 to C5, CVDD
RVDD
Min.
0.5
0.01
50
Typ.
1
0.1
100
Max.
10
1
500
Unit
kΩ
μF
Ω
1. The above constants are subject to change without prior notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constants
will not guarantee successful operation. Perform thorough evaluation using the actual
application to set the constants.
3. R1 to R5 should be the same constant. C1 to C5 and CVDD should be the same constant.
4. Set RVDD, C1 to C5, and CVDD so that the condition (RVDD) × (C1 to C5, CVDD) ≥ 5 × 10−6 is satisfied.
5. Set R1 to R5, C1 to C5, and CVDD so that the condition (R1 to R5) × (C1 to C5, CVDD) ≥ 1 × 10−4 is
satisfied.
6. Since the CO pin may become detection status transiently when the battery is being connected,
connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse
from cutoff.
15
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8215A Series
Rev.2.6_00
2. 4-serial cell
SCP
EB+
VDD
RVDD
CVDD
VC1
R1
BAT1
C1
VC2
R2
BAT2
S-8215A
Series
C2
VC3
R3
BAT3
C3
VC4
R4
BAT4
FET
CO
DP
C4
VC5
VSS
EB−
Figure 14
Table 9 Constants for External Components
No.
1
2
3
Caution
16
Part
R1 to R4
C1 to C4, CVDD
RVDD
Min.
0.5
0.01
50
Typ.
1
0.1
100
Max.
10
1
500
Unit
kΩ
μF
Ω
1. The above constants are subject to change without prior notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constants
will not guarantee successful operation. Perform thorough evaluation using the actual
application to set the constants.
3. R1 to R4 should be the same constant. C1 to C4 and CVDD should be the same constant.
4. Set RVDD, C1 to C4, and CVDD so that the condition (RVDD) × (C1 to C4, CVDD) ≥ 5 × 10−6 is satisfied.
5. Set R1 to R4, C1 to C4, and CVDD so that the condition (R1 to R4) × (C1 to C4, CVDD) ≥ 1 × 10−4 is
satisfied.
6. Since the CO pin may become detection status transiently when the battery is being connected,
connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse
from cutoff.
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.2.6_00
S-8215A Series
3. 3-serial cell
SCP
EB+
VDD
RVDD
CVDD
VC1
R1
BAT1
C1
VC2
R2
BAT2
S-8215A
Series
C2
VC3
R3
BAT3
FET
C3
VC4
CO
DP
VC5
VSS
EB−
Figure 15
Table 10 Constants for External Components
No.
1
2
3
Caution
Part
R1 to R3
C1 to C3, CVDD
RVDD
Min.
0.5
0.01
50
Typ.
1
0.1
100
Max.
10
1
500
Unit
kΩ
μF
Ω
1. The above constants are subject to change without prior notice.
2. It has not been confirmed whether the operation is normal or not in circuits other than the above
example of connection. In addition, the example of connection shown above and the constants
will not guarantee successful operation. Perform thorough evaluation using the actual
application to set the constants.
3. R1 to R3 should be the same constant. C1 to C3 and CVDD should be the same constant.
4. Set RVDD, C1 to C3, and CVDD so that the condition (RVDD) × (C1 to C3, CVDD) ≥ 5 × 10−6 is satisfied.
5. Set R1 to R3, C1 to C3, and CVDD so that the condition (R1 to R3) × (C1 to C3, CVDD) ≥ 1 × 10−4 is
satisfied.
6. Since the CO pin may become detection status transiently when the battery is being connected,
connect the positive terminal of BAT1 last in order to prevent the three terminal protection fuse
from cutoff.
17
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8215A Series
Rev.2.6_00
[For SCP, contact]
Global Sales & Marketing Division, Dexerials Corporation
Gate City Osaki East Tower 8F, 1-11-2
Osaki, Shinagawa-ku, Tokyo, 141-0032, Japan
TEL +81-3-5435-3946
Contact Us: http://www.dexerials.jp/en/
Precautions
18
•
Do not connect batteries charged with VCUn + VHCn or higher. If the connected batteries include a battery charged with
VCUn + VHCn or higher, the S-8215A series may become overcharge status after all pins are connected.
•
In some application circuits, even if an overcharged battery is not included, the order of connecting batteries may be
restricted to prevent transient output of CO detection pulses when the batteries are connected. Perform thorough
evaluation with the actual application circuit.
•
Before the battery connection, short-circuit the battery side pins RVDD and R1, shown in the figure in " Battery
Protection IC Connection Examples".
•
The application conditions for the input voltage, output voltage, and load current should not exceed the package power
dissipation.
•
Do not apply to this IC an electrostatic discharge that exceeds the performance ratings of the built-in electrostatic
protection circuit.
•
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement of patents
owned by a third party by products including this IC.
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.2.6_00
S-8215A Series
Characteristics (Typical Data)
1. Detection voltage
1. 2 VCU + VHC vs. Ta
1. 1 VCU vs. Ta
VHC = −0.3 V
+
VCU = 4.3 V
−40 −25
0
25
Ta [°C]
50
−40 −25
75 85
0
25
Ta [°C]
50
75 85
2. Current consumption
2. 1 IOPE vs. Ta
2. 2 IOPED vs. Ta
VDD = 11.5 V
μ
μ
VDD = 16.5 V
−40 −25
0
25
Ta [°C]
50
75 85
−40 −25
0
25
Ta [°C]
50
75 85
2. 3 IOPE vs. VDD
Ta = +25°C
60
IOPE [μA]
50
40
30
20
10
0
0
5
10
15
20
VDD [V]
25
30
19
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
S-8215A Series
Rev.2.6_00
3. Delay time
3. 1 tCU vs. Ta
VDD = 19 V
−40 −25
0
25
Ta [°C]
50
75 85
4. Output current
4. 1 ICOL vs. VDD
4. 2 ICOH vs. VDD
Ta = +25°C
20
750
7.5
5.0
2.5
0.0
Ta = +25°C
1000
ICOH [μA]
ICOL [mA]
10.0
500
250
0
0
5
10
15
20
VDD [V]
25
30
0
5
10
15
20
VDD [V]
25
30
BATTERY PROTECTION IC FOR 3-SERIAL TO 5-SERIAL CELL PACK (SECONDARY PROTECTION)
Rev.2.6_00
S-8215A Series
Marking Specifications
1. TMSOP-8
8
Top view
7
6
5
(1):
(2) to (4):
(5):
(6) to (8):
Blank
Product code (Refer to Product name vs. Product code)
Blank
Lot number
(1) (2) (3) (4)
(5) (6) (7) (8)
1
2
3
4
Product name vs. Product code
Product Code
(2)
(3)
(4)
V
6
A
V
6
B
V
6
C
V
6
D
V
6
E
V
6
F
V
6
H
V
6
I
V
6
J
V
6
K
V
6
L
V
6
M
Product Name
S-8215AAA-K8T2U
S-8215AAB-K8T2U
S-8215AAC-K8T2U
S-8215AAD-K8T2U
S-8215AAE-K8T2U
S-8215AAF-K8T2U
S-8215AAH-K8T2U
S-8215AAI-K8T2U
S-8215AAJ-K8T2U
S-8215AAK-K8T2U
S-8215AAL-K8T2U
S-8215AAM-K8T2U
Product Name
S-8215AAN-K8T2U
S-8215AAO-K8T2U
S-8215AAP-K8T2U
S-8215AAQ-K8T2U
S-8215AAR-K8T2U
S-8215AAS-K8T2U
S-8215AAT-K8T2U
S-8215AAU-K8T2U
S-8215AAV-K8T2U
S-8215AAW-K8T2U
S-8215AAX-K8T2U
S-8215AAY-K8T2U
S-8215AAZ-K8T2U
Product Code
(2)
(3)
(4)
V
6
N
V
6
O
V
6
P
V
6
Q
V
6
R
V
6
S
V
6
T
V
6
U
V
6
V
V
6
W
V
6
X
V
6
Y
V
6
Z
2. SNT-8A
8
Top view
7
6
5
(1):
(2) to (4):
(5), (6):
(7) to (11):
(1) (2) (3) (4)
Blank
Product code (Refer to Product name vs. Product code)
Blank
Lot number
(5) (6) (7) (8)
(9) (10) (11)
1
2
3
4
Product name vs. Product code
Product Name
S-8215AAA-I8T1U
S-8215AAG-I8T1U
S-8215AAV-I8T1U
Product Code
(2)
(3)
(4)
V
6
A
V
6
G
V
6
V
21
2.90±0.2
8
5
1
4
0.13±0.1
0.2±0.1
0.65±0.1
No. FM008-A-P-SD-1.2
TITLE
TMSOP8-A-PKG Dimensions
No.
FM008-A-P-SD-1.2
ANGLE
UNIT
mm
ABLIC Inc.
2.00±0.05
4.00±0.1
4.00±0.1
1.00±0.1
+0.1
1.5 -0
1.05±0.05
0.30±0.05
3.25±0.05
4
1
5
8
Feed direction
No. FM008-A-C-SD-2.0
TITLE
TMSOP8-A-Carrier Tape
FM008-A-C-SD-2.0
No.
ANGLE
UNIT
mm
ABLIC Inc.
16.5max.
13.0±0.3
Enlarged drawing in the central part
13±0.2
(60°)
(60°)
No. FM008-A-R-SD-1.0
TITLE
TMSOP8-A-Reel
No.
FM008-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
4,000
1.97±0.03
8
7
6
5
3
4
+0.05
1
0.5
2
0.08 -0.02
0.48±0.02
0.2±0.05
No. PH008-A-P-SD-2.1
TITLE
SNT-8A-A-PKG Dimensions
No.
PH008-A-P-SD-2.1
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
ø1.5 -0
2.25±0.05
4.0±0.1
2.0±0.05
ø0.5±0.1
0.25±0.05
0.65±0.05
4.0±0.1
4 321
5 6 78
Feed direction
No. PH008-A-C-SD-2.0
TITLE
SNT-8A-A-Carrier Tape
No.
PH008-A-C-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PH008-A-R-SD-1.0
TITLE
SNT-8A-A-Reel
No.
PH008-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
5,000
0.52
2.01
2
0.52
0.2 0.3
1.
2.
1
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
1.
2.
3.
4.
0.03 mm
SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1.
2.
(0.25 mm min. / 0.30 mm typ.)
(1.96 mm ~ 2.06 mm)
TITLE
No. PH008-A-L-SD-4.1
SNT-8A-A
-Land Recommendation
PH008-A-L-SD-4.1
No.
ANGLE
UNIT
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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