2Pai Semi
Enhanced ESD, 3.0 kV rms/6.0 kV rms
150Kbps Dual-Channel Digital Isolators
π120U/π121U/π122U
Data Sheet
FEATURES
Ultra low power consumption (150Kbps):
0.55mA/Channel
High data rate: π12xAxx: 600Mbps
π12xExx: 200Mbps
π12xMxx: 10Mbps
π12xUxx: 150kbps
High common-mode transient immunity: 150 kV/µs typical
High robustness to radiated and conducted noise
Isolation voltages:
π12xx3x: AC 3000Vrms
π12xx6x: AC 6000Vrms
High ESD rating:
ESDA/JEDEC JS-001-2017
Human body model (HBM) ±8kV, all pins
Safety and regulatory approvals (Pending)：
UL certificate number: E494497
3000Vrms/6000Vrms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate number: 40047929
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 707V peak/1200V peak
CQC certification per GB4943.1-2011
3 V to 5.5 V level translation
Wide temperature range: -40°C to 125°C
8/16-lead, RoHS-compliant, (W)SOIC package
APPLICATIONS
to 600Mbps (see the Ordering Guide). The devices operate with
the supply voltage on either side ranging from 3.0 V to 5.5 V,
providing compatibility with lower voltage systems as well as
enabling voltage translation functionality across the isolation
barrier. The fail-safe state is available in which the outputs
transition to a preset state when the input power supply is not
applied.
FUNCTIONAL BLOCK DIAGRAMS
π120X3X
VDD1
1
8
VDD2
VIA
2
7
VOA
VIB
3
6
VOB
GND1
4
5
GND2
π121X3X
VDD1
1
8
VDD2
VIA
2
7
VOA
OB
V
3
6
VIB
GND1
4
5
GND2
VDD1
1
VOA
2
VIB
GND 1
π122X3X
8
VDD2
7
VIA
3
6
VOB
4
5
GND2
General-purpose multichannel isolation
Industrial field bus isolation
GENERAL DESCRIPTION
The π1xxxxx is a 2PaiSemi digital isolators product family that
includes over hundreds of digital isolator products. By using
maturated standard semiconductor CMOS technology and
2PaiSEMI iDivider technology, these isolation components
provide outstanding performance characteristics and reliability
superior to alternatives such as optocoupler devices and other
integrated isolators.
Intelligent voltage divider technology (iDivider technology) is a
new generation digital isolator technology invented by 2PaiSEMI.
It uses the principle of capacitor voltage divider to transmit
voltage signal directly cross the isolator capacitor without signal
modulation and demodulation.
π120X6X
GND 1
1
16
GND2
NC
2
15
NC
VDD1
3
14
VDD2
VIA
4
13
VOA
VIB
5
12
VOB
NC
6
11
NC
GND 1
7
10
NC
GND 1
8
9
GND2
GND 1
1
16
GND2
NC
2
15
NC
VDD1
3
14
VDD2
VIA
4
13
VOA
VOB
5
12
VIB
NC
6
11
NC
GND 1
7
10
NC
GND 1
8
9
GND2
GND1
1
16
GND2
NC
2
15
NC
VDD1
3
14
VDD2
VOA
4
13
VIA
VIB
5
12
VOB
π121X6X
π122X6X
NC
6
11
NC
GND 1
7
10
NC
GND1
8
9
GND2
Figure1. π120xxx/π121xxx/π122xxx functional Block Diagram
VDD1
VDD2
CIN
COUT
0.1uF
0.1uF
1
2
3
4
VIN_A
VIN_B
GND1
VDD1
VIA
VIB
GND1
VDD2
VOA
VOB
GND 2
π120
8
7
6
5
VOUT_A
VOUT_B
GND2
Figure2. π120xxx Typical Application Circuit
The π1xxxxx isolator data channels are independent and are
available in a variety of configurations with a withstand voltage
rating of 1.5 kV rms to 6.0 kV rms and the data rate from DC up
Rev.1
Information furnished by 2Pai semi is believed to be accurate and reliable. However, no
responsibility is assumed by 2Pai semi for its use, nor for any infringements of patents or
other rights of third parties that may result from its use. Specifications subject to change
without notice. No license is granted by implication or otherwise under any patent or
patent rights of 2Pai semi.
Trademarks and registered trademarks are the property of their respective owners.
Room 308-309, No.22, Boxia Road, Pudong New District, Shanghai, 201203, China
021-50850681
2Pai Semiconductor Co., Limited. All rights reserved.
http://www.rpsemi.com/
π120U/π121U/π122U
Data Sheet
PIN CONFIGURATIONS AND FUNCTIONS
π120U3x Pin Function Descriptions
Pin No.
Name
Description
1
VDD1
Supply Voltage for Isolator Side 1.
2
VIA
Logic Input A.
3
VIB
Logic Input B.
4
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
5
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
6
VOB
Logic Output B.
7
VOA
Logic Output A.
8
VDD2
Supply Voltage for Isolator Side 2.
Figure3. π120U3x Pin Configuration
π121U3x Pin Function Descriptions
Pin No.
Name
Description
1
VDD1
Supply Voltage for Isolator Side 1.
VIA
2
2
VIA
Logic Input A.
VOB
3
3
VOB
Logic Output B.
GND1
4
4
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
5
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
6
VIB
Logic Input B.
7
VOA
Logic Output A.
8
VDD2
Supply Voltage for Isolator Side 2.
VDD1 1
π121x4
8 VDD2
7 VOA
TOP VIEW
(Not to scale)
6 VIB
5 GND2
Figure4. π121U3x Pin Configuration
π122U3x Pin Function Descriptions
Pin No.
Name
Description
1
VDD1
Supply Voltage for Isolator Side 1.
VOA 2
2
VOA
Logic Output A.
VIB 3
3
VIB
Logic Input B.
4
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
5
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
6
VOB
Logic Output B.
7
VIA
Logic Input A.
8
VDD2
Supply Voltage for Isolator Side 2.
VDD1 1
GND1 4
π120U6x Pin Function Descriptions
π122x4
7 VIA
TOP VIEW
(Not to scale)
6
VOB
5 GND2
Figure5. π122U3x Pin Configuration
16 GND2
GND1 1
Pin No.
Name
Description
1
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
2
NC
No connect.
3
VDD1
Supply Voltage for Isolator Side 1.
4
VIA
Logic Input A.
VIB 5
5
VIB
Logic Input B.
NC 6
6
NC
No Connect.
7
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
8
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
9
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
Rev. 1 | Page 2 of 15
8 VDD2
π120x6
NC
2
VDD1
3
14 VDD2
VIA
4
13 VOA
TOP VIEW
(Not to scale)
15 NC
12 VOB
11 NC
GND1 7
10 NC
GND1 8
9 GND2
Figure6. π120U6x Pin Configuration
π120U/π121U/π122U
Data Sheet
10
NC
No Connect.
11
NC
No Connect.
12
VOB
Logic Output B.
13
VOA
Logic Output A.
14
VDD2
Supply Voltage for Isolator Side 2.
15
NC
No Connect.
16
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
π121U6x Pin Function Descriptions
Pin No.
Name
Description
1
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
2
NC
No Connect.
3
VDD1
Supply Voltage for Isolator Side 1.
4
VIA
Logic Input A.
5
VOB
Logic Output B.
6
NC
No Connect.
7
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
8
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
9
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
10
NC
No Connect.
11
NC
No Connect.
12
VIB
Logic Input B.
13
VOA
Logic Output A.
14
VDD2
Supply Voltage for Isolator Side 2.
15
NC
No Connect.
16
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
GND1 1
NC 2
16 GND2
π121x6
15 NC
VDD1 3
14 VDD2
VIA 4
13 VOA
VOB
5
NC
6
TOP VIEW
(Not to scale)
12 VIB
11 NC
GND1 7
10 NC
GND1 8
9 GND2
Figure7. π121U6x Pin Configuration
Figure8. π121x6 Pin Configuration
π122U6x Pin Function Descriptions
Pin No.
Name
Description
1
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
2
NC
No Connect.
3
VDD1
Supply Voltage for Isolator Side 1.
4
VOA
Logic Output A.
5
VIB
Logic Input B.
6
NC
No Connect.
7
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
8
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
GND1 7
10 NC
GND1 8
9 GND2
GND1 1
NC 2
9
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
10
NC
No Connect.
11
NC
No Connect.
12
VOB
Logic Output B.
13
VIA
Logic Input A.
14
VDD2
Supply Voltage for Isolator Side 2.
15
NC
No Connect.
16
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
16 GND2
π122x6
15 NC
VDD1 3
14 VDD2
VOA 4
13 VIA
VIB
5
NC
6
TOP VIEW
(Not to scale)
12 VOB
11 NC
Figure8. π122U6x Pin Configuration
Figure9. π122x6 Pin Configuration
Rev. 1 | Page 3 of 15
π120U/π121U/π122U
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 1. Absolute Maximum Ratings4
Parameter
Rating
Supply Voltages (VDD1-GND1, VDD2-GND2)
Input Voltages
−0.5 V to +7.0 V
(VIA, VIB)1
Output Voltages
−0.5 V to VDDx + 0.5 V
(VOA, VOB)1
−0.5 V to VDDx + 0.5 V
Average Output Current per Pin2 Side 1 Output Current (IO1)
−10 mA to +10 mA
Average Output Current per Pin2 Side 2 Output Current (IO2)
−10 mA to +10 mA
Common-Mode Transients
Immunity 3
−150 kV/µs to +150 kV/µs
Storage Temperature (TST) Range
−65°C to +150°C
Ambient Operating Temperature (TA) Range
−40°C to +125°C
Notes:
1 VDDx is the side voltage power supply VDD, where x = 1 or 2.
2 See Figure9 for the maximum rated current values for various temperatures.
3 See Figure18 for Common-mode transient immunity (CMTI) measurement.
4 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating
conditions for extended periods may affect product reliability.
RECOMMENDED OPERATING CONDITIONS
Table 2. Recommended Operating Conditions
Parameter
Supply Voltage
High Level Input Signal Voltage
Symbol
Min
VDDx 1
3
VIH
0.7*VDDx
Low Level Input Signal Voltage
VIL
0
High Level Output Current
IOH
-6
Low Level Output Current
IOL
Maximum Data Rate
Typ
1
Max
Unit
5.5
V
VDDx
1
0.3*VDDx
V
1
V
mA
6
mA
0
150
Kbps
Junction Temperature
TJ
-40
150
°C
Ambient Operating Temperature
TA
-40
125
°C
Notes:
1 VDDx is the side voltage power supply VDD, where x = 1 or 2.
Truth Tables
Table 3. π120xxx/π121xxx/π122xxx Truth Table
Default Low
Default High
VOx Output1
VOx Output1
Test Conditions
/Comments
Powered2
Low
Low
Normal operation
Powered2
High
High
Normal operation
Open
Powered2
Powered2
Low
High
Default output
Don’t Care4
Unpowered3
Powered2
Low
High
Default output5
Don’t Care4
Powered2
Unpowered3
High Impedance
High Impedance
VIx Input1
VDDI State1
VDDO State1
Low
Powered2
High
Powered2
Notes:
1 VIx/VOx are the input/output signals of a given channel (A or B). VDDI/VDDO are the supply voltages on the input/output signal sides of this given channel.
Rev. 1 | Page 4 of 15
π120U/π121U/π122U
Data Sheet
2 Powered
means VDDx≥ 2.9 V
means VDDx < 2.3V
4 Input signal (VIx) must be in a low state to avoid powering the given VDDI1 through its ESD protection circuitry.
5 If the VDDI goes into unpowered status, the channel outputs the default logic signal after around 1us. If the VDDI goes into powered status, the channel outputs the input
status logic signal after around 3us.
3 Unpowered
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Table 4. Switching Specifications
VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, unless otherwise noted.
Parameter
Minimum Pulse Width
Symbol
Maximum Data Rate
Propagation Delay Time1,4
Pulse Width Distortion4
Part to Part Propagation Delay
Skew4
Channel to Channel Propagation
Delay Skew4
Min
Typ
Max
PW
6.5
150
Common-Mode Transient
Immunity3
CMTI
ESD（HBM - Human body
model）
ESD
Within PWD limit
us
The different time between 50% input signal to
50% output signal 50% @ 5VDC supply
3.2
4.8
us
@ 3.3VDC supply
0
0.02
0.2
us
The max different time between tpHL and tpLH@
5VDC supply. And The value is | tpHL - tpLH |
0
0.02
0.2
us
@ 3.3VDC supply
0.3
us
The max different propagation delay time
between any two devices at the same
temperature, load and voltage @ 5VDC supply
0.3
us
0
0.2
us
0
0.2
us
tCSK
tr/tf
Kbps
4.5
tPSK
Output Signal Rise/Fall Time4
Test Conditions/Comments
Within pulse width distortion (PWD) limit
3.0
tpHL, tpLH
PWD
Unit
us
100
@ 3.3VDC supply
The max amount propagation delay time
differs between any two output channels in
the single device @ 5VDC supply.
@ 3.3VDC supply
1.5
ns
10% to 90% signal terminated 50，See
figure15.
150
kV/µs
VIN = VDDx2 or 0V, VCM = 1000 V.
±8
kV
All pins
Notes:
1 tpLH = low-to-high propagation delay time, tpHL = high-to-low propagation delay time. See figure 16.
2V
DDx is the side voltage power supply VDD, where x = 1 or 2.
3 See Figure18 for Common-mode transient immunity (CMTI) measurement.
4 Output Signal Terminated 50
Table 5. DC Specifications
VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, unless otherwise noted.
Parameter
Rising Input Signal Voltage
Threshold
Falling Input Signal Voltage
Threshold
High Level Output Voltage
Low Level Output Voltage
Symbol
Min
VIT+
Typ
Max
0.6*VDDx1
0.7*VDDx1
Unit
Test Conditions/Comments
V
VIT-
0.3* VDDX1
0.4* VDDX1
V
VOH 1
VDDx − 0.1
VDDx
V
−20 µA output current
VDDx − 0.2
VDDx − 0.1
V
−2 mA output current
V
20 µA output current
VOL
0
0.1
Rev. 1 | Page 5 of 15
π120U/π121U/π122U
Data Sheet
Input Current per Signal
Channel
VDDx1 Undervoltage Rising
Threshold
VDDx1 Undervoltage Falling
Threshold
VDDx1 Hysteresis
0.1
0.2
V
2 mA output current
0 V ≤ Signal voltage ≤ VDDX1
IIN
−10
0.5
10
µA
VDDxUV+
2.45
2.65
2.9
V
VDDxUV−
2.3
2.5
2.75
V
VDDxUVH
0.15
V
Notes:
1 VDDx is the side voltage power supply VDD, where x = 1 or 2.
Table 6. Quiescent Supply Current
VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, CL = 0 pF, unless otherwise noted.
Parameter
π120Uxx Quiescent Supply Current @ 5VDC Supply
@ 3.3VDC Supply
π121Uxx Quiescent Supply Current @ 5VDC Supply
@ 3.3VDC Supply
π122Uxx Quiescent Supply Current @ 5VDC Supply
@ 3.3VDC Supply
Symbol
Min
Typ
Max
Unit
IDD1 (Q)
154
IDD2 (Q)
708
IDD1 (Q)
Test Conditions
192
250
µA
0V Input signal
885
1151
µA
0V Input signal
61
76
99
µA
5V Input signal
IDD2 (Q)
767
959
1247
µA
5V Input signal
IDD1 (Q)
113
141
183
µA
0V Input signal
IDD2 (Q)
696
870
1131
µA
0V Input signal
IDD1 (Q)
60
75
98
µA
3.3V Input signal
IDD2 (Q)
758
948
1232
µA
3.3V Input signal
IDD1 (Q)
431
539
700
µA
0V Input signal
IDD2 (Q)
431
539
701
µA
0V Input signal
IDD1 (Q)
414
518
673
µA
5V Input signal
IDD2 (Q)
414
518
673
µA
5V Input signal
IDD1 (Q)
404
506
657
µA
0V Input signal
IDD2 (Q)
405
506
658
µA
0V Input signal
IDD1 (Q)
409
512
665
µA
3.3V Input signal
IDD2 (Q)
410
512
666
µA
3.3V Input signal
IDD1 (Q)
431
539
701
µA
0V Input signal
IDD2 (Q)
431
539
701
µA
0V Input signal
IDD1 (Q)
414
518
673
µA
5V Input signal
IDD2 (Q)
414
518
673
µA
5V Input signal
IDD1 (Q)
405
506
658
µA
0V Input signal
IDD2 (Q)
405
506
658
µA
0V Input signal
IDD1 (Q)
410
512
666
µA
3.3V Input signal
IDD2 (Q)
410
512
666
µA
3.3V Input signal
Table 7. Total Supply Current vs. Data Throughput (CL = 0 pF)
VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, CL = 0 pF, unless otherwise noted.
Parameter
Symbol
π120Uxx Supply Current @ 5VDC
@ 3.3VDC
2 Kbps
Min
Typ
Max
IDD1
0.13
IDD2
0.92
IDD1
0.10
50Kbps
Min
Typ
Max
0.20
0.13
1.38
0.93
0.15
0.10
Rev. 1 | Page 6 of 15
150Kbps
Min
Typ
Max
Unit
0.20
0.13
0.20
mA
1.40
0.94
1.41
mA
0.15
0.10
0.15
mA
π120U/π121U/π122U
Data Sheet
π121Uxx Supply Current @ 5VDC
@ 3.3VDC
π122Uxx Supply Current @ 5VDC
@ 3.3VDC
IDD2
0.91
1.37
0.91
1.37
0.92
1.38
mA
IDD1
0.53
0.79
0.53
0.80
0.54
0.80
mA
IDD2
0.53
0.80
0.53
0.80
0.54
0.81
mA
IDD1
0.51
0.76
0.51
0.77
0.51
0.77
mA
IDD2
0.51
0.77
0.51
0.77
0.51
0.77
mA
IDD1
0.53
0.80
0.53
0.80
0.54
0.81
mA
IDD2
0.53
0.80
0.53
0.80
0.54
0.81
mA
IDD1
0.51
0.77
0.51
0.77
0.51
0.77
mA
IDD2
0.51
0.77
0.51
0.77
0.51
0.77
mA
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 8. Insulation Specifications
Parameter
Symbol
Rated Dielectric Insulation Voltage
Minimum External Air Gap
(Clearance)
Minimum External Tracking
(Creepage)
Minimum Internal Gap (Internal
Clearance)
Tracking Resistance (Comparative
Tracking Index)
Value
Unit
Test Conditions/Comments
π12xU3x
π12xU6x
3000
6000
L (CLR)
4
8
mm min
L (CRP)
4
8
mm min
11
21
µm min
Insulation distance through insulation
>400
>400
V
DIN IEC 112/VDE 0303 Part 1
II
II
CTI
Material Group
V rms
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Material Group (DIN VDE 0110, 1/89, Table 1)
PACKAGE CHARACTERISTICS
Table 9. Package Characteristics
Parameter
Symbol
Resistance (Input to Output)1
Capacitance (Input to
Output)1
Typical Value
Unit
π12xU3x
π12xU6x
RI-O
10 11
10 11
Ω
Test Conditions/Comments
CI-O
0.6
0.6
pF
@1MHz
Input Capacitance2
CI
3
3
pF
@1MHz
IC Junction to Ambient Thermal
Resistance
θJA
100
45
°C/W
Thermocouple located at center
of package underside
Notes:
1The device is considered a 2-terminal device; SOIC-8 Pin 1 - Pin 4(WSOIC-16 Pin 1-Pin8) are shorted together as the one terminal, and SOIC-8 Pin 5 - Pin 8(WSOIC-16 Pin 9-
Pin16) are shorted together as the other terminal.
2Testing from the input signal pin to ground.
REGULATORY INFORMATION
See Table 10 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross
isolation waveforms and insulation levels.
Table10. Regulatory
π12xU3x
Regulatory
UL
Recognized under UL 1577
Component Recognition Program1
Single Protection, 3000 V rms Isolation Voltage
File (E494497)
π12xU6x
Recognized under UL 1577
Component Recognition Program1
Single Protection, 6000V rms Isolation Voltage
File (pending)
Rev. 1 | Page 7 of 15
π120U/π121U/π122U
Data Sheet
CSA
Approved under CSA Component Acceptance Notice 5A
Approved under CSA Component Acceptance Notice 5A
CSA 60950-1-07+A1+A2 and
CSA 60950-1-07+A1+A2 and
IEC 60950-1, second edition, +A1+A2:
IEC 60950-1, second edition, +A1+A2:
Basic insulation at 500 V rms (707 V peak)
Basic insulation at 845 V rms (1200 V peak)
Reinforced insulation at 250 V rms
Reinforced insulation at 422 V rms
(353 V peak)
(600 V peak)
File (pending)
VDE
CQC
DIN V VDE V 0884-10 (VDE V
File (pending)
0884-10):2006-122
DIN V VDE V 0884-10 (VDE V 0884-10):2006-122
Basic insulation, VIORM = 707 V peak, VIOSM = 4615 V peak
Basic insulation, VIORM = 1200 V peak, VIOSM = 7000 V peak
File (40047929)
File (pending)
Certified under
Certified under
CQC11-471543-2012
CQC11-471543-2012
GB4943.1-2011
Basic insulation at 500 V rms (707 V peak) working voltage
GB4943.1-2011
Basic insulation at 845 V rms (1200 V peak) working voltage
Reinforced insulation at
Reinforced insulation at
250 V rms (353 V peak)
422 V rms (600 V peak)
File (pending)
File (pending)
Notes:
1 In accordance with UL 1577, each π120U3x/π121U3x/π122U3x is proof tested by applying an insulation test voltage ≥ 3600 V rms for 1 sec; each π120U6x/π121U6x/π122U6x
is proof tested by applying an isulation test voltage ≥ 7200 V rms for 1 sec
2 In accordance with DIN V VDE V 0884-10, each π120U3x/π121U3x/π122U3x is proof tested by applying an insulation test voltage ≥ 1326 V peak for 1 sec (partial discharge
detection limit = 5 pC); each π120U6x/π121U6x/π122U6x is proof tested by ≥ 2250V peak for 1 sec. The * marking branded on the component designates DIN V VDE V
0884-10 approval.
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance
of the safety data. The * marking on packages denotes DIN V VDE V 0884-10 approval.
Table 11. VDE Insulation Characteristics
Description
Test Conditions/Comments
Symbol
Characteristic
π12xU3x
π12xU6x
For Rated Mains Voltage ≤ 150 V rms
I to IV
I to IV
For Rated Mains Voltage ≤ 300 V rms
I to III
I to III
Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
I to III
I to III
40/105/21
40/105/21
2
1200
V peak
VIORM
2
707
VIORM × 1.875 = Vpd (m), 100% production
test, tini = tm = 1 sec, partial discharge <
5 pC
Vpd (m)
1326
2250
V peak
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10
sec, partial discharge < 5 pC
Vpd (m)
1061
1800
V peak
849
1440
V peak
4200
8500
V peak
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10
sec, partial discharge < 5 pC
VIOTM
Rev. 1 | Page 8 of 15
π120U/π121U/π122U
Data Sheet
Surge Isolation Voltage Basic
Basic insulation, 1.2 µs rise time, 50 µs,
50% fall time
VIOSM
Surge Isolation Voltage Reinforced
Reinforced insulation, 1.2 µs rise time,
50 µs, 50% fall time
VIOSM
Safety Limiting Values
Maximum value allowed in the event of
a failure (see Figure 9)
4615
7000
V peak
V peak
Maximum Junction Temperature
TS
150
150
°C
Total Power Dissipation at 25°C
PS
1.56
2.78
W
RS
>109
>109
Ω
Insulation Resistance at TS
VIO = 800 V
π12xU3x
π12xU6x
3
Propagation Delay Time(uS)
Power Supply Undervoltage
Threshold
Figure9. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per VDE
2.9
2.8
2.7
2.6
2.5
2.4
VDDxUV+(V）
VDDxUV−(V）
2.3
2.2
0
50
100
150
3.2
3
2.8
tpHL(uS)@3.3V
tpLH(uS)@3.3V
tpHL(uS)@5V
tpLH(uS)@5V
2.6
2.4
2.2
0
100
150
Free-Air Temperature ( °C)
Free-Air Temperature ( °C)
Figure10. UVLO vs. Free-Air Temperature
50
Figure11. Propagation Delay Time vs. Free-Air Temperature
Figure11. Transition time waveform measurement
Figure12. Propagation delay time waveform measurement
Rev. 1 | Page 9 of 15
π120U/π121U/π122U
π120Uxx Quiescent Supply Current (mA)
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
@3.3V Supply with 0V Input
@3.3V Supply with 3.3V Input
@5V Supply with 0V Input
@5V Supply with 5V Input
0
50
100
150
Free-Air Temperature ( °C)
Figure12. π121Uxx/π122Uxx Quiescent Supply Current vs.
Free-Air Temperature
π120Uxx Quiescent Supply Current (mA)
π122Uxx Quiescent Supply Current (mA)
Data Sheet
0.8
0.7
0.6
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 3.3V Input
IDD2@ 3.3V Input
0.5
0.4
0.3
0.2
0.1
0
0
50
100
150
Free-Air Temperature ( °C)
Figure13. π120Uxx Quiescent Supply Current with 3.3V Supply
vs. Free-Air Temperature
0.8
0.7
Figure12. Propagation delay time waveform measurement
0.6
Figure11. Transition time waveform measurement
0.5
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 5V Input
IDD2@ 5V Input
0.4
0.3
0.2
0.1
0
0
50
100
150
Free-Air Temperature ( °C)
Figure14. π120Uxx Quiescent Supply Current with 5V Supply vs. Free-Air Temperature
VDDX
VDDX
Figure12. Propagation delay time waveform measurement
Figure15. Transition time waveform measurement
Figure16. Propagation delay time waveform measurement
Rev. 1 | Page 10 of 15
π120U/π121U/π122U
Data Sheet
APPLICATIONS INFORMATION
the user may also include resistors (50–300 Ω) in series with the
inputs and outputs if the system is excessively noisy.
OVERVIEW
The π1xxxxx are 2PaiSemi digital isolators product family based
on 2PaiSEMI unique iDivider technology. Intelligent voltage
Divider technology (iDivider technology) is a new generation
digital isolator technology invented by 2PaiSEMI. It uses the
principle of capacitor voltage divider to transmit signal directly
cross the isolator capacitor without signal modulation and
demodulation. Compare to the traditional Opto-couple
technology, icoupler technology, OOK technology, iDivider is a
more essential and concise isolation signal transmit technology
which leads to greatly simplification on circuit design and
therefore significantly improves device performance, such as
lower power consumption, faster speed, enhanced antiinterference ability, lower noise.
By using maturated standard semiconductor CMOS technology
and the innovative iDivider design, these isolation components
provide outstanding performance characteristics and reliability
superior to alternatives such as optocoupler devices and other
integrated isolators. The π1xxxxx isolator data channels are
independent and are available in a variety of configurations with
a withstand voltage rating of 1.5 kV rms to 6.0 kV rms and the
data rate from DC up to 600Mbps (see the Ordering Guide).
The π120Uxx/π121Uxx/π122Uxx are the outstanding 150Kbps
dual-channel digital isolators with the enhanced ESD capability.
the devices transmit data across an isolation barrier by layers of
silicon dioxide isolation.
The devices operate with the supply voltage on either side
ranging from 3.0 V to 5.5 V, offering voltage translation of 3.3 V
and 5 V logic.
The π120Uxx/π121Uxx/π122Uxx have very low propagation
delay and high speed. The input/output design techniques allow
logic and supply voltages over a wide range from 3.0 V to 5.5 V,
offering voltage translation of 3.3 V and 5 V logic. The
architecture is designed for high common-mode transient
immunity and high immunity to electrical noise and magnetic
interference.
Avoid reducing the isolation capability, Keep the space
underneath the isolator device free from metal such as planes,
pads, traces and vias.
To minimize the impedance of the signal return loop, keep the
solid ground plane directly underneath the high-speed signal path,
the closer the better. The return path will couple between the
nearest ground plane to the signal path. Keep suitable trace width
for controlled impedance transmission lines interconnect.
To reduce the rise time degradation, keep the length of
input/output signal traces as short as possible, and route low
inductance loop for the signal path and It’s return path.
VDD1
VIA/VOA
VIB/VOB
VDD2
VOA/VIA
VOB/VIB
GND1
GND2
Figure17.Recommended Printed Circuit Board Layout
CMTI MEASUREMENT
PAI12X系列
To measure the Common-Mode Transient Immunity (CMTI) of
π1xxxxx isolator under specified common-mode pulse magnitude
(VCM) and specified slew rate of the common-mode pulse
(dVCM/dt) and other specified test or ambient conditions, The
common-mode pulse generator (G1) will be capable of providing
fast rising and falling pulses of specified magnitude and duration
of the common-mode pulse (VCM) and the maximum commonmode slew rates (dVCM/dt) can be applied to π1xxxxx isolator
coupler under measurement. The common-mode pulse is applied
between one side ground GND1 and the other side ground GND2
of π1xxxxx isolator and shall be capable of providing positive
transients as well as negative transients.
See the Ordering Guide for the model numbers that have the failsafe output state of low or high.
PCB LAYOUT
The low-ESR ceramic bypass capacitors must be connected
between VDD1 and GND1 and between VDD2 and GND2. The
bypass capacitors are placed on the PCB as close to the isolator
device as possible. The recommended bypass capacitor value is
between 0.1 μF and 10 μF. To enhance the robustness of a design,
Figure18. Common-mode transient immunity (CMTI) measurement
Rev. 1 | Page 11 of 15
π120U/π121U/π122U
Data Sheet
OUTLINE DIMENSIONS
Figure19. 8-Lead Standard Small Outline Package [8-Lead SOIC_N]
Figure20. 16-Lead Wide Body Outline Package [16-Lead SOIC_W]
Rev. 1 | Page 12 of 15
π120U/π121U/π122U
Data Sheet
REEL INFORMATION
8-Lead SOIC_N
Figure16. Propagation delay time waveform measurement
16-Lead SOIC_W
Rev. 1 | Page 13 of 15
π120U/π121U/π122U
Data Sheet
ORDERING GUIDE
π120U31
Pai120U31
−40°C to +125°C
No.
of
Inp
uts,
VDD1
Side
2
0
3
High
8-Lead SOIC_N
S-8-N
4000 per reel
π120U30
Pai120U30
−40°C to +125°C
2
0
3
Low
8-Lead SOIC_N
S-8-N
4000 per reel
π121U31
Pai121U31
−40°C to +125°C
1
1
3
High
8-Lead SOIC_N
S-8-N
4000 per reel
π121U30
Pai121U30
−40°C to +125°C
1
1
3
Low
8-Lead SOIC_N
S-8-N
4000 per reel
π122U31
Pai122U31
−40°C to +125°C
1
1
3
High
8-Lead SOIC_N
S-8-N
4000 per reel
π122U30
Pai122U30
−40°C to +125°C
1
1
3
Low
8-Lead SOIC_N
S-8-N
4000 per reel
π120U61
Pai120U61
−40°C to +125°C
2
0
6
High
16-Lead SOIC_W
S-16-W
1500 per reel
π120U60
Pai120U60
−40°C to +125°C
2
0
6
Low
16-Lead SOIC_W
S-16-W
1500 per reel
π121U61
Pai121U61
−40°C to +125°C
1
1
6
High
16-Lead SOIC_W
S-16-W
1500 per reel
π121U60
Pai121U60
−40°C to +125°C
1
1
6
Low
16-Lead SOIC_W
S-16-W
1500 per reel
π122U61
Pai122U61
−40°C to +125°C
1
1
6
High
16-Lead SOIC_W
S-16-W
1500 per reel
π122U60
Pai122U60
−40°C to +125°C
1
1
6
Low
16-Lead SOIC_W
S-16-W
1500 per reel
Model Name
Temperature
Range
No. of
Inputs,
VDD2
Side
Withstand
Voltage
Rating (kV
rms)
FailSafe
Output
State
Package
Description
Package
Option
PART NUMBER NAMED RULE
π(1)(2)(0)(A)(3)(0)(S)
SeriesNumber:
1,2,3...
Total Channel Am ount:
N=N Channels N=1,2,3,4,5,6...
Reverse Channel Amount:
N=N Channels N=0,1,2,3...
Data Rate:A=600Mbps
E=200Mbps
M=10Mbps
U=150Kbps
Isolation Voltag es:
N=1
1.5KVrms AC
N=3
3KVrms AC
N=6
6KVrms AC
Fail-Safe Output Stat e:
0=Logic Low
1=Logic High
Optional：
S=SSOP Package
Q=AEC-Q100 Qualified
Notes:
Pai12xxxx is equals to π12xxxx in the customer BOM
Rev. 1 | Page 14 of 15
Quantity
π120U/π121U/π122U
Data Sheet
REVISION HISTORY
Revision
Updated
Date
Page
Change Record
1
Jason
2018/09/17
All
2
Jason
2018/11/28
P11
3
Devin
2019/09/08
P1,P11,P13,P14
Initial version
Changed the recommended bypass capacitor value from between 0.1 μF and 1
μF to between 0.1 μF and 10 μF.
P1: Changed the address from ‘Room 19307, Building 8, No.498,
GuoShouJing Road’ to ‘Room 308-309, No.22, Boxia Road’; Add
iDivider technology description in General Description.
Changed ESD(HBM) from 7KV to 8KV.
P11: Add iDivider technology description in overview.
P13: Updated 16-Lead SOIC_W reel drawing.
P14: Add character ‘S’ and ‘Q’ in part number named rule; Changed the
SOIC_W quantity from ‘1000 per reel’ to ‘1500 per reel’.
Rev. 1 | Page 15 of 15
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