FT24C512A-ETR-T

Fremont Micro Devices 24C512A Two-Wire Serial EEPROM 512K (8-bit wide) FEATURES            tia l  en  fid  Low voltage and low power operations:  FT24C512A: VCC = 1.8V to 5.5V Maximum Standby current < 1µA . 128 bytes page write mode. Partial page write operation allowed. Internally organized: 65,536×8 (512K). Standard 2-wire bi-directional serial interface. Schmitt trigger, filtered inputs for noise protection. Self-timed write cycle (5ms maximum). 1 MHz (2.5-5V), 400 kHz (1.8V) compatibility. Automatic erase before write operation. Write protect pin for hardware data protection. High reliability: typically 1,000,000 cycles endurance. 100 years data retention. o o Industrial temperature range (-40 C to 85 C). Standard 8-pin DIP/SOP/MSOP/TSSOP/UDFN Pb-free packages. on  DESCRIPTION The FT24C512A series are 524,288 bits of serial Electrical Erasable and Programmable Read Only C Memory, commonly known as EEPROM. They are organized as 65,536 words of 8 bits (one byte) each. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage applications. These devices are available in standard 8-lead DIP, 8-lead SOP, 8-lead MSOP, 8-lead TSSOP and 8-lead UDFN packages. A standard 2-wire serial interface is used to address all read and write FM D functions. Our extended VCC range (1.8V to 5.5V) devices enables wide spectrum of applications. PIN CONFIGURATION Pin Name Pin Function A2, A1, A0 Device Address Inputs SDA Serial Data Input / Open Drain Output SCL Serial Clock Input WP Write Protect NC No-Connect Table 1 © 2016 Fremont Micro Devices Inc. DS24C512-A1--page1 Fremont Micro Devices 24C512A All three packaging types come in Pb-free certified. FT24C512A 1 8 2 7 3 6 4 5 8L 8L 8L 8L 8L VCC WP SCL SDA DIP SOP MSOP TSSOP UDFN tia l A0 A1 A2 GND Figure 1: Package Type en ABSOLUTE MAXIMUM RATINGS o o -40 C to 85 C o o -50 C to 125 C Input voltage on any pin relative to ground: -0.3V to VCC + 0.3V Maximum voltage: 8V fid Industrial operating temperature: Storage temperature: ESD Protection on all pins: >2000V FM D C on * Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device. Functional operation of the device at conditions beyond those listed in the specification is not guaranteed. Prolonged exposure to extreme conditions may affect device reliability or functionality. © 2016 Fremont Micro Devices Inc. DS24C512-A1--page2 Fremont Micro Devices 24C512A Figure 2: Block Diagram PIN DESCRIPTIONS (A) SERIAL CLOCK (SCL) The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of this clock is to clock data out of the EEPROM device. (B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0) tia l These are the chip select input signals for the serial EEPROM devices. Typically, these signals are hardwired to either VIH or VIL. If left unconnected, they are internally recognized as VIL. (C) SERIAL DATA LINE (SDA) en SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can be wired-OR with other open-drain output devices. (D) WRITE PROTECT (WP) fid The FT24C512A device has a WP pin to protect the whole EEPROM array from programming. Programming operations are allowed if WP pin is left un-connected or input to VIL. Conversely all programming functions are disabled if WP pin is connected to VIH or VCC. Read operations is not on affected by the WP pin’s input level. MEMORY ORGANIZATION C The FT24C512A devices have 512 pages respectively. Since each page has 128 bytes, random word addressing to FT24C512A will require 16 bits data word addresses. FM D DEVICE OPERATION (A) SERIAL CLOCK AND DATA TRANSITIONS The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock SCL is at VIL. Any SDA signal transition may interpret as either a START or STOP condition as described below. (B) START CONDITION With SCL ≥VIH, a SDA transition from high to low is interpreted as a START condition. All valid commands must begin with a START condition. (C) STOP CONDITION With SCL ≥ VIH, a SDA transition from low to high is interpreted as a STOP condition. All valid read or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after a read command. A STOP condition after page or byte write command will trigger the chip into the © 2016 Fremont Micro Devices Inc. DS24C512-A1--page3 Fremont Micro Devices 24C512A STANDBY mode after the self-timed internal programming finish (see Figure 3). (D) ACKNOWLEDGE The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The ACKNOWLEDGE signal occurs on the 9th serial clock after each word. (E) STANDBY MODE The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP tia l bit in read mode, or after completing a self-time internal programming operation. en SCL fid SDA START Condition STOP Condition Data Transition on Data Valid START Condition FM D SCL C Figure 3: Timing diagram for START and STOP conditions Data in Data out ACK Figure 4: Timing diagram for output ACKNOWLEDGE © 2016 Fremont Micro Devices Inc. DS24C512-A1--page4 Fremont Micro Devices 24C512A DEVICE ADDRESSING The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to invoke a valid read or write command. The first four most significant bits of the device address must be 1010, which is common to all serial EEPROM devices. The next three bits are device address bits. These th th th three device address bits (5 , 6 and 7 ) are to match with the external chip select/address pin states. If a match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8 th read/write bit, otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all th th th device address bits (5 , 6 and 7 ) as noted below. The last or 8th bit is a read/write command bit. If the th 8 bit is at VIH then the chip goes into read mode. If a “0” is detected, the device enters programming tia l mode. WRITE OPERATION BYTE WRITE en (A) A write operation requires two 8-bit data word address following the device address word and ACKNOWLEDGE signal. Upon receipt of this address, the EEPROM will respond with a “0” and then fid clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will again output a “0”. The addressing device, such as a microcontroller, must terminate the write sequence with a STOP condition. At this time the EEPROM enters into an internally-timed write cycle state. All completed (figure 5). (B) PAGE WRITE on inputs are disabled during this write cycle and the EEPROM will not respond until the writing is C The 512K EEPROM are capable of 128-byte page write. A page write is initiated the same way as a byte write, but the microcontroller does not send a STOP condition after the first data word is clocked in. The microcontroller can transmit up to 127 more data FM D words after the EEPROM acknowledges receipt of the first data word. The EEPROM will respond with a “0” after each data word is received. The microcontroller must terminate the page write sequence with a STOP condition (see Figure 6). The lower 7 bits of the data word address are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. If more than 128 data words are transmitted to the EEPROM, the data word address will “roll over” and the previous data will be overwritten. (C) ACKNOWLEDGE POLLING ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal programming. By issuing a valid read or write address command, the EEPROM will not acknowledge at the 9 th clock cycle if the device is still in the self-timed programming mode. However, if the programming completes and the chip has returned to the STANDBY mode, the device will return a th valid ACKNOWLEDGE signal at the 9 clock cycle. © 2016 Fremont Micro Devices Inc. DS24C512-A1--page5 Fremont Micro Devices 24C512A READ OPERATIONS th The read command is similar to the write command except the 8 read/write bit in address word is set to “1”. The three read operation modes are described as follows: (A) CURRENT ADDRESS READ The EEPROM internal address word counter maintains the last read or write address plus one if the power supply to the device has not been cut off. To initiate a current address read operation, the th micro-controller issues a START bit and a valid device address word with the read/write bit (8 ) set to th bit data word will then be serially clocked out. automatically increase by one. tia l “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9 serial clock cycle. An 8The internal address word counter will then For current address read the micro-controller will not issue an th ACKNOWLEDGE signal on the 18 clock cycle. The micro-controller issues a valid STOP bit after th the 18 clock cycle to terminate the read operation. The device then returns to STANDBY mode (see (B) en Figure 7). SEQUENTIAL READ fid The sequential read is very similar to current address read. The micro-controller issues a START bit th and a valid device address word with read/write bit (8 ) set to “1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9 th serial clock cycle. An 8-bit data word will then be serially on clocked out. Meanwhile the internally address word counter will then automatically increase by one. Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the C incremented internal address counter. If the micro-controller needs another data, it sends out an th ACKNOWLEDGE signal on the 27 clock cycle. Another 8-bit data word will then be serially clocked out. This sequential read continues as long as the micro-controller sends an ACKNOWLEDGE signal after receiving a new data word. When the internal address counter reaches its maximum valid FM D address, it rolls over to the beginning of the memory array address. Similar to current address read, the micro-controller can terminate the sequential read by not acknowledging the last data word received, but sending a STOP bit afterwards instead (figure 8). (C) RANDOM READ Random read is a two-steps process. The first step is to initialize the internal address counter with a target read address using a “dummy write” instruction. The second step is a current address read. To initialize the internal address counter with a target read address, the micro-controller issues a th START bit first, follows by a valid device address with the read/write bit (8 ) set to “0”. The EEPROM will then acknowledge. The micro-controller will then send two address words. Again the EEPROM will acknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller performs a current address read instruction to read the data. Note that once a START bit is issued, the EEPROM will reset the internal programming process and continue to execute the new instruction - which is to read the current address (figure 9). © 2016 Fremont Micro Devices Inc. DS24C512-A1--page6 Fremont Micro Devices 24C512A S W T R A I D E V IC E R ADDRESS T S T T F IR S T W O R D SECOND W ORD ADDRESS ADDRESS E O DATA P S D A L IN E M L R A M A L A A S S / C S C S C C B B W K B K B K K W T R A I D E V IC E R ADDRESS T S T T E F IR S T W O R D SECOND W ORD A D D R E S S (N ) A D D R E S S (N ) S D A L IN E L R A M A S S / C S C B B W K B D A T A (N ) K D A T A (N + X ) P ... L A A A S C C C B K K K fid M O en S tia l Figure 5: Byte Write on Figure 6: Page Write S T A R T C DEVICE ADDRESS R E A D S T O P DATA FM D SDA LINE DEVICE ADDRESS R E A D N O LRA S / C B WK M S B A C K Figure 7: Current Address Read DATA (N) DATA (N+1) DATA (N+2) S T O P DATA (N+3) SDA LINE RA / C WK A C K A C K A C K N O A C K Figure 8: Sequential Read © 2016 Fremont Micro Devices Inc. DS24C512-A1--page7 Fremont Micro Devices S T A R T 24C512A DEVICE ADDRESS W R I T E FIRST WORD ADDRESS(N) SECOND WORD ADDRESS(N) S T A R T DEVICE ADDRESS R E A D S T O P DATA (N) SDA LINE M S B LRA S / C B WK M S B A C K L A S C B K M S B N O LRA S / C B WK Figure 9: Random Read tLO W t S U ,S T A t H D .S T A S D A IN AA tLO W t H D .D A T t S U .D A T tDH t S U .S T O t BUF on t tR fid SCL SDA OUT t H IG H en tF tia l A C K FM D C Figure 10: SCL and SDA Bus Timing © 2016 Fremont Micro Devices Inc. DS24C512-A1--page8 Fremont Micro Devices 24C512A AC CHARACTERISTICS 1.8V Parameter Min Clock frequency, SCL tHIGH tI tAA tBUF Endurance ) Unit Max 1000 kHz Clock pulse width low Clock pulse width high Noise suppression (1) time Clock low to data out valid Time the bus must be free before a new transmission can (1) start START hold time 1.3 0.4 µs 0.6 0.4 µs START set-up time 0.6 Data in hold time Input fall time (1) STOP set-up time Date out hold time 50 ns 0.9 0.55 µs 0.6 100 0.5 µs 0.25 µs 0.25 µs 0 µs 100 ns 0.3 0.3 µs 300 100 ns fid Input rise time (1) 100 1.3 0 Data in set-up time (1 Min 400 0.6 Write cycle time o 25 C, Page Mode, 3.3V 0.25 50 on tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Max tia l fSCL tLOW 2.5-5.0 V en Symbol µs 50 5 1,000,000 ns 5 ms Write Cycles FM D C Notes: 1. This Parameter is expected by characterization but are not fully screened by test. 2. AC Measurement conditions: RL (Connects to Vcc): 1.3KΩ Input Pulse Voltages: 0.3Vcc to 0.7Vcc Input and output timing reference Voltages: 0.5Vcc © 2016 Fremont Micro Devices Inc. DS24C512-A1--page9 Fremont Micro Devices 24C512A DC CHARACTERISTICS Symbol Parameter Test Conditions Min Typical Max Units 5.5 V 0.4 1.0 mA VCC1 24C××A supply VCC ICC1 Supply read current VCC @ 5.0V SCL = 100 kHz ICC2 Supply write current VCC @ 5.0V SCL = 100 kHz 2.0 3.0 mA ISB1 Supply current VCC @ 1.8V, VIN = VCC or VSS 0.02 1.0 µA ISB2 Supply current VCC @ 2.5V, VIN = VCC or VSS 1.0 µA ISB3 Supply current VCC @ 5.0V, VIN = VCC or VSS 1.0 µA IIL VIN = VCC or VSS 3.0 µA VIL Input leakage current Output leakage current Input low level VIH Input high level VOL2 Output low level VCC @ 3.0V, IOL = 2.1 mA VOL1 Output low level VCC @ 1.8V, IOL = 0.15 mA tia l 3.0 µA -0.6 VCC×0.3 V VCC×0.7 VCC +0.5 V 0.4 V 0.4 V en VIN = VCC or VSS 0.07 FM D C on fid ILO 1.8 © 2016 Fremont Micro Devices Inc. DS24C512-A1--page10 Fremont Micro Devices 24C512A ORDERING INFORMATION FT24CxxxA - x x x - x Density 512: 512kbits Packaging B: Tube T: Tape and Reel Temp. Range E: -40℃-85℃ HSF R: RoHS G: Green en Temperature Range Vcc HSF Packaging Ordering Code DIP8 -40℃-85℃ 1.8V-5.5V RoHS Green SOP8 -40℃-85℃ 1.8V-5.5V MSOP8 -40℃-85℃ 1.8V-5.5V Tube Tube Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tape and Reel Tape and Reel FT24C512A-EDR-B FT24C512A-EDG-B FT24C512A-ESR-B FT24C512A-ESR-T FT24C512A-ESG-B FT24C512A-ESG-T FT24C512A-EMR-B FT24C512A-EMR-T FT24C512A-EMG-B FT24C512A-EMG-T FT24C512A-ETR-B FT24C512A-ETR-T FT24C512A-ETG-B FT24C512A-ETG-T FT24C512A-ENR-T FT24C512A-ENG-T fid Package RoHS on Density tia l Package D: DIP8 S: SOP8 M: MSOP8 T: TSSOP8 N:UDFN Green FM D C RoHS 512kbits TSSOP8 UDFN -40℃-85℃ 1.8V-5.5V -40℃-85℃ 1.8V-5.5V © 2016 Fremont Micro Devices Inc. Green RoHS Green RoHS Green DS24C512-A1--page11 Fremont Micro Devices 24C512A Dimensions In Millimeters on Symbol fid en tia l DIP8 PACKAGE OUTLINE DIMENSIONS Dimensions In Inches Max Min Max A 3.710 4.310 0.146 0.170 A1 0.510 A2 3.200 3.600 0.126 0.142 0.380 0.570 0.015 0.022 B B1 C Min 0.020 1.524（BSC） 0.204 0.360 0.060（BSC） 0.008 0.014 D 9.000 9.400 0.354 0.370 E 6.200 6.600 0.244 0.260 E1 7.320 7.920 0.288 0.312 FM D C e 2.540 (BSC) L 3.000 3.600 0.100（BSC） 0.118 0.142 E2 8.400 9.000 0.331 © 2016 Fremont Micro Devices Inc. 0.354 DS24C512-A1--page12 Fremont Micro Devices 24C512A A Dimensions In Inches Min Max Min Max 1.350 1.750 0.053 0.069 0.100 0.250 0.004 0.010 A2 1.350 1.550 0.053 0.061 b 0.330 0.510 0.013 0.020 c 0.170 0.250 0.006 0.010 D 4.700 5.100 0.185 0.200 E 3.800 4.000 0.150 0.157 E1 5.800 6.200 0.228 0.244 0.050（BSC） 0.016 0.050 FM D A1 Dimensions In Millimeters C Symbol on fid en tia l SOP8 PACKAGE OUTLINE DIMENSIONS (150mil) e 1.270 (BSC) L 0.400 1.270 θ 0° 8° © 2016 Fremont Micro Devices Inc. 0° 8° DS24C512-A1--page13 Fremont Micro Devices 24C512A Symbol C on fid en tia l MSOP8 PACKAGE OUTLINE DIMENSIONS Dimensions In Millimeters Dimensions In Inches Max Min Max 0.820 1.100 0.320 0.043 A1 0.020 0.150 0.001 0.006 A2 0.750 0.950 0.030 0.037 b 0.250 0.380 0.010 0.015 c 0.090 0.230 0.004 0.009 D 2.900 3.100 0.114 0.122 FM D Min A e 0.65 (BSC) 0.026 (BSC) E 2.900 3.100 0.114 0.122 E1 4.750 5.050 0.187 0.199 L 0.400 0.800 0.016 0.031 θ 0° 6° 0° 6° © 2016 Fremont Micro Devices Inc. DS24C512-A1--page14 Fremont Micro Devices 24C512A Symbol C on fid en tia l TSSOP8 PACKAGE OUTLINE DIMENSIONS Dimensions In Millimeters Dimensions In Inches Max Min Max D 2.900 3.100 0.114 0.122 E 4.300 4.500 0.169 0.177 b 0.190 0.300 0.007 0.012 c 0.090 0.200 0.004 0.008 E1 6.250 6.550 0.246 0.258 FM D Min A 1.100 0.043 A2 0.800 1.000 0.031 0.039 A1 0.020 0.150 0.001 0.006 e L 0.65 (BSC) 0.500 H θ 0.026 (BSC) 0.700 0.020 0.25 (TYP) 1° © 2016 Fremont Micro Devices Inc. 0.028 0.01 (TYP) 7° 1° 7° DS24C512-A1--page15 Fremont Micro Devices 24C512A A A1 Dimensions In Millimeters C Symbol on fid en tia l UDFN8 PACKAGE OUTLINE DIMENSIONS FM D b Min Max 0.450 0.550 Min 0.017 Max 0.021 0.000 0.050 0.000 0.002 0.180 0.300 0.007 0.039 b1 c Dimensions In Inches 0.160REF 0.100 0.006REF 0.200 0.004 0.008 0.083 0.062 D 1.900 2.100 0.075 D2 1.400 1.600 0.055 e 0.500BSC Nd 1.500BSC 0.020BSC 0.059BSC E 2.900 3.100 0.114 E2 1.500 1.700 0.059 0.067 L 0.300 0.500 0.012 0.020 h 0.200 0.300 0.066 0.12 © 2016 Fremont Micro Devices Inc. 0.122 DS24C512-A1--page16 Fremont Micro Devices 24C512A Fremont Micro Devices (SZ) Limited #5-8, 10/F, Changhong Building, Ke-Ji Nan 12 Road, Nanshan District, Shenzhen Tel: (86 755) 86117811 Fax: (86 755) 86117810 Fremont Micro Devices (Hong Kong) Limited tia l #16, 16/F, Blk B, Veristrong Industrial Centre, 34-36 Au Pui Wan Street, Fotan, Shatin, Hong Kong Tel: (852) 27811186 Fax: (852) 27811144 Fremont Micro Devices (USA), Inc. en 42982 Osgood Road Fremont, CA 94539 Tel: (1-510) 668-1321 Fax: (1-510) 226-9918 FM D C on fid Web Site: http://www.fremontmicro.com/ * Information furnished is believed to be accurate and reliable. However, Fremont Micro Devices, Incorporated (BVI) assumes no responsibility for the consequences of use of such information or for any infringement of patents of other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Fremont Micro Devices, Incorporated (BVI). Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. Fremont Micro Devices, Incorporated (BVI) products are not authorized for use as critical components in life support devices or systems without express written approval of Fremont Micro Devices, Incorporated (BVI). The FMD logo is a registered trademark of Fremont Micro Devices, Incorporated (BVI). All other names are the property of their respective owners. © 2016 Fremont Micro Devices Inc. DS24C512-A1--page17