74HC160D,652

74HC160 Presettable synchronous BCD decade counter; asynchronous reset Rev. 4 — 27 March 2019 Product data sheet 1. General description The 74HC160 is a synchronous presettable decade counter with an internal look-ahead carry. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positivegoing edge of the clock (CP). The outputs (Q0 to Q3) of the counters may be preset HIGH or LOW. A LOW at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock. Preset takes place regardless of the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR) sets Q0 to Q3 LOW regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function). The look-ahead carry simplifies serial cascading of the counters. Both CEP and CET must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH output of Q0. This pulse can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits • • • • • • • • Complies with JEDEC standard no. 7A CMOS input levels Synchronous counting and loading 2 count enable inputs for n-bit cascading Asynchronous reset Positive-edge triggered clock ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package 74HC160D Temperature range Name Description Version -40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC160 Nexperia Presettable synchronous BCD decade counter; asynchronous reset 4. Functional diagram 3 D0 9 PE 4 D1 5 D2 6 D3 9 PARALLEL LOAD CIRCUITRY 7 10 CET 7 CEP 2 CP 1 MR 10 D INH CP RD Q0 14 Fig. 1. TC 15 DECADE COUNTER Q1 13 Q2 12 3 PE D0 CEP 4 5 6 D1 D2 D3 CET 2 CP 1 MR TC 15 Q0 Q1 Q2 Q3 Q3 11 14 13 12 11 aaa-024737 Functional diagram aaa-012184 Fig. 2. 1 9 7 10 2 3 R Logic symbol CTRDIV10 M1 G3 G4 C2/1,3,4+ 14 1,2D 4 13 5 12 6 11 4CT = 9 15 aaa-024738 Fig. 3. IEC logic symbol 74HC160 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 27 March 2019 © Nexperia B.V. 2019. All rights reserved 2 / 15 74HC160 Nexperia Presettable synchronous BCD decade counter; asynchronous reset D0 D1 D2 D3 CET CEP PE D CP FF 1 Q CP D FF 2 Q CP Q RD D FF 3 Q CP Q RD D FF 4 Q CP Q RD Q RD MR Q0 Q1 Q2 Q3 TC aaa-024739 Fig. 4. Logic diagram 5. Pinning information 5.1. Pinning 74HC160 MR 1 16 VCC CP 2 15 TC D0 3 14 Q0 D1 4 13 Q1 D2 5 12 Q2 D3 6 11 Q3 CEP 7 10 CET GND 8 9 PE aaa-024740 Fig. 5. Pin configuration SO16 (SOT109-1) 74HC160 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 27 March 2019 © Nexperia B.V. 2019. All rights reserved 3 / 15 74HC160 Nexperia Presettable synchronous BCD decade counter; asynchronous reset 5.2. Pin description Table 2. Pin description Symbol Pin Description MR 1 asynchronous master reset (active LOW) CP 2 clock input (LOW-to-HIGH, edge triggered) D0, D1, D2, D3 3, 4, 5, 6 data input CEP 7 count enable input GND 8 ground (0 V) PE 9 parallel enable input (active LOW) CET 10 count enable carry input Q0, Q1, Q2, Q3 14, 13, 12, 11 flip-flop output TC 15 terminal count output VCC 16 supply voltage 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; qn = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition. Operating mode Inputs Outputs MR CP CEP CET PE Dn Qn TC Reset (clear) L X X X X X L L Parallel load H ↑ X X I I L L H ↑ X X I h H [1] Count H ↑ h h h X count [1] Hold (do nothing) H X I X h X qn [1] H X X I h X qn L [1] The TC output is HIGH when CET is HIGH and the counter is at terminal count (HLLH); 0 1 2 3 4 15 5 14 6 13 7 12 11 10 9 8 aaa-024742 Fig. 6. State diagram 74HC160 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 27 March 2019 © Nexperia B.V. 2019. All rights reserved 4 / 15 74HC160 Nexperia Presettable synchronous BCD decade counter; asynchronous reset MR PE D0 D1 D2 D3 CP CEP CET Q0 Q1 Q2 Q3 TC 7 8 9 reset preset 0 1 count 2 3 inhibit aaa-024743 Typical timing sequence: reset outputs to zero; preset to BCD seven; count to eight, nine, zero, one, two and three; inhibit. Fig. 7. Typical timing sequence 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current IOK output clamping current IO output current ICC Min Max Unit -0.5 +7.0 V VI < -0.5 V or VI > VCC + 0.5 V - ±20 mA VO < -0.5 V or VO > VCC + 0.5 V - ±20 mA -0.5 V < VO < VCC + 0.5 V - ±25 mA supply current - +50 mA IGND ground current -50 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] Conditions [1] For SO16 package: above 70 °C the value of Ptot derates linearly at 8 mW/K. 74HC160 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 27 March 2019 © Nexperia B.V. 2019. All rights reserved 5 / 15 74HC160 Nexperia Presettable synchronous BCD decade counter; asynchronous reset 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate Min Typ Max Unit 2.0 5.0 6.0 V 0 - VCC V 0 - VCC V -40 +25 +125 °C VCC = 2.0 V - - 625 ns/V VCC = 4.5 V - 1.67 139 ns/V VCC = 6.0 V - - 83 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V VI = VIH or VIL HIGH-level output voltage IO = -20 μA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = -20 μA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = -20 μA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = -4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = -5.2 mA; VCC = 6.0 V HIGH-level input voltage LOW-level input voltage 5.48 5.81 - 5.34 - 5.2 - V VI = VIH or VIL LOW-level output voltage IO = 20 μA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 μA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V - - ±0.1 - ±1.0 - ±1.0 μA II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80.0 - 160.0 μA CI input capacitance - 3.5 - - - - - pF 74HC160 Product data sheet VI = VCC or GND; VCC = 6.0 V All information provided in this document is subject to legal disclaimers. Rev. 4 — 27 March 2019 © Nexperia B.V. 2019. All rights reserved 6 / 15 74HC160 Nexperia Presettable synchronous BCD decade counter; asynchronous reset 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Fig. 13. Symbol Parameter tpd propagation delay Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 61 185 - 230 - 280 ns VCC = 4.5 V - 22 37 - 46 - 56 ns VCC = 5.0 V; CL = 15 pF - 19 - - - - - ns VCC = 6.0 V - 18 31 - 39 - 48 ns VCC = 2.0 V - 69 215 - 270 - 325 ns VCC = 4.5 V - 25 43 - 54 - 65 ns VCC = 5.0 V; CL = 15 pF - 21 - - - - - ns VCC = 6.0 V - 20 31 - 46 - 55 ns VCC = 2.0 V - 47 150 - 190 - 225 ns VCC = 4.5 V - 17 30 - 38 - 45 ns VCC = 5.0 V; CL = 15 pF - 14 - - - - - ns VCC = 6.0 V - 14 26 - 33 - 38 ns VCC = 2.0 V - 69 210 - 265 - 315 ns VCC = 4.5 V - 25 42 - 53 - 63 ns VCC = 5.0 V; CL = 15 pF - 21 - - - - - ns VCC = 6.0 V - 20 36 - 45 - 54 ns VCC = 2.0 V - 69 220 - 275 - 330 ns VCC = 4.5 V - 25 44 - 55 - 66 ns VCC = 5.0 V; CL = 15 pF - 21 - - - - - ns VCC = 6.0 V - 20 37 - 47 - 56 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 3 - 17 - 20 - ns VCC = 2.0 V 80 28 - 100 - 120 - ns VCC = 4.5 V 16 10 - 20 - 24 - ns VCC = 6.0 V 14 8 - 17 - 20 - ns CP to Qn; see Fig. 8 [1] CP to TC; see Fig. 8 CET to TC; see Fig. 9 tPHL High to LOW propagation delay MR to Qn; see Fig. 10 MR to TC; see Fig. 10 tt tW tW transition time see Fig. 8 and Fig. 9 pulse width pulse width 74HC160 Product data sheet [2] CP HIGH or LOW; see Fig. 8 MR LOW; see Fig. 10 All information provided in this document is subject to legal disclaimers. Rev. 4 — 27 March 2019 © Nexperia B.V. 2019. All rights reserved 7 / 15 74HC160 Nexperia Presettable synchronous BCD decade counter; asynchronous reset Symbol Parameter trec recovery time tsu set-up time Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 100 30 - 125 - 150 - ns VCC = 4.5 V 20 11 - 25 - 30 - ns VCC = 6.0 V 17 9 - 21 - 26 - ns VCC = 2.0 V 80 22 - 100 - 120 - ns VCC = 4.5 V 16 8 - 20 - 24 - ns VCC = 6.0 V 14 6 - 17 - 20 - ns VCC = 2.0 V 135 41 - 170 - 205 - ns VCC = 4.5 V 27 15 - 34 - 41 - ns VCC = 6.0 V 23 12 - 29 - 35 - ns VCC = 2.0 V 200 63 - 250 - 300 - ns VCC = 4.5 V 40 23 - 50 - 60 - ns VCC = 6.0 V 34 18 - 43 - 51 - ns VCC = 2.0 V 0 -17 - 0 - 0 - ns VCC = 4.5 V 0 -6 - 0 - 0 - ns VCC = 6.0 V 0 -5 - 0 0 - ns VCC = 2.0 V 0 -41 - 0 - 0 - ns VCC = 4.5 V 0 -15 - 0 - 0 - ns VCC = 6.0 V 0 -12 - 0 0 - ns VCC = 2.0 V 0 -58 - 0 - 0 - ns VCC = 4.5 V 0 -21 - 0 - 0 - ns VCC = 6.0 V 0 -17 - 0 0 - ns VCC = 2.0 V 6 18 - 4.8 - 4 - MHz VCC = 4.5 V 30 55 - 24 - 20 - MHz MR to CP; see Fig. 10 Dn to CP; see Fig. 11 PE to CP; see Fig. 11 CEP, CET to CP; see Fig. 12 th hold time Dn to CP; see Fig. 11 PE to CP; see Fig. 11 CEP, CET to CP; see Fig. 12 fmax maximum frequency CP; see Fig. 8 VCC = 5.0 V; CL = 15 pF VCC = 6.0 V CPD [1] [2] [3] power dissipation capacitance VI = GND to VCC; fi = 1 MHz [3] - 61 - - - - - MHz 35 66 - 28 - 24 - MHz - 39 - - - - - pF tpd is the same as tPHL and tPLH. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in μW): 2 2 PD = CPD x VCC x fi x N + ∑(CL x VCC x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; 2 ∑(CL x VCC x fo) = sum of outputs. 74HC160 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 27 March 2019 © Nexperia B.V. 2019. All rights reserved 8 / 15 74HC160 Nexperia Presettable synchronous BCD decade counter; asynchronous reset 10.1. Waveforms and test circuit 1/fmax VI CP input VM GND tW tPHL VOH Qn, TC output tPLH 90 % 90 % VM 10 % VOL 10 % tTHL tTLH aaa-012353 Measurement points are given in Table 8. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 8. The clock (CP) to outputs (Qn, TC) propagation delays, pulse width, output transition times and maximum frequency VI CET input VM GND tPLH tPHL VOH 90 % TC output VOL 10 % 90 % VM 10 % tTLH tTHL aaa-012354 Measurement points are given in Table 8. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 9. The count enable carry input (CET) to terminal count output (TC) propagation delays and output transition times VI VM MR input GND t rec tW VI CP input VM GND t PHL VOH Qn, TC output VM VOL mna913 Measurement points are given in Table 8. Logic levels VOL and VOH are typical output voltage levels that occur with the output load. Fig. 10. The master reset (MR) pulse width, master reset to output (Qn, TC) propagation delays, and the master reset to clock (CP) recovery times 74HC160 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 27 March 2019 © Nexperia B.V. 2019. All rights reserved 9 / 15 74HC160 Nexperia Presettable synchronous BCD decade counter; asynchronous reset VI VM PE input GND tsu VI tsu th th VM CP input GND tsu VI tsu th th VM Dn input GND aaa-012356 The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. Fig. 11. The data input (Dn) and parallel enable input (PE) set-up and hold times CEP, CET input VI VM GND tsu VI CP input th tsu th VM GND aaa-012358 The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. Fig. 12. The count enable input (CEP) and count enable carry input (CET) set-up and hold times Table 8. Measurement points Input Output VM VI VM 0.5 x VCC GND to VCC 0.5 x VCC 74HC160 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 27 March 2019 © Nexperia B.V. 2019. All rights reserved 10 / 15 74HC160 Nexperia Presettable synchronous BCD decade counter; asynchronous reset VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VCC G VI DUT VCC VO RT RL S1 open CL 001aad983 Test data is given in Table 9. Test circuit definitions: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistance. S1 = Test selection switch Fig. 13. Test circuit for measuring switching times Table 9. Test data Input S1 position Load VI tr, tf CL RL tPHL, tPLH VCC 6 ns 15 pF, 50 pF 1 kΩ open 74HC160 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 27 March 2019 © Nexperia B.V. 2019. All rights reserved 11 / 15 74HC160 Nexperia Presettable synchronous BCD decade counter; asynchronous reset 11. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e w M bp 0 2.5 detail X 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 14. Package outline SOT109-1 (SO16) 74HC160 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 27 March 2019 © Nexperia B.V. 2019. All rights reserved 12 / 15 74HC160 Nexperia Presettable synchronous BCD decade counter; asynchronous reset 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC160 v.4 20190327 Product data sheet - 74HC_HCT160 v.3 Modifications: • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74HC160DB (SOT338-1) removed. 74HC160 v.3 20160927 Modifications: • • • 74HC_HCT160 v.2 74HC160 Product data sheet Product data sheet - 74HC_HCT160 v.2 The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Type numbers 74HCT160D, 74HCT160PW, 74HCT160N, 74HC160N and 74HC160PW removed. 19901201 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 4 — 27 March 2019 - © Nexperia B.V. 2019. All rights reserved 13 / 15 74HC160 Nexperia Presettable synchronous BCD decade counter; asynchronous reset 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. 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Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74HC160 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. 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Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 4 — 27 March 2019 © Nexperia B.V. 2019. All rights reserved 14 / 15 74HC160 Nexperia Presettable synchronous BCD decade counter; asynchronous reset Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 4 6. Functional description................................................. 4 7. Limiting values............................................................. 5 8. Recommended operating conditions..........................6 9. Static characteristics....................................................6 10. Dynamic characteristics............................................ 7 10.1. Waveforms and test circuit........................................ 9 11. Package outline........................................................ 12 12. Abbreviations............................................................ 13 13. Revision history........................................................13 14. Legal information......................................................14 © Nexperia B.V. 2019. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 27 March 2019 74HC160 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 27 March 2019 © Nexperia B.V. 2019. All rights reserved 15 / 15