INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
74HC/HCT4066
Quad bilateral switches
Product specification
Supersedes data of 1998 Oct 02
File under Integrated Circuits, IC06
1998 Nov 10
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
The 74HC/HCT4066 have four independent analog
switches. Each switch has two input/output terminals (nY,
nZ) and an active HIGH enable input (nE). When nE is
LOW the belonging analog switch is turned off.
FEATURES
• Very low “ON” resistance:
50 Ω (typ.) at VCC = 4.5 V
45 Ω (typ.) at VCC = 6.0 V
35 Ω (typ.) at VCC = 9.0 V
The “4066” is pin compatible with the “4016” but exhibits a
much lower “ON” resistance. In addition, the “ON”
resistance is relatively constant over the full input signal
range.
• Output capability: non-standard
• ICC category: SSI.
GENERAL DESCRIPTION
The 74HC/HCT4066 are high-speed Si-gate CMOS
devices and are pin compatible with the “4066” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
tPZH/ tPZL
turn-on time nE to Vos
tPHZ/ tPLZ
turn-off time nE to Vos
CI
input capacitance
CPD
power dissipation capacitance per switch
CS
max. switch capacitance
CL = 15 pF; RL = 1 kΩ; VCC = 5 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
a) PD = CPD × VCC2 × fi + ∑ {(CL + CS) × VCC2 × fo} where:
b) fi = input frequency in MHz
c) fo = output frequency in MHz
d) ∑ {(CL + CS) × VCC2 × fo} = sum of outputs
e) CL = output load capacitance in pF
f) CS = maximum switch capacitance in pF
g) VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
1998 Nov 10
2
HCT
11
12
ns
13
16
ns
3.5
3.5
pF
11
12
pF
8
8
pF
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
74HC4066
DIP14
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
74HC4066
SO14
plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
74HC4066
SSOP14
plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
74HC4066
TSSOP14
plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
74HCT4066
DIP14
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
74HCT4066
SO14
plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
74HCT4066
SSOP14
plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
74HCT4066
TSSOP14
plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
1, 4, 8, 11
1Y to 4Y
independent inputs/outputs
2, 3, 9, 10
1Z to 4Z
independent inputs/outputs
7
GND
ground (0 V)
13, 5, 6, 12
1E to 4E
enable inputs (active HIGH)
14
VCC
positive supply voltage
handbook, halfpage
handbook, halfpage
1Y
1
14 VCC
1Z
2
13 1E
2Z
3
12 4E
2Y
4
2E
5
10 4Z
3E
6
9
GND
4066
3Z
5
2E
6
3E
12
4E
1Y
1
1Z
2
2Y
4
2Z
3
3Y
8
3Z
9
4Y
11
4Z
10
MGR254
MGR253
Fig.1 Pin configuration.
1998 Nov 10
1E
11 4Y
8 3Y
7
13
Fig.2 Logic symbol.
3
Philips Semiconductors
Product specification
Quad bilateral switches
2
1
handbook, halfpage
74HC/HCT4066
1
handbook, halfpage
1
13 #
13 #
3
4
4
5 #
5 #
8
6 #
1
3
X1
1
6 #
10
11
2
X1
1
9
8
1
1
9
X1
12 #
11
MGR255
1
12 #
1
10
X1
MGR256
a.
b.
Fig.3 IEC logic symbol.
FUNCTION TABLE
INPUT NE
SWITCH
L
off
H
on
Note
1. H = HIGH voltage level; L = LOW voltage level.
handbook, halfpage13
1E
1
5
4
6
8
12
11
1Y
2E
2Y
3E
3Y
4E
4Y
nY
handbook, halfpage
1Z
2Z
3Z
2
3
9
4Z
10
nE
MGR257
VCC
GND
Fig.4 Functional diagram.
1998 Nov 10
VCC
nZ
MGR258
Fig.5 Schematic diagram (one switch).
4
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to GND
(GND = 0 V)
SYMBOL
PARAMETER
MIN.
MAX.
−0.5
UNIT
CONDITIONS
VCC
DC supply voltage
+11.0
V
±IIK
DC digital input diode current
20
mA
for VI < − 0.5 V or VI > VCC + 0.5 V
±ISK
DC switch diode current
20
mA
for VS < − 0.5 V or VS > VCC + 0.5 V
±IIS
DC switch current
25
mA
for −0.5 V < VS < VCC + 0.5 V
±ICC;
±IGND
DC VCC or GND current
50
mA
Tstg
storage temperature range
+150
°C
Ptot
power dissipation per package
PS
−65
for temperature range: −40 to +125 °C
74HC/HCT
plastic DIL
750
mW
above +70 °C: derate linearly with 12 mW/K
plastic mini-pack (SO)
500
mW
above +70 °C: derate linearly with 8 mW/K
power dissipation per switch
100
mW
Note
1. To avoid drawing VCC current out of terminal nZ, when switch current flows in terminal nY, the voltage drop across
the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current will flow
out of terminal nY. In this case there is no limit for the voltage drop across the switch, but the voltages at nY and nZ
may not exceed VCC or GND.
RECOMMENDED OPERATING CONDITIONS
74HC
SYMBOL
74HCT
PARAMETER
UNIT
min.
typ.
5.0
max.
min.
typ.
VCC
DC supply voltage
2.0
10.0
4.5
5.5
V
VI
DC input voltage range
GND
VCC
GND
VCC
V
VS
DC switch voltage range
GND
VCC
GND
VCC
V
Tamb
operating ambient
temperature range
−40
+85
−40
+85
°C
Tamb
operating ambient
temperature range
−40
+125
−40
+125
°C
tr, tf
input rise and fall times
500
ns
1998 Nov 10
6.0
1000
5.0
6.0
CONDITIONS
max.
see DC and AC
CHARACTERISTICS
VCC = 2.0 V
500
VCC = 4.5 V
400
VCC = 6.0 V
250
VCC = 10.0 V
5
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
DC CHARACTERISTICS FOR 74HC/HCT
For 74HC: VCC = 2.0, 4.5, 6.0 and 9.0 V; For 74HCT: VCC = 4.5 V
Tamb (°C)
TEST CONDITIONS
74HC/HCT
SYMBOL
PARAMETER
−40 to +85
+25
−40 to +125
UNIT V
IS
CC
(V) (µA)
VIS
VI
min. typ. max. min. max. min. max.
RON
RON
RON
∆RON
ON-resistance (peak)
ON-resistance (rail)
ON-resistance (rail)
maximum variation of
ON-resistance between
any two channels
−
−
−
−
Ω
2.0
54
95
118
142
Ω
4.5
42
84
105
126
Ω
6.0
VCC VIH
to
or
1000
GND VIL
1000
32
70
88
105
Ω
9.0
1000
80
−
−
−
Ω
2.0
100
35
75
95
115
Ω
4.5
27
65
82
100
Ω
6.0
GND VIH
or
1000
VIL
1000
20
55
70
85
Ω
9.0
1000
100 −
−
−
Ω
2.0
100
42
80
106
128
Ω
4.5
1000
35
75
94
113
Ω
6.0
1000
27
60
78
95
Ω
9.0
1000
−
Ω
2.0
5
Ω
4.5
4
Ω
6.0
3
Ω
9.0
100
VCC
VIH
or
VIL
VCC VIH
to
or
GND VIL
Note
1. At supply voltages approaching 2 V, the analog switch ON-resistance becomes extremely non-linear. Therefore it is
recommended that these devices be used to transmit digital signals only, when using these supply voltages.
1998 Nov 10
6
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
dbook, full pagewidth
HIGH
(from enable inputs)
V
nY
nZ
Vis = 0 to VCC − GND
Iis
GND
MGR259
Fig.6 Test circuit for measuring ON-resistance (RON).
handbook, full pagewidth
LOW
(from enable inputs)
nY
VI = VCC or GND
nZ
A
A
VO = GND or VCC
GND
MGR260
Fig.7 Test circuit for measuring OFF-state current.
handbook, full pagewidth
HIGH
(from enable inputs)
nY
VI = VCC or GND
nZ
A
A
GND
MGR261
Fig.8 Test circuit for measuring ON-state current.
1998 Nov 10
7
VO (open circuit)
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
MGR262
60
handbook, halfpage
RON
(Ω)
VCC = 4.5 V
50
6V
40
9V
30
20
10
0
1.8
3.6
5.4
7.2
9
Vis (V)
Fig.9 Typical ON-resistance (RON) as a function of input voltage (Vis) for Vis = 0 to VCC.
1998 Nov 10
8
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
DC CHARACTERISTICS FOR 74HC
Voltage are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
−40 to +85
+25
min. typ. max.
VIH
VIL
±II
HIGH-level input
voltage
LOW-level input
voltage
input leakage
current
min.
−40 to
+125
UNIT V
CC
(V)
VI
OTHER
max. min. max
1.5
1.2
1.5
1.5
V
3.15
2.4
3.15
3.15
4.5
4.2
3.2
4.2
4.2
6.0
6.3
4.7
6.3
6.3
9.0
0.8
0.50
0.50
0.50
2.1
1.35
1.35
1.35
4.5
2.8
1.80
1.80
1.80
6.0
4.3
2.70
2.70
2.70
9.0
0.1
1.0
1.0
0.2
2.0
2.0
V
2.0
2.0
µA
6.0
VCC
10.0 or
GND
±IS
analog switch
OFF-state
current per
channel
0.1
1.0
1.0
µA
10.0 VIH
or
VIL
VS = VCC − GND
(see Fig.7)
±IS
analog switch
ON-state current
0.1
1.0
1.0
µA
10.0 VIH
or
VIL
VS = VCC − GND
(see Fig.8)
ICC
quiescent
supply current
2.0
20.0
40.0
µA
6.0
4.0
40.0
80.0
1998 Nov 10
9
VCC Vis = GND or
VCC;
10.0 or
GND Vos = VCC or
GND
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL
PARAMETER
−40 to +85
+25
min.
tPHL/tPLH
tPZH/tPZL
tPHZ/tPLZ
propagation delay
Vis to Vos
turn-on time
nE to Vos
turn-off time
nE to Vos
1998 Nov 10
min.
min.
UNIT V
CC
(V)
typ.
max.
8
60
75
90
3
12
15
18
4.5
2
10
13
15
6.0
2
8
10
12
9.0
36
100
125
150
13
20
25
30
4.5
10
17
21
26
6.0
8
13
16
20
9.0
44
150
190
225
16
30
38
45
4.5
13
26
33
38
6.0
16
24
16
20
9.0
10
max.
−40 to +125
OTHER
max.
ns
ns
ns
2.0
2.0
2.0
RL = ∞;
CL = 50 pF
(see Fig.18)
RL = 1 kΩ;
CL = 50 pF
(see Figs 19
and 20)
RL = 1 kΩ;
CL = 50 pF
(see Figs 19
and 20)
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
DC CHARACTERISTICS FOR 74HCT
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
min.
VIH
HIGH-level
input voltage
VIL
LOW-level
input voltage
±II
2.0
+25
−40 to +85
typ.
max. min. max.
1.6
1.2
2.0
−40 to +125
min.
UNIT V
CC
(V)
VI
OTHER
max.
2.0
V
4.5
to
5.5
0.8
0.8
0.8
V
4.5
to
5.5
input leakage
current
0.1
1.0
1.0
µA
5.5
VCC
or
GND
±IS
analog switch
OFF-state
current per
channel
0.1
1.0
1.0
µA
5.5
VIH
or
VIL
VS = VCC − GND
(see Fig.7)
±IS
analog switch
ON-state
current
0.1
1.0
1.0
µA
5.5
VIH
or
VIL
VS = VCC − GND
(see Fig.8)
ICC
quiescent
supply current
2.0
20.0
40.0
µA
4.5
to
5.5
VCC
or
GND
Vis = GND or
VCC; Vos = VCC or
GND
∆ICC
additional
quiescent
supply current
per input pin
for unit load
coefficient is 1
(note 1)
360
450
490
µA
4.5
to
5.5
VCC − other inputs at
2.1 V VCC or GND
100
Note
1. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given here. To determine ∆ICC per input,
multiply this value by the unit load coefficient shown in the table below.
Table 1
1998 Nov 10
INPUT
UNIT LOAD COEFFICIENT
nE
1.00
11
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL
PARAMETER
−40 to +85
+25
−40 to +125
min. typ. max. min. max.
min.
UNIT V
CC
(V)
OTHER
max.
tPHL/tPLH
propagation
delay Vis to Vos
3
12
15
18
ns
4.5
RL = ∞; CL = 50 pF
(see Fig.18)
tPZH/tPZL
turn-on time
nE to Vos
12
24
30
36
ns
4.5
RL = 1 kΩ; CL = 50 pF
(see Figs 19 and 20)
tPHZ/tPLZ
turn-off time
nE to Vos
20
35
44
53
ns
4.5
RL = 1 kΩ; CL = 50 pF
(see Figs 19 and 20)
ADDITIONAL AC CHARACTERISTICS FOR 74HC/HCT
Recommended conditions and typical values GND = 0 V; tr = tf = 6 ns
SYMBOL
PARAMETER
sine wave distortion f = 1 kHz
V(p−p)
fmax
CS
TYP.
UNIT
VCC
(V)
VIS(p−p)
(V)
CONDITIONS
RL = 10 kΩ; CL = 50 pF
(see Fig.16)
0.04
%
4.5
4.0
0.02
%
9.0
8.0
sine wave distortion f = 10 kHz
0.12
%
4.5
4.0
0.06
%
9.0
8.0
switch “OFF” signal feed-through
−50
dB
4.5
note 3
−50
dB
9.0
RL = 600 Ω; CL = 50 pF;
f = 1 MHz (see Figs 10 and 17)
crosstalk between any two
switches
−60
dB
4.5
note 3
−60
dB
9.0
RL = 600 Ω; CL = 50 pF;
f = 1 MHz (see Fig.12)
crosstalk voltage between enable
or address input to any switch
(peak-to-peak value)
110
mV
4.5
220
mV
9.0
minimum frequency response
(−3 dB)
180
MHz
4.5
200
MHz
9.0
maximum switch capacitance
8
pF
RL = 10 kΩ; CL = 50 pF
(see Fig.16)
RL = 600 Ω; CL = 50 pF;
f = 1 MHz (nE, square wave
between VCC and GND,
tr = tf = 6 ns) (see Fig.14)
note 4
RL = 50 Ω; CL = 10 pF
(see Figs 11 and 15)
Notes
1. Vis is the input voltage at nY or nZ terminal, whichever is assigned as an input.
2. Vos is the output voltage at nY or nZ terminal, whichever is assigned as an output.
3. Adjust input voltage Vis is 0 dBM level (0 dBM = 1 mW into 600 Ω).
4. Adjust input voltage Vis is 0 dBM level at Vos for 1 MHz (0 dBM = 1 mW into 50 Ω).
1998 Nov 10
12
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
MGR263
0
handbook, full pagewidth
(dB)
−20
−40
−60
−80
−100
10
102
103
104
105
f (kHz)
106
Test conditions: VCC = 4.5 V; GND = 0 V; RL = 50 Ω; Rsource = 1 kΩ.
Fig.10 Typical switch “OFF” signal feed-through as a function of frequency.
MGR264
5
handbook, full pagewidth
(dB)
0
−5
10
102
103
104
Test conditions: VCC = 4.5 V; GND = 0 V; RL = 50 Ω; Rsource = 1 kΩ.
Fig.11 Typical frequency response.
1998 Nov 10
13
105
f (kHz)
106
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
VCC
handbook, full pagewidth
2RL
0.1 µF
Vi
nY/nZ
nZ/nY
RL
2RL
CL
channel
ON
GND
MGM265
Fig.12 Test circuit for measuring crosstalk between any two switches; channel ON condition.
VCC
handbook, full pagewidth
VCC
2RL
2RL
nY/nZ
nZ/nY
2RL
2RL
channel
OFF
Vos
CL dB
GND
MGR266
Fig.13 Test circuit for measuring crosstalk between any two switches; channel OFF condition.
VCC
handbook, full pagewidth
The crosstalk is defined as follows
(oscilloscope output):
VCC
GND
2RL
fpage
VCC
nE
nY/nZ
2RL
nZ/nY
D.U.T.
V(p-p)
2RL
2RL
CL
Vos
oscilloscope
MGR267
GND
MGR268
Fig.14 Test circuit for measuring crosstalk between control and any switch.
1998 Nov 10
14
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
VCC
handbook, full pagewidth
0.1 µF
Vis
sine-wave
2RL
nY/nZ
nZ/nY
CL
2RL
Vos
dB
channel
ON
GND
MGR269
Adjust input voltage to obtain 0 dBM at Vos when fin = 1 MHz. After set-up frequency of fin is increased to obtain a reading of −3 dB at Vos.
Fig.15 Test circuit for measuring minimum frequency response.
VCC
handbook, full pagewidth
10 µF
fin = 1 kHz Vis
sine-wave
2RL
nY/nZ
nZ/nY
2RL
CL
channel
ON
Vos
DISTORTION
METER
GND
MGR270
Fig.16 Test circuit for measuring sine wave distortion.
VCC
handbook, full pagewidth
0.1 µF
Vis
2RL
nY/nZ
nZ/nY
2RL
CL
Vos
dB
channel
OFF
GND
MGR271
Fig.17 Test circuit for measuring switch “OFF” signal feed-through.
1998 Nov 10
15
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
AC WAVEFORMS
tr
handbook, full pagewidth
tf
VCC
90%
Vis
50%
10%
GND
Vos
50%
tPLH
tPHL
MGR272
(1) HC: VM = 50%; VI = GND to VCC; HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.18 Waveforms showing the input (Vis) to output (Vos) propagation delays.
tf
tr
90 %
nE INPUT
V M (1)
10 %
t PLZ
OUTPUT
LOW - to - OFF
OFF - to - LOW
t PZL
50 %
10 %
t PHZ
t PZH
90 %
OUTPUT
HIGH - to - OFF
OFF - to - HIGH
50 %
outputs
disabled
outputs
enabled
MGA846
outputs
enabled
Fig.19 Waveforms showing the turn-on and turn-off times.
TEST CIRCUIT AND WAVEFORMS
VCC Vis
handbook, full pagewidth
PULSE
GENERATOR
VI
VCC
VO
RL
switch
open
D.U.T.
CL
RT
GND
MGR273
Fig.20 Test circuit for measuring AC performance.
1998 Nov 10
16
Philips Semiconductors
Product specification
Quad bilateral switches
Table 2
Table 3
74HC/HCT4066
Conditions
TEST
SWITCH
VIS
tPZH
GND
VCC
tPZL
VCC
GND
tPHZ
GND
VCC
tPLZ
VCC
GND
others
open
pulse
Definitions for Figs 20 and 21:
SYMBOL
DEFINITION
CL
load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values)
RT
termination resistance should be equal to the output impedance ZO of the pulse generator
tr
tf = 6 ns, when measuring fmax, there is no constraint on tr, tf with 50% duty factor
tW
handbook, full pagewidth
AMPLITUDE
90%
NEGATIVE
INPUT PULSE
VM
10%
0V
tTHL (tf)
tTLH (tr)
tTLH (tr)
tTHL (tf)
AMPLITUDE
90%
POSITIVE
INPUT PULSE
VM
10%
0V
tW
MGR274
Fig.21 Input pulse definitions.
Table 4
tr; tf
FAMILY
AMPLITUDE
VM
fmax;
PULSE WIDTH
OTHER
74HC
VCC
50%
< 2 ns
6 ns
74HCT
3.0 V
1.3 V
< 2 ns
6 ns
1998 Nov 10
17
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
PACKAGE OUTLINES
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
w M
b1
(e 1)
b
MH
8
14
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
2.2
inches
0.17
0.020
0.13
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.10
0.30
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.087
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT27-1
050G04
MO-001AA
1998 Nov 10
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
92-11-17
95-03-11
18
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.010 0.057
0.004 0.049
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.050
0.028
0.024
0.01
0.01
0.004
0.028
0.012
inches 0.069
0.244
0.039
0.041
0.228
0.016
θ
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06S
MS-012AB
1998 Nov 10
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-23
97-05-22
19
o
8
0o
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
D
SOT337-1
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
7
1
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.0
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
1.4
0.9
8
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT337-1
1998 Nov 10
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-02-04
96-01-18
MO-150AB
20
o
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.10
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
1998 Nov 10
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
94-07-12
95-04-04
MO-153
21
o
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
SOLDERING
Introduction
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
WAVE SOLDERING
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mount components are mixed on
one printed-circuit board. However, wave soldering is not
always suitable for surface mount ICs, or for printed-circuit
boards with high population densities. In these situations
reflow soldering is often used.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
Through-hole mount packages
SOLDERING BY DIPPING OR BY SOLDER WAVE
• For packages with leads on two sides and a pitch (e):
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
MANUAL SOLDERING
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400 °C, contact may be up to 5 seconds.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Surface mount packages
REFLOW SOLDERING
MANUAL SOLDERING
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
1998 Nov 10
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
22
Philips Semiconductors
Product specification
Quad bilateral switches
74HC/HCT4066
Suitability of IC packages for wave, reflow and dipping soldering methods
SOLDERING METHOD
MOUNTING
PACKAGE
WAVE
suitable(2)
Through-hole mount DBS, DIP, HDIP, SDIP, SIL
Surface mount
HLQFP, HSQFP, HSOP, SMS
not
PLCC(4),
suitable(3)
REFLOW(1)
DIPPING
−
suitable
suitable
−
suitable
suitable
−
LQFP, QFP, TQFP
not recommended(4)(5)
suitable
−
SQFP
not suitable
suitable
−
suitable
−
SO
SSOP, TSSOP, VSO
not
recommended(6)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
3. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1998 Nov 10
23
Philips Semiconductors – a worldwide company
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For all other countries apply to: Philips Semiconductors,
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5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245106/00/03/pp24
Date of release: 1998 Nov 10
Document order number:
9397 750 04779
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