74LV74D,118

74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 5 — 24 March 2021 Product data sheet 1. General description The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the nQ output. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. 2. Features and benefits • • • • • • • Wide supply voltage range from 1.0 V to 5.5 V Optimized for low voltage applications from 1.0 V to 3.6 V CMOS low power dissipation Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Direct interface with TTL levels (2.7 V to 3.6 V) ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV74D -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LV74PW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LV74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 4. Functional diagram 4 4 10 1SD 2SD 2 12 1D D 2D SD 3 1CP CP 11 2CP 2 1Q Q 2Q 5 9 1 FF RD 1Q Q 2Q 10 6 8 C1 1D 1RD 2RD 13 1 13 6 R 9 S 11 12 5 S 3 C2 2D 8 R aaa-008836 Fig. 1. aaa-008837 Logic symbol Fig. 2. 4 1SD 2 1D 3 1CP SD D Q CP IEC logic symbol 1Q 5 1Q 6 2Q 9 2Q 8 FF1 Q RD 1 1RD 10 2SD 12 2D 11 2CP SD Q D CP FF2 Q RD 13 2RD aaa-008838 Fig. 3. Functional diagram 74LV74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 © Nexperia B.V. 2021. All rights reserved 2 / 15 74LV74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Q C C C C C C D Q C C RD SD CP C aaa-008839 C Fig. 4. Logic diagram (one flip-flop) 5. Pinning information 5.1. Pinning 74LV74 1RD 1 14 VCC 1D 2 13 2RD 1CP 3 12 2D 1SD 4 11 2CP 1Q 5 10 2SD 1Q 6 9 2Q GND 7 8 2Q 74LV74 1RD 1 14 VCC 1D 2 13 2RD 1CP 3 12 2D 1SD 4 11 2CP 1Q 5 10 2SD 1Q 6 9 2Q GND 7 8 2Q aaa-008835 Fig. 5. aaa-033316 Pin configuration SOT108-1 (SO14) Fig. 6. Pin configuration SOT402-1 (TSSOP14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1RD, 2RD 1, 13 asynchronous reset-direct input (active-LOW) 1D, 2D 2, 12 data inputs 1CP, 2CP 3, 11 clock input (LOW-to-HIGH), edge-triggered) 1SD, 2SD 4, 10 asynchronous set-direct input (active-LOW) 1Q, 2Q 5, 9 true flip-flop outputs 1Q, 2Q 6, 8 complement flip-flop outputs GND 7 ground (0 V) VCC 14 supply voltage 74LV74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 © Nexperia B.V. 2021. All rights reserved 3 / 15 74LV74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 6. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition; Qn+1 = state after the next LOW-to-HIGH CP transition Input Output nSD nRD nCP nD nQ nQ Qn+1 nQ n+1 L H X X H L - - H L X X L H - - L L X X H H - - H H ↑ L - - L H H H ↑ H - - H L 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current IO output current ICC supply current IGND ground current Tstg storage temperature Ptot total power dissipation [1] [2] Conditions Min Max -0.5 +7 V - 20 mA -0.5 +7 V VO > VCC or VO < 0 - ±50 mA -0.5 V < VO < VCC + 0.5 V - ±25 mA - ±50 mA - ±50 mA -65 +150 °C - 500 [1] VI < -0.5 V or VI > VCC + 0.5 V [1] Tamb = -40 °C to +125 °C [2] Unit The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SOT108-1 (SO14) package: Ptot derates linearly with 10.1 mW/K above 100 °C. For SOT402-1 (TSSOP14) package: Ptot derates linearly with 7.3 mW/K above 81 °C. 74LV74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 © Nexperia B.V. 2021. All rights reserved 4 / 15 74LV74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter VCC supply voltage [1] VI input voltage VO output voltage Tamb ambient temperature Δt/ΔV input transition rise and fall rate [1] Conditions Min Typ Max Unit 1.0 3.3 5.5 V 0 - VCC V 0 - VCC V -40 - +125 °C VCC = 1.0 V to 2.0 V 0 - 500 ns/V VCC = 2.0 V to 2.7 V 0 - 200 ns/V VCC = 2.7 V to 3.6 V 0 - 100 ns/V VCC = 3.6 V to 5.5 V 0 - 50 ns/V 74LV74 is guaranteed to function down to VCC = 1.0 V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V. 74LV74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 © Nexperia B.V. 2021. All rights reserved 5 / 15 74LV74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage VIL LOW-level input voltage VOH HIGH-level output voltage Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ[1] Max Min Max VCC = 1.2 V 0.9 - - 0.9 - V VCC = 2.3 V to 2.7 V 1.4 - - 1.4 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V to 5.5 V 0.7VCC - - 0.7VCC - V VCC = 1.2 V - - 0.3 - 0.3 V VCC = 2.3 V to 2.7 V - - 0.6 - 0.6 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3VCC - 0.3VCC VCC = 1.2 V - 1.2 VCC = 2.0 V 1.8 2.0 - 1.8 - V VCC = 2.7 V 2.5 2.7 - 2.5 - V VCC = 3.0 V 2.8 3.0 - 2.8 - V VCC = 4.5 V 4.3 4.5 - 4.3 - V VCC = 3.0 V; IO = -6 mA 2.40 2.82 - 2.20 - V VCC = 4.5 V; IO = -12 mA 3.60 4.20 - 3.50 - V VCC = 1.2 V - 0 - - - VCC = 2.0 V - 0 0.2 0.2 V VCC = 2.7 V - 0 0.2 0.2 V VCC = 3.0 V - 0 0.2 0.2 V VCC = 4.5 V - 0 0.2 0.2 V VCC = 3.0 V; IO = 6 mA - 0.25 0.40 - 0.50 V VCC = 4.5 V; IO = 12 mA - 0.35 0.55 - 0.65 V VI = VIH or VIL; IO = -100 μA - standard outputs: VI = VIH or VIL VOL LOW-level output voltage VI = VIH or VIL; IO = 100 μA standard outputs: VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 5.5 V - - ±1 - ±1 μA ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 20 - 80 μA ΔICC additional supply current VI = VCC – 0.6 V; VCC = 2.7 V to 3.6 V - - 500 - 850 μA CI input capacitance - 3.5 - [1] pF Typical values are measured at Tamb = 25 °C. 74LV74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 © Nexperia B.V. 2021. All rights reserved 6 / 15 74LV74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V): for test circuit, see Fig. 9 Symbol Parameter tpd propagation delay Conditions -40 °C to +85 °C Min Typ[1] VCC = 1.2 V - VCC = 2.0 V - VCC = 2.7 V -40 °C to +125 °C Unit Max Min 70 - - - ns 24 44 - 56 ns - 18 28 - 41 ns - 13 26 - 33 ns - 11 - - - ns - 9.5 17 - 23 ns VCC = 1.2 V - 90 - - - ns VCC = 2.0 V - 31 46 - 58 ns VCC = 2.7 V - 23 34 - 43 ns - 17 27 - 34 ns - 14 - - - ns - 12 19 - 24 ns VCC = 1.2 V - 90 - - - ns VCC = 2.0 V - 31 46 - 58 ns VCC = 2.7 V - 23 34 - 43 ns - 17 27 - 34 ns - 14 - - - ns - 12 19 - 24 ns VCC = 2.0 V 34 10 - 41 - ns VCC = 2.7 V 25 8 - 30 - ns nCP to nQ, nQ; see Fig. 7 VCC = 3.0 V to 3.6 V [2] [3] VCC = 3.3 V; CL = 15 pF VCC = 4.5 V to 5.5 V Max [4] nSD to nQ, nQ; see Fig. 8 VCC = 3.0 V to 3.6 V [3] VCC = 3.3 V; CL = 15 pF VCC = 4.5 V to 5.5 V [4] nRD to nQ, nQ; see Fig. 8 VCC = 3.0 V to 3.6 V [3] VCC = 3.3 V; CL = 15 pF VCC = 4.5 V to 5.5 V tW pulse width [4] nCP input HIGH to LOW; see Fig. 7 VCC = 3.0 V to 3.6 V [3] 20 7 - 24 - ns VCC = 4.5 V to 5.5 V [4] 15 6 - 18 - ns VCC = 2.0 V 34 10 - 41 - ns VCC = 2.7 V 25 8 - 30 - ns nSD or nRD pulse width LOW; see Fig. 8 trec recovery time 74LV74 Product data sheet VCC = 3.0 V to 3.6 V [3] 20 7 - 24 - ns VCC = 4.5 V to 5.5 V [4] 15 6 - 18 - ns VCC = 1.2 V - 5 - - - ns VCC = 2.0 V 14 2 - 15 - ns VCC = 2.7 V 10 1 - 11 - ns nRD; see Fig. 8 VCC = 3.0 V to 3.6 V [3] 8 1 - 9 - ns VCC = 4.5 V to 5.5 V [4] 6 1 - 7 - ns All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 © Nexperia B.V. 2021. All rights reserved 7 / 15 74LV74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Symbol Parameter tsu th fmax CPD [1] [2] [3] [4] [5] set-up time hold time maximum frequency power dissipation capacitance Conditions -40 °C to +85 °C -40 °C to +125 °C Unit Min Typ[1] Max Min Max VCC = 1.2 V - 10 VCC = 2.0 V 22 4 - - - ns - 26 - ns VCC = 2.7 V 12 3 - 15 - ns nD to nCP; see Fig. 7 VCC = 3.0 V to 3.6 V [3] 8 2 - 10 - ns VCC = 4.5 V to 5.5 V [4] 6 1 - 8 - ns VCC = 1.2 V - -10 - - - ns VCC = 2.0 V 3 -2 - 3 - ns VCC = 2.7 V 3 -2 - 3 - ns nD to nCP; see Fig. 7 VCC = 3.0 V to 3.6 V [3] 3 -2 - 3 - ns VCC = 4.5 V to 5.5 V [4] 3 -2 - 3 - ns VCC = 2.0 V 14 40 - 12 - MHz VCC = 2.7 V 50 90 - 40 - MHz nCP; see Fig. 7 VCC = 3.0 V to 3.6 V [3] 60 100 - 48 - MHz VCC = 4.5 V to 5.5 V [4] 70 110 - 56 - MHz [5] - 24 - - - pF VI = GND to VCC Typical values are measured at Tamb = 25 °C. tpd is the same as tPHL and tPLH. Typical value measured at VCC = 3.3 V. Typical values are measured at VCC = 5.0 V. 2 2 CPD is used to determine the dynamic power dissipation PD = CPD x VCC x fi + Σ(CL x VCC x fo) (PD in μW), where: fi = input frequency in MHz; fo = output frequency in MHz; 2 Σ(CL x VCC x fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in V. 74LV74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 © Nexperia B.V. 2021. All rights reserved 8 / 15 74LV74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 10.1. Waveforms and test circuit VI nD input VM GND tsu th 1/fmax VI nCP input tsu th VM GND tPHL VOH nQ output tW tPLH VM VOL VOH nQ output VM VOL tPLH tPHL aaa-008840 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 7. Clock pulse (nCP) to output (nQ, nQ) propagation delays, nCP pulse width and maximum frequency VI nCP input VM GND trec VI nSD input VM GND tW VI VM nRD input GND VOH tW tPLH nQ output tPHL VM VOL VOH nQ output VOL VM tPHL tPLH aaa-008842 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig. 8. The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD to nCP recovery time 74LV74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 © Nexperia B.V. 2021. All rights reserved 9 / 15 74LV74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Table 8. Measurement points Supply voltage Input Output VCC VM VM < 2.7 V 0.5VCC 0.5VCC 2.7 V to 3.6 V 1.5 V 1.5 V ≥ 4.5 V 0.5VCC 0.5VCC VI negative pulse tW 90 % VM 0V VI positive pulse 0V VM 10 % tf tr tr tf 90 % VM VM 10 % tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 9. Test circuit for measuring switching times Table 9. Test data Supply voltage Input VEXT Load VI tr, tf CL RL tPHL, tPLH < 2.7 V VCC 2.5 ns 50 pF 1 kΩ open 2.7 V to 3.6 V 2.7 V 2.5 ns 50 pF, 15 pF 1 kΩ open ≥ 4.5 V VCC 2.5 ns 50 pF 1 kΩ open 74LV74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 © Nexperia B.V. 2021. All rights reserved 10 / 15 74LV74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 A2 Q A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 10. Package outline SOT108-1 (SO14) 74LV74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 © Nexperia B.V. 2021. All rights reserved 11 / 15 74LV74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm D SOT402-1 E A X c y HE v M A Z 8 14 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 7 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig. 11. Package outline SOT402-1 (TSSOP14) 74LV74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 © Nexperia B.V. 2021. All rights reserved 12 / 15 74LV74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LV74 v.5 20210324 Product data sheet - 74LV74 v.4 Modifications: • • • • • The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Section 1 and Section 2 updated. Section 7: Derating values for Ptot total power dissipation updated. Type number 74LV74DB (SOT337-1/SSOP14) removed. 74LV74 v.4 20151209 Modifications: • 74LV74 v.3 20130909 Modifications: • • • 74LV74_CNV v.2 74LV74 Product data sheet Product data sheet - 74LV74 v.3 - 74LV74_CNV v.2 Type number 74LV74N (SOT27-1) removed. Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Family data added, see Section 9 April 1998 Product specification - All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 - © Nexperia B.V. 2021. All rights reserved 13 / 15 74LV74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Data sheet status Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 © Nexperia B.V. 2021. All rights reserved 14 / 15 74LV74 Nexperia Dual D-type flip-flop with set and reset; positive-edge trigger Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................1 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 3 6. Functional description................................................. 4 7. Limiting values............................................................. 4 8. Recommended operating conditions..........................5 9. Static characteristics....................................................6 10. Dynamic characteristics............................................ 7 10.1. Waveforms and test circuit........................................ 9 11. Package outline........................................................ 11 12. Abbreviations............................................................ 13 13. Revision history........................................................13 14. Legal information......................................................14 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 24 March 2021 74LV74 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 March 2021 © Nexperia B.V. 2021. All rights reserved 15 / 15