HEF4894BTT-Q100,11

HEF4894B-Q100 12-stage shift-and-store register LED driver Rev. 1 — 12 July 2012 Product data sheet 1. General description The HEF4894B-Q100 is a 12-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input (D) to the parallel LED driver outputs (QP0 to QP11). Data is shifted on positive-going clock (CP) transitions. The data in each shift register stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in the storage register appears at the output whenever the output enable (OE) input signal is HIGH. Two serial outputs (QS1 and QS2) are available for cascading a number of HEF4894B-Q100 devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed operation in cascaded systems with a fast clock rise time. The same serial data is available at QS2 on the next negative going clock edge. This is used for cascading HEF4894B-Q100 devices when the clock has a slow rise time. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Fully static operation  5 V, 10 V, and 15 V parametric ratings  Standardized symmetrical output characteristics  ESD protection:  MIL-STD-833, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )  Complies with JEDEC standard JESD 13-B HEF4894B-Q100 Nexperia 12-stage shift-and-store register LED driver 3. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C. Type number Package Name Description Version HEF4894BT-Q100 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 HEF4894BTT-Q100 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 4. Functional diagram 2 3 1 CP STR QS1 11 QS2 12 QP0 4 QP1 5 QP2 6 QP3 7 QP4 8 QP5 9 QP6 18 D QP7 17 QP8 16 QP9 15 QP10 14 QP11 13 OE 19 Fig 1. 001aai639 Logic Symbol D CP 2 12 12-STAGE SHIFT REGISTER 3 11 STR OE 1 QS1 12-BIT STORAGE REGISTER 19 OPEN-DRAIN OUTPUTS 4 5 QP0 6 7 QP2 QP1 Fig 2. QS2 8 9 QP4 QP3 18 17 QP6 QP5 16 15 QP8 QP7 14 13 QP10 QP9 QP11 001aag118 Functional diagram HEF4894B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © Nexperia B.V. 2017. All rights reserved 2 of 18 HEF4894B-Q100 Nexperia 12-stage shift-and-store register LED driver STAGE 0 D D Q STAGE 1 TO 10 D Q10S STAGE 11 D FF0 D FF11 CP QS1 Q Q QS2 LATCH CP LE CP D D Q Q LATCH LATCH LE LE STR OE QP0 QP1 Fig 3. QP11 QP10 001aag119 Logic diagram 5. Pinning information 5.1 Pinning HEF4894B-Q100 STR 1 20 VDD D 2 19 OE CP 3 18 QP6 QP0 4 17 QP7 QP1 5 16 QP8 QP2 6 15 QP9 QP3 7 14 QP10 QP4 8 13 QP11 QP5 9 12 QS2 VSS 10 11 QS1 aaa-003548 Fig 4. Pin configuration HEF4894B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © Nexperia B.V. 2017. All rights reserved 3 of 18 HEF4894B-Q100 Nexperia 12-stage shift-and-store register LED driver 5.2 Pin description Table 2. Pin description Symbol Pin Description D 2 serial input QP0 to QP11 4, 5, 6, 7, 8, 9, 18, 17, 16, 15, 14, 13 parallel output QS1 11 serial output QS2 12 serial output CP 3 clock input STR 1 strobe input OE 19 output enable input VDD 20 supply voltage VSS 10 ground (0 V) 6. Functional description Table 3. Function table[1] At the positive clock edge the information in the 10th register stage is transferred to the 11th register stage and the QS output Control Input Parallel output Serial output CP OE STR D QP0 QPn QS1[2] QS2[3]  L X X Z Z Q10S no change  L X X Z Z no change Q11S  H L X no change no change Q10S no change  H H L Z QPn 1 Q10S no change  H H H L QPn1 Q10S no change  H H H no change no change no change Q11S [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = LOW-to-HIGH clock transition;  = HIGH-to-LOW clock transition; Z = high-impedance OFF-state. [2] Q10S = the data in register stage 10 before the LOW to HIGH clock transition. [3] Q11S = the data in register stage 11 before the HIGH to LOW clock transition. HEF4894B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © Nexperia B.V. 2017. All rights reserved 4 of 18 HEF4894B-Q100 Nexperia 12-stage shift-and-store register LED driver clock input data input strobe input output enable input internal Q0S (FF 1) QP0 output internal Q10S (FF 11) QP10 output serial QS1 output serial QS2 output 001aag121 Fig 5. Timing diagram 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II input leakage current IO output current Conditions Min Max 0.5 VI < 0.5 V or VI > VDD + 0.5 V +18 10 0.5 QSn outputs; VO < 0.5 V or VO > VDD + 0.5 V - QPn outputs; VO < 0.5 V VDD + 0.5 Unit V mA V 10 mA - 40 mA - 10 mA QSn outputs - 10 mA QPn outputs - 40 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +125 C Ptot total power dissipation Tamb = 40 C to +125 C SO20 and TSSOP20 package P [1] power dissipation per output [1] - 500 mW - 100 mW For SO20 package: Ptot derates linearly with 8 mW/K above 70 C. For TSSOP20 package: Ptot derates linearly with 5.5 mW/K above 60 C. HEF4894B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © Nexperia B.V. 2017. All rights reserved 5 of 18 HEF4894B-Q100 Nexperia 12-stage shift-and-store register LED driver 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD VI Conditions Min Typ Max Unit supply voltage 3 - 15 V input voltage 0 - VDD V Tamb ambient temperature in free air 40 - +125 C t/V input transition rise and fall rate VDD = 5 V - - 3.75 s/V VDD = 10 V - - 0.5 s/V VDD = 15 V - - 0.08 s/V 9. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH VIL VOH VOL Conditions HIGH-level input voltage IO < 1 A LOW-level input voltage IO < 1 A HIGH-level output voltage LOW-level output voltage IOL II HIGH-level output current LOW-level output current input leakage current HEF4894B_Q100 Product data sheet Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit Min Max Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 - 0.05 V 5V - 0.75 - 0.75 - 1.5 - 1.5 V 10 V - 0.75 - 0.75 - 1.5 - 1.5 V 15 V - 0.75 - 0.75 - 1.5 - 1.5 V VO = 2.5 V 5V - 1.7 - 1.4 - 1.1 - 1.1 mA VO = 4.6 V 5V - 0.64 - 0.5 - 0.36 - 0.36 mA VO = 9.5 V 10 V - 1.6 - 1.3 - 0.9 - 0.9 mA VO = 13.5 V 15 V - 4.2 - 3.4 - 2.4 - 2.4 mA QSn outputs; IO < 1 A QSn outputs; IO < 1 A QPn outputs; IO < 20 mA IOH VDD QSn outputs QSn outputs VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.2 - 2.4 - 2.4 - mA 15 V - 0.1 - 0.1 - 1.0 - 1.0 A All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © Nexperia B.V. 2017. All rights reserved 6 of 18 HEF4894B-Q100 Nexperia 12-stage shift-and-store register LED driver Table 6. Static characteristics …continued VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter IOZ IDD CI OFF-state output current supply current Conditions VDD QPn output is HIGH; VO = 15 V Min Max Min Max Min Max Min Max 5V - 2 - 2 - 15 - 15 A 10 V - 2 - 2 - 15 - 15 A 15 V - 2 - 2 - 15 - 15 A 5V - 5 - 5 - 150 - 150 A 10 V - 10 - 10 - 300 - 300 A 15 V - 20 - 20 - 600 - 600 A - - - - 7.5 - - - - pF Extrapolation formula Min Typ Max IO = 0 A input capacitance Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit 10. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 C unless otherwise specified. For test circuit see Figure 10. Symbol Parameter tPHL HIGH to LOW propagation delay Conditions CP to QS1; see Figure 6 CP to QS2; see Figure 6 tPLH LOW to HIGH propagation delay CP to QS1; see Figure 6 CP to QS2; see Figure 6 tPZL OFF-state to LOW propagation delay CP to QPn; see Figure 6 STR to QPn; see Figure 7 tPLZ LOW to OFF-state propagation delay CP to QPn; see Figure 6 and 7 STR to QPn; see Figure 7 HEF4894B_Q100 Product data sheet VDD 5V [1] Unit 132 ns + (0.55 ns/pF)CL - 160 320 ns 10 V 53 ns + (0.23 ns/pF)CL - 65 130 ns 15 V 37 ns + (0.16 ns/pF)CL - 45 90 ns 5V 92 ns + (0.55 ns/pF)CL - 120 240 ns 10 V 39 ns + (0.23 ns/pF)CL - 50 100 ns 15 V 32 ns + (0.16 ns/pF)CL - 40 80 ns 102 ns + (0.55 ns/pF)CL - 130 260 ns 44 ns + (0.23 ns/pF)CL - 55 110 ns 15 V 32 ns + (0.16 ns/pF)CL - 40 80 ns 5V 102 ns + (0.55 ns/pF)CL - 130 260 ns 10 V 49 ns + (0.23 ns/pF)CL - 60 120 ns 15 V 37 ns + (0.16 ns/pF)CL - 45 90 ns 5V 10 V [1] 5V - 240 480 ns 10 V - 80 160 ns 15 V - 55 110 ns 5V - 140 280 ns 10 V - 70 140 ns 15 V - 55 110 ns 5V - 170 340 ns 10 V - 75 150 ns 15 V - 60 120 ns 5V - 100 200 ns 10 V - 40 100 ns 15 V - 35 70 ns All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © Nexperia B.V. 2017. All rights reserved 7 of 18 HEF4894B-Q100 Nexperia 12-stage shift-and-store register LED driver Table 7. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 C unless otherwise specified. For test circuit see Figure 10. Symbol Parameter ten Conditions VDD OE to QPn; see Figure 8 5V Extrapolation formula [2] 10 V 15 V OE to QPn; see Figure 8 tdis 5V [2] 10 V 15 V transition time tt pulse width tW QS1, QS2; see Figure 6 5V set-up time hold time th fclk(max) [1] maximum clock frequency Typ Max Unit - 100 200 ns - 55 110 ns - 50 100 ns - 80 160 ns - 40 80 ns - 30 60 ns 35 ns + (1.00 ns/pF)CL - 85 170 ns 10 V 19 ns + (0.42 ns/pF)CL - 40 80 ns 15 V 16 ns + (0.28 ns/pF)CL - 30 60 ns CP; LOW and HIGH; 5 V see Figure 6 10 V 60 30 - ns 30 15 - ns 15 V 24 12 - ns 5V 80 40 - ns 10 V 60 30 - ns 15 V 24 12 - ns 5V 60 30 - ns 10 V 20 10 - ns 15 V 15 5 - ns STR; HIGH; see Figure 7 tsu [1][3] Min D to CP; see Figure 9 D to CP; see Figure 9 CP; see Figure 6 5V +5 15 - ns 10 V 20 5 - ns 15 V 20 5 - ns 5V 5 10 - MHz 10 V 11 22 - MHz 15 V 14 28 - MHz The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). [2] ten is the same as tPZL and tdis is the same as tPLZ. [3] tt is the same as tTLH and tTHL. Table 8. Dynamic power dissipation PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C. Symbol Parameter PD dynamic power dissipation HEF4894B_Q100 Product data sheet VDD Typical formula Where 5V PD = 1200  fi + (fo  CL)  VDD W 10 V PD = 5550  fi + (fo  CL)  VDD W 15 V PD = 15000  fi + (fo  CL)  VDD2 W 2 2 All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; (fo  CL) = sum of the outputs; VDD = supply voltage in V. © Nexperia B.V. 2017. All rights reserved 8 of 18 HEF4894B-Q100 Nexperia 12-stage shift-and-store register LED driver 11. Waveforms 1/fclk(max) VI VM CP input VSS tW tW tPLZ tPZL VDD VY QPn output VX VOL tPLH VOH tPHL 90 % VM QS1 output VOL 10 % tTHL tTLH tPLH VOH tPHL 90 % VM QS2 output 10 % VOL tTLH tTHL 001aag222 Parallel output measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Propagation delay clock (CP) to output (QPn, QS1, QS2), clock pulse width and maximum clock frequency Table 9. Measurement points Supply Input Output VDD VM VM VX VY 5 V to 15 V 0.5VDD 0.5VDD 0.1VO 0.9VO VI VM CP input VSS VI STR input VM VSS VDD tW tPLZ tPZL VY QPn output VOL VX 001aag802 Measurement points are given in Table 9. VOL is the typical output voltage level that occurs with the output load. Fig 7. Strobe (STR) to output (QPn) propagation delays and the strobe pulse width HEF4894B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © Nexperia B.V. 2017. All rights reserved 9 of 18 HEF4894B-Q100 Nexperia 12-stage shift-and-store register LED driver VI OE input VM VSS tPLZ tPZL VDD output LOW to OFF-state OFF-state to LOW VOL VY VX outputs enabled outputs disabled outputs enabled 001aag803 Measurement points are given in Table 9. VOL is the typical output voltage level that occurs with the output load. Fig 8. Enable and disable times for input OE VI CP input VM VSS tsu tsu th th VI VM D input VSS VDD QPn output VOL 001aag805 Measurement points are given in Table 9. VOL is a typical output voltage level that occurs with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Set-up and hold times for the data input (D) HEF4894B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © Nexperia B.V. 2017. All rights reserved 10 of 18 HEF4894B-Q100 Nexperia 12-stage shift-and-store register LED driver VI 90 % input pulse VSS 10 % tf tr VEXT VDD G VI VO RL DUT CL RT 001aag804 Test data is given in Table 10. Definitions for test circuit: DUT - Device Under Test; RL = Load resistance; CL = load capacitance; RT = Termination resistance should be equal to output impedance of Zo of the pulse generator; VEXT = External voltage for measuring switching times. Fig 10. Test circuit for measuring switching times Table 10. Test data Supply Input VDD VI tr, tf tPLZ, tPZL tPLH, tPHL CL RL 5 V to 15 V VDD  20 ns VDD open 50 pF 1 k HEF4894B_Q100 Product data sheet VEXT Load All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © Nexperia B.V. 2017. All rights reserved 11 of 18 HEF4894B-Q100 Nexperia 12-stage shift-and-store register LED driver 12. Application information Application example: serial-to-parallel data converting LED driver. 9'' 9'' 43 43 9'' ' 2( 3:0GLPPHU LQSXW 675 43 43 +()%4 46 &3 43 43 9'' ' 966 2( 675 +()%4 43 43 46 &3 966 &21752/$1' 6