TSL1410R

TSL1410R 1280 × 1 LINEAR SENSOR ARRAY WITH HOLD r r D D D D D D D D D D D TAOS043E − APRIL 2007 1280 × 1 Sensor-Element Organization 400 Dot-Per-Inch (DPI) Sensor Pitch High Linearity and Uniformity Wide Dynamic Range . . . 4000:1 (72 dB) Output Referenced to Ground Low Image Lag . . . 0.5% Typ Operation to 8 MHz Single 3-V to 5-V Supply Rail-to-Rail Output Swing (AO) No External Load Resistor Required Replacement for TSL1410 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 Description The TSL1410R linear sensor array consists of two sections of 640 photodiodes, each with associated charge amplifier circuitry, aligned to form a contiguous 1280 × 1 pixel array. The device incorporates a pixel data-hold function that provides simultaneous-integration start and stop times for all pixels. The pixels measure 63.5 μm by 55.5 μm with 63.5-μm center-to-center spacing and 8-μm spacing between pixels. Operation is simplified by internal logic that requires only a serial-input (SI) pulse and a clock. VPP SI1 HOLD1 CLK1 GND AO1 SO1 SI2 HOLD2 CLK2 SO2 AO2 VDD The device is intended for use in a wide variety of applications including mark and code reading, OCR and contact imaging, edge detection and positioning, and optical encoding. Functional Block Diagram (each section) Pixel 1 (641) Pixel 2 (642) 1 Integrator Reset 2 S1 _ 2 1 Pixel 3 (643) Pixel 640 (1280) 13 Analog Bus 3 Output Buffer 6, 12 VDD AO + S2 Sample/Hold/ Output 5 Gain Trim Switch Control Logic 7, 11 Hold CLK SI 3, 9 Hold Q1 4, 10 Q2 GND Q3 SO Q640 (Q1280) 640-Bit Shift Register (2 each) 2, 8 The LUMENOLOGY r Company Copyright E 2007, TAOS Inc. r Texas Advanced Optoelectronic Solutions Inc. 1001 Klein Road S Suite 300 S Plano, TX 75074 S (972) r 673-0759 www.taosinc.com 1 TSL1410R 1280 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS043E − APRIL 2007 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AO1 6 O Analog output, section 1. AO2 12 O Analog output, section 2. CLK1 4 I Clock, section 1. CLK1 controls charge transfer, pixel output, and reset. CLK2 10 I Clock, section 2. CLK2 controls charge transfer, pixel output, and reset. GND 5 HOLD1 3 I Hold signal. HOLD1 shifts pixel data to parallel buffer. HOLD1 is normally connected to SI1 and HOLD2 in serial mode and to SI1 in parallel mode. HOLD2 9 I Hold signal. HOLD2 shifts pixel data to parallel buffer. HOLD2 is normally connected to SI2 in parallel mode. SI1 2 I Serial input (section 1). SI1 defines the start of the data-out sequence. SI2 8 I Serial input (section 2). SI2 defines the start of the data-out sequence. SO1 7 O Serial output (section 1). SO1 provides a signal to drive the SI2 input in serial mode. SO2 11 O Serial output (section 2). SO2 provides a signal to drive the SI input of another device for cascading or as an end-of-data indication. VDD 13 Supply voltage for both analog and digital circuitry. VPP 1 Normally grounded. Ground (substrate). All voltages are referenced to GND. Detailed Description The sensor consists of 1280 photodiodes, called pixels, arranged in a linear array. Light energy impinging on a pixel generates photocurrent that is then integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel and the integration time. The output and reset of the integrators are controlled by a 640-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. Another signal, called HOLD, is generated from the rising edge of SI1 when SI1 and HOLD1 are connected together. This causes all 640 sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO. The integrator reset period ends 18 clock cycles after the SI pulse is clocked in. Then the next integration period begins. On the 640th clock rising edge, the SI pulse is clocked out on the SO1 pin (section 1) and becomes the SI pulse for section 2 (when SO1 is connected to SI2). The rising edge of the 641st clock cycle terminates the SO1 pulse, and returns the analog output AO of section 1 to high-impedance state. Similarly, SO2 is clocked out on the 1280th clock pulse. Note that a 1281st clock pulse is needed to terminate the SO2 pulse and return AO of Section 2 to the high-impedance state. If a minimum integration time is desired, the next SI pulse may be presented after a minimum delay of tqt (pixel charge transfer time) after the 1281st clock pulse. Sections 1 and 2 may be operated in parallel or in serial fashion. AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail output voltage swing. With VDD = 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V for saturation light level. When the device is not in the output phase, AO is in a high-impedance state. The voltage developed at analog output (AO) is given by: Vout = Vdrk + (Re) (Ee)(tint) where: Vout Vdrk Re Ee tint is the analog output voltage for white condition is the analog output voltage for dark condition is the device responsivity for a given wavelength of light given in V/(μJ/cm2) is the incident irradiance in μW/cm2 is integration time in seconds A 0.1 μF bypass capacitor should be connected between VDD and ground as close as possible to the device. Copyright E 2007, TAOS Inc. 2 The LUMENOLOGY r Company r www.taosinc.com r TSL1410R 1280 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS043E − APRIL 2007 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VDD + 0.3V Input clamp current, IIK (VI < 0) or (VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA to 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 mA to 25 mA Voltage range applied to any output in the high impedance or power-off state, VO . . . −0.3 V to VDD + 0.3 V Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 mA to 25 mA Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 mA to 40 mA Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 mA to 25 mA Maximum light exposure at 638 nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mJ/cm2 Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to 85°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Recommended Operating Conditions MIN NOM Supply voltage, VDD 3 5 Input voltage, VI 0 High-level input voltage, VIH Low-level input voltage, VIL VDD × 0.7 Wavelength of light source, λ 400 0 Clock frequency, fclock 5 MAX UNIT 5.5 V VDD V VDD V VDD × 0.3 V 1100 nm 8000 kHz Sensor integration time, Serial, tint (see Note 1) 0.17775 100 ms Sensor integration time, Parallel, tint (see Note 1) Setup time, serial input, tsu(SI) 0.09775 100 ms 20 Hold time, serial input, th(SI) (see Note 2) 0 Operating free-air temperature, TA 0 Load capacitance, CL Load resistance, RL 300 ns ns 70 °C 330 pF Ω NOTES: 1. Integration time is calculated as follows: tint(min) = (1280 − 18) y clock period + 20 ms where 1280 is the number of pixels in series, 18 is the required logic setup clocks, and 20 ms is the pixel charge transfer time (tqt) 2. SI must go low before the rising edge of the next clock pulse. The LUMENOLOGY r Company Copyright E 2007, TAOS Inc. r www.taosinc.com r 3 TSL1410R 1280 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS043E − APRIL 2007 Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms, RL = 330 Ω, Ee = 12.5 μW/cm2 (unless otherwise noted) (see Note 3) PARAMETER TEST CONDITIONS MIN TYP MAX 1.6 2 2.4 UNIT V 0 0.1 0.3 V Vout Analog output voltage (white, average over 1280 pixels) See Note 4 Vdrk Analog output voltage (dark, average over 1280 pixels) Ee = 0 PRNU Pixel response nonuniformity See Note 5 Nonlinearity of analog output voltage See Note 6 ±0.4% Output noise voltage See Note 7 1 Re Responsivity See Note 8 20 30 Vsat Analog output saturation voltage VDD = 5 V, RL = 330 Ω 4.5 4.8 VDD = 3 V, RL = 330 Ω 2.5 2.8 SE Saturation exposure DSNU Dark signal nonuniformity All pixels, Ee = 0, See Note 10 IL Image lag See Note 11 IDD Supply current IIH High-level input current VI = VDD IIL Low-level input current VI = 0 Ci Input capacitance, SI 25 pF Ci Input capacitance, CLK 25 pF ±20% VDD = 5 V, See Note 9 155 VDD = 3 V, See Note 9 90 0.05 mVrms 38 V/ (μJ/cm 2) V nJ/cm 2 0.15 V 0.5% VDD = 5 V, Ee = 0 30 45 VDD = 3 V, Ee = 0 25 40 mA 10 μA 10 μA NOTES: 3. All measurements made with a 0.1 μF capacitor connected between VDD and ground. 4. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm. 5. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU. 6. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white). 7. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period. 8. Re(min) = [Vout(min) − Vdrk(max)] ÷ (Ee × tint) 9. SE(min) = [Vsat(min) − Vdrk(min)] × 〈Ee × tint) ÷ [Vout(max) − Vdrk(min)] 10. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination. 11. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition: IL + V out (IL) * V drk V out (white) * V drk 100 Timing Requirements (see Figure 1 and Figure 2) MIN tsu(SI) Setup time, serial input (see Note 12) th(SI) Hold time, serial input (see Note 12 and Note 13) tpd(SO) Propagation delay time, SO tw Pulse duration, clock high or low 50 tr, tf Input transition (rise and fall) time 0 tqt Pixel charge transfer time NOM MAX 20 ns 0 ns 50 20 UNIT ns ns 500 ns μs NOTES: 12. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns. 13. SI must go low before the rising edge of the next clock pulse. Copyright E 2007, TAOS Inc. 4 The LUMENOLOGY r Company r www.taosinc.com r TSL1410R 1280 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS043E − APRIL 2007 Dynamic Characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figures 7 and 8) PARAMETER ts Analog output settling time to ± 1% tpd(SO) Propagation delay time, SO1, SO2 TEST CONDITIONS RL = 330 Ω, MIN CL = 50 pF TYP MAX UNIT 120 ns 50 ns TYPICAL CHARACTERISTICS CLK tqt SI1 Internal Reset Integration 18 Clock Cycles tint Not Integrating Integrating ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ 1281 Clock Cycles AO Hi-Z Hi-Z Figure 1. Timing Waveforms (serial connection) tw 1 2 640 641 2.5 V CLK 5V 0V tsu(SI) SI 5V 50% 0V th(SI) tpd(SO) tpd(SO) SO ts AO Pixel 1 Pixel 640 Figure 2. Operational Waveforms (Each Section) The LUMENOLOGY r Company Copyright E 2007, TAOS Inc. r www.taosinc.com r 5 TSL1410R 1280 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS043E − APRIL 2007 TYPICAL CHARACTERISTICS NORMALIZED IDLE SUPPLY CURRENT vs FREE-AIR TEMPERATURE PHOTODIODE SPECTRAL RESPONSIVITY 1 2 IDD — Normalized Idle Supply Current TA = 25°C Relative Responsivity 0.8 0.6 0.4 0.2 0 300 1.5 1 0.5 0 400 500 600 700 800 900 1000 1100 0 10 20 Figure 3 50 60 70 Figure 4 DARK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE WHITE OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 2 0.10 VDD = 5 V tint = 0.5 ms to 15 ms tint = 0.5 ms tint = 1 ms VDD = 5 V 0.09 1.5 Vout — Output Voltage Vout — Output Voltage — V 40 TA − Free-Air Temperature − °C λ − Wavelength − nm 1 0.5 0 0.08 tint = 15 ms tint = 5 ms tint = 2.5 ms 0.07 0.06 0 10 20 30 40 60 50 TA − Free-Air Temperature − °C 70 0 10 20 30 40 60 50 TA − Free-Air Temperature − °C Copyright E 2007, TAOS Inc. 70 Figure 6 Figure 5 6 30 The LUMENOLOGY r Company r www.taosinc.com r TSL1410R 1280 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS043E − APRIL 2007 TYPICAL CHARACTERISTICS SETTLING TIME vs. LOAD 600 SETTLING TIME vs. LOAD 600 VDD = 3 V Vout = 1 V 500 470 pF Settling Time to 1% — ns Settling Time to 1% — ns 500 400 220 pF 300 200 100 pF 100 0 VDD = 5 V Vout = 1 V 400 220 pF 300 200 100 pF 100 10 pF 0 470 pF 200 400 600 800 RL — Load Resistance − W 1000 0 10 pF 0 200 400 600 800 RL — Load Resistance − W Figure 7 1000 Figure 8 APPLICATION INFORMATION 1 1 2 3 4 2 3 4 SI1/HOLD1/HOLD2 CLK1 and CLK2 5 6 CLK1 and CLK2 5 6 7 SO1 SI2 8 9 10 11 12 13 SI1/HOLD1 7 AO1 SO1 8 SI2/HOLD2 9 10 11 12 SO2 AO1/AO2 13 VDD SERIAL SO2 AO2 VDD PARALLEL Figure 9. Operational Connections The LUMENOLOGY r Company Copyright E 2007, TAOS Inc. r www.taosinc.com r 7 TSL1410R 1280 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS043E − APRIL 2007 APPLICATION INFORMATION Integration Time The integration time of the linear array is the period during which light is sampled and charge accumulates on each pixel’s integrating capacitor. The flexibility to adjust the integration period is a powerful and useful feature of the TAOS TSL14xx linear array family. By changing the integration time, a desired output voltage can be obtained on the output pin while avoiding saturation for a wide range of light levels. The integration time is the time between the SI (Start Integration) positive pulse and the HOLD positive pulse minus the 18 setup clocks. The TSL14xx linear array is normally configured with the SI and HOLD pins tied together. This configuration will be assumed unless otherwise noted. Sending a high pulse to SI (observing timing rules for setup and hold to clock edge) starts a new cycle of pixel output and integration setup. However, a minimum of (n+1) clocks, where n is the number of pixels, must occur before the next high pulse is applied to SI. It is not necessary to send SI immediately on/after the (n+1) clocks. A wait time adding up to a maximum total of 100 ms between SI pulses can be added to increase the integration time creating a higher output voltage in low light applications. Each pixel of the linear array consists of a light-sensitive photodiode. The photodiode converts light intensity to a voltage. The voltage is sampled on the Sampling Capacitor by closing switch S2 (position 1) (see the Functional Block Diagram on page 1). Logic controls the resetting of the Integrating Capacitor to zero by closing switch S1 (position 2). At SI input, all of the pixel voltages are simultaneously scanned and held by moving S2 to position 2 for all pixels. During this event, S2 for pixel 1 is in position 3. This makes the voltage of pixel 1 available on the analog output. On the next clock, S2 for pixel 1 is put into position 2 and S2 for pixel 2 is put into position 3 so that the voltage of pixel 2 is available on the output. Following the SI pulse and the next 17 clocks after the SI pulse is applied, the S1 switch for all pixels remains in position 2 to reset (zero out) the integrating capacitor so that it is ready to begin the next integration cycle. On the rising edge of the 19th clock, the S1 switch for all the pixels is put into position 1 and all of the pixels begin a new integration cycle. The first 18 pixel voltages are output during the time the integrating capacitor is being reset. On the 19th clock following an SI pulse, pixels 1 through 18 have switch S2 in position 1 so that the sampling capacitor can begin storing charge. For the period from the 19th clock through the nth clock, S2 is put into position 3 to read the output voltage during the nth clock. On the next clock the previous pixel S2 switch is put into position 1 to start sampling the integrating capacitor voltage. For example, S2 for pixel 19 moves to position 1 on the 20th clock. On the n+1 clock, the S2 switch for the last (nth) pixel is put into position 1 and the output goes to a high-impedance state. If a SI was initiated on the n+1 clock, there would be no time for the sampling capacitor of pixel n to charge to the voltage level of the integrating capacitor. The minimum time needed to guarantee the sampling capacitor for pixel n will charge to the voltage level of the integrating capacitor is the charge transfer time of 20 μs. Therefore, after n+1 clocks, an extra 20 μs wait must occur before the next SI pulse to start a new integration and output cycle. The minimum integration time for any given array is determined by time required to clock out all the pixels in the array and the time to discharge the pixels. The time required to discharge the pixels is a constant. Therefore, the minimum integration period is simply a function of the clock frequency and the number of pixels in the array. A slower clock speed increases the minimum integration time and reduces the maximum light level for saturation on the output. The minimum integration time shown in this data sheet is based on the maximum clock frequency of 8 MHz. Copyright E 2007, TAOS Inc. 8 The LUMENOLOGY r Company r www.taosinc.com r TSL1410R 1280 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS043E − APRIL 2007 APPLICATION INFORMATION The minimum integration time can be calculated from the equation: T int(min) + 1 ǒmaximum clock Ǔ frequency (n * 18)pixels ) 20ms where: n is the number of pixels In the case of the TSL1410R with the maximum clock frequency of 8 MHz, the minimum integration time would be: T int(min) + 0.125 ms (640 * 18) ) 20 ms + 97.75 ms It is good practice on initial power up to run the clock (n+1) times after the first SI pulse to clock out indeterminate data from power up. After that, the SI pulse is valid from the time following (n+1) clocks. The output will go into a high-impedance state after the n+1 high clock edge. It is good practice to leave the clock in a low state when inactive because the SI pulse required to start a new cycle is a low-to-high transition. The integration time chosen is valid as long as it falls in the range between the minimum and maximum limits for integration time. If the amount of light incident on the array during a given integration period produces a saturated output (Max Voltage output), then the data is not accurate. If this occurs, the integration period should be reduced until the analog output voltage for each pixel falls below the saturation level. The goal of reducing the period of time the light sampling window is active is to lower the output voltage level to prevent saturation. However, the integration time must still be greater than or equal to the minimum integration period. If the light intensity produces an output below desired signal levels, the output voltage level can be increased by increasing the integration period provided that the maximum integration time is not exceeded. The maximum integration time is limited by the length of time the integrating capacitors on the pixels can hold their accumulated charge. The maximum integration time should not exceed 100 ms for accurate measurements. It should be noted that the data from the light sampled during one integration period is made available on the analog output during the next integration period and is clocked out sequentially at a rate of one pixel per clock period. In other words, at any given time, two groups of data are being handled by the linear array: the previous measured light data is clocked out as the next light sample is being integrated. Although the linear array is capable of running over a wide range of operating frequencies up to a maximum of 8 MHz, the speed of the A/D converter used in the application is likely to be the limiter for the maximum clock frequency. The voltage output is available for the whole period of the clock, so the setup and hold times required for the analog-to-digital conversion must be less than the clock period. The LUMENOLOGY r Company Copyright E 2007, TAOS Inc. r www.taosinc.com r 9 TSL1410R 1280 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS043E − APRIL 2007 MECHANICAL INFORMATION TOP VIEW 1.180 (29,97) 1.170 (29,72) 0.100 (2,54) x 12 = 1.2 (30,48) (Tolerance Noncumulative) 0.175 (4,24) 0.165 (4,19) To Pixel 1 0.021 (0,533) DIA 13 Places 0.095 (2,21) 0.080 (2,03) 0.100 (2,54) BSC 1 0.510 (12,95) 0.490 (12,45) 13 0.242 (6,15) 0.222 (5,64) 0.091 (2,31) 0.087 (2,21) DIA (2 Places) Centerline of Pixels is on the Centerline of Mounting Holes DETAIL A 3.548 (90,120) 3.528 (89,611) 0.228 (5,79) 0.208 (5,28) 0.086 (2,184) 0.076 (1,930) 3.705 (94,11) 3.695 (93,85) 0.130 (3,30) 0.120 (3,05) Cover Glass (Index of Refraction = 1.52) 0.015 (0,38) Typical Free Area ÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈÈ 0.027 (0,690) Linear Array 0.048 (1,22) 0.038 (0,97) ÌÌÌÌÌÌ ÌÌÌÌÌÌ Cover Glass Bonded Chip Bypass Cap DETAIL A NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). Pixel centers are in line with center line of mounting holes. The gap between the individual sensor dies in the array is 57 μm typical (51 μm minimum and 75 μm maximum). This drawing is subject to change without notice. Figure 10. TSL1410R Mechanical Specifications Copyright E 2007, TAOS Inc. 10 The LUMENOLOGY r Company r www.taosinc.com r TSL1410R 1280 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS043E − APRIL 2007 MECHANICAL INFORMATION THEORETICAL PIXEL LAYOUT FOR IDEAL CONTINUOUS DIE 8.00 63.50 55.50 N−2 N−1 N 1 2 3 ACTUAL MULTI-DIE PIXEL LAYOUT FOR DIE-TO-DIE EDGE JOINING N−2 N−1 95.50 76.50 64.00 Note B N 1 2 3 46.00 154.50 37.00 11.00 25.50 14.50 13.00 Note C NOTES: A. B. C. D. All linear dimensions are in micrometers. Spacing between outside pixels of adjacent die is typical. Die-to-die spacing. This drawing is subject to change without notice. Figure 11. Edge Pixel Layout Dimensions The LUMENOLOGY r Company Copyright E 2007, TAOS Inc. r www.taosinc.com r 11 TSL1410R 1280 × 1 LINEAR SENSOR ARRAY WITH HOLD TAOS043E − APRIL 2007 PRODUCTION DATA — information in this document is current at publication date. Products conform to specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard warranty. Production processing does not necessarily include testing of all parameters. NOTICE Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems. TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER’S RISK. LUMENOLOGY, TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are registered trademarks of Texas Advanced Optoelectronic Solutions Incorporated. Copyright E 2007, TAOS Inc. 12 The LUMENOLOGY r Company r www.taosinc.com r