PSMN1R6-40YLC:115

PSMN1R6-40YLC N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology 22 August 2012 Product data sheet 1. Product profile 1.1 General description Logic level enhancement mode N-channel MOSFET in LFPAK package. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 1.2 Features and benefits • High reliability Power SO8 package, qualified to 150°C • Optimised for 4.5V Gate drive utilising NextPower Superjunction technology • Ultra low QG, QGD, & QOSS for high system efficiencies at low and high loads • Ultra low Rdson and low parasitic inductance 1.3 Applications • DC-to-DC converters • Load switching • Power OR-ing • Server power supplies • Sync rectifier 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 150 °C - - 40 V ID drain current Tmb = 25 °C; VGS = 10 V; Fig. 1 - - 100 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - - 288 W Tj junction temperature -55 - 150 °C - 1.45 1.8 mΩ - 1.25 1.55 mΩ - 15.3 - nC [1] Static characteristics RDSon drain-source on-state resistance VGS = 4.5 V; ID = 25 A; Tj = 25 °C; Fig. 12 VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 12 Dynamic characteristics QGD gate-drain charge VGS = 4.5 V; ID = 25 A; VDS = 20 V; Fig. 14 PSMN1R6-40YLC Nexperia N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology Symbol Parameter Conditions Min Typ Max Unit QG(tot) total gate charge VGS = 4.5 V; ID = 25 A; VDS = 20 V; - 59 - nC Fig. 14 [1] Continuous current is limited by package. 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D G mbb076 1 2 3 S 4 LFPAK; PowerSO8 (SOT1023) 3. Ordering information Table 3. Ordering information Type number Package PSMN1R6-40YLC Name Description Version LFPAK; Power-SO8 Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT1023 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage 25 °C ≤ Tj ≤ 150 °C - 40 V VDGR drain-gate voltage 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ - 40 V VGS gate-source voltage -20 20 V ID drain current VGS = 10 V; Tmb = 25 °C; Fig. 1 [1] - 100 A VGS = 10 V; Tmb = 100 °C; Fig. 1 [1] - 100 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 4 - 1304 A Ptot total power dissipation Tmb = 25 °C; Fig. 2 - 288 W Tstg storage temperature -55 150 °C PSMN1R6-40YLC Product data sheet All information provided in this document is subject to legal disclaimers. 22 August 2012 © Nexperia B.V. 2017. All rights reserved 2 / 14 PSMN1R6-40YLC Nexperia N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology Symbol Parameter Tj Conditions Min Max Unit junction temperature -55 150 °C Tsld(M) peak soldering temperature - 260 °C VESD electrostatic discharge voltage 1 - kV - 100 A MM (JEDEC JESD22-A115) Source-drain diode IS source current Tmb = 25 °C ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 1304 A VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; - 391 mJ [1] Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy Vsup ≤ 40 V; RGS = 50 Ω; unclamped; Fig. 3 [1] Continuous current is limited by package. 003aag974 400 ID (A) 003aab937 120 Pder (%) 300 80 200 100 0 40 (1) 0 50 100 150 Tmb 0 200 0 50 100 150 (°C) Fig. 1. Continuous drain current as a function of mounting base temperature PSMN1R6-40YLC Product data sheet Fig. 2. 200 Normalized total power dissipation as a function of solder point temperature All information provided in this document is subject to legal disclaimers. 22 August 2012 Tmb (°C) © Nexperia B.V. 2017. All rights reserved 3 / 14 PSMN1R6-40YLC Nexperia N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology 003aag975 103 IAL (A) 102 (1) 10 (2) 1 10-3 Fig. 3. 10-2 10-1 1 tAL (ms) 10 Single pulse avalanche rating; avalanche current as a function of avalanche time 003aag976 104 ID (A) 103 Limit RDSon = VDS / ID tp =10 µ s 10 2 100 µ s 10 1 ms DC 10 ms 100 ms 1 10-1 10-1 Fig. 4. 1 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base Fig. 5 - 0.35 0.43 K/W PSMN1R6-40YLC Product data sheet All information provided in this document is subject to legal disclaimers. 22 August 2012 © Nexperia B.V. 2017. All rights reserved 4 / 14 PSMN1R6-40YLC Nexperia N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology 003aag977 1 Z th(j-mb) (K/W) δ = 0.5 10-1 0.2 0.1 0.05 10 -2 P 0.02 single shot 10 tp -3 Fig. 5. 10-6 10-5 10-4 10-3 10-2 tp T δ= t T 10-1 1 tp (s) Transient thermal impedance from junction to mounting base as a function of pulse duration 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 40 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 36 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; 1.05 1.46 1.95 V ID = 10 mA; VDS = VGS; Tj = 150 °C 0.5 - - V ID = 1 mA; VDS = VGS; Tj = -55 °C - - 2.25 V VDS = 40 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 40 V; VGS = 0 V; Tj = 150 °C - - 100 µA VGS = 16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 4.5 V; ID = 25 A; Tj = 25 °C; - 1.45 1.8 mΩ - - 3.2 mΩ - 1.25 1.55 mΩ - - 2.7 mΩ - 1.17 2.34 Ω Static characteristics V(BR)DSS VGS(th) IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance Fig. 10; Fig. 11 Fig. 12 VGS = 4.5 V; ID = 25 A; Tj = 150 °C; Fig. 12; Fig. 13 VGS = 10 V; ID = 25 A; Tj = 25 °C; Fig. 12 VGS = 10 V; ID = 25 A; Tj = 150 °C; Fig. 12; Fig. 13 RG gate resistance PSMN1R6-40YLC Product data sheet f = 1 MHz All information provided in this document is subject to legal disclaimers. 22 August 2012 © Nexperia B.V. 2017. All rights reserved 5 / 14 PSMN1R6-40YLC Nexperia N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology Symbol Parameter Conditions Min Typ Max Unit ID = 25 A; VDS = 20 V; VGS = 10 V; - 126 - nC - 59 - nC ID = 0 A; VDS = 0 V; VGS = 10 V - 115 - nC gate-source charge ID = 25 A; VDS = 20 V; VGS = 4.5 V; - 17.7 - nC QGS(th) pre-threshold gatesource charge Fig. 14 - 12.5 - nC QGS(th-pl) post-threshold gatesource charge - 5.2 - nC QGD gate-drain charge - 15.3 - nC VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 20 V; Fig. 14 - 2.4 - V Ciss input capacitance VDS = 20 V; VGS = 0 V; f = 1 MHz; - 7790 - pF Coss output capacitance Tj = 25 °C; Fig. 16 - 1063 - pF Crss reverse transfer capacitance - 409 - pF td(on) turn-on delay time VDS = 20 V; RL = 0.8 Ω; VGS = 4.5 V; - 41 - ns tr rise time RG(ext) = 4.7 Ω - 48 - ns td(off) turn-off delay time - 86 - ns tf fall time - 42 - ns Qoss output charge - 38.7 - nC Dynamic characteristics QG(tot) total gate charge Fig. 14; Fig. 15 ID = 25 A; VDS = 20 V; VGS = 4.5 V; Fig. 14 QGS VGS = 0 V; VDS = 20 V; f = 1 MHz; Tj = 25 °C Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; Fig. 17 - 0.77 1.1 V trr reverse recovery time IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; - 44 - ns - 62 - nC - 26 - ns - 18 - ns VDS = 20 V; Fig. 18 Qr recovered charge IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 20 V ta reverse recovery rise time tb reverse recovery fall time PSMN1R6-40YLC Product data sheet VGS = 0 V; IS = 25 A; dIS/dt = -100 A/µs; VDS = 20 V; Fig. 18 All information provided in this document is subject to legal disclaimers. 22 August 2012 © Nexperia B.V. 2017. All rights reserved 6 / 14 PSMN1R6-40YLC Nexperia N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology 003aag978 100 4.5 10 ID (A) 3 003aag979 10 2.8 RDSon (mΩ) 2.6 80 8 2.4 60 6 40 4 20 2 VGS (V) = 2.2 0 Fig. 6. 0 0.25 0.5 0.75 VDS(V) 0 1 Output characteristics; drain current as a Fig. 7. function of drain-source voltage; typical values 003aag980 360 gfs (S) 300 0 4 8 12 VGS (V) 16 Drain-source on-state resistance as a function of gate-source voltage; typical values 003aag981 100 ID (A) 80 240 60 180 40 120 20 60 Tj = 150 °C Tj = 25 °C 0 Fig. 8. 0 20 40 60 80 ID (A) 0 100 Forward transconductance as a function of drain current; typical values PSMN1R6-40YLC Product data sheet Fig. 9. 0 2 3 VGS (V) 4 Transfer characteristics; drain current as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. 22 August 2012 1 © Nexperia B.V. 2017. All rights reserved 7 / 14 PSMN1R6-40YLC Nexperia N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology 003aag982 10-1 ID (A) 003aag983 3 VGS(th) (V) 10-2 Min 10-3 Typ Max (1mA) ID = 5mA 2 Max 1mA 10-4 1 Min (5mA) 10-5 10-6 0 1 2 0 -60 3 V GS (V) Fig. 10. Sub-threshold drain current as a function of gate-source voltage 120 Tj (°C) 180 003aag985 2 VGS (V) = 2.4 RDSon (mΩ) 60 Fig. 11. Gate-source threshold voltage as a function of junction temperature 003aag984 5 0 a 4 1.5 2.6 3 1 2.8 2 1 10 0.5 3 3.5 4.5 10 30 50 70 90 ID (A) 0 -60 110 Fig. 12. Drain-source on-state resistance as a function of drain current; typical values PSMN1R6-40YLC Product data sheet 0 60 120 Tj (°C) 180 Fig. 13. Normalized drain-source on-state resistance factor as a function of junction temperature All information provided in this document is subject to legal disclaimers. 22 August 2012 © Nexperia B.V. 2017. All rights reserved 8 / 14 PSMN1R6-40YLC Nexperia N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology 003aag986 10 VDS VGS (V) ID 8 VGS(pl) 6 8V 32 V 4 VGS(th) VGS V DS = 20 V QGS1 QGS2 QGS 2 QGD QG(tot) 003aaa508 0 0 30 60 120 QG 150 (nC) 90 Fig. 15. Gate charge waveform definitions Fig. 14. Gate-source voltage as a function of gate charge; typical values 003aag987 104 Ciss C (pF) 003aag988 100 IS (A) 80 60 10 Coss 3 40 C rss 20 Tj = 150°C Tj = 25 °C 102 10-1 1 10 VDS (V) 0 102 0 0.3 0.6 0.9 VSD(V) 1.2 Fig. 16. Input, output and reverse transfer capacitances Fig. 17. Source current as a function of source-drain as a function of drain-source voltage; typical voltage; typical values values PSMN1R6-40YLC Product data sheet All information provided in this document is subject to legal disclaimers. 22 August 2012 © Nexperia B.V. 2017. All rights reserved 9 / 14 PSMN1R6-40YLC Nexperia N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology 003a a f 444 ID (A) trr ta tb 0 0.25 IR M IRM t (s ) Fig. 18. Reverse recovery timing definition PSMN1R6-40YLC Product data sheet All information provided in this document is subject to legal disclaimers. 22 August 2012 © Nexperia B.V. 2017. All rights reserved 10 / 14 PSMN1R6-40YLC Nexperia N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology 7. Package outline Plastic single-ended surface-mounted package (LFPAK); 4 leads A E SOT1023 E1 A b1 b2 (3x) c1 mounting base H D1 D L 1 2 3 4 b e A1 w A X c C θ Lp detail X 0 2.5 mm 5 mm scale Dimensions Unit y C A A1 b b1 b2 c c1 D(1) D1(1) E(1) E1(1) max 1.10 0.15 0.50 4.41 0.25 0.30 4.70 4.45 5.30 nom 0.85 min 0.95 0.00 0.35 3.62 0.19 0.24 4.45 4.95 3.7 3.5 e 1.27 H L Lp 6.2 1.3 0.85 5.9 0.8 0.40 w y 0.25 0.1 θ 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm per side are not included. Outline version sot1023_po References IEC JEDEC JEITA European projection Issue date 09-05-26 11-12-09 SOT1023 Fig. 19. Package outline LFPAK; Power-SO8 (SOT1023) PSMN1R6-40YLC Product data sheet All information provided in this document is subject to legal disclaimers. 22 August 2012 © Nexperia B.V. 2017. All rights reserved 11 / 14 PSMN1R6-40YLC Nexperia N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 8. 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Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 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All rights reserved 12 / 14 PSMN1R6-40YLC Nexperia N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. 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The English version shall prevail in case of any discrepancy between the translated and English versions. 8.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. PSMN1R6-40YLC Product data sheet All information provided in this document is subject to legal disclaimers. 22 August 2012 © Nexperia B.V. 2017. All rights reserved 13 / 14 PSMN1R6-40YLC Nexperia N-channel 40 V 1.55 mΩ logic level MOSFET in LFPAK using NextPower technology 9. Contents 1 1.1 1.2 1.3 1.4 Product profile ....................................................... 1 General description .............................................. 1 Features and benefits ...........................................1 Applications .......................................................... 1 Quick reference data ............................................ 1 2 Pinning information ............................................... 2 3 Ordering information ............................................. 2 4 Limiting values .......................................................2 5 Thermal characteristics .........................................4 6 Characteristics ....................................................... 5 7 Package outline ................................................... 11 8 8.1 8.2 8.3 8.4 Legal information .................................................12 Data sheet status ............................................... 12 Definitions ...........................................................12 Disclaimers .........................................................12 Trademarks ........................................................ 13 © Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 22 August 2012 PSMN1R6-40YLC Product data sheet All information provided in this document is subject to legal disclaimers. 22 August 2012 © Nexperia B.V. 2017. All rights reserved 14 / 14