WD2RE01GX809-667G-PQ

DDR2-400, 533,667,800 One Rank, x8 Registered SDRAM DIMM Pb-free 512MB - WD2RE512X809 1GB - WD2RE01GX809 2GB - WD2RE02GX809 Features:              Figure 1: Available profiles 240-pin Registered ECC DDR2 SDRAM Dual-In-Line Memory Module for DDR2-400,533,667 and 800. JEDEC standard VDD=1.8V (+/- 0.1V) power supply One rank 512MB, 1GB, and 2GB Modules are built with 9 x8 DDR2 SDRAM devices in a FBGA 60-ball Pb-Free package ECC error detection and correction Programmable CAS Latency of 3,4,5 and 6; Burst Length of 4 and 8 Auto Refresh and Self Refresh Mode OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) SPD (Serial Presence Detect) with EEPROM All input/output are SSTL_18 compatible All contacts are gold plated One clock delay for register ROHS compliant Standard: 1.181" Description: The following specification covers the family of One-Rank Registered ECC DDR2 modules using x8 FBGA SDRAMs. Please reference Figure 1 for available profiles and the product ordering guide for available options including speed grade and silicon manufacturer. Speed Grades: Speed Grade -400C -533E -667G -800G -800I Data Rate (MHz) CL3 CL4 CL5 CL6 400 400 533 667 800 800 Clock/Data Rate Latency Module Speed 5.0ns/400MHz 3.75ns/533MHz 3ns/667MHz 2.5ns/800MHz 2.5ns/800MHz 3-3-3 4-4-4 5-5-5 5-5-5 6-6-6 PC2-3200 PC2-4200 PC2-5300 PC2-6400 PC2-6400 Address Summary Table: Module Configuration Refresh Device Configuration Row Addressing Column Addressing Bank Address Module Rank 512MB 64M x 72 8K 64M x 8 (9 components) A0-A13(16K) A0-A9 (1K) BA0-BA2 1 1GB 128M x 72 8K 128M x 8 (9 components) A0-A13(16K) A0-A9 (1K) BA0-BA2 1 2GB 256M x 72 8K 256M x 8 (9 components) A0-A14 (32K) A0-A9 (1K) BA0-BA2 1 *Specifications are for reference purposes only and are subject to change by Wintec without notice. Green Rev. 1.5 – Mar.’14 Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.  2014Wintec Industries, Inc. 1 DDR2-400, 533,667,800 One Rank, x8 Registered SDRAM DIMM Pb-free Pin Configuration: Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS RESET# NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 Pin Symbol 31 DQ19 32 VSS 33 DQ24 34 DQ25 35 VSS 36 DQS3# 37 DQS3 38 VSS 39 DQ26 40 DQ27 41 VSS 42 CB0 43 CB1 44 VSS 45 DQS8# 46 DQS8 47 VSS 48 CB2 49 CB3 50 VSS 51 VDDQ 52 CKE0 53 VDD 54 BA2 55 ERR_OUT 56 VDDQ 57 A11 58 A7 59 VDD 60 A5 Pin Symbol 61 A4 62 VDDQ 63 A2 64 VDD KEY 65 VSS 66 VSS 67 VDD 68 PAR_IN 69 VDD 70 A10/AP 71 BA0 72 VDDQ 73 WE# 74 CAS# 75 VDDQ 76 NC/S1# 77 ODT1 78 VDDQ 79 VSS 80 DQ32 81 DQ33 82 VSS 83 DQS4# 84 DQS4 85 VSS 86 DQ34 87 DQ35 88 VSS 89 DQ40 90 DQ41 Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin 91 VSS 121 VSS 151 VSS 181 VDDQ 211 92 DQS5# 122 DQ4 152 DQ28 182 A3 212 93 DQS5 123 DQ5 153 DQ29 183 A1 213 94 VSS 124 VSS 154 VSS 184 VDD 214 95 DQ42 125 DM0/DQS9 155 DM3/DQS12 KEY 215 96 DQ43 126 NC/DQS9# 156 NC/DQS12# 185 CK0 216 97 VSS 127 VSS 157 VSS 186 CK0# 217 98 DQ48 128 DQ6 158 DQ30 187 VDD 218 99 DQ49 129 DQ7 159 DQ31 188 A0 219 100 VSS 130 VSS 160 VSS 189 VDD 220 101 SA2 131 DQ12 161 CB4 190 BA1 221 102 NC,TEST1 132 DQ13 162 CB5 191 VDDQ 222 103 VSS 133 VSS 163 VSS 192 RAS# 223 104 DQS6# 134 DM1/DQS10 164 DM8/DQS17 193 S0# 224 105 DQS6 135 NC/DQS10# 165 NC/DQS17# 194 VDDQ 225 106 VSS 136 VSS 166 VSS 195 ODT0 226 107 DQ50 137 RFU 167 CB6 196 A13 227 108 DQ51 138 RFU 168 CB7 197 VDD 228 109 VSS 139 VSS 169 VSS 198 VSS 229 110 DQ56 140 DQ14 170 VDDQ 199 DQ36 230 111 DQ57 141 DQ15 171 NC/CKE1 200 DQ37 231 112 VSS 142 VSS 172 VDD 201 VSS 232 113 DQS7# 143 DQ20 173 NC/A15 202 DM4/DQS13 233 114 DQS7 144 DQ21 174 NC/A14 203 NC/DQS13# 234 115 VSS 145 VSS 175 VDDQ 204 VSS 235 116 DQ58 146 DM2/DQS11 176 A12 205 DQ38 236 117 DQ59 147 NC/DQS11# 177 A9 206 DQ39 237 118 VSS 148 VSS 178 VDD 207 VSS 238 119 SDA 149 DQ22 179 A8 208 DQ44 239 120 SCL 150 DQ23 180 A6 209 DQ45 240 210 VSS Symbol DM5/DQS14 NC/DQS14# VSS DQ46 DQ47 VSS DQ52 DQ53 VSS RFU RFU VSS DM6/DQS15 NC/DQS15# VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7/DQS16 NC/DQS16# VSS DQ62 DQ63 VSS VDDSPD SA0 SA1 NC - No Connect, RFU - Reserved for Future Use 1. The Test pin (Pin 102) is reserved for bus analysis and is not connected on normal memory modules 2. CKE1 and S1# pin are used for dual-rank Registered DIMM 3. A13 (Pin 196) is for 512MB and above DIMM. Pin Locations: Front View 64 Pin 1 Pin 240 65 184 185 120 121 Back View 240-pin DIMM Green Rev. 1.5 – Mar.’14 Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.  2014Wintec Industries, Inc. 2 DDR2-400, 533,667,800 One Rank, x8 Registered SDRAM DIMM Pb-free Functional Block Diagram: One Rank 64M x 72 (512MB), 128M x 72 (1GB), and 256M x 72 (2GB) DDR2 Registered SDRAM DIMM (x8 organization) RCS0# DQS4 DQS4# DM4/DQS13 DQS0 DQS0# DM0/DQS9 DQS9# NU/ DM/ CS# DQS# DQS RDQS# RDQS U0 DQ[0:7] 8 DQS5 DQS5# DM5/DQS14 NU/ DM/ CS# DQS# DQS RDQS# RDQS U5 DQ[40:47] 8 DQS6 DQS6# DM6/DQS15 8 DQS2 DQS2# DM2/DQS11 NU/ DM/ CS# DQS# DQS RDQS# RDQS U6 DQ[48:55] 8 DQS7 DQS7# DM7/DQS16 8 DQS3 DQS3# DM3/DQS12 NU/ DM/ CS# DQS# DQS RDQS# RDQS DQS16# U3 DQ[24:31] 8 VDDSPD NU/ DM/ CS# DQS# DQS RDQS# RDQS To SPD To U0 - U8 To U0 - U8 To U0 - U8 VDD/VDDQ VREF Vss U8 CB[0:7] NU/ DM/ CS# DQS# DQS RDQS# RDQS U7 DQ[56:63] 8 DQS8 DQS8# DM8/DQS17 DQS17# NU/ DM/ CS# DQS# DQS RDQS# RDQS DQS15# U2 DQ[16:23] DQS12# NU/ DM/ CS# DQS# DQS RDQS# RDQS DQS14# U1 DQ[8:15] DQS11# U4 DQ[32:39] 8 DQS1 DQS1# DM1/DQS10 DQS10# NU/ DM/ CS# DQS# DQS RDQS# RDQS DQS13# 8 SERIAL PD SCL PAR_IN BA0-BA2 A0-A13 RAS# CAS# WE# CKE0 ODT0 CS0#* RESET# ERR_OUT R E G I S T E R RBA0-RBA2 -> BA0-BA2 to U0 - U8 RA0-RA13 -> A0-A13 to U0 - U8 RRAS# -> RAS# to U0 - U8 RCAS# -> CAS# to U0 - U8 RWE# -> WE# to U0 - U8 RCKE0 -> CKE0 to U0 - U8 RODT0 -> ODT0 to U0 - U8 RS0# -> CS0# to U0 - U8 CK0 CK0# RESET# SDA A0 A1 A2 SA0 SA1 SA2 P L L CK to U0 - U8 CK# to U0 - U8 CK to all registers CK# to all registers Note: 1. *) CS0# connects to DCS# of Register 1 and CSR# of Register 2; CSR# of Register 1 and DCS# of Register 2 connects to VDD 2. DQ/DM/DQS, address and control resistor values are 22 Ohms. Green Rev. 1.5 – Mar.’14 Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.  2014Wintec Industries, Inc. 3 DDR2-400, 533,667,800 One Rank, x8 Registered SDRAM DIMM Pb-free Absolute Maximum Ratings: Exposure to stresses greater than these absolute maximum rating conditions for extended periods may affect reliability of the module. Symbol VDD VDDQ VDDL VIN, VOUT TSTG TOPR TCASE IIL IOL Parameter VDD supply voltage relative to VSS VDDQ supply voltage relative to VSS VDDL supply voltage relative to VSS Voltage on any pin relative to VSS Storage temperature Operating Temperature (Ambient) DRAM Component Case Temperature Input Leakage Current; Any input 0V  VIN  0.95V Output Leakage Current; 0V  VOUT  VDDQ; DQS and ODT are disabled Min Max Units -1.0 -0.5 -0.5 -0.5 -55 0 0 -5 -5 2.3 2.3 2.3 2.3 +100 +70 +95 5 5 V V V V C C C A A DC Operating Conditions: Parameter Supply Voltage VDDL Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Symbol Min Nom Max VDD VDDL VDDQ VREF VTT 1.7 1.7 1.7 0.49 x VDDQ VREF - 40 1.8 1.8 1.8 0.50 x VDDQ VREF 1.9 1.9 1.9 0.51 x VDDQ VREF + 40 Units Notes V V V V mV 1 4 4 2 3 NOTE: 1. VDD and VDDQ must keep track of each other. VDDQ cannot exceed the value of VDD 2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same 3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF 4. VDDQ must tracks VDD; and VDDL tracks VDD Green Rev. 1.5 – Mar.’14 Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.  2014Wintec Industries, Inc. 4 DDR2-400, 533,667,800 One Rank, x8 Registered SDRAM DIMM Pb-free Electrical Characteristics and AC Timings: VDD = +1.8V ± 0.1V, VDDQ = +1.8V ± 0.1V, VREF = VSS, f =100MHz, 0°C≤TCASE ≤+85°C, VOUT (DC) = VDDQ/2 -5 DDR2-400 MIN MAX -600 +600 -3.75 DDR2-533 MIN MAX -500 +500 -3 DDR2-667 MIN MAX -450 +450 -2.5 DDR2-800 MIN MAX -400 +400 ps DQS output access time from CK/ CK tDQSCK -500 +500 -450 +450 -400 +400 -350 +350 ps CK high-level width CK low-level width tCH tCL 0.55 0.55 - 0.48 0.48 0.52 0.52 - tCK tCK ps CL=3 CL=4 tCK CL=5 CL=6 tDH tDS tIPW 8,000 8,000 - 8,000 8,000 - 0.48 0.48 MIN (tCH, tCL) 5,000 3,750 3,000 175 100 0.6 0.52 0.52 - tHP 0.45 0.45 MIN (tCH, tCL) 5,000 3,750 225 100 0.6 0.55 0.55 - CK half period 0.45 0.45 MIN (tCH, tCL) 5,000 5,000 275 150 0.6 8,000 8,000 8,000 - 5,000 3,750 2,500 2,500 125 50 0.6 8,000 8,000 8,000 8,000 - ps ps ps ps ps ps tCK tDIPW 0.35 - 0.35 - 0.35 - 0.35 - tCK tHZ - tACmax - tACmax - tACmax X tLZ tACmin tACmax tACmin tACmax tACmin tACmax tACmin tACmax ps - 350 - 300 - 240 x 200 ps tHPtQHS WL-0.25 450 - tHPtQHS WL0.25 0.35 400 - - ps ps WL0.25 0.35 tHPtQHS WL-0.25 300 - WL+ 0.25 - 340 tHPtQHS WL+0. 25 - Parameter DQ output access time from CK/ CK Clock cycle time DQ and DM input hold time DQ and DM input setup time Control & Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK/ CK Data-out low-impedance time from CK/ CK DQS-DQ skew for DQS and associated DQ signals Data hold skew factor Data output hold time from DQS Symbol tAC tDQSQ tQHS tQH Write command to 1st DQS latching transition DQS input low/high pulse width tDQSS tDQSL/H 0.35 WL+ 0.25 - DQS falling edge to CK setup time tDSS 0.2 - 0.2 - 0.2 DQS falling edge hold time from CK tDSH 0.2 - 0.2 - 2 - 2 0 0.25 0.40 0.9 0.4 45 55 105 15 15 0.60 1.1 0.6 70,000 - 0 0.25 0.40 0.9 0.4 45 60 105 15 15 Mode register set command cycle time tMRD Write preamble setup time Write preamble Write postamble Read preamble Read postamble Active to Precharge command Active to Active command period Refresh to Refresh command interval Active to Read/Write delay Precharge command period Green Rev. 1.5 – Mar.’14 tWPRES tWPRE tWPST tRPRE tRPST tRAS tRC tRFC tRCD tRP min (tCH, tCL) ps tCK 0.35 WL+ 0.25 - - 0.2 - tCK 0.2 - 0.2 - tCK - 2 - 2 - tCK 0.60 1.1 0.6 70,000 - 0 0.35 0.4 0.9 0.4 45 60 105 15 - 0.6 1.1 0.6 70,000 15 0 0.35 0.40 0.9 0.4 45 57.5/60 0.60 1.1 0.6 70,000 - ps tCK tCK tCK tCK ns ns ns ns ns 105 - 12.5/15 12.5/15 - Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.  2014Wintec Industries, Inc. 5 Units tCK DDR2-400, 533,667,800 One Rank, x8 Registered SDRAM DIMM Pb-free VDD = +1.8V ± 0.1V, VDDQ = +1.8V ± 0.1V, VREF = VSS, f =100MHz, 0°C≤TCASE ≤+85°C, VOUT (DC) = VDDQ/2 Parameter Active bank A to Active bank B command CAS A to CAS B command period Write recovery time Auto Precharge write recovery + Precharge time Internal Write to Read command delay Internal Read to Precharge command delay Exit precharge power down to any nonRead command Exit Self-Refresh to Read command Exit Self-Refresh to non-Read command CKE minimum high and low pulse width Average periodic refresh interval OCD drive mode output delay CKE low to CK, CK uncertainty Symbol tRRD -5 DDR2-400 MIN MAX 7.5 - tCCD tWR tDAL 2 15 WR+tRP tWTR tRTP tXP tXSRD tXSNR -3.75 DDR2-533 MIN MAX 7.5 - - 2 15 - WR+tRP 10 7.5 - 2 - -3 DDR2-667 MIN MAX 7.5 - - 2 15 - - WR+tRP - 7.5 7.5 - 7.5 7.5 - 2 - 2 - 200 - 200 - 200 - tRFC+10 - tRFC+10 - tRFC+10 - tCKE 3 - 3 - 3 tREFI tOIT tDELAY 0 7.8 12 0 7.8 12 tIS+tCK +tIH - tIS+tCK +tIH - -2.5 DDR2-800 MIN MAX 7.5 2 15 WR+tR P 7.5 7.5 2 tCK ns tCK - ns ns - tCK - tCK ns - 200 tRFC + 10 3 - tCK 7.8 0 12 7.8 0 12 - tIS+tCK +tIH tIS+tCK +tIH - Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.  2014Wintec Industries, Inc. 6 ns - Note: These parameters are applicable for all 3 chip manufacturers, Micron, Hynix, and Samsung. Green Rev. 1.5 – Mar.’14 Units s ns ns DDR2-400, 533,667,800 One Rank, x8 Registered SDRAM DIMM Pb-free Physical Dimensions – Standard: 1.181" Height DDR2 Registered DIMM One physical rank, 9 components x8 organised 240 185 184 Pin 121 BACK 0.106/(2.7) Max 5.250/(133.35±0.15) 5.171/(131.35) Register 0.1575/(4.0) 1.181/(30.0) PLL 0.10/(2.54) 0.118/(3.0) Pin 1 0.25/(6.35) 2.55/(64.77) 64 0.039/ (1.0) 65 0.05/ (1.27) 1.95/(49.5) 5.014/(127.35) FRONT 120 0.050±0.004/ (1.27±0.1) SIDE Note: 1. Dimensions are in inches/(mm) 2. Outline dimensions and tolerances are in accordance with the JEDEC standard Green Rev. 1.5 – Mar.’14 Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.  2014Wintec Industries, Inc. 7 DDR2-400, 533,667,800 One Rank, x8 Registered SDRAM DIMM Pb-free Ordering Guide: DDR2-400, 533, 667, 800MHz, One-Rank x8, Registered ECC DIMM WD2RE512X809 WD2RE01GX809 WD2RE02GX809 x – yyyy(j) – ZZZ x: Profile Naming Guide: yyyy: Speed (Blank) = Std. (1.18") V = VLP. (0.72") 400C = DDR2-400@CL3 533E = DDR2-533@CL4 667G = DDR2-667@CL5 800G = DDR2-800@CL5 800I = DDR2-800@CL6 (Blank) ZZZ: DRAM/Die/Register = Std. C = Hynix A = A die E = E die P = Samsung B = B die F = F die H = Micron C = C die G = G die D = D die Q = Q die I = Inphi D = IDT (Call for additional DRAM options and latest die-revision) Configuration/Availability: Density PT # Profile Speed 400C, 533E, 667G, 800G/I 512MB WD2RE512X809 (Std), V 1-GB WD2RE01GX809 (Std), V 2-GB WD2RE02GX809 (Std), V - 400C, 533E, 667G, 800G/I 400C, 533E, 667G, 800G/I DRAM/Die - ZZZ Example: WD2RE01GX809-400C-QB 1GB DDR2-400 REG/ECC Infineon B-Die using 128Mx8 Config Contact Us: Wintec Industries OEM Group 675 Sycamore Drive Milpitas, CA 95035 Ph: 408-856-0663 Fax: 408-856-0518 oemsales@wintecind.com http://www.wintecind.com/oem Green Rev. 1.5 – Mar.’14 Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.  2014Wintec Industries, Inc. 8 DDR2-400, 533,667,800 One Rank, x8 Registered SDRAM DIMM Pb-free Revision History: Revision 1.0 (December 2004)  Initial Release Revision 1.1 (August 2005)  ROHS version  Added DRAM Case temperature TCASE Revision 1.2 (Sept 2007)  Added 800MHz speed grade Revision 1.3 (Jan 2010)  1GB row address mapping updated Revision 1.4 (Nov 2013)  Updated the Ordering Guide Revision 1.5 (Mar 2014)  Updated the Ordering Guide Green Rev. 1.5 – Mar.’14 Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.  2014Wintec Industries, Inc. 9