XM25QH32B
3V 32M-BIT
SERIAL NOR FLASH WITH
DUAL AND QUAD SPI&QPI
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. M Issue Date: 2018/07/17
XM25QH32B
Contents
FEATURES ............................................................................................................................................................... 3
GENERAL DESCRIPTION ...................................................................................................................................... 4
1. ORDERING INFORMATION ...................................................................................................................... 5
2. BLOCK DIAGRAM...................................................................................................................................... 6
3. CONNECTION DIAGRAMS ....................................................................................................................... 7
4. SIGNAL DESCRIPTIONS ............................................................................................................................ 8
4.1. Serial Data Input (DI) / IO0 ................................................................................................................ 8
4.2. Serial Data Output (DO) / IO1 ............................................................................................................ 8
4.3. Serial Clock (CLK) ............................................................................................................................. 8
4.4. Chip Select (CS#) ............................................................................................................................... 8
4.5. Write Protect (WP#) / IO2 .................................................................................................................. 9
4.6. HOLD (HOLD#) / IO3 ....................................................................................................................... 9
4.7. RESET (RESET#) / IO3 ..................................................................................................................... 9
5. MEMORY ORGANIZATION ..................................................................................................................... 10
5.1. Flash Memory Array ......................................................................................................................... 10
5.2. Security Registers ............................................................................................................................. 10
5.2.1 Security Register 0 ...................................................................................................................11
5.2.2 Serial Flash Discoverable Parameters (SFDP) Address Map ..................................................11
5.2.3 SFDP Header Field Definitions .............................................................................................. 12
5.2.4 JEDEC SFDP Basic SPI Flash Parameter ............................................................................... 13
6. FUNCTION DESCRIPTION ...................................................................................................................... 18
6.1 SPI Operations ................................................................................................................................... 18
6.1.1 SPI Modes ............................................................................................................................... 18
6.1.2 Dual SPI Modes ...................................................................................................................... 18
6.1.3 Quad SPI Modes ..................................................................................................................... 18
6.1.4 QPI Function ........................................................................................................................... 19
6.1.5 Hold Function ......................................................................................................................... 19
6.1.6 Software Reset & Hardware RESET# pin .............................................................................. 19
6.2. Status Register .................................................................................................................................. 20
6.2.1 BUSY...................................................................................................................................... 22
6.2.2 Write Enable Latch (WEL) ..................................................................................................... 22
6.2.3 Block Protect Bits (BP2, BP1, BP0) ....................................................................................... 22
6.2.4 Top / Bottom Block Protect (TB) ............................................................................................ 22
6.2.5 Sector / Block Protect (SEC) .................................................................................................. 22
6.2.6 Complement Protect (CMP) ................................................................................................... 23
6.2.7 The Status Register Protect (SRP1, SRP0) ............................................................................. 23
6.2.8 Erase / Program Suspend Status (SUS)................................................................................... 23
6.2.9 Security Register Lock Bits (LB3, LB2, LB1, LB0) .............................................................. 23
6.2.10 Quad Enable (QE)................................................................................................................. 24
6.2.11 HOLD# or RESET# Pin Function (HRSW) ......................................................................... 24
6.2.12 Output Driver Strength (DRV1, DRV0)................................................................................ 24
6.2.13 High Frequency Mode Enable Bit (HFM) ............................................................................ 24
6.2.14 Latency Control (LC)............................................................................................................ 24
6.3. Write Protection ................................................................................................................................ 25
6.3.1 Write Protect Features ............................................................................................................. 25
6.3.2 Block Protection Maps............................................................................................................ 27
6.4. Page Program .................................................................................................................................... 29
6.5. Sector Erase, Block Erase and Chip Erase........................................................................................ 29
6.6. Polling during a Write, Program or Erase Cycle ............................................................................... 29
6.7. Active Power, Stand-by Power and Deep Power-Down Modes ....................................................... 29
7. INSTRUCTIONS ........................................................................................................................................ 30
7.1 Configuration and Status Commands ................................................................................................ 35
7.1.1 Read Status Register (05h/35h/15h) ....................................................................................... 35
7.1.2 Write Enable (06h) .................................................................................................................. 35
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. M Issue Date: 2018/07/17
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XM25QH32B
7.1.3 Write Enable for Volatile Status Register (50h) ...................................................................... 36
7.1.4 Write Disable (04h) ................................................................................................................. 36
7.1.5 Write Status Register (01h/31h/11h) ....................................................................................... 36
7.2 Program and Erase Commands .......................................................................................................... 37
7.2.1 Page Program (PP) (02h) ........................................................................................................ 37
7.2.2 Quad Input Page Program (32h) ............................................................................................. 38
7.2.3 Sector Erase (SE) (20h) .......................................................................................................... 39
7.2.4 Block Erase (BE) (D8h) and Half Block Erase (52h) ............................................................. 39
7.2.5 Chip Erase (CE) (C7h or 60h) ................................................................................................ 40
7.2.6 Erase / Program Suspend (75h)............................................................................................... 41
7.2.7 Erase / Program Resume (7Ah) .............................................................................................. 41
7.3 Read Commands ................................................................................................................................ 42
7.3.1 Read Data (03h) ...................................................................................................................... 42
7.3.2 Fast Read (0Bh) ...................................................................................................................... 42
7.3.3 Fast Read Dual Output (3Bh) ................................................................................................. 43
7.3.4 Fast Read Quad Output (6Bh)................................................................................................. 44
7.3.5 Fast Read Dual I/O (BBh)....................................................................................................... 44
7.3.6 Fast Read Quad I/O (EBh) ...................................................................................................... 45
7.3.7 Word Read Quad I/O (E7h) .................................................................................................... 46
7.3.8 Octal Word Read Quad I/O (E3h) ........................................................................................... 47
7.3.9 Set Burst with Wrap (77h) ...................................................................................................... 48
7.4 Reset Commands ............................................................................................................................... 49
7.4.1 Software Reset Enable (66h) .................................................................................................. 50
7.4.2 Software Reset (99h) .............................................................................................................. 50
7.5 ID and Security Commands ............................................................................................................... 50
7.5.1 Deep Power-down (DP) (B9h)................................................................................................ 50
7.5.2 Release Power-down / Device ID (ABh) ................................................................................ 50
7.5.3 Read Manufacturer / Device ID (90h) .................................................................................... 51
7.5.4 Read Identification (RDID) (9Fh) .......................................................................................... 52
7.5.5 Read SFDP Register (5Ah) ..................................................................................................... 53
7.5.6 Erase Security Registers (44h) ................................................................................................ 53
7.5.7 Program Security Registers (42h) ........................................................................................... 54
7.5.8 Read Security Registers (48h) ................................................................................................ 54
7.5.9 Read Manufacturer / Device ID Dual I/O (92h) ..................................................................... 55
7.5.10 Read Unique ID Number (4Bh) ............................................................................................ 55
7.5.11 Set Read Parameters (C0h) ................................................................................................... 56
7.5.12 Burst Read with Wrap (0Ch)................................................................................................. 56
7.5.13 Enter QPI Mode (38h) .......................................................................................................... 57
7.5.14 Exit QPI Mode (FFh) ............................................................................................................ 57
8. ELECTRICAL CHARACTERISTIC .......................................................................................................... 58
8.1. Absolute Maximum Ratings ............................................................................................................. 59
8.2. Recommended Operating Ranges ..................................................................................................... 59
8.3. DC Characteristics ............................................................................................................................ 60
8.4. AC Measurement Conditions ............................................................................................................ 60
8.5. AC Electrical Characteristics ............................................................................................................ 61
9. PACKAGE MECHANICAL ....................................................................................................................... 63
9.1. SOP 208mil 8L ................................................................................................................................. 63
9.2. SOP 150mil 8L ................................................................................................................................. 63
9.3. WSON 5x6 8L .................................................................................................................................. 64
REVISION LIST ..................................................................................................................................................... 65
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. M Issue Date: 2018/07/17
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XM25QH32B
FEATURES
Low power supply operation
- Single 2.7V-3.6V supply
32 Mbit Serial Flash
- 32 M-bit/4M-byte/16,384 pages
- 256 bytes per programmable page
- Uniform 4K-byte Sectors, 32K/64K-byte Blocks
Package Options
- SOP 208mil 8L
- SOP 150mil 8L
- WSON 5x6 8L
- All Pb-free packages are RoHS compliant
New Family of SpiFlash Memories
- Standard SPI: CLK, CS#, DI, DO, WP#, HOLD#
/ RESET#
- Dual SPI: CLK, CS#, DI, DO, WP#, HOLD# /
RESET#
- Quad SPI: CLK, CS#, IO0, IO1, IO2, IO3
- QPI: CLK, CS#, IO0, IO1, IO2, IO3
- Software & Hardware Reset
- Auto-increment Read capability
Temperature Ranges
- Consumer (-20°C to +85°C)
- Industrial (-40°C to +85°C)
Low power consumption
- 9 mA typical active current
- 2 uA typical power down current
Efficient “Continuous Read” and QPI Mode
- Continuous Read with 8/16/32/64-Byte Wrap
- As few as 8 clocks to address memory
- Quad Peripheral Interface(QPI) reduces
instruction overhead
Flexible Architecture with 4KB sectors
- Sector Erase (4K-bytes)
- Block Erase (32K/64K-bytes)
- Page Program up to 256 bytes
- Typical 100K erase/program cycles
- More than 20-year data retention
Advanced Security Feature
- Software and Hardware Write-Protect
- Power Supply Lock-Down and OTP
protection
- Top/Bottom, Complement array protection
- 64-Bit Unique ID for each device
- Discoverable parameters(SFDP) register
- 3X256-Bytes Security Registers with OTP
locks
- Volatile & Non-volatile Status Register Bits
High performance program/erase speed
- Page program time: 500us typical
- Sector erase time: 50ms typical
- Block erase time: 300ms typical
- Chip erase time: 10 Seconds typical
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. M Issue Date: 2018/07/17
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XM25QH32B
GENERAL DESCRIPTION
The XM25QH32B of non-volatile flash memory device supports the standard Serial Peripheral Interface
(SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two
bit (Dual I/O or DIO) and four bit (quad I/O or QIO) serial protocols. This multiple width interface is called SPI
Multi-I/O or MIO.
The SPI protocols use only 4 to 6 signals:
Chip Select (CS#)
Serial Clock (CLK)
Serial Data
- IO0 (DI)
- IO1 (DO)
- IO2 (WP#)
- IO3 (HOLD# / RESET#)
The XM25QH32B support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as
2-clocks instruction cycle Quad Peripheral Interface (QPI): Serial Clock, Chip Select, Serial Data I/O0 (DI),
I/O1 (DO), I/O2 (WP#), and I/O3 (HOLD# / RESET#). SPI clock frequencies of up to 104MHz are supported
allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O
when using the Fast Read Dual/Quad I/O and QPI instructions. These transfer rates can outperform standard
Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory
access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in
place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide
further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID and
SFDP Register, a 64-bit Unique Serial Number and three 256-bytes Security Registers.
The XM25QH32B provides an ideal storage solution for systems with limited space, signal connections,
and power. These memories' flexibility and performance is better than ordinary serial flash devices. They are
ideal for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data.
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. M Issue Date: 2018/07/17
XM25QH32B
1. ORDERING INFORMATION
The ordering part number is formed by a valid combination of the following:
XM
25
QH
32
B X
X
X
X
-xx
[1]
SPECIAL OPTIONS
xx = for UID, start from
01 to distinguish
different UID request
Packing Type
T: Tape & Reel
R: Tray
Green Code
P: Pb free only green package
G: Pb free and halogen free
Temperature Range
I: Industrial (-40°C to +85°C)
E: Extended (-20°C to +85°C)
Package Type
H: SOP 208mil 8L
J: SOP 150mil 8L
W: WSON 5x6 8L
Version
A: A Version
B: B Version
C: C Version
Device Density
128: 128 Mbit 64: 64 Mbit
32: 32 Mbit
16: 16 Mbit
80: 8 Mbit
40: 4 Mbit
20: 2 Mbit
Series
QH: 3V, 4KB uniform-sector
Product Family
25: SPI Interface Flash
Wuhan Xinxin
Semiconductor
Figure 1.1 Ordering Information
Notes:
1、This option code is not included on the part marketing.
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. M Issue Date: 2018/07/17
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XM25QH32B
2. BLOCK DIAGRAM
Figure 2.1 Block Diagram
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XM25QH32B
3. CONNECTION DIAGRAMS
Figure 3.1 8-pin SOP (150/208mil)
Figure 3.2 8-Contact 5 x 6 mm WSON
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XM25QH32B
4. SIGNAL DESCRIPTIONS
Table 4.1 Pin Descriptions
Symbol
Pin Name
CLK
Serial Clock Input
DI(IO0)
Serial Data Input(Data input output 0) (1)
DO(IO1)
Serial Data Output(Data input output 1) (1)
CS#
Chip Enable
WP#(IO2)(3)
Write Protect (Data input output 2) (2)
HOLD# / RESET#(3)(IO3)
Hold or Reset input(Data input output 3) (2)
VCC
Power Supply (2.7-3.6V)
GND
Ground
Notes:
(1) IO0 and IO1 are used for Standard and Dual SPI instructions.
(2) IO0—IO3 are used for QUAD SPI / QPI instructions.
(3) WP# and HOLD# / RESET# functions are only available for Standard and Dual SPI.
4.1. Serial Data Input (DI) / IO0
The SPI Serial Data Input (DI) pin is used to transfer data serially into the device. It receives instructions,
address and data to be programmed. Data is latched on the rising edge of the Serial Clock (CLK) input pin.
The DI pin becomes IO0 - an input and output during Dual and Quad commands for receiving instructions,
address, and data to be programmed (values latched on rising edge of serial CLK clock signal) as well as
shifting out data (on the falling edge of CLK).
4.2. Serial Data Output (DO) / IO1
The SPI Serial Data Output (DO) pin is used to transfer data serially out of the device. Data is shifted out
on the falling edge of the Serial Clock (CLK) input pin. DO becomes IO1 - an input and output during Dual and
Quad commands for receiving instructions, addresses, and data to be programmed (values latched on rising
edge of serial CLK clock signal) as well as shifting out data (on the falling edge of CLK).
4.3. Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Mode")
4.4. Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output pins are at high impedance.
When deselected, the devices power consumption will be at standby levels unless an internal erase,
program or status register cycle is in progress. When CS# is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, CS# must transition from high to low before a new instruction will be accepted.
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XM25QH32B
4.5. Write Protect (WP#) / IO2
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1 and BP2, TB, SEC, CMP) bits and Status
Register Protect (SRP0) bits, a portion or the entire memory array can be hardware protected.
The WP# function is not available when the Quad mode is enabled. The WP# function is replaced by IO2
for input and output during Quad mode for receiving addresses and data to be programmed (values are
latched on rising edge of the CLK signal) as well as shifting out data (on the falling edge of CLK).
4.6. HOLD (HOLD#) / IO3
The HOLD# pin allows the device to be paused while it is actively selected. When HRSW bit is ‘0’ (factory
default is ‘0’), the HOLD# pin is enabled. When HOLD# is brought low, while CS# is low, the DO pin will be at
high impedance and signals on the DI and CLK pins will be ignored (don’t care). When HOLD# is brought high,
device operation can resume. The HOLD# function can be useful when multiple devices are sharing the same
SPI signals. The HOLD# pin is active low. When the QE bit of Status Register-2 is set for Quad I/O, the
HOLD# pin function is not available since this pin is used for IO3.
4.7. RESET (RESET#) / IO3
The RESET# pin allows the device to be reset by the controller. When HRSW bit is ‘1’ (factory default is
‘0’), the RESET# pin is enabled. Drive RESET# low for a minimum period of ~1us (tRESET*) will interrupt any
on-going external/internal operations, regardless the status of other SPI signals (CS#, CLK, DI, DO, WP#
and/or HOLD#). The Hardware Reset function is only available for standard SPI and Dual SPI operation,
when QE=0, the IO3 pin can be configured either as a HOLD# pin or as a RESET# pin depending on Status
Register setting, when QE=1, this pin is the Serial Data IO (IO3) for Quad I/O operation.
Wuhan Xinxin Semiconductor Manufacturing Corp.
Rev. M Issue Date: 2018/07/17
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XM25QH32B
5. MEMORY ORGANIZATION
5.1. Flash Memory Array
The memory is organized as:
- 4,194,304bytes
- Uniform Sector Architecture 64 blocks of 64-Kbyte
- 1024 sectors of 4-Kbyte
- 16, 384 pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector,
Block or Chip Erasable but not Page Erasable.
(1)
Table 5.1
Block/ Security
Register/SFDP
Security Register 3
Memory Organization
Sector
Address range
-
003000H
0030FFH
Security Register 2
-
002000H
0020FFH
Security Register 1
Security Register 0
(SFDP)
-
001000H
0010FFH
-
000000H
0000FFH
1023
3FF000H
3FFFFFH
......
......
......
1008
3F0000H
3F0FFFH
1007
3EF000H
3EFFFFH
Block 63
Block 62
......
......
Block 2
Block 1
Block 0
......
......
......
992
3E0000H
3E0FFFH
......
......
......
......
......
......
......
......
......
......
......
......
......
......
......
......
......
......
47
02F000H
02FFFFH
......
......
......
32
020000H
020FFFH
01FFFFH
31
01F000H
......
......
......
16
010000H
010FFFH
15
00F000H
00FFFFH
......
......
......
0
000000H
000FFFH
Notes:
(1) These are condensed tables that use a couple of sectors as references. There are address ranges that are not explicitly
listed. All 4-kB sectors have the pattern XXX000h-XXXFFFh.
5.2. Security Registers
The XM25QH32B provides four 256-byte Security Registers. Each register can be used to store
information that can be permanently protected by programming One Time Programmable (OTP) lock bits in
Status Register-2.
Register 0 is used by XMC to store and protect the Serial Flash Discoverable Parameters (SFDP)
information that is also accessed by the Read SFDP command. See Table 5.1.
Wuhan Xinxin Semiconductor Manufacturing Corp.
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XM25QH32B
The three additional Security Registers can be erased, programmed, and protected individually. These
registers may be used by system manufacturers to store and permanently protect security or other important
information separate from the main memory array.
5.2.1 Security Register 0
Serial Flash Discoverable Parameters (SFDP — JEDEC ):
This document defines the Serial Flash Discoverable Parameters (SFDP) revision B data structure for
XM25QH32B family. These data structure values are an update to the earlier revision SFDP data structure in
the XM25QH32B family devices.
The Read SFDP (RSFDP) command (5Ah) reads information from a separate flash memory address
space for device identification, feature, and configuration information, in accord with the JEDEC standard for
Serial Flash Discoverable Parameters.
The SFDP data structure consists of a header table that identifies the revision of the JESD216 header
format that is supported and provides a revision number and pointer for each of the SFDP parameter tables
that are provided. The parameter tables follow the SFDP header. However, the parameter tables may be
placed in any physical location and order within the SFDP address space. The tables are not necessarily
adjacent nor in the same order as their header table entries.
The SFDP header points to the following parameter tables:
Basic Flash
– This is the original SFDP table.
The physical order of the tables in the SFDP address space is: SFDP Header, and Basic Flash.The SFDP
address space is programmed by XMC and read-only for the host system.
5.2.2 Serial Flash Discoverable Parameters (SFDP) Address Map
The SFDP address space has a header starting at address zero that identifies the SFDP data structure
and provides a pointer to each parameter. One Basic Flash parameter is mandated by the JEDEC standard.
Table 5.2 SFDP Overview Map — Security Register 0
Byte Address
0000h
...
0030h
...
006Fh
0070h to 00FFh
Description
Location zero within JEDEC SFDP space – start of SFDP header
Remainder of SFDP header followed by undefined space
Start of SFDP parameter
Remainder of SFDP JEDEC parameter followed by undefined space
End of SFDP space
Reserved space
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5.2.3 SFDP Header Field Definitions
Table 5.3 SFDP Header (Sheet 1 of 1)
Add (h)
(Byte)
DW Add
(Bit)
Data
SFDP Minor Revision Number
SFDP Major Revision Number
00h
01h
02h
03h
04h
05h
07 : 00
15 : 08
23 : 16
31 : 24
07 : 00
15 : 08
53h
46h
44h
50h
00h
01h
Number of Parameter Headers (NPH)
06h
23 : 16
01h
Unused
ID Number(JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length (in double
word)
07h
08h
31 : 24
07 : 00
FFh
00h
Star from 0x00
Star from 0x01
This number is 0-based.Therefore,0
indicates 1 parameter header.
Reserved
00h:it indicates a JEDEC specified header.
09h
15 : 08
00h
Star from 0x00
0Ah
23 : 16
01h
Star from 0x01
0Bh
31 : 24
09h
How many DWORDs in the parameter
table
0Ch
0Dh
0Eh
0Fh
10h
07 : 00
15 : 08
23 : 16
31 : 24
07 : 00
30h
00h
00h
FFh
20h
11h
15 : 08
00h
Start from 00h
12h
23 : 16
01h
Start from 01h
13h
31 : 24
04h
How many DWORDs in the parameter
table
14h
15h
16h
17h
07 : 00
15 : 08
23 : 16
31 : 24
60h
00h
00h
FFh
Description
SFDP Signature
Parameter Table Pointer (PTP)
Unused
ID number(Manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length(in double
word)
Parameter Table Pointer(PTP)
Unused
Wuhan Xinxin Semiconductor Manufacturing Corp.
Comment
Fixed: 50444653h
First address of JEDEC Flash Parameter
table
It indicates manufacture ID
First address
Parameter table
Rev. M Issue Date: 2018/07/17
of
VENDOR
Flash
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XM25QH32B
5.2.4 JEDEC SFDP Basic SPI Flash Parameter
Table 5.4 Basic SPI Flash Parameter, JEDEC Flash Parameter Tables (Sheet 1 of 9)
Add (h) DW Add
Description
Data
Comment
(Byte)
(Bit)
01 : 00
01b
02
1b
03
0b
04
0b
07 : 05
111b
15 : 08
20h
16
1b
18 : 17
00b
19
0b
20
1b
(1-4-4) Fast Read
21
1b
(1-1-4) Fast Read
22
1b
23
31 : 24
1b
FFh
Block / Sector Erase sizes
Write Granularity
Volatile Status Register Block Protect
bits
30h
Write Enable Instruction Select for
Writing to Volatile Status Registers
Unused
31h
4KB Erase Instruction
(1-1-2) Fast Read(1)
Address Bytes Number
addressing flash array
used
in
Double Transfer Rate(DTR) clocking
(1-2-2) Fast Read
Unused
Unused
32h
33h
00:Reserved, 01:4KB erase,
10:Reserved, 11:not supported 4KB
erase
0:1Byte,1:64Byte or larger
0: Block Protect bits in device's status
register are solely non-volatile or may
be
programmed either as volatile using the
50h instruction for write enable or
non-volatile using the 06h instruction
for write enable.
1: Block Protect bits in device's status
register are solely volatile.
0:use 50h instruction
1:use 06h instruction
Contains 111b and can never be
changed
0 = not supported
1 = supported
00:3Byte only, 01:3 or 4Byte
10:4Byte only, 11:Reserved
0 = not supported
1 = supported
0 = not supported
1 = supported
0 = not supported
1 = supported
0 = not supported
1 = supported
Table 5.4 Basic SPI Flash Parameter, JEDEC Flash Parameter Tables (Sheet 2 of 9)
Add (h) DW Add
Description
Data
Comment
(Byte)
(Bit)
Flash Memory Density
37h : 34h
Wuhan Xinxin Semiconductor Manufacturing Corp.
31 : 00
For densities 2 gigabits or less,
bit-31 is set to 0b. The field 30:0
defines the size in bits.
Example: 00FFFFFFh = 16
megabits
For densities 4 gigabits and above,
01FFFFFFh
bit-31 is set to 1b. The field 30:0
defines ‘N’ where the
density is computed as 2^N bits (N
must be >= 32).
Example: 80000021h = 2^33 = 8
gigabits
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Table 5.4 Basic SPI Flash Parameter, JEDEC Flash Parameter Tables (Sheet 3 of 9)
Add (h) DW Add
Description
Data
Comment
(Byte)
(Bit)
(1-4-4)Fast Read number of Wait
states(2)
(1-4-4)Fast Read number of Mode
Clocks(3)
38h
(1-4-4)Fast Read instruction
39h
(1-1-4)Fast Read Number of Wait states
(1-1-4)Fast Read Number of Mode
Clocks
(1-1-4)Fast Read Instruction
04 : 00
00100b
07 : 05
010b
15 : 08
EBh
20 : 16
01000b
23 : 21
000b
31 : 24
6Bh
3Ah
3Bh
00000b:Not supported;00100b:4
00110b:6 01000b:8
Mode clocks:
000b:Not supported;010: 2 clocks
00000b:Not suppoted;00100b:4
00100b:6; 01000b:8
Mode clocks:
000b:Not supported;010b:2 clocks
Table 5.4 Basic SPI Flash Parameter, JEDEC Flash Parameter Tables (Sheet 4 of 9)
Add (h) DW Add
Description
Data
Comment
(Byte)
(Bit)
(1-1-2)Fast Read Number of Wait states
(1-1-2)Fast Read Number of Mode
Clocks
(1-1-2)Fast Read Instruction
(1-2-2)Fast Read Instruction
01000b
07 : 05
000b
15 : 08
3Bh
20 : 16
00100b
23 : 21
000b
31 : 24
BBh
3Ch
3Dh
(1-2-2)Fast Read Number of Wait states
(1-2-2)Fast Read Number of Mode
Clocks
04 : 00
3Eh
3Fh
00000b:Not supported;00100b:4
00110b:6;01000b:8
Mode clocks:
000b:Not supported;010:2 clocks
00000b:Not supported; 00010b:2;
00100b:4;00110b:6;01000b:8
Mode clocks:
000b:Notsupported;010:2 clocks;
100:4 clocks
Table 5.4 Basic SPI Flash Parameter, JEDEC Flash Parameter Tables (Sheet 5 of 9)
Add (h) DW Add
Description
Data
Comment
(Byte)
(Bit)
(2-2-2)Fast Read
Unused
40h
(4-4-4)Fast Read
Unused
Unused
43h : 41h
00
0b
03 : 01
111b
04
1b
07 : 05
31 : 08
111b
FFFFFFh
0 = not supported
1 = supported
0 = not supported
1 = supported
Table 5.4 Basic SPI Flash Parameter, JEDEC Flash Parameter Tables (Sheet 6 of 9)
Add (h) DW Add
Description
Data
Comment
(Byte)
(Bit)
45h : 44h 15 : 00
FFh
Unused
(2-2-2)Fast Read Number of Wait states
(2-2-2) Fast Read Number of Mode
Clocks
(2-2-2)Fast Read Instruction
20 : 16
00000b
23 : 21
000b
31 : 24
FFh
46h
47h
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00000b:Not supported;00100b:4
00110b:6;01000b:8
Mode Clocks:
000b:Not supported;010:2 clocks
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Table 5.4 Basic SPI Flash Parameter, JEDEC Flash Parameter Tables (Sheet 7 of 9)
Add (h) DW Add
Description
Data
Comment
(Byte)
(Bit)
49h : 48h 15 : 00
FFFFh
Unused
(4-4-4)Fast Read Number of Wait states
20 : 16
00010b
23 : 21
010b
31 : 24
EBh
4Ah
(4-4-4) Fast Read Number of Mode
Clocks
(4-4-4)Fast Read Instruction
4Bh
00000b:Not supported;
00010b:2;00100b:4;
00110b:6;01000b:8
Mode Clocks:
000b:Not supported;010:2 clocks
Table 5.4 Basic SPI Flash Parameter, JEDEC Flash Parameter Tables (Sheet 8 of 9)
Add (h) DW Add
Description
Data
Comment
(Byte)
(Bit)
Erase Type 1 Size
4Ch
07 : 00
0Ch
Erase Type 1 Erase Instruction
4Dh
15 : 08
20h
Erase Type 2 Size
4Eh
23 : 16
0Fh
Erase Type 2 Erase Instruction
4Fh
31 : 24
52h
Sector/block size=2N bytes(4)
0Ch:4KB;0Fh:32KB;10h:64KB
Sector/block size=2N bytes
00h:NA;0Fh:32KB;10h:64KB
Table 5.4 Basic SPI Flash Parameter, JEDEC Flash Parameter Tables (Sheet 9 of 9)
Add (h) DW Add
Description
Data
Comment
(Byte)
(Bit)
Sector/block size=2N bytes
00h:NA;0Fh:32KB;10h:64KB
Erase Type 3 Size
50h
07 : 00
10h
Erase Type 3 Erase Instruction
51h
15 : 08
D8h
Erase Type 4 Size
52h
23 : 16
00h
Sector/block size=2N bytes
00h:NA;0Fh:32KB;10h:64KB
Erase Type 4 Erase Instruction
53h
31 : 24
FFh
Not support
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Table 5.5 Basic SPI Flash Parameter, XMC Flash Parameter Tables
Add (h) DW Add
Description
Data
Comment
(Byte)
(Bit)
2000h=2.000V
07:00
00h
61h:60h
Vcc supply maximum voltage
2700h=2.700V
15:08
36h
Vcc supply minimum voltage
23:16
00h
31:24
27h
63h:62h
H/W Reset# pin
0
H/W Hold# pin
1
Deep Power Down Mode
2
S/W Reset
3
S/W Reset Instruction
65h:64h
11:04
Program suspend/resume
12
Erase suspend/resume
13
Unused
14
Wrap-Around Read mode
15
Wrap-Around Read mode instruction
Wrap-Around Read data length
66h
23:16
67h
31:24
0 = not supported
1 = supported
0Ch
64h
0
Individual block lock
Individual
block
lock
bit(Volatile/Nonvolatile)
Individual block lock Instruction
Individual block lock Volatile protect bit
default protect status
Secured OTP
F99Fh
3600h=3.600V
1650h=1.65V
1750h=1.75V
2250h=2.25V
2300h=2.3V
2350h=2.35V
2650h=2.65V
2700h=2.7V
0 = not supported
1 = supported
0 = not supported
1 = supported
0 = not supported
1 = supported
0 = not supported
1 = supported
Reset Enable(66h)should be issued
before Reset instruction
0 = not supported
1 = supported
0 = not supported
1 = supported
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
64h:8B&16B&32B&64B
0 = not supported
1 = supported
0:Volatile 1:Nonvolatile
1
09:02
0:Protect 1:Unprotect
10
6Bh:68h
F800h
11
Read Lock
12
Permanent Lock
13
0 = not supported
1 = supported
0 = not supported
1 = supported
0 = not supported
1 = supported
15:14
Unused
31:16
FFh
Unused
6Fh:6Ch
31:00
FFh
Unused
Note 1: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the
instruction (x),
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address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1),
(2-2-2),and (4-4-4)
Note 2: Wait States is required dummy clock cycles after the address bits or optional mode clocks.
Note 3: Mode clocks is optional control bits that follow the address bits. These bits are driven by the system
controller
if they are specified. (eg,read performance enhance toggling bits)
Note 4: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 5: All unused and undefined area data is blank FFh.
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6. FUNCTION DESCRIPTION
6.1 SPI Operations
6.1.1 SPI Modes
The XM25QH32B can be driven by an embedded microcontroller (bus master) in either of the two
following clocking modes.
Mode 0 with Clock Polarity (CPOL) = 0 and, Clock Phase (CPHA) = 0
Mode 3 with CPOL = 1 and, CPHA = 1
For these two modes, input data is always latched in on the rising edge of the CLK signal and the output
data is always available on the falling edge of the CLK clock signal.
The difference between the two modes is the clock polarity when the bus master is in standby mode and
not transferring any data.
CLK will stay at logic low state with CPOL = 0, CPHA = 0
CLK will stay at logic high state with CPOL = 1, CPHA = 1
CS#
CPOL=0_CPHA=0_CLK
CPOL=1_CPHA=1_CLK
DI
MSB
DO
MSB
Figure 6.1 SPI Modes
Timing diagrams throughout the rest of the document are generally shown as both mode 0 and 3 by
showing CLK as both high and low at the fall of CS#. In some cases a timing diagram may show only mode 0
with CLK low at the fall of CS#. In such case, mode 3 timing simply means clock is high at the fall of CS# so
no CLK rising edge set up or hold time to the falling edge of CS# is needed for mode 3.
CLK cycles are measured (counted) from one falling edge of CLK to the next falling edge of CLK. In
mode 0 the beginning of the first CLK cycle in a command is measured from the falling edge of CS# to the first
falling edge of CLK because CLK is already low at the beginning of a command.
6.1.2 Dual SPI Modes
The XM25QH32B supports Dual SPI Operation when using the Fast Read Dual Output (3Bh) and Fast
Dual I/O (BBh) instruction. These features allow data to be transferred from the device at twice the rate
possible with the standard SPI. These instructions are ideal for quickly downloading code to RAM upon
Power-up (code-shadowing) or for executing non-speed-critical code directly from the SPI bus (XIP). When
using Dual SPI commands, the DI and DO pins become bidirectional I/O pins: IO0 and IO1.
6.1.3 Quad SPI Modes
The XM25QH32B supports Quad SPI operation when using the Fast Read Quad Output (6Bh), Fast
Read Quad I/O (EBh) instruction, Word Read Quad I/O(E7h), and Octal Word Read Quad I/O(E3h). These
instructions allow data to be transferred to or from the device four times the rate of ordinary Serial Flash. The
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Quad Read instructions offer a significant improvement in continuous and random access transfer rates
allowing fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI
instructions, the DI and DO pins become bidirectional IO0 and IO1, and the WP# and HOLD# / RESET# pins
become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in
Status Register-2 to be set.
6.1.4 QPI Function
The XM25QH32B supports Quad Peripheral Interface (QPI) operations when the device is switched from
Standard/Dual/Quad SPI mode to QPI mode using the “Enter QPI (38h)” instruction. The typical SPI protocol
requires that the byte-long instruction code being shifted into the device only via DI pin in eight serial clocks.
The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial clocks are required.
This can significantly reduce the SPI instruction overhead and improve system performance in an XIP
environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only one mode can be active at
any given time. “Enter QPI (38h)” and “Exit QPI (FFh)” instructions are used to switch between these two
modes. Upon power-up or after a software reset using “Reset (99h)” instruction, the default state of the device
is Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile Quad Enable bit (QE) in Status
Register-2 is required to be set. When using QPI instructions, the DI and DO pins become bidirectional IO0
and IO1, and the WP# and HOLD# / RESET# pins become IO2 and IO3 respectively.
6.1.5 Hold Function
For Standard SPI and Dual SPI operations, the HOLD# / RESET# (IO3) signal allows the device interface
operation to be paused while it is actively selected (when CS# is low). The Hold function may be useful in
cases where the SPI data and clock signals are shared with other devices. For example, if the page buffer is
only partially written when a priority interrupt requires use of the SPI bus, the Hold function can save the state
of the interface and the data in the buffer so programming command can resume where it left off once the bus
is available again. The Hold function is only available for standard SPI and Dual SPI operation, not during
Quad SPI.
To initiate a Hold condition, the device must be selected with CS# low. A Hold condition will activate on
the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the Hold
condition will activate after the next falling edge of CLK. The Hold condition will terminate on the rising edge of
the HOLD# signal if the CLK signal is already low. If the CLK is not already low the Hold condition will
terminate after the next falling edge of CLK. During a Hold condition, the Serial Data Output, (DO) or IO0 and
IO1, are high impedance and Serial Data Input, (DI) or IO0 and IO1, and Serial Clock (CLK) are ignored. The
Chip Select (CS#) signal should be kept active (low) for the full duration of the Hold operation to avoid
resetting the internal logic state of the device.
6.1.6 Software Reset & Hardware RESET# pin
The XM25QH32B can be reset to the initial power-on state by a software Reset sequence, either in SPI
mode or QPI mode. This sequence must include two consecutive commands: Enable Reset (66h) & Reset
(99h). If the command sequence is successfully accepted, the device will take approximately 10us (tRST) to
reset. No command will be accepted during the reset period.
XM25QH32B can also be configured to utilize a hardware RESET# pin. The HRSW bit in the Status
Register-3 is the configuration bit for HOLD# pin function or RESET# pin function. When HRSW=0 (factory
default), the pin acts as a HOLD# pin as described above; when HRSW =1, the pin acts as a RESET# pin.
Drive the RESET# pin low for a minimum period of ~1us (tRESET*) will reset the device to its initial power-on
state. Any on-going Program/Erase operation will be interrupted and data corruption may happen. While
RESET# is low, the device will not accept any command input.
If QE bit is set to 1, the HOLD# or RESET# function will be disabled, the pin will become one of the four
data I/O pins.
Hardware RESET# pin has the highest priority among all the input signals. Drive RESET# low for a
minimum period of ~1us (tRESET*) will interrupt any on-going external/internal operations, regardless the status
of other SPI signals (CS#, CLK, DI, DO, WP# and/or HOLD#).
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Note:
1. While a faster RESET# pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum is recommended to
ensure reliable operation.
6.2. Status Register
The Read and Write Status Registers commands can be used to provide status and control of the flash
memory device.
Status Register-1 (SR1) and Status Register-2 (SR2) can be used to provide status on the availability of
the flash memory array, whether the device is write enabled or disabled, the state of write protection, Quad
SPI setting, Security Register lock status, and Erase / Program Suspend status.
SR1 and SR2 contain non-volatile bits in locations SR1[7:2] and SR2[6:0] that control sector protection,
OTP Register Protection, Status Register Protection, and Quad mode. Bits located in SR2[7], SR1[1], and
SR1[0] are read only volatile bits for suspend, write enable, and busy status. These are updated by the
memory control logic. The SR1[1] write enable bit is set only by the Write Enable (06h) command and cleared
by the memory control logic when an embedded operation is completed.
Write access to the non-volatile Status Register bits is controlled by the state of the non-volatile Status
Register Protect bits SR1[7] and SR2[0] (SRP0, SRP1), the Write Enable command (06h) preceding a Write
Status Registers command, and while Quad mode is not enabled, the WP# pin.
A volatile version of bits SR2[6], SR2[1], and SR1[7:2] that control sector protection and Quad Mode is
used to control the behavior of these features after power up. During power up or software reset, these
volatile bits are loaded from the non-volatile version of the Status Register bits. The Write Enable for Volatile
Status Register (50h) command can be used to write these volatile bits when the command is followed by a
Write Status Registers (01h/31h) command. This gives more flexibility to change the system configuration and
memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the
endurance of the Status Register non-volatile bits.
Write access to the volatile SR1 and SR2 Status Register bits is controlled by the state of the non-volatile
Status Register Protect bits SR1[7] and SR2[0] (SRP0, SRP1), the Write Enable for Volatile Status Register
command (50h) preceding a Write Status Registers command, and the WP# pin while Quad mode is not
enabled.
Status Register-3 (SR3) is used to configure and provide status on the variable HOLD# or RESET#
function, Output Driver Strength, High Frequency Enable Bitand read latency.
Write access to the volatile SR3 Status Register bits is controlled by Write Enable for Volatile Status
Register command (50h) preceding a Write Status Register command. The SRP bits do not protect SR3.
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Table 6.1 Status Register-1 (SR1)
Bits
Field
Function
7
SRP0
Status Register
Protect 0
6
SEC
Sector / Block
Protect
5
TB
Top / Bottom
protect
4
3
2
BP2
BP1
BP0
Block Protect
Bits
1
WEL
Write Enable
Latch
0
BUSY
Embedded
Operation
Status
Default
State
Description
0
0 = WP# input has no effect or Power Supply
Lock Down mode
1 = WP# input can protect the Status
Register or OTP Lock Down.
0
0 = BP2-BP0 protect 64-kB blocks
1 = BP2-BP0 protect 4-kB sectors
0
0 = BP2-BP0 protect from the Top down
1 = BP2-BP0 protect from the Bottom up
0
0
0
000b = No protection
Volatile,
Read only
0
0 = Not Write Enabled, no embedded
operation can start
1 = Write Enabled, embedded operation can
start
Volatile,
Read only
0
0 = Not Busy, no embedded operation in
progress
1 = Busy, embedded operation in progress
Type
Non-volatile
and Volatile
versions
Table 6.2 Status Register-2 (SR2)
Bits
Field
Function
Type
Default
State
7
SUS
Suspend Status
Volatile, Read
Only
0
0 = Erase / Program not suspended
1 = Erase / Program suspended
6
CMP
Complement
Protect
Non-volatile and
Volatile versions
0
0 = Normal Protection Map
1 = Complementary Protection Map
5
LB3
4
LB2
3
LB1
2
LB0
1
QE
0
Security Register
Lock Bits
0
OTP
0
0
Quad Enable
SRP1
Status Register
Protect 1
OTP Lock Bits 3:0 for Security Registers
3:0
0 = Security Register not protected
1 = Security Register protected
Security register 0 contains the Serial Flash
Discoverable Parameters and is always
programmed and locked by XMC.
0
0 = Quad Mode Not Enabled, the WP# pin
and HOLD# / RESET# are enabled
1 = Quad Mode Enabled, the IO2 and IO3
pins are enabled, and WP# and HOLD# /
RESET# functions are disabled
0
0 = SRP1 selects whether WP# input has
effect on protection of the status register
1 = SRP1 selects Power Supply Lock Down
or OTP Lock Down mode
Non-volatile and
Volatile versions
0
Description
Note:
1. A Software/Hardware reset or Power Down reset is required before non-volatile Status Register bits writing(06h+01/31h)
when writing volatile Status Register command(50h+01h/31h) has been issued earlier within one power up-power down cycle.
2. When write non-volatile Status Register bits(06h+01/31h), please contact XMC sales representative for the application note
of polling status bit check.
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Table 6.3 Status Register-3 (SR3)
Bits
Field
7
HRSW(1)
6
DRV1(1)
Function
HOLD# or
RESET#
function
Type
Default State
0
1
The DRV1 & DRV0 bits are used to determine
the output driver strength for the Read
operations.
Output Driver
Strength
5
4
DRV0(1)
Volatile
HFM
High
Frequency
Mode Enable
Bit
Latency
Control
(LC)(2)
Variable SPI
Read Latency
Control
3
2
1
Description
When HRSW=0, the pin acts as HOLD#; when
HRSW=1, the pin acts as RESET#. HRSW
functions are only available when QE=0.
0
0
0
0
0
0
0
0= QPI High Frequency Mode Disabled
1 = QPI High Frequency Mode Enabled
Defines the number of read latency cycles in
Fast Read, Dual Out, Quad Out, Dual IO, and
Quad IO commands. Binary values for 1 to 15
latency cycles. A value of zero disables the
variable latency mode.
Note:
1.Default state for these three bits could be modified. please contact sales.
2. LC[3:0] only controls SPI read latency and will be reset to default while switching from QPI to SPI. QPI read latency is set by C0
instruction.
6.2.1 BUSY
BUSY is a read only bit in the status register (SR1[0]) which is set to a “1” state when the device is
executing a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction.
During this time the device will ignore further instructions except for the Read Status Register instruction (see
tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status register instruction has
completed, the BUSY bit will be cleared to a “0” state indicating the device is ready for further instructions.
6.2.2 Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (SR1[1]) which is set to a 1 after
executing a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is written disabled.
A write disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.
6.2.3 Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read / write bits in the Status Register (SR1[4:2]) that
provide Write Protection control and status. Block Protect bits can be set using the Write Status Registers
Command (see tW in Section 8.5). All, none or a portion of the memory array can be protected from Program
and Erase commands (see Section 6.4.2, Block Protection Maps). The factory default setting for the Block
Protection Bits is 0 (none of the array is protected.)
6.2.4 Top / Bottom Block Protect (TB)
The non-volatile Top / Bottom bit (TB SR1[5]) controls whether the Block Protect Bits (BP2, BP1, BP0)
protect from the Top (TB=0) or the Bottom (TB=1) of the array as shown in Section 6.4.2, Block Protection
Maps. The factory default setting is TB=0. The TB bit can be set with the Write Status Registers Command
depending on the state of the SRP0, SRP1 and WEL bits.
6.2.5 Sector / Block Protect (SEC)
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The non-volatile Sector / Block Protect bit (SEC SR1[6]) controls if the Block Protect Bits (BP2, BP1, BP0)
protect either 4-kB Sectors (SEC=1) or 64-kB Blocks (SEC=0) of the array as shown in Section 6.4.2, Block
Protection Maps. The default setting is SEC=0.
6.2.6 Complement Protect (CMP)
The Complement Protect bit (CMP SR2[6]) is a non-volatile read / write bit in the Status Register (SR2[6]).
It is used in conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array
protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be
reversed. For instance, when CMP=0, a top 4-kB sector can be protected while the rest of the array is not;
when CMP=1, the top 4-kB sector will become unprotected while the rest of the array become read-only.
Refer to Section 6.4.2, Block Protection Maps for details. The default setting is CMP=0.
6.2.7 The Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read / write bits in the Status Register
(SR2[0] and SR1[7]). The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down, or one time programmable (OTP) protection.
Table 6.4 Status Register Protect
SRP1
SRP0
WP#
Status Register
Description
0
0
X
Software Protection
WP# pin has no control. SR1 and SR2 can be written to after a
Write Enable command, WEL=1. [Factory Default]
0
1
0
Hardware Protected
When WP# pin is low the SR1 and SR2 are locked and cannot
be written.
0
1
1
Hardware
Unprotected
When WP# pin is high SR1 and SR2 are unlocked and can be
written to after a Write Enable command, WEL=1.
1
0
X
Power Supply Lock
Down
SR1 and SR2 are protected and cannot be written to again until
the next power-down, power-up cycle. (1)
1
1
X
One Time Program
(2)
SR1 and SR2 are permanently protected and cannot be written.
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up, or Software Reset cycle will change SRP1, SRP0 to (0, 0) state.
2. The One-Time Program feature is available upon special order. Contact XMC for details.
3. Busy, WEL, and SUS (SR1[1:0] and SR2[7]) are volatile read only status bits that are never affected by the Write Status
Registers command.
4. The non-volatile version of CMP, QE, SRP1, SRP0, SEC, TB, and BP2-BP0 (SR2[6,1,0] and SR1[6:2]) bits and the OTP
LB3-LB0 bits are not writable when protected by the SRP bits and WP# as shown in the table. The non-volatile version of
these Status Register bits is selected for writing when the Write Enable (06h) command precedes the Write Status Registers
(01h) command.
5. The volatile version of CMP, QE, SRP1, SRP0, SEC, TB, and BP2-BP0 (SR2[6,1,0] and SR1[6:2]) bits are not writable
when protected by the SRP bits and WP# as shown in the table. The volatile version of these Status Register bits is selected
for writing when the Write Enable for volatile Status Register (50h) command precedes the Write Status Registers (01h)
command. There is no volatile version of the LB3-LB0 bits and these bits are not affected by a volatile Write Status Registers
command.
6. The volatile SR3 bits are not protected by the SRP bits and may be written at any time by volatile (50h) Write Enable
command preceding the Write Status Registers (01h/11h) command.
6.2.8 Erase / Program Suspend Status (SUS)
The Suspend Status bit is a read only bit in the status register (SR2[7]) that is set to 1 after executing an
Erase / Program Suspend (75h) command. The SUS status bit is cleared to 0 by Erase / Program Resume
(7Ah) command as well as a power-down, power-up cycle.
6.2.9 Security Register Lock Bits (LB3, LB2, LB1, LB0)
The Security Register Lock Bits (LB3, LB2, LB1, LB0) are non-volatile One Time Program (OTP) bits in
Status Register (SR2[5:2]) that provide the write protect control and status to the Security Registers. The
default state of LB[3:1] is 0, Security Registers 1 to 3 are unlocked. LB[3:1] can be set to 1 individually using
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the Write Status Registers command. LB[3:1] are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-byte Security Register will become read-only permanently. Security Register 0 is
programmed with the SFDP parameters and LB0 is programmed to 0 by XMC.
6.2.10 Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read / write bit in the Status Register (SR2[1]) that allows
Quad SPI operation. When the QE bit is set to a 0 state (factory default), the WP# pin and HOLD# / RESET#
are enabled. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and WP# and HOLD# /
RESET# functions are disabled.
Note: If the WP# or HOLD# / RESET# pins are tied directly to the power supply or ground during standard SPI or Dual SPI operation, the
QE bit should never be set to a 1.
6.2.11 HOLD# or RESET# Pin Function (HRSW)
The HRSW bit is used to determine whether HOLD# or RESET# function should be implemented on the
hardware pin for 8-pin packages. When HRSW=0, the pin acts as #HOLD; when HRSW=1, the pin acts as
RESET#. However, HOLD# or RESET# functions are only available when QE=0. If QE is set to 1, the HOLD#
and RESET# functions are disabled, the pin acts as a dedicated data I/O pin.
6.2.12 Output Driver Strength (DRV1, DRV0)
The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1, DRV0
0, 0
0, 1
1, 0
1, 1
Driver Strength
50%
25%
75%(default)
100%
6.2.13 High Frequency Mode Enable Bit (HFM)
The HFM bit is used to determine whether the device is in QPI High Frequency Mode. When HFM bit sets
to 1, it means the device is in QPI High Frequency Mode, when HFM bit sets 0 (default), it means the device is
not in QPI High Frequency Mode. This Mode allows pre-charge of internal charge pump, so the voltages
required for accessing the flash memory array are readily available for QPI read. After the HFM is executed,
the device will maintain a slightly higher standby current (ICC8) than standard SPI operation.
6.2.14 Latency Control (LC)
Status Register-3 provides bits (SR3[3:0]) to select the number of read latency cycles used in each Fast
Read command(only in SPI mode). The Read Data command is not affected by the latency code. The binary
value of this field selects from 1 to 15 latency cycles. The default is 0 to provide backward compatibility to
legacy devices. The Latency Control bits may be set to select a number of read cycles optimized for the
frequency in use. If the number of latency cycles is not sufficient for the operating frequency, invalid data will
be read.
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Table 6.5 Latency Cycles Versus Frequency for -40°C to 85°C/105°C at 2.7V to 3.6V
Latency Control
Fast Read
0
(legacy read latency)
104
(8 dummy)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
95
104
104
104
104
104
104
104
104
104
104
104
104
104
104
Read Command Maximum Frequency (MHz)
Quad
Dual I/O
Quad I/O
Output
104
104
104
104
(4 mode, 0
(2 mode, 4
(8 dummy)
(8 dummy)
dummy)
dummy)
95
104
75
60
104
104
90
75
104
104
104
90
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
104
Dual
Output
Word Read
Quad I/O
104
(2 mode, 2
dummy)
90
104
104
104
104
104
104
104
104
104
104
104
104
104
104
Notes:
1. The default dummy referred in this document is the dummy configuration when LC[3:0]=0.
2.Value guaranteed by design and/or characterization, not 100% tested in production.
6.3. Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the XM25QH32B
provides the following data protection mechanisms:
6.3.1 Write Protect Features
Device resets when VCC is below threshold
Time delay write disable after Power-Up
Write enable / disable commands and automatic write disable after erase or program
Command length protection
- All commands that Write, Program or Erase must complete on a byte boundary (CS# driven high after
a full 8 bits have been clocked) otherwise the command will be ignored.
Software and Hardware write protection using Status Register control
- WP# input protection
- Lock Down write protection until next power-up or Software Reset
- One-Time Program (OTP) write protection
Write Protection using the Deep Power-Down command
Upon power-up or at power-down, the XM25QH32B will maintain a reset condition while VCC is below the
threshold value of VWI, (see Figure 8.1). While reset, all operations are disabled and no commands are
recognized. During power-up and after the VCC voltage exceeds VWI, all program and erase related
commands are further disabled for a time delay of tPUW. This includes the Write Enable, Page Program,
Sector Erase, Block Erase, Chip Erase and the Write Status Registers commands. Note that the chip select
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pin (CS#) must track the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached.
If needed a pull-up resistor on CS# can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable command must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Registers command will be accepted. After completing a
program, erase or write command the Write Enable Latch (WEL) is automatically cleared to a write-disabled
state of 0.
Software controlled main flash array write protection is facilitated using the Write Status Registers
command to write the Status Register (SR1,SR2) and Block Protect (SEC, TB, BP2, BP1 and BP0) bits.
The BP method allows a portion as small as 4-kB sector or the entire memory array to be configured as
read only. Used in conjunction with the Write Protect (WP#) pin, changes to the Status Register can be
enabled or disabled under hardware control. See the Table 6.4 for further information.
Additionally, the Deep Power-Down (DPD) command offers an alternative means of data protection as all
commands are ignored during the DPD state, except for the Release from Deep-Power-Down (RES ABh)
command. Thus, preventing any program or erase during the DPD state.
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6.3.2 Block Protection Maps
Table 6.6
Status Register (1)
XM25QH32B Block Protection (CMP = 0)
XM25QH32B(32 Mbit) Block Protection (CMP=0) (2)
Protected
Protected
Protected Block(s)
Protected Addresses
Density
Portion
SEC
TB
BP2
BP1
BP0
X
X
0
0
0
None
None
None
None
0
0
0
0
1
63
3F0000h – 3FFFFFh
64 kB
Upper 1/64
0
0
0
1
0
62 and 63
3E0000h – 3FFFFFh
128 kB
Upper 1/32
0
0
0
1
1
60 thru 63
3C0000h – 3FFFFFh
256 kB
Upper 1/16
0
0
1
0
0
56 thru 63
380000h – 3FFFFFh
512 kB
Upper 1/8
0
0
1
0
1
48 thru 63
300000h – 3FFFFFh
1 MB
Upper 1/4
0
0
1
1
0
32 thru 63
200000h – 3FFFFFh
2MB
Upper 1/2
0
1
0
0
1
0
000000h – 00FFFFh
64 kB
Lower 1/64
0
1
0
1
0
0 and 1
000000h – 01FFFFh
128 kB
Lower 1/32
0
1
0
1
1
0 thru 3
000000h – 03FFFFh
256 kB
Lower 1/16
0
1
1
0
0
0 thru 7
000000h – 07FFFFh
512 kB
Lower 1/8
0
1
1
0
1
0 thru 15
000000h – 0FFFFFh
1 MB
Lower 1/4
0
1
1
1
0
0 thru 31
000000h – 1FFFFFh
2 MB
Lower 1/2
X
X
1
1
1
0 thru 63
000000h – 3FFFFFh
4 MB
1
0
0
0
1
63
3FF000h – 3FFFFFh
4 kB
1
0
0
1
0
63
3FE000h – 3FFFFFh
8 kB
1
0
0
1
1
63
3FC000h – 3FFFFFh
16 kB
1
0
1
0
X
63
3F8000h – 3FFFFFh
32 kB
1
0
1
1
0
63
3F8000h – 3FFFFFh
32 kB
1
1
0
0
1
0
000000h – 000FFFh
4 kB
1
1
0
1
0
0
000000h – 001FFFh
8 kB
1
1
0
1
1
0
000000h – 003FFFh
16 kB
1
1
1
0
X
0
000000h – 007FFFh
32 kB
1
1
1
1
0
0
000000h – 007FFFh
32 kB
All
Upper
1/1024
Upper
1/512
Upper
1/256
Upper
1/128
Upper
1/128
Lower
1/1024
Lower
1/512
Lower
1/256
Lower
1/128
Lower
1/128
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
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Table 6.7 XM25QH32B Block Protection (CMP = 1)
Status Register (1)
SEC
TB
BP2
BP1
BP0
X
X
0
0
0
XM25QH32B(32 Mbit) Block Protection (CMP=1) (2)
Protected
Protected
Protected Block(s)
Protected Addresses
Density
Portion
0 thru 63
000000h – 3FFFFFh
4 MB
All
Lower
63/64
Lower
31/32
Lower
15/16
0
0
0
0
1
0 thru 62
000000h – 3EFFFFh
4032 kB
0
0
0
1
0
0 thru 61
000000h – 3DFFFFh
3986 kB
0
0
0
1
1
0 thru 59
000000h – 3BFFFFh
3840 kB
0
0
1
0
0
0 thru 55
000000h – 37FFFFh
3584 kB
Lower 7/8
0
0
1
0
1
0 thru 47
000000h – 2FFFFFh
3 MB
Lower 3/4
0
0
1
1
0
0 thru 31
000000h – 1FFFFFh
2 MB
Lower 1/2
0
1
0
0
1
1 thru 63
010000h – 3FFFFFh
4032 kB
0
1
0
1
0
2 thru 63
020000h – 3FFFFFh
3986 kB
0
1
0
1
1
4 thru 63
040000h – 3FFFFFh
3840 kB
0
1
1
0
0
8 thru 63
080000h – 3FFFFFh
3584 kB
Upper 7/8
0
1
1
0
1
16 thru 63
100000h – 3FFFFFh
3 MB
Upper 3/4
0
1
1
1
0
32 thru 63
200000h – 3FFFFFh
2 MB
Upper 1/2
X
X
1
1
1
None
None
None
None
1
0
0
0
1
0 thru 63
000000h – 3FEFFFh
4092 kB
1
0
0
1
0
0 thru 63
000000h – 3FDFFFh
4088 kB
1
0
0
1
1
0 thru 63
000000h – 3FBFFFh
4080 kB
1
0
1
0
X
0 thru 63
000000h – 3F7FFFh
4064 kB
1
0
1
1
0
0 thru 63
000000h – 3F7FFFh
4064 kB
1
1
0
0
1
0 thru 63
001000h – 3FFFFFh
4092 kB
1
1
0
1
0
0 thru 63
002000h – 3FFFFFh
4088 kB
1
1
0
1
1
0 thru 63
004000h – 3FFFFFh
4080 kB
1
1
1
0
X
0 thru 63
008000h – 3FFFFFh
4064 kB
1
1
1
1
0
0 thru 63
008000h – 3FFFFFh
4064 kB
Upper
63/64
Upper
31/32
Upper
15/16
Lower
1023/1024
Lower
511/512
Lower
255/256
Lower
127/128
Lower
127/128
Upper
1023/1024
Upper
511/512
Upper
255/256
Upper
127/128
Upper
127/128
Notes:
1. X = don’t care.
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
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6.4. Page Program
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a
Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program
cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to
be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the
same page of memory.
6.5. Sector Erase, Block Erase and Chip Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the
bytes of memory need to be erased to all 1s (FFh). This can be achieved a sector at a time, using the Sector
Erase (SE) instruction, a block at a time using the Block Erase (BE) instruction or throughout the entire
memory, using the Chip Erase (CE) instruction. This starts an internal Erase cycle (of duration t SE tBE or tCE).
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
6.6. Polling during a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE or
CE) can be achieved by not waiting for the worst case delay (tW , tPP, tSE, tBE or tCE). The Write In Progress
(WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to
establish when the previous Write cycle, Program cycle or Erase cycle is complete.
6.7. Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select
(CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have
completed (Program, Erase, Write Status Register). The device then goes into the Standby Power mode. The
device consumption drops to ICC1.
The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode
(DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode
until another specific instruction (the Release from Deep Power-down Mode and Read Device ID (RDI)
instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as
an extra software protection mechanism, when the device is not in active use, to protect the device from
inadvertent Program or Erase instructions.
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7. INSTRUCTIONS
The instruction set of the XM25QH32B consists of forty basic instructions that are fully controlled through
the SPI bus. Instructions are initiated with the falling edge of Chip Select (CS#). The first byte of data clocked
into the DI input provides the instruction code. Data on the DI input is sampled on the rising edge of clock with
most significant bit (MSB) first.
The QPI instruction set of the XM25QH32B consists of 32 basic instructions that are fully controlled
through the SPI bus (see Instruction Set Table 7.5). Instructions are initiated with the falling edge of Chip
Select (CS#). The first byte of data clocked through IO[3:0] pins provides the instruction code. Data on all four
IO pins are sampled on the rising edge of clock with most significant bit (MSB) first. All QPI instructions,
addresses, data and dummy bytes are using all four IO pins to transfer every byte of data with every two serial
clocks (CLK).
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the rising
edge of edge CS#. Clock relative timing diagrams for each instruction are included in figures 7.1 through 7.43.
All read instructions can be completed after any clocked bit. However, all instructions that Write, Program or
Erase must complete on a byte boundary (CS driven high after a full 8-bits have been clocked) otherwise the
instruction will be ignored. This feature further protects the device from inadvertent writes. Additionally, while
the memory is being programmed or erased, or when the Status Register is being written, all instructions
except for Read Status Register and Erase/Program Suspend will be ignored until the program or erase cycle
completes.
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Table 7.1 Command Set (Configuration, Status, Erase, Program Instructions , SPI Mode)
Command Name
BYTE 1
(Instruction)
BYTE 2
Read Status Register-1
05h
SR1[7:0](2)
Read Status Register-2
35h
SR2[7:0](2)
Read Status Register-3
15h/33h
SR3[7:0](2)
BYTE 3
BYTE 4
BYTE 5
Write Enable
06h
Write Enable for Volatile
Status Register
50h
Write Disable
04h
Write Status Registers-1
01h
SR1[7:0](5)
Write Status Registers-2
31h
SR2[7:0]
Write Status Registers-3
11h
SR3[7:0]
Set Burst with Wrap
77h
xxh
xxh
xxh
W[7:0](3)
Page Program
02h
A23—A16
A15—A8
A7—A0
D7—D0
Quad Page Program
32h
A23—A16
A15—A8
A7—A0
D7—D0(4)
Sector Erase (4 KB)
20h
A23—A16
A15—A8
A7—A0
Block Erase (32 KB)
52h
A23—A16
A15—A8
A7—A0
Block Erase (64 KB)
D8h
A23—A16
A15—A8
A7—A0
Chip Erase
BYTE 6
C7h/60h
Erase/Program
75h
Suspend
Erase/Program Resume
7Ah
Enter QPI Mode
38h
Enable Reset
66h
Reset Device
99h
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “()” indicate data being
read from the device on the DO pin.
2. Status Register contents will repeat continuously until CS# terminates the command.
3. Set Burst with Wrap Input format.
IO0 = x, x, x, x, x, x, W4, x]
IO1 = x, x, x, x, x, x, W5, x]
IO2 = x, x, x, x, x, x, W6 x]
IO3 = x, x, x, x, x, x, x,x
4. Quad Page Program Input Data:
IO0 =(D4,D0,...)
IO1 = ( D5,D1,...)
IO2 = ( D6,D2,...)
IO3 =( D7,D3,...)
5. The 01h command could continuously write up to three bytes to registers SR1, SR2, SR3.
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Table 7.2 Command Set (Read Instructions , SPI Mode)
Command Name
BYTE 1
(Instruction)
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
Read Data
03h
A23—A16
A15—A8
A7—A0
(D7—D0,…)
Fast Read
Fast Read Dual
Output
Fast Read Quad
Output
0Bh
A23—A16
A15—A8
A7—A0
dummy
(D7—D0,…)
3Bh
A23—A16
A15—A8
A7—A0
dummy
(D7—D0,…)(1)
6Bh
A23—A16
A15—A8
A7—A0
dummy
(D7—D0,…)(3)
Fast Read Dual I/O
BBh
A23—A8(2)
A7—A0,M7
—M0(2)
(D7—D0,…)(1)
Fast Read Quad
I/O
EBh
A23—A0,M7
—M0(4)
(x,x,x,x,D7—
D0,...)
(D7—D0,…)(3)
QUAD I/O WORD
FAST READ(5)
E7H
A23—A0,M7
—M0(4)
(x,x,D7—D0,
...)
(D7—D0,…)(3)
Octal Word Read
Quad I/O(5)
E3h
A23—A0,M7
—M0(4)
(D7—D0,…)(
3)
(D7—D0,…)(3)
Notes:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
3. Quad Output Data
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
4. Quad Input Address
IO0 = A20, A16, A12, A8, A4, A0, M4, M0
IO1 = A21, A17, A13, A9, A5, A1, M5, M1
IO2 = A22, A18, A14, A10, A6, A2, M6, M2
IO3 = A23, A19, A15, A11, A7, A3, M7, M3
5. For Word Read Quad I/O, the lowest address bit must be 0. (A0 = 0),and for Octal Word Read Quad I/O, the lowest four
address bits must be 0. (A3, A2, A1, A0 = 0)
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Table 7.3 Command Set (Read ID, OTP Instructions
Command
Name
BYTE 1
(Instruction)
Deep
Power-down
Release
Power down /
Device ID
Manufacturer/
Device ID(2)
Manufacturer/
Device ID by
Dual I/O
(1)
, SPI Mode)
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
ABh
dummy
dummy
dummy
Device ID(1)
90h
dummy
dummy
00h
Manufacturer
Device ID
92h
A23—A8
A7—A0,M[7:0]
(MF[7:0],ID[7:0])
9Fh
Manufacturer
Memory Type
Capacity
5Ah
00h
00h
A7—A0
dummy
(D7—D0,…)
48h
A23—A16
A15—A8
A7—A0
dummy
(D7—D0,…)
44h
A23—A16
A15—A8
A7—A0
42h
A23—A16
A15—A8
A7—A0
D7—D0,…
4Bh
dummy
dummy
dummy
dummy
B9h
JEDEC ID
Read SFDP
Register
Read
Security
Registers(3)
Erase
Security
Registers(3)
Program
Security
Registers(3)
Read Unique
ID
(ID63-ID0)
Notes:
1. The Device ID will repeat continuously until CS# terminates the command.
2. See Section 6.4.1, Legacy Device Identification Commands on page 51 for Device ID information. The 90h instruction is followed
by an address. Address = 0 selects Manufacturer ID as the first returned data as shown in the table. Address = 1 selects Device ID as
the first returned data followed by Manufacturer ID.
3. Security Register Address:
Security Register 0: A23-16 = 00h; A15-8 = 00h; A7-0 = byte address
Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address
Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address
Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address
(1)
Table 7.4
Manufacturer and Device Identification(SPI and QPI Mode)
OP Code
Data1
Data2
Data3
ABh
Device ID = 15h
-
-
90h/92h
Manufacturer ID = 20h
Device ID = 15h
9Fh(SPI Mode)
9Fh(QPI Mode)
Manufacturer ID = 20h
Manufacturer ID = 20h
(2)
Capacity = 16h
(2)
Capacity = 16h
Memory Type =40h
Memory Type =60h
Notes:
(1) Please contact sales for more information
(2) Data2 40h is for SPI mode and the 60h is for QPI mode.
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Table 7.5 Command Set (QPI Instructions
(1)
, QPI Mode)
BYTE 1
(Instruction)
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
Clock Number
(0, 1)
(2, 3)
(4, 5)
(6, 7)
(8, 9)
(10, 11)
Write Enable
06h
Write Enable for Volatile
Status Register
50h
Write Disable
04h
Read Status Register-1
05h
(S7-S0)(1)
Write Status Register-1(3)
01h
(S7-S0)(3)
Read Status Register-2
35h
(S15-S8)(1)
Write Status Register-2
31h
(S15-S8)
Read Status Register-3
15h/33h
(S23-S16)(1)
Write Status Register-3
11h
(S23-S16)
Command Name
Chip Erase
C7h/60h
Erase / Program Suspend
75h
Erase / Program Resume
7Ah
Deep Power-down
B9h
Set Read Parameters
C0h
P7-P0
Release Power down / ID
ABh
Dummy
Dummy
Dummy
(ID7-ID0)(1)
Manufacturer/Device ID
90h
Dummy
Dummy
00h
(MF7-MF0)
(ID7-ID0)
JEDEC ID
9Fh
(MF7-MF0)
(ID15-ID8)
(ID7-ID0)
Exit QPI Mode
FFh
Enable Reset
66h
Reset Device
99h
Page Program
02h
A23-A16
A15-A8
A7-A0
D7-D0(4)
D7-D0(2)
Sector Erase (4KB)
20h
A23-A16
A15-A8
A7-A0
Block Erase (32KB)
52h
A23-A16
A15-A8
A7-A0
Block Erase (64KB)
D8h
A23-A16
A15-A8
A7-A0
Fast Read
0Bh
A23-A16
A15-A8
A7-A0
Dummy(5)
D7-D0
A7-A0
(5)
D7-D0
Burst Read with Wrap(6)
Fast Read Quad I/O
0Ch
EBh
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
Dummy
(5)
M7-M0
D7-D0
Notes:
1. The Status Register contents and Device ID will repeat continuously until CS# terminates the instruction.
2. At least one byte of data input is required for Page Program, Quad Page Program and Program Security Registers, up to 256 bytes
of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and
overwrite previously sent data.
3. Write Status Register-1 (01h) can also be used to program Status Register-1&2&3, see section 7.1.5.
4. Quad SPI data input/output format:
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
5. The number of dummy clocks for QPI Fast Read, QPI Fast Read Quad I/O & QPI Burst Read with Wrap is controlled by read
parameter P7 – P4.
6. The wrap around length for QPI Burst Read with Wrap is controlled by read parameter P3 – P0.
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7.1 Configuration and Status Commands
7.1.1 Read Status Register (05h/35h/15h)
The Read Status Register commands allow the 8-bit Status Registers to be read. The command is
entered by driving CS# low and shifting the instruction code “05h” for Status Register-1, “35h” for Status
Register-2, “15h” for Status Register-3 into the DI pin on the rising edge of CLK. The Status Register bits are
then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in
Figure 7.1. The Status Register bits are shown in Section 6.2, Status Registers.
The Read Status Register-1 (05h) command may be used at any time, even during a Program, Erase, or
Write Status Registers cycle. This allows the BUSY status bit to be checked to determine when the operation
is complete and if the device can accept another command.
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
DI
Mode 3
Mode 0
Mode 0
05h/35h/15h
DO
S7~S0 out
Instruction
S7~S0 out
Status
Updated Status
Figure 7.1a Read Status Register Instruction(SPI Mode)
CS#
Mode 3
CLK
0
1
2
3
4
5
Mode 0
IO0
4
0 S4 S0 S4 S0 S4
IO1
5
1 S5 S1 S5 S1 S5
IO2
6
2 S6 S2 S6 S2 S6
7
3 S7 S3 S7 S3 S7
IO3
InstructionSR-1/2/3 SR-1/2/3
05h/35h/15h out
out
Figure 7.1b Read Status Register Instruction(QPI Mode)
7.1.2 Write Enable (06h)
The Write Enable instruction (Figure 7.2) sets the Write Enable Latch (WEL) bit in the Status Register to a
1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase and Write
Status Register instruction. The Write Enable instruction is entered by driving CS# low, shifting the instruction
code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then driving CS# high.
CS#
Mode 3
CLK
CS#
Mode 3
CLK
DI
0
1
2
3
4
Mode 0
5
6
7
DO
1
Mode 3
Mode 0
Mode 3
Mode 0
06h
0
Mode 0
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Instruction
Instruction
06h
Figure 7.2 Write Enable Instruction(SPI or QPI Mode)
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7.1.3 Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in section 6.2 can also be written to as volatile bits. This
gives more flexibility to change the system configuration and memory protection schemes quickly without
waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile
bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h)
instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable for Volatile Status
Register instruction (Figure 7.3) will not set the Write Enable Latch (WEL)bit, it is only valid for the Write
Status Register instruction to change the volatile Status Register bit values.
CS#
Mode 3
CLK
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 0
1
Mode 3
Mode 0
Mode 3
Mode 0
50h
DI
0
Mode 0
DO
IO0
4
0
IO1
5
1
IO2
6
2
IO3
7
3
Instruction
Instruction
50h
Figure 7.3 Write Enable for Volatile Status Register Instruction(SPI or QPI Mode)
7.1.4 Write Disable (04h)
The Write Disable instruction (Figure 7.4) resets the Write Enable Latch (WEL) bit in the Status Register
to a 0. The Write Disable instruction is entered by driving CS# low, shifting the instruction code “04h” into the
DI pin and then driving CS# high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase
instructions.
CS#
Mode 3
CLK
CS#
Mode 3
CLK
0
1
2
3
4
Mode 0
DI
5
6
7
DO
1
Mode 3
Mode 0
Mode 3
Mode 0
04h
0
Mode 0
IO0
4
0
IO1
5
1
IO2
6
2
7
3
Instruction
IO3
Instruction
04h
Figure 7.4 Write Disable Instruction(SPI or QPI Mode)
7.1.5 Write Status Register (01h/31h/11h)
The Write Status Registers command allows the Status Registers to be written. Only non-volatile Status
Register bits SRP0, SEC, TB, BP2, BP1, BP0 (SR1[7:2]) CMP, LB3, LB2, LB1, QE, SRP1 (SR2[6:0]), and the
volatile bits SR3[6:0] can be written. All other Status Register bit locations are read-only and will not be
affected by the Write Status Registers command. LB[3:0] are non-volatile OTP bits; once each is set to 1, it
cannot be cleared to 0. The Status Register bits are shown in Section 6.2, Status Registers. Any reserved bits
should only be written to their default value.
To write non-volatile Status Register bits, a standard Write Enable (06h) command must previously have
been executed for the device to accept the Write Status Registers Command (Status Register bit WEL must
equal 1). Once write enabled, the command is entered by driving CS# low, sending the instruction code “01h”,
and then writing the Status Register data bytes as illustrated in Figure 7.5.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) command must
have been executed prior to the Write Status Registers command (Status Register bit WEL remains 0).
However, SRP1 and LB3, LB2, LB1, LB0 cannot be changed because of the OTP protection for these bits.
Upon power-off, the volatile Status Register bit values will be lost, and the non-volatile Status Register bit
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values will be restored when power on again.
To complete the Write Status Registers command, the CS# pin must be driven high after the eighth bit of
a data value is clocked in (CS# must be driven high on an 8-bit boundary). If this is not done the Write Status
Registers command will not be executed.
The Write Status Register instruction allows the Status Register to be written. A Write Enable instruction
must previously have been executed for the device to accept the Write Status Register Instruction (Status
Register bit WEL must equal to 1). Once write enabled, the instruction is entered by driving CS# low, sending
the instruction code “01h”, and then writing the status register data byte as illustrated in Figure 7.5.
During non-volatile Status Register write operation (06h combined with 01h/31h), after CS# is driven high,
the self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics).
While the Write Status Register cycle is in progress, the Read Status Register instruction may still be
accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and
a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status Register
cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
During volatile Status Register write operation (50h combined with 01h/31h/11h), after CS# is driven high,
the Status Register bits will be refreshed to the new values within the time period of t SHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
If CS# is driven high after the eighth clock, the Write Status Register-1 (01h) instruction will only program
the Status Register-1, the Status Register-2 will not be affected.
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Mode 0
DI
Mode 3
Mode 0
01h/31h/11h
S7~S0 in
DO
Instruction
Input Status Register
Figure 7.5a Write Status Register Instruction(SPI Mode)
CS#
Mode 3
CLK
0
1
2
3
Mode 0
Mode 0
IO0
4
0 S4 S0
IO1
5
1 S5 S1
IO2
6
2 S6 S2
7
3 S7 S3
IO3
Mode 3
InstructionSR-1/2/3
01h/31h/11h in
Figure 7.5b Write Status Register Instruction(QPI Mode)
7.2 Program and Erase Commands
7.2.1 Page Program (PP) (02h)
The Page Program instruction allows up to 256 bytes of data to be programmed at previously erased to
all 1s (FFh) memory locations. A Write Enable instruction must be executed before the device will accept the
Page Program Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the
CS# pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and at least one
data byte, into the DI pin. The CS# pin must be held low for the entire length of the instruction while data is
being sent to the device. The Page Program instruction sequence is shown in Figure 7.6.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits)
should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page
length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial
page) can be programmed without having any effect on other bytes within the same page. One condition to
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perform a partial page program is that the number of clocks cannot exceed the remaining page length. If more
than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite
previously sent data.
As with the write and erase instructions, the CS# pin must be driven high after the eighth bit of the last
byte has been latched. If this is not done the Page Program instruction will not be executed. After CS# is
driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC
Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may still
be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and
becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the
Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The
Page Program instruction will not be executed if the addressed page is protected by the Block Protect (TB,
SEC, BP2, BP1, and BP0) bits (see Status Register Memory Protection table).
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Mode 0
DI
02h
24-bit
8-bit
8-bit
DO
Instruction
Input Data 1
Address
Input Data 2
Figure 7.6a Page Program Instruction (SPI Mode)
CS#
Mode 3
CLK
0
1
2
3
4
5
7
8
9
10 11 12 13 14 15 512 513 514 515516 517518 519
Mode 3
Mode 0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
9 5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
5
1
6
2 22 18 14 10 6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
6
2
7
3 23 19 15 11 7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
7
3
IO0
4
0 20 16 12 8
IO1
5
1 21 17 13
IO2
IO3
6
Mode 0
Instruction
Address
D1
D2
D3
D4
D253
D254
D255
D256
02h
Figure 7.6b Page Program Instruction(QPI Mode)
7.2.2 Quad Input Page Program (32h)
The Quad Input Page Program instruction allows up to 256 byte of data to be programmed at previously
erased (FFh) memory locations using four pins: IO0, IO1, IO2 and IO3. The Quad Input Page Program can
improved performance for PROM Programmer and applications that have slow clock speeds
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