BJ8P509FNB

BJ8P509F PRODUCT SPECIFICATION (V1.0) 第 1 页 共 39 页 BJ8P509F V1.0 Jul,2015 Contents 1.Features.............................................................................................................................................4 2. General Description.........................................................................................................................5 3. Block Diagram................................................................................................................................ 6 4. Pin connection and Pin descriptions............................................................................................... 6 4.1 Pin Assignments.................................................................................................................... 6 4.2 Pin descriptions..................................................................................................................... 7 5.memory organization........................................................................................................................7 5.1 Program Memory Organization......................................................................................... 7 5.2 Data Memory Organization................................................................................................8 6. Functional description................................................................................................................... 10 6.1 Operational Registers.......................................................................................................... 10 6.1.1 INDF (Indirect Addressing Register).......................................................................10 6.1.2 TMR0 (Time Clock/Counter register)..................................................................... 11 6.1.3 PCL (Low Bytes of Program Counter) & Stack...................................................... 11 6.1.4 STATUS (Status Register)....................................................................................... 13 6.1.5 FSR (Indirect Data Memory Address Pointer)........................................................ 14 6.1.6 PORTB (Port Data Register)....................................................................................14 6.1.7 PCON (Power Control Register)............................................................................. 14 6.1.8 WUCON (Port B Input Change Interrupt/Wake-up Control Register)................... 15 6.1.9 PCHBUF (High Byte Buffer of Program Counter)................................................. 15 6.1.10 PDCON (Pull-down Control Register)..................................................................15 6.1.11 ODCON (Open-drain Control Register)................................................................16 6.1.12 PHCON (Pull-high Control Register)....................................................................16 6.1.13 INTEN (Interrupt Mask Register)..........................................................................17 6.1.14 INTFLAG (Interrupt Status Register)................................................................... 18 6.1.15 ACC (Accumulator)............................................................................................... 18 6.1.16 OPTION Register...................................................................................................18 6.1.17 IOSTB (Port I/O Control Register)........................................................................19 6.2 I/O Port................................................................................................................................ 19 6.3 Timer0/WDT & pre-scaler............................................................................................... 21 6.3.1 Timer0...................................................................................................................... 21 6.3.1.1 Using Timer0 with an Internal Clock : Timer mode.....................................22 6.3.1.2 Using Timer0 with an External Clock : Counter mode................................ 22 6.3.2 Watchdog Timer (WDT).......................................................................................... 22 6.3.3 pre-scaler.................................................................................................................. 23 6.4 Interrupts............................................................................................................................. 24 6.4.1 External INT Interrupt............................................................................................. 24 6.4.2 Timer0 Interrupt....................................................................................................... 24 6.4.3 Port B Input Change Interrupt..................................................................................24 6.5 Power-down Mode (SLEEP).............................................................................................. 25 第 2 页 共 39 页 BJ8P509F V1.0 Jul,2015 6.5.1 Wake-up from SLEEP Mode....................................................................................25 6.6 Reset.................................................................................................................................... 26 6.6.1 Power-up Reset Timer(PWRT)................................................................................ 26 6.6.2 Oscillator Start-up Timer(OST)............................................................................... 27 6.6.3 Reset Sequence.........................................................................................................27 6.7 Hexadecimal Convert to Decimal (HCD)...........................................................................29 6.8 Oscillator Configurations....................................................................................................30 7. Absolute maximum....................................................................................................................... 34 8. Operating conditions.................................................................................................................. 34 9. Package Dimension....................................................................................................................... 35 9.1 8-PIN DIP............................................................................................................................35 9.2 8-PIN SOP...........................................................................................................................36 9.3 6-PIN SOT23.......................................................................................................................37 9.4 8-PIN TSSOP8.................................................................................................................... 38 10.Edition statement..........................................................................................................................39 第 3 页 共 39 页 BJ8P509F V1.0 Jul,2015 1.Features  Only 42 single word instructions  All instructions are single cycle except for program branches which are two-cycle  13-bit wide instructions  All OTP ROM area GOTO instruction  All OTP ROM area subroutine CALL instruction 8-bit wide data path  5-level deep hardware stack  Operating speed: DC-20 MHz clock input DC-100 ns instruction cycle Device Pins# I/O# OTP ROM(word) Ram(Byte) BJ8P509FNB 8 6 1K 49 BJ8P509FDB 8 6 1K 49 BJ8P509FGA 6 4 1K 49 BJ8P509FTB 8 6 1K 49  Direct, indirect addressing modes for data accessing  8-bit real time clock/counter (Timer0) with 8-bit programmable pre-scaler  Internal Power-on Reset (POR)  Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR)  Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST)  On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog enable/disable control  One I/O port IOB with independent direction control  Soft-ware I/O pull-high/pull-down or open-drain control  One internal interrupt source: Timer0 overflow; Two external interrupt source: INT pin, Port B input change  Wake-up from SLEEP by INT pin or Port B input change  Power saving SLEEP mode  Built-in 8MHz, 4MHz, 1MHz, and 455KHz internal RC oscillator  Programmable Code Protection  Built-in internal RC oscillator  Selectable oscillator options: - ERC: External Resistor/Capacitor Oscillator - HF: High Frequency Crystal/Resonator Oscillator - XT: Crystal/Resonator Oscillator - LF: Low Frequency Crystal Oscillator - IRC: Internal Resistor/Capacitor Oscillator - ERIC: External Resistor/Internal Capacitor Oscillator  Wide-operating voltage range: 2.3V to 5.5V 第 4 页 共 39 页 BJ8P509F 2.General V1.0 Jul,2015 Description The BJ8P509F series is a family of low-cost, high speed, high noise immunity, OTP ROM-based 8-bit CMOS Micro-controllers. It employs a RISC architecture with only 42 instructions. All instructions are single cycle except for program branches which take two cycles. The easy to use and easy to remember instruction set reduces development time significantly. The BJ8P509F series consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer (PWRT), Oscillator Start-up Timer(OST), Watchdog Timer, OTP ROM, SRAM, tristate I/O port, I/O pull-high/open-drain/pull-down control, Power saving SLEEP mode, real time programmable clock/counter, Interrupt, Wake-up from SLEEP mode, and Code Protection for these products. There are three oscillator configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator. The BJ8P509F address 1K×13 of program memory. The BJ8P509F can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. 第 5 页 共 39 页 BJ8P509F V1.0 Jul,2015 3. Block Diagram 4. Pin connection and Pin descriptions 4.1 Pin Assignments SOT23-6 8-PIN SOP/DIP/TSSOP 第 6 页 共 39 页 BJ8P509F V1.0 Jul,2015 4.2 Pin descriptions 5.memory organization BJ8P509F 5.1 memory is organized into program memory and data memory. Program Memory Organization The BJ8P509F have a 10-bit Program Counter capable of addressing a 1K×13 program memory space. The RESET vector for the BJ8P509F is at 3FFh. The H/W interrupt vector is at 008h. And the S/W interrupt vector is at 002h. BJ8P509F supports all OTP ROM area CALL/GOTO instructions without page. FIGURE 1.1: Program Memory Map and STACK 第 7 页 共 39 页 BJ8P509F 5.2 V1.0 Jul,2015 Data Memory Organization Data memory is composed of Special Function Registers and General Purpose Registers. The General Purpose Registers are accessed either directly or indirectly through the FSR register. The Special Function Registers are registers used by the CPU and peripheral functions to control the operation of the device. 第 8 页 共 39 页 BJ8P509F V1.0 第 9 页 共 39 页 Jul,2015 BJ8P509F V1.0 Jul,2015 6. Functional description 6.1 Operational Registers 6.1.1 INDF (Indirect Addressing Register) The INDF Register is not a physical register. Any instruction accessing the INDF register can actually access the register pointed by FSR Register. Reading the INDF register itself indirectly (FSR=”0”) will read 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). The bits 5-0 of FSR register are used to select up to 64 registers (address: 00h ~ 3Fh). EXAMPLE 2.1: INDIRECT ADDRESSING ‧ Register file 38 contains the value 10h ‧ Register file 39 contains the value 0Ah ‧ Load the value 38 into the FSR Register ‧ A read of the INDF Register will return the value of 10h ‧ Increment the value of the FSR Register by one (@FSR=39h) ‧ A read of the INDR register now will return the value of 0Ah. FIGURE 2.1: Direct/Indirect Addressing 第 10 页 共 39 页 BJ8P509F V1.0 Jul,2015 6.1.2 TMR0 (Time Clock/Counter register) 6.1.3 PCL (Low Bytes of Program Counter) & Stack BJ8P509F devices have a 10-bit wide Program Counter (PC) and five-level deep 10-bit hardware push/pop stack. The low byte of PC is called the PCL register. This register is readable and writable. The high byte of PC is called the PCH register. This register contains the PC bits and is not directly readable or writable. All updates to the PCH register go through the PCHBUF register. As a program instruction is executed, the Program Counter will contain the address of the next program instruction to be executed. The PC value is increased by one, every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, the PC is provided by the GOTO instruction word. The PCL register is mapped to PC, and the PCHBUF register is not updated. For a CALL instruction, the PC is provided by the CALL instruction word. The next PC will be loaded (Pushed) onto the top of STACK. The PCL register is mapped to PC, and the PCHBUF register is not updated. For a RETIA, RETFIE, or RETURN instruction, the PC are updated (Popped) from the top of STACK. The PCL register is mapped to PC, and the PCHBUF register is not updated. For any instruction where the PCL is the destination, the PC is provided by the instruction word or ALU result. However, the PC will come from the PCHBUF bits (PCHBUF PCH). PCHBUF register is never updated with the contents of PCH. FIGURE 2.2: Loading of PC in Different Situations 第 11 页 共 39 页 BJ8P509F V1.0 第 12 页 共 39 页 Jul,2015 BJ8P509F V1.0 Jul,2015 6.1.4 STATUS (Status Register) This register contains the arithmetic status of the ALU, the RESET status. If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS Register as 000u u1uu (where u = unchanged). C : Carry/borrow bit. ADDAR, ADDIA = 1, a carry occurred. = 0, a carry did not occur. SUBAR, SUBIA = 1, a borrow did not occur. = 0, a borrow occurred. Note : A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR, RLR) instructions, this bit is loaded with either the high or low order bit of the source register. DC : Half carry/half borrow bit. ADDAR, ADDIA = 1, a carry from the 4th low order bit of the result occurred. = 0, a carry from the 4th low order bit of the result did not occur. SUBAR, SUBIA = 1, a borrow from the 4th low order bit of the result did not occur. = 0, a borrow from the 4th low order bit of the result occurred. Z : Zero bit. = 1, the result of a logic operation is zero. = 0, the result of a logic operation is not zero. PD : Power down flag bit. = 1, after power-up or by the CLRWDT instruction. = 0, by the SLEEP instruction. TO : Time overflow flag bit. = 1, after power-up or by the CLRWDT or SLEEP instruction. = 0, a watch-dog time overflow occurred. 第 13 页 共 39 页 BJ8P509F V1.0 Jul,2015 GP1:GP0 : General purpose read/write bits. RST : Bit for wake-up type. = 1, Wake-up from SLEEP on Port B input change. = 0, Wake-up from other reset types. 6.1.5 FSR (Indirect Data Memory Address Pointer) Bit5:Bit0 : Select registers address in the indirect addressing mode. See 2.1.1 for detail description. Bit7:Bit6 : Not used. Read as “1”s. 6.1.6 PORTB (Port Data Register) Reading the port (PORTB register) reads the status of the pins independent of the pin’s input/output modes. Writing to these ports will write to the port data latch. PORTB is a 8-bit port data register. And IOB3 is input only. 6.1.7 PCON (Power Control Register) Bit4:Bit0 : Not used. Read as “1”s. LVDTE : LVDT (low voltage detector) enable bit. = 0, Disable LVDT. = 1, Enable LVDT. EIS : Define the function of IOB0/INT pin. = 0, IOB0 (bi-directional I/O pin) is selected. The path of INT is masked. = 1, INT (external interrupt pin) is selected. In this case, the I/O control bit of IOB0 must be set to “1”. The path of Port B input change of IOB0 pin is masked by 第 14 页 共 39 页 BJ8P509F V1.0 Jul,2015 hardware, the status of INT pin can also be read by way of reading PORTB. WDTE : WDT (watch-dog timer) enable bit. = 0, Disable WDT. = 1, Enable WDT. 6.1.8 WUCON (Port B Input Change Interrupt/Wake-up Control Register) WUB0 : = 0, Disable the input change interrupt/wake-up function of IOB0 pin. = 1, Enable the input change interrupt/wake-up function of IOB0 pin. WUB1 : = 0, Disable the input change interrupt/wake-up function of IOB1 pin. = 1, Enable the input change interrupt/wake-up function of IOB1 pin. WUB2 : = 0, Disable the input change interrupt/wake-up function of IOB2 pin. = 1, Enable the input change interrupt/wake-up function of IOB2 pin. WUB3 : = 0, Disable the input change interrupt/wake-up function of IOB3 pin. = 1, Enable the input change interrupt/wake-up function of IOB3 pin. WUB4 : = 0, Disable the input change interrupt/wake-up function of IOB4 pin. = 1, Enable the input change interrupt/wake-up function of IOB4 pin. WUB5 : = 0, Disable the input change interrupt/wake-up function of IOB5 pin. = 1, Enable the input change interrupt/wake-up function of IOB5 pin. 6.1.9 PCHBUF (High Byte Buffer of Program Counter) Bit1:Bit0 : See 2.1.3 for detail description. Bit7:Bit2 : Not used. Read as “0”s. 6.1.10 PDCON (Pull-down Control Register) 第 15 页 共 39 页 BJ8P509F V1.0 Bit3:0 : General purpose read/write bits. /PDB0 : = 0, Enable the internal pull-down of IOB0 pin. = 1, Disable the internal pull-down of IOB0 pin. /PDB1 : = 0, Enable the internal pull-down of IOB1 pin. = 1, Disable the internal pull-down of IOB1 pin. /PDB2 : = 0, Enable the internal pull-down of IOB2 pin. = 1, Disable the internal pull-down of IOB2 pin. Bit7 : General purpose read/write bit. 6.1.11 ODCON (Open-drain Control Register) ODB0 : = 0, Disable the internal open-drain of IOB0 pin. = 1, Enable the internal open-drain of IOB0 pin. ODB1 : = 0, Disable the internal open-drain of IOB1 pin. = 1, Enable the internal open-drain of IOB1 pin. ODB2 : = 0, Disable the internal open-drain of IOB2 pin. = 1, Enable the internal open-drain of IOB2 pin. Bit3 : General purpose read/write bit. ODB4 : = 0, Disable the internal open-drain of IOB4 pin. = 1, Enable the internal open-drain of IOB4 pin. ODB5 : = 0, Disable the internal open-drain of IOB5 pin. = 1, Enable the internal open-drain of IOB5 pin. 6.1.12 PHCON (Pull-high Control Register) 第 16 页 共 39 页 Jul,2015 BJ8P509F V1.0 Jul,2015 /PHB0 : = 0, Enable the internal pull-high of IOB0 pin. = 1, Disable the internal pull-high of IOB0 pin. /PHB1 : = 0, Enable the internal pull-high of IOB1 pin. = 1, Disable the internal pull-high of IOB1 pin. /PHB2 : = 0, Enable the internal pull-high of IOB2 pin. = 1, Disable the internal pull-high of IOB2 pin. Bit3 : General purpose read/write bit. /PHB4 : = 0, Enable the internal pull-high of IOB4 pin. = 1, Disable the internal pull-high of IOB4 pin. /PHB5 : = 0, Enable the internal pull-high of IOB5 pin. = 1, Disable the internal pull-high of IOB5 pin. 6.1.13 INTEN (Interrupt Mask Register) T0IE : Timer0 overflow interrupt enable bit. = 0, Disable the Timer0 overflow interrupt. = 1, Enable the Timer0 overflow interrupt. PBIE : Port B input change interrupt enable bit. = 0, Disable the Port B input change interrupt. = 1, Enable the Port B input change interrupt . INTIE : External INT pin interrupt enable bit. = 0, Disable the External INT pin interrupt. = 1, Enable the External INT pin interrupt. Bit6:BIT3 : Not used. Read as “1”s. GIE : Global interrupt enable bit. = 0, Disable all interrupts. For wake-up from SLEEP mode through an interrupt event, the device will continue execution at the instruction after the SLEEP instruction. 第 17 页 共 39 页 BJ8P509F V1.0 Jul,2015 = 1, Enable all un-masked interrupts. For wake-up from SLEEP mode through an interrupt event, the device will branch to the interrupt address (008h). Note : When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit will be cleared by hardware to disable any further interrupts. The RETFIE instruction will exit the interrupt routine and set the GIE bit to re-enable interrupt. 6.1.14 INTFLAG (Interrupt Status Register) T0IF : Timer0 overflow interrupt flag. Set when Timer0 overflows, reset by software. PBIF : Port B input change interrupt flag. Set when Port B input changes, reset by software. INTIF : External INT pin interrupt flag. Set by rising/falling (selected by INTEDG bit (OPTION)) edge on INT pin, reset by software. Bit7:BIT3 : Not used. Read as “0”s. 6.1.15 ACC (Accumulator) Accumulator is an internal data transfer, or instruction operand holding. It can not be addressed. 6.1.16 OPTION Register By executing the OPTION instruction, the contents of the ACC Register will be transferred to the OPTION Register. The OPTION Register is a 7-bit wide, write-only register which contains various control bits to configure the Timer0/WDT pre-scaler, Timer0, and the external INT interrupt. The OPTION Register are “write-only” and are set all “1”s except INTEDG bit. 第 18 页 共 39 页 BJ8P509F V1.0 Jul,2015 PSA : pre-scaler assign bit. = 1, WDT (watch-dog timer). = 0, TMR0 (Timer0). T0SE : TMR0 source edge select bit. = 1, Falling edge on T0CKI pin. = 0, Rising edge on T0CKI pin. T0CS : TMR0 clock source select bit. = 1, External T0CKI pin. Pin IOB2/T0CKI is forced to be an input even if IOST IOB2 = “0”. = 0, internal instruction clock cycle. INTEDG : Interrupt edge select bit. = 1, interrupt on rising edge of INT pin. = 0, interrupt on falling edge of INT pin. Bit7 : Not used. 6.1.17 IOSTB (Port I/O Control Register) The Port I/O Control Registers are loaded with the contents of the ACC Register by executing the IOST R (06h) instruction. A ‘1’ from a IOST Register bit puts the corresponding output driver in hi-impedance state (input mode). A ‘0’ enables the output buffer and puts the contents of the output data latch on the selected pins (output mode). The IOST Registers are “write-only” and are set (output drivers disabled) upon RESET. 6.2 I/O Port Port B is bi-directional tristate I/O port. Port B is an 8-pin I/O port. Please note that IOB3 is an input only pin. All I/O pins have data direction control register (IOSTB) which 第 19 页 共 39 页 BJ8P509F V1.0 Jul,2015 can configure these pins as output or input. The exceptions are IOB3 which is input only and IOB2 which may be controlled by the T0CS bit (OPTION). IOB and IOB have its corresponding pull-high control bits (PHCON register) to enable the weak internal pull-high. The weak pull-high is automatically turned off when the pin is configured as an output pin. IOB have its corresponding pull-down control bits (PDCON register) to enable the weak internal pull-down. The weak pull-down is automatically turned off when the pin is configured as an output pin. IOB and IOB have its corresponding open-drain control bits (ODCON register) to enable the open-drain output when these pins are configured to be an output pin. IOB also provides the input change interrupt/wake-up function. Each pin has its corresponding input change interrupt/wake-up enable bits (WUCON) to select the input change interrupt/wake-up source. The IOB0 is also an external interrupt input signal by setting the EIS bit (PCON). In this case, IOB0 input change interrupt/wake-up function will be disabled by hardware even if it is enabled by software. The CONFIGURATION words can set several I/Os to alternate functions. When acting as alternate functions the pins will read as “0” during port read. FIGURE 2.3: Block Diagram of I/O PIN s 第 20 页 共 39 页 BJ8P509F V1.0 Jul,2015 6.3 Timer0/WDT & pre-scaler 6.3.1 Timer0 The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the 第 21 页 共 39 页 BJ8P509F V1.0 Jul,2015 internal clock or by an external clock source (T0CKI pin). 6.3.1.1 Using Timer0 with an Internal Clock : Timer mode Timer mode is selected by clearing the T0CS bit (OPTION). In timer mode, the timer0 register (TMR0) will increment every instruction cycle (without pre-scaler). If TMR0 register is written, the increment is inhibited for the following two cycles. 6.3.1.2 Using Timer0 with an External Clock : Counter mode Counter mode is selected by setting the T0CS bit (OPTON). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKl. The incrementing edge is determined by the source edge select bit T0SE (OPTION). The external clock requirement is due to internal phase clock (To sc) synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization. When no pre-scaler is used, the external clock input is the same as the pre-scaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the pre-scaler output on the T2 and T4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC and low for at least 2 To sc. When a pre-scaler is used, the external clock input is divided by the asynchronous pre-scaler. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc divided by the pre-scaler value. 6.3.2 Watchdog Timer (WDT) The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. So the WDT will still run even if the clock on the OSCI and OSCO pins is turned off, such as in SLEEP mode. During normal operation or in SLEEP mode, a WDT time-out will cause the device reset and the TO bit (STATUS) will be cleared. The WDT can be disabled by clearing the control bit WDTE (PCON) to “0”. The WDT has a nominal time-out period of 18 ms, 4.5ms, 288ms or 72ms selected by SUT bits of configuration word (without pre-scaler). If a longer time-out period is desired, a pre-scaler with a division ratio of up to 1:128 can be assigned to the WDT controlled by the OPTION register. Thus, the longest time-out period is approximately 36.8 seconds. The CLRWDT instruction clears the WDT and the pre-scaler, if assigned to the WDT, and prevents it from timing out 第 22 页 共 39 页 BJ8P509F V1.0 Jul,2015 and generating a device reset. The SLEEP instruction resets the WDT and the pre-scaler, if assigned to the WDT. This gives the maximum SLEEP time before a WDT Wake-up Reset. 6.3.3 pre-scaler An 8-bit counter (down counter) is available as a pre-scaler for the Timer0, or as a post scaler for the Watchdog Timer (WDT). Note that the pre-scaler may be used by either the Timer0 module or the WDT, but not both. Thus, a pre-scaler assignment for the Timer0 means that there is no pre-scaler for the WDT, and vice-verse. The PSA bit (OPTION) determines pre-scaler assignment. The PS bits (OPTION) determine pre-scaler ratio. When the pre-scaler is assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the pre-scaler. When it is assigned to WDT, a CLRWDT instruction will clear the pre-scaler along with the WDT. The pre-scaler is neither readable nor writable. On a RESET, the pre-scaler contains all ‘1’s. To avoid an unintended device reset, CLRWDT or CLRR TMR0 instructions must be executed when changing the pre-scaler assignment from Timer0 to the WDT, and vice-verse. FIGURE 2.4: Block Diagram of The Timer0/WDT pre-scaler 第 23 页 共 39 页 BJ8P509F V1.0 Jul,2015 6.4 Interrupts The BJ8P509F series has up to three sources of interrupt: 1. External interrupt INT pin. 2. TMR0 overflow interrupt. 3. Port B input change interrupt (pins IOB7:IOB0). INTFLAG is the interrupt flag register that recodes the interrupt requests in the relative flags. A global interrupt enable bit, GIE (INTEN), enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. Individual interrupts can be enabled/disabled through their corresponding enable bits in INTEN register regardless of the status of the GIE bit. When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit will be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address 008h. The interrupt flag bits must be cleared by software before re-enabling GIE bit to avoid recursive interrupts. The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt. The flag bit (except PBIF bit) in INTFLAG register is set by interrupt event regardless of the status of its mask bit. Reading the INTFLAG register will be the logic AND of INTFLAG and INTEN. When an interrupt is generated by the INT instruction, the next instruction will be fetched from address 002h. 6.4.1 External INT Interrupt External interrupt on INT pin is rising or falling edge triggered selected by INTEDG (OPTION). When a valid edge appears on the INT pin the flag bit INTIF (INTFLAG) is set. This interrupt can be disabled by clearing INTIE bit (INTEN). The INT pin interrupt can wake-up the system from SLEEP condition, if bit INTIE was set before going to SLEEP. If GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared, the program will execute next PC after wake-up. 6.4.2 Timer0 Interrupt An overflow (Ff h 00h) in the TMR0 register will set the flag bit T0IF (INTFLAG). This interrupt can be disabled by clearing T0IE bit (INTEN). 6.4.3 Port B Input Change Interrupt 第 24 页 共 39 页 BJ8P509F V1.0 Jul,2015 An input change on IOB set flag bit PBIF (INTFLAG). This interrupt can be disabled by clearing PBIE bit (INTEN). Before the port B input change interrupt is enabled, reading PORTB (any instruction accessed to PORTB, including read/write instructions) is necessary. Any pin which corresponding WUB ON bit (WUCON) is cleared to “0” or configured as output or IOB0 pin configured as INT pin will be excluded from this function. The port B input change interrupt also can wake-up the system from SLEEP condition, if bit PBIE was set before going to SLEEP. And GIE bit also decides whether or not the processor branches to the interrupt vector following wake-up. If GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared, the program will execute next PC after wake-up. 6.5 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. When SLEEP instruction is executed, the PD bit (STATUS) is cleared, the TO bit is set, the watchdog timer will be cleared and keeps running, and the oscillator driver is turned off. All I/O pins maintain the status they had before the SLEEP instruction was executed. 6.5.1 Wake-up from SLEEP Mode The device can wake-up from SLEEP mode through one of the following events: 1. RSTB reset. 2. WDT time-out reset (if enabled). 3. Interrupt from RB0/INT pin, or PORTB change interrupt. External RSTB reset and WDT time-out reset will cause a device reset. The PD and TO bits can be used to determine the cause of device reset. The PD bit is set on power-up and is cleared when SLEEP instruction is executed. The TO bit is cleared if a WDT time-out occurred. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set. Wake-up is regardless of the GIE bit. If GIE bit is cleared, the device will continue execution at the instruction after the SLEEP instruction. If the GIE bit is set, the device will branch to the interrupt address (008h). In HF or LF oscillation mode, the system wake-up delay time is 18/4.5/288/72ms (selected by SUT bits of configuration word) plus 16 oscillator cycles time. And in IRC/ERIC or ERC oscillation mode, the system wake-up delay time is 140us. 第 25 页 共 39 页 BJ8P509F V1.0 Jul,2015 6.6 Reset BJ8P509F devices may be RESET in one of the following ways: 1. Power-on Reset (POR) 2. Brown-out Reset (BOR) 3. RSTB Pin Reset 4. WDT time-out Reset Some registers are not affected in any RESET condition. Their status is unknown on Power-on Reset and unchanged in any other RESET. Most other registers are reset to a “reset state” on Power-on Reset, RSTB or WDT Reset. A Power-on RESET pulse is generated on-chip when V dd rise is detected. To use this feature, the user merely ties the RSTB pin to V dd. On-chip Low Voltage Detector (LVD) places the device into reset when V dd is below a fixed voltage. This ensures that the device does not continue program execution outside the valid operation V dd range. Brown-out RESET is typically used in AC line or heavy loads switched applications. A RSTB or WDT Wake-up from SLEEP also results in a device RESET, and not a continuation of operation before SLEEP. The TO and PD bits (STATUS) are set or cleared depending on the different reset conditions. 6.6.1 Power-up Reset Timer(PWRT) The Power-up Reset Timer provides a nominal 18/4.5/288/72ms (selected by SUT bits of configuration word) (or 140us, varies based on oscillator selection and reset condition) delay after Power-on Reset (POR), Brown-out Reset (BOR), RSTB Reset or WDT time-out Reset. The device is kept in reset state as long as the PWRT is active. The PWDT delay will vary from device to device due to V dd, temperature, and process variation. 第 26 页 共 39 页 BJ8P509F V1.0 Jul,2015 6.6.2 Oscillator Start-up Timer(OST) The OST timer provides a 16 oscillator cycle delay (from OSCI input) after the PWRT delay (18/4.5/288/72ms) is over in HF or LF oscillation mode. This delay ensures that the X’TAL oscillator or resonator has started and stabilized. The device is kept in reset state as long as the OST is active. This counter only starts incrementing after the amplitude of the OSCI signal reaches the oscillator input thresholds. 6.6.3 Reset Sequence When Power-on Reset (POR), Brown-out Reset (BOR), RSTB Reset or WDT time-out Reset is detected, the reset sequence is as follows: 1. The reset latch is set and the PWRT & OST are cleared. 2. When the internal POR, BOR, RSTB Reset or WDT time-out Reset pulse is finished, then the PWRT begins counting. 3. After the PWRT time-out, the OST is activated. 4. And after the OST delay is over, the reset latch will be cleared and thus end the on-chip reset signal. In HF or LF oscillation mode, the totally system reset delay time is 18/4.5/288/72ms plus 16 oscillator cycle time. And in IRC/ERIC or ERC oscillation mode, the totally system reset delay time is 18/4.5/288/72ms after Power-on Reset (POR), Brown-out Reset (BOR), or 140us after RSTB Reset or WDT time-out Reset. FIGURE 2.5: Simplified Block Diagram of on-chip Reset Circuit 第 27 页 共 39 页 BJ8P509F V1.0 第 28 页 共 39 页 Jul,2015 BJ8P509F V1.0 Jul,2015 6.7 Hexadecimal Convert to Decimal (HCD) Decimal format is another number format for BJ8P509F. When the content of the data memory has been assigned as decimal format, it is necessary to convert the results to decimal format after the execution of ALU instructions. When the decimal converting operation is processing, all of the operand data (including the contents of the data memory (RAM), accumulator (ACC), immediate data, and look-up table) should be in the decimal format, or the results of conversion will be incorrect. Instruction DAA can convert the ACC data from hexadecimal to decimal format after any addition operation and restored to ACC. The conversion operation is illustrated in example 2.2. EXAMPLE 2.2: DAA CONVERSION MOVIA 90h ; Set immediate data = decimal format number “90” (ACC 90h) MOVAR 30h ;Load immediate data “90” to data memory address 30H MOVIA 10h ;Set immediate data = decimal format number “10” (ACC 10h) ADDAR 30h, 0 ;Contents of the data memory address 30H and ACC are binary-added ;the result loads to the ACC (ACC A0h, C 0) DAA ;Convert the content of ACC to decimal format, and restored to ACC ;The result in the ACC is “00” and the carry bit C is “1”. This represents the ;decimal number “100” Instruction DAS can convert the ACC data from hexadecimal to decimal format after any subtraction operation and restored to ACC. The conversion operation is illustrated in example 2.3. EXAMPLE 2.3: DAS CONVERSION MOVIA 10h ;Set immediate data = decimal format number “10” (ACC 10h) MOVAR 30h ;Load immediate data “10” to data memory address 30H MOVIA 20h ;Set immediate data = decimal format number “20” (ACC 20h) SUBAR 30h,0 ;Contents of the data memory address 30H and ACC are binary-subtracted ;the result loads to the ACC (ACC F0h, C 0) DAS ;Convert the content of ACC to decimal format, and restored to ACC ;The result in the ACC is “90” and the carry bit C is “0”. This represents the ;decimal number “ -10” 第 29 页 共 39 页 BJ8P509F V1.0 Jul,2015 6.8 Oscillator Configurations BJ8P509F can be operated in six different oscillator modes. three configuration bits (Fo sc) to select the appropriate modes: ‧ ERC: External Resistor/Capacitor Oscillator ‧ HF: High Frequency Crystal/Resonator Oscillator ‧ XT: Crystal/Resonator Oscillator ‧ LF: Low Frequency Crystal Oscillator ‧ IRC: Internal Resistor/Capacitor Oscillator ‧ ERIC: External Resistor/Internal Capacitor Oscillator Users can program In LF, XT, or HF modes, a crystal or ceramic resonator in connected to the OSCI and OSCO pins to establish oscillation. When in LF, XT, or HF modes, the devices can have an external clock source drive the OSCI pin. The ERC device option offers additional cost savings for timing insensitive applications. The RC oscillator frequency is a function of the resistor (Rex t) and capacitor (C ext), the operating temperature, and the process parameter. The IRC/ERIC device option offers largest cost savings for timing insensitive applications. These devices offer 4 different internal RC oscillator frequency, 8MHz, 4MHz, 1MHz, and 455KHz, which is selected by two configuration bits (RCM). Or user can change the oscillator frequency with external resistor. The ERIC oscillator frequency is a function of the resistor (Rex t), the operating temperature, and the process parameter. FIGURE 2.6: HF, or LF Oscillator Modes (Crystal Operation or Ceramic Resonator) FIGURE 2.7: HF, or LF Oscillator Modes (External Clock Input Operation) 第 30 页 共 39 页 BJ8P509F V1.0 FIGURE 2.8: ERC Oscillator Mode (External RC Oscillator) FIGURE 2.9: ERIC Oscillator Mode FIGURE 2.10: (External R, Internal C Oscillator) IRC Oscillator Mode (Internal R, Internal C Oscillator) 第 31 页 共 39 页 Jul,2015 BJ8P509F 6.9 V1.0 Configurations Word 第 32 页 共 39 页 Jul,2015 BJ8P509F V1.0 第 33 页 共 39 页 Jul,2015 BJ8P509F V1.0 7. Absolute maximum 8. Ambient Operating Temperature 0℃ to +70℃ Store Temperature -65℃ to +150℃ DC Supply Voltage (VDD) 0V to +6.0V Input Voltage with respect to Ground (VSS) -0.3V to (VDD + 0.3)V Operating conditions DC Supply Voltage +2.3V to +5.5V Operating Temperature 0℃ to +70℃ 第 34 页 共 39 页 Jul,2015 BJ8P509F V1.0 9. Package Dimension 9.1 8-PIN DIP 第 35 页 共 39 页 Jul,2015 BJ8P509F V1.0 9.2 8-PIN SOP 第 36 页 共 39 页 Jul,2015 BJ8P509F V1.0 9.3 6-PIN SOT23 第 37 页 共 39 页 Jul,2015 BJ8P509F V1.0 9.4 8-PIN TSSOP8 第 38 页 共 39 页 Jul,2015 BJ8P509F V1.0 10.Edition statement Edition Date Content VER 1.0 Jul ,2015 First Edition 第 39 页 共 39 页 Jul,2015