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NRF9160-SIBA-R

NRF9160-SIBA-R

  • 厂商:

    NORDIC(北欧)

  • 封装:

    Module

  • 描述:

    NRF9160-SIBA-R

  • 数据手册
  • 价格&库存
NRF9160-SIBA-R 数据手册
nRF9160 Product Specification v2.0 4418_1315 v2.0 / 2020-09-21 nRF9160 features Features: Microcontroller: LTE modem: • ARM Cortex -M33 • Transceiver and baseband • 243 EEMBC CoreMark score running from flash memory • 3GPP LTE release 13 Cat-M1 and Cat-NB1 compliant • Data watchpoint and trace (DWT), embedded trace macrocell (ETM), and • 3GPP release 13 coverage enhancement instrumentation trace macrocell (ITM) • 3GPP LTE release 14 Cat-NB2 compliant • Serial wire debug (SWD) • GPS receiver • Trace port • 1 MB flash • 256 kB low leakage RAM • ARM Trustzone • ARM Cryptocell 310 • Up to 4x SPI master/slave with EasyDMA • Up to 4x I2C compatible two-wire master/slave with EasyDMA • Up to 4x UART (CTS/RTS) with EasyDMA • I2S with EasyDMA • Digital microphone interface (PDM) with EasyDMA • 4x pulse width modulator (PWM) unit with EasyDMA • 12-bit, 200 ksps ADC with EasyDMA - eigth configurable channels with • • 3x 32-bit timer with counter mode • 2x real-time counter (RTC) • Programmable peripheral interconnect (PPI) • 32 general purpose I/O pins • Single supply voltage: 3.0 – 5.5 V • All necessary clock sources integrated • Package: 10 × 16 x 1.04 mm LGA • Up to 23 dBm output power • -108 dBm sensitivity (LTE-M) for low band, -107 dBm for mid band • • Single 50 Ω antenna interface LTE band support in hardware: • Cat-M1: B1, B2, B3, B4, B5, B8, B12, B13, B14, B17, B18, B19, B20, B25, B26, B28, B66 • Cat-NB1/NB2: B1, B2, B3, B4, B5, B8, B12, B13, B17, B19, B20, B25, B26, B28, B66 • programmable gain • GPS L1 C/A supported RF transceiver for global coverage Supports SIM and eSIM with an ETSI TS 102 221 compatible UICC interface • Power saving features: DRX, eDRX, PSM • IP v4/v6 stack • Secure socket (TLS/DTLS) API Current consumption @ 3.7 V: • Power saving mode (PSM) floor current: 2.7 µA • eDRX @ 82.91s: 18 µA in Cat-M1, 37 µA in Cat-NB1 (UICC included) Applications: • Sensor networks • Industrial • Logistics and asset tracking • Retail and monitor devices • Smart energy • Medical devices • Smart building automation • Wearables • Smart agriculture 4418_1315 v2.0 ii Contents nRF9160 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii 1 Revision history. 2 About this document. 3 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 11 2.1 Document status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Peripheral chapters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Register tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Fields and values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Permissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4.1 DUMMY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 12 12 12 12 13 Product overview. 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Peripheral ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Peripherals with shared ID . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 Peripheral registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.4 Bit set and clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.5 Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.6 Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.7 Publish and subscribe . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.8 Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.10 Secure/non-secure peripherals . . . . . . . . . . . . . . . . . . . . . . . . 14 14 15 16 17 17 17 17 18 18 18 18 19 Application core. 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 CPU and support module configuration . . . . . . . . . . . . . . . . . . . . . 4.1.2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Peripheral access control capabilities . . . . . . . . . . . . . . . . . . . . . . 4.3 VMC — Volatile memory controller . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 NVMC — Non-volatile memory controller . . . . . . . . . . . . . . . . . . . . . . 4.4.1 Writing to flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 Erasing a secure page in flash . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.3 Erasing a non-secure page in flash . . . . . . . . . . . . . . . . . . . . . . . 4.4.4 Writing to user information configuration registers (UICR) . . . . . . . . . . . . . 4.4.5 Erase all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.6 NVMC protection mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.7 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.9 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 FICR — Factory information configuration registers . . . . . . . . . . . . . . . . . . 4418_1315 v2.0 iii 20 20 21 21 23 24 27 27 28 29 29 30 30 30 30 30 31 32 35 35 5 6 4.5.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 UICR — User information configuration registers . . . . . . . . . . . . . . . . . . . 4.6.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.1 EasyDMA error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7.2 EasyDMA array list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 AHB multilayer interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 41 41 45 46 46 47 Power and clock management. 48 . . . . . . . . . . . . . . . . . . . . . . . 5.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 POWER — Power control . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 CLOCK — Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 REGULATORS — Voltage regulators control . . . . . . . . . . . . . . . . . . . . 48 48 50 51 53 56 58 59 64 64 70 77 Peripherals. 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 CRYPTOCELL — ARM TrustZone CryptoCell 310 . . . . . . . . . . . . . . . . . . . . 79 6.1.1 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.1.2 Always-on (AO) power domain . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.1.3 Lifecycle state (LCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.1.4 Cryptographic key selection . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.1.5 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.1.6 Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.1.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.1.8 Host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.2 DPPI - Distributed programmable peripheral interconnect . . . . . . . . . . . . . . . 86 6.2.1 Subscribing to and publishing on channels . . . . . . . . . . . . . . . . . . . . 87 6.2.2 DPPI configuration (DPPIC) . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.2.3 Connection examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.2.4 Special considerations for a system implementing TrustZone for Cortex-M processors . . . 90 6.2.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3 EGU — Event generator unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.4 GPIO — General purpose input/output . . . . . . . . . . . . . . . . . . . . . . . 97 6.4.1 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.4.2 Pin sense mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.4.3 GPIO security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.4.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.4.5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.5 GPIOTE — GPIO tasks and events . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.5.1 Pin events and tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.5.2 Port event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.5.3 Tasks and events pin configuration . . . . . . . . . . . . . . . . . . . . . . 108 6.5.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.5.5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 4418_1315 v2.0 iv 6.6 IPC — Interprocessor communication . . . . . . . . . . . . . . . . . . . . . . . 6.6.1 IPC and PPI connections . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.3 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 I2S — Inter-IC sound interface . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.1 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.2 Transmitting and receiving . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.3 Left right clock (LRCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.4 Serial clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.5 Master clock (MCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.6 Width, alignment and format . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.7 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.8 Module operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.9 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.11 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 KMU — Key management unit . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.1 Functional view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.2 Access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.3 Protecting the UICR content . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.4 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 PDM — Pulse density modulation interface . . . . . . . . . . . . . . . . . . . . . 6.9.1 Master clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.2 Module operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.3 Decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.4 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.5 Hardware example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.7 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.8 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 PWM — Pulse width modulation . . . . . . . . . . . . . . . . . . . . . . . . 6.10.1 Wave counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.2 Decoder with EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.3 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.4 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 RTC — Real-time counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.1 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.2 Resolution versus overflow and the prescaler . . . . . . . . . . . . . . . . . 6.11.3 Counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.4 Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.5 Tick event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.6 Event control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.7 Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.8 Task and event jitter/delay . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12 SAADC — Successive approximation analog-to-digital converter . . . . . . . . . . . . 6.12.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.2 Digital output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.3 Analog inputs and channels . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.4 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.5 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4418_1315 v2.0 v 113 115 116 119 119 120 120 121 121 122 122 124 126 128 128 139 139 140 140 141 141 145 149 149 150 150 150 151 152 152 160 161 161 165 172 172 172 183 184 184 185 185 186 186 186 188 190 198 198 198 199 200 200 202 6.12.6 Resistor ladder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.7 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.8 Acquisition time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.9 Limits event monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.11 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.12 Performance factors . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13 SPIM — Serial peripheral interface master with EasyDMA . . . . . . . . . . . . . . 6.13.1 SPI master transaction sequence . . . . . . . . . . . . . . . . . . . . . . . 6.13.2 Master mode pin configuration . . . . . . . . . . . . . . . . . . . . . . . 6.13.3 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.4 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.5 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.7 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14 SPIS — Serial peripheral interface slave with EasyDMA . . . . . . . . . . . . . . . . 6.14.1 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.2 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.3 SPI slave operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.4 Semaphore operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.5 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14.7 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15 SPU — System protection unit . . . . . . . . . . . . . . . . . . . . . . . . . 6.15.1 General concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15.2 Flash access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15.3 RAM access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15.4 Peripheral access control . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15.5 Pin access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15.6 DPPI access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15.7 External domain access control . . . . . . . . . . . . . . . . . . . . . . . 6.15.8 TrustZone for Cortex-M ID allocation . . . . . . . . . . . . . . . . . . . . . 6.15.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16 TIMER — Timer/counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16.1 Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16.2 Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16.3 Task delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16.4 Task priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16.5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16.6 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17 TWIM — I2C compatible two-wire interface master with EasyDMA . . . . . . . . . . . 6.17.1 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.2 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.3 Master write sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.4 Master read sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.5 Master repeated start sequence . . . . . . . . . . . . . . . . . . . . . . . 6.17.6 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.7 Master mode pin configuration . . . . . . . . . . . . . . . . . . . . . . . 6.17.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.9 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17.10 Pullup resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18 TWIS — I2C compatible two-wire interface slave with EasyDMA . . . . . . . . . . . . 6.18.1 Shared resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.2 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4418_1315 v2.0 vi 203 204 204 205 206 223 224 224 225 226 227 227 227 228 239 240 241 241 241 243 244 244 257 259 259 260 263 266 268 268 270 271 272 281 282 282 282 282 283 290 290 292 292 292 293 294 295 295 296 310 311 311 313 313 6.18.3 TWI slave responding to a read command . . . . . . . . . . . . . . . . . . . 6.18.4 TWI slave responding to a write command . . . . . . . . . . . . . . . . . . . 6.18.5 Master repeated start sequence . . . . . . . . . . . . . . . . . . . . . . . 6.18.6 Terminating an ongoing TWI transaction . . . . . . . . . . . . . . . . . . . . 6.18.7 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.8 Slave mode pin configuration . . . . . . . . . . . . . . . . . . . . . . . . 6.18.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18.10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19 UARTE — Universal asynchronous receiver/transmitter with EasyDMA . . . . . . . . . 6.19.1 EasyDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19.2 Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19.3 Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19.4 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19.5 Using the UARTE without flow control . . . . . . . . . . . . . . . . . . . . 6.19.6 Parity and stop bit configuration . . . . . . . . . . . . . . . . . . . . . . . 6.19.7 Low power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19.8 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19.9 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19.10 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20 WDT — Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20.1 Reload criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20.2 Temporarily pausing the watchdog . . . . . . . . . . . . . . . . . . . . . . 6.20.3 Watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20.5 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 LTE modem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 SIM card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 LTE modem coexistence interface . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 LTE modem RF control external interface . . . . . . . . . . . . . . . . . . . . . . 7.5 RF front-end interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.7.1 Key RF parameters for Cat-M1 . . . . . . . . . . . . . . . . . . . . . . . . 7.7.2 Key RF parameters for Cat-NB1 and Cat-NB2 . . . . . . . . . . . . . . . . . . 7.7.3 Receiver parameters for Cat-M1 . . . . . . . . . . . . . . . . . . . . . . . 7.7.4 Receiver parameters for Cat-NB1 and Cat-NB2 . . . . . . . . . . . . . . . . . . 7.7.5 Transmitter parameters for Cat-M1 . . . . . . . . . . . . . . . . . . . . . . 7.7.6 Transmitter parameters for Cat-NB1 and Cat-NB2 . . . . . . . . . . . . . . . . 8 GPS receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Debug and trace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.1 Special consideration regarding debugger access . . . . . . . . . . . . . . . . . 9.1.2 DAP - Debug access port . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.3 Debug interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.4 Real-time debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.5 Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1.7 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4418_1315 v2.0 vii 314 315 316 317 317 317 317 331 331 332 332 333 335 335 335 335 336 336 354 354 354 355 355 355 359 360 360 361 362 363 364 364 364 364 365 366 366 366 366 367 367 369 369 369 370 370 371 371 371 372 9.2 CTRL-AP - Control access port . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.1 Reset request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2 Erase all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.3 Mailbox interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.4 Disabling erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.5 Debugger registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 TAD - Trace and debug control . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Hardware and layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1 LGA pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 16.00 x 10.50 mm package . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Reference circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Schematic SIxA LGA127 . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 Reflow conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating conditions. 372 373 373 373 374 374 378 380 380 385 385 385 388 388 388 389 390 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 11.1 VDD_GPIO considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 12 Absolute maximum ratings. 13 Ordering information. 13.1 13.2 13.3 13.4 13.5 . . . . . . . . . . . . . . . . . . . . . . . . 392 . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 IC marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Box labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Code ranges and values . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Regulatory information. 15 Legal notices. 4418_1315 v2.0 393 393 394 395 396 . . . . . . . . . . . . . . . . . . . . . . . . . . 398 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 viii 1 Revision history Date Version Description September 2020 2.0 Updated the following: • Updated format of all figures • Removed deprecated columns in all register tables • CPU on page 20 - Updated CoreMark® values • Power supply monitoring on page 51 - Added LTE modem startup and shutdown information to Device startup times • Current consumption on page 58: • Updated application domain, LTE modem, and GPS receiver information • • Added LTE modem PSM TAU event energy and duration information • Updated parameters PWM — Pulse width modulation on page 161 - Added code example for typical configuration • SPU — System protection unit on page 259 - Editorial updates • UARTE — Universal asynchronous receiver/transmitter with EasyDMA on page 331 - Added parameters • Pin assignments on page 385 - Updated description for SIM_DET pin • Absolute maximum ratings on page 392 - Updated ATEX compliance parameters April 2020 1.2 • Ordering information on page 393 - Updated Order code • Legal notices on page 399 - Updated text for Life support applications Updated the following: • Operating conditions on page 391 – Updated with MAGPIO, COEX, MIPI RFFE, SIMIF pins voltage supply references • Absolute maximum ratings on page 392: • Updated with GPS antenna input level and ATEX compliance information • • • • Decreased maximum storage temperature to 95 °C Power and clock management: • Updated ENABLE pin information • Added SYSTEM DISABLED mode information • Updated Pin reset voltage level and pull-up information Current consumption on page 58: • Updated peripherals consumption information • Added SYSTEM DISABLED mode information • Updated LTE modem Cat-M1 information • Added Cat-NB1 information • Updated GPS receiver information LTE modem: • Added MAGPIO, COEX, and MIPI RFFE timing information • Added NB2 mode and COEX features availability information • Added information on SIM card power down support during eDRX idle mode 4418_1315 v2.0 9 Revision history Date Version Description • GPS receiver on page 367 - updated with performance information • Pin reset on page 56 - updated description and added schematic • Current consumption on page 58 - I GPS_SINGLE value increased due to design changes to improve performance in poor conditions Added: • October 2019 1.1 Reflow conditions on page 390 Updated: • Debug and trace Overview on page 369: Added debug access port. Updated SDK version • Memory on page 21: Added a reference • LGA pin assignments on page 385: Several updates • Operating conditions on page 391: Changed chapter name. Updated MAGPIO values. Updated VDD_GPIO restrictions. • Ordering information on page 393: Updated Product options Added: • May 2019 4418_1315 v2.0 1.0 Reference circuitry on page 388 First release 10 2 About this document This document is organized into chapters that are based on the modules and peripherals available in the IC. The relevant Product Specification version for each nRF9160 revision is described by the nRF9160 Compatibility Matrix. 2.1 Document status The document status reflects the level of maturity of the document. Document name Description Objective Product Specification (OPS) Applies to document versions up to 1.0. This document contains target specifications for product development. Product Specification (PS) Applies to document versions 1.0 and higher. This document contains final product specifications. Nordic Semiconductor ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Table 1: Defined document names 2.2 Peripheral chapters Every peripheral has a unique capitalized name or an abbreviation of its name, e.g. TIMER, used for identification and reference. This name is used in chapter headings and references, and it will appear in the ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer to identify the peripheral. The peripheral instance name, which is different from the peripheral name, is constructed using the peripheral name followed by a numbered postfix, starting with 0, for example, TIMER0. A postfix is normally only used if a peripheral can be instantiated more than once. The peripheral instance name is also used in the CMSIS to identify the peripheral instance. The chapters describing peripherals may include the following information: • A detailed functional description of the peripheral • Register configuration for the peripheral • Electrical specification tables, containing performance data which apply for the operating conditions described in Peripheral chapters on page 11. 4418_1315 v2.0 11 About this document 2.3 Register tables Individual registers are described using register tables. These tables are built up of two sections. The first three colored rows describe the position and size of the different fields in the register. The following rows describe the fields in more detail. 2.3.1 Fields and values The Id (Field Id) row specifies the bits that belong to the different fields in the register. If a field has enumerated values, then every value will be identified with a unique value id in the Value Id column. A blank space means that the field is reserved and read as undefined, and it also must be written as 0 to secure forward compatibility. If a register is divided into more than one field, a unique field name is specified for each field in the Field column. The Value Id may be omitted in the single-bit bit fields when values can be substituted with a Boolean type enumerator range, e.g. true/false, disable(d)/enable(d), on/ off, and so on. Values are usually provided as decimal or hexadecimal. Hexadecimal values have a 0x prefix, decimal values have no prefix. The Value column can be populated in the following ways: • Individual enumerated values, for example 1, 3, 9. • Range of values, e.g. [0..4], indicating all values from and including 0 and 4. • Implicit values. If no values are indicated in the Value column, all bit combinations are supported, or alternatively the field's translation and limitations are described in the text instead. If two or more fields are closely related, the Value Id, Value, and Description may be omitted for all but the first field. Subsequent fields will indicate inheritance with '..'. A feature marked Deprecated should not be used for new designs. 2.3.2 Permissions Different fields in a register might have different access permissions enforced by hardware. The access permission for each register field is documented in the Access column in the following ways: Access Description Hardware behavior RO Read-only Field can only be read. A write will be ignored. WO Write-only Field can only be written. A read will return an undefined value. RW Read-write Field can be read and written multiple times. W1 Write-once Field can only be written once per reset. Any subsequent write will be ignored. A read will return an undefined value. RW1 Read-write-once Field can be read multiple times, but only written once per reset. Any subsequent write will be ignored. Table 2: Register field permission schemes 2.4 Registers Register Offset Description DUMMY 0x514 Example of a register controlling a dummy feature Table 3: Register overview 4418_1315 v2.0 12 About this document 2.4.1 DUMMY Address offset: 0x514 Example of a register controlling a dummy feature Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D D D D Reset 0x00050002 ID R/W Field A RW FIELD_A B RW C C C B 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value ID Value Description Disabled 0 The example feature is disabled NormalMode 1 The example feature is enabled in normal mode ExtendedMode 2 The example feature is enabled along with extra functionality Example of a read-write field with several enumerated values FIELD_B Example of a deprecated read-write field This field is deprecated. C D RW RW Disabled 0 The override feature is disabled Enabled 1 The override feature is enabled ValidRange [2..7] FIELD_C Example of a read-write field with a valid range of values Example of allowed values for this field FIELD_D 4418_1315 v2.0 A A Example of a read-write field with no restriction on the values 13 3 Product overview 3.1 Introduction The nRF9160 is a low-power cellular IoT (Internet of Things) solution, integrating an ARM® Cortex®-M33 processor with advanced security features, a range of peripherals, as well as a complete LTE modem compliant with 3GPP LTE release 13 Cat-M1 and Cat-NB1, and 3GPP LTE release 14 Cat-NB1 and Cat-NB2 standards. The ARM Cortex-M33 processor is exclusively for user application software, and it offers 1 MB of flash and 256 kB of RAM dedicated to this use. The M33 application processor shares the power, clock and peripheral architecture with Nordic Semiconductor nRF51 and nRF52 Series of PAN/LAN SoCs, ensuring minimal porting efforts. The peripheral set offers a variety of analog and digital functionality enabling single-chip implementation of a wide range of cellular IoT (Internet of Things) applications. ARM TrustZone technology, Cryptocell 310 and supporting blocks for system protection and key management, are embedded to enable advanced security needed for IoT applications. The LTE modem integrates a very flexible transceiver that in hardware supports frequency range from 700 to 2200 MHz (through a single 50 Ω antenna pin), and a baseband processor handling LTE Cat-M1/ NB1/NB2 protocol layers L1-L3 as well as IP upper layers offering secure socket API for the application. The modem is supported by pre-qualified software builds available for free from Nordic Semiconductor. On specific nRF9160 device variants, the LTE modem supports A-GPS operation during sleep intervals in the LTE operation (RRC idle and PSM modes). Note: Cat-NB2 is supported in LTE modem HW, but needs modem firmware support to get enabled. Please refer to nRF9160 modem firmware release notes found under nRF91 FW binaries downloads concerning availability of Cat-NB2 feature support". 3.2 Block diagram This block diagram illustrates the overall system. Arrows with white heads indicate signals that share physical pins with other signals. 4418_1315 v2.0 14 Product overview ETM trace ITM trace nRF9160 Debug ETM AHB-AP CPU RAM2 RAM3 slave slave RAM1 slave RAM0 slave RAM3 slave RAM2 slave slave SysTick master NVIC RAM1 slave RAM0 ARM CORTEX-M33 AHB multilayer SCL AHB TO APB BRIDGE CODE FICR UICR LTE-M modem master DPPI KMU SPU master ARM TrustZone CryptoCell 310 TWIS [0..3] EasyDMA ANT - LTE / ANT - GPS NVMC UARTE [0..3] EasyDMA SDA master RTS CTS TXD RXD EasyDMA slave SAADC slave AIN0 – AIN7 AREF0 – AREF1 slave slave GPIO slave P0 (P0.0 – P0.31) USIM / GPS DMA master master 1.8 V USIM APB GPIOTE TWIM [0..3] EasyDMA SCK MOSI MISO CSN MISO MOSI SCK master TIMER [0..2] IPC SPIM [0..3] EasyDMA PWM[0..3] master WDT POWER master CLOCK PDM EasyDMA master Clock control MCK LRCK SCL SDOUT SDIN OUT0-OUT3 EasyDMA master SPIS [0..3] EasyDMA CLK DIN RTC [0..1] APB SCL SDA High frequency clock sources High frequency clock sources I2S REGULATORS EasyDMA master Figure 1: Block diagram 3.3 Peripheral interface Peripherals are controlled by the CPU through configuration registers, as well as task and event registers. Task registers are inputs, enabling the CPU and other peripherals to initiate a functionality. Event registers are outputs, enabling a peripheral to trigger tasks in other peripherals and/or the CPU by tying events to CPU interrupts. 4418_1315 v2.0 15 Product overview Channel inputs from DPPI Peripheral EN SUBSCRIBE n TASK n CHIDX write k OR SHORTS task Peripheral core event INTEN m EVENT m IRQ signal to NVIC EN PUBLISH m CHIDX Channel outputs to DPPI Figure 2: Peripheral interface The distributed programmable peripheral interconnect (DPPI) feature enables peripherals to connect events to tasks without CPU intervention. Note: For more information on DPPI and the DPPI channels, see DPPI - Distributed programmable peripheral interconnect on page 86. 3.3.1 Peripheral ID Every peripheral is assigned a fixed block of 0x1000 bytes of address space, which is equal to 1024 x 32 bit registers. See Instantiation on page 24 for more information about which peripherals are available and where they are located in the address map. There is a direct relationship between peripheral ID and base address. For example, a peripheral with base address 0x40000000 is assigned ID=0, a peripheral with base address 0x40001000 is assigned ID=1, and a peripheral with base address 0x4001F000 is assigned ID=31. Peripherals may share the same ID, which may impose one or more of the following limitations: • Shared registers or common resources • Limited availability due to mutually exclusive operation; only one peripheral in use at a time 4418_1315 v2.0 16 Product overview • Enforced peripheral behavior when switching between peripherals (disable the first peripheral before enabling the second) 3.3.2 Peripherals with shared ID In general (with the exception of ID 0), peripherals sharing an ID and base address may not be used simultaneously. Only one peripheral can be enabled at a given ID. When switching between two peripherals sharing an ID, the following should be performed to prevent unwanted behavior: 1. 2. 3. 4. Disable the previously used peripheral. Disable any publish/subscribe connection to the DPPI system for the peripheral that is being disabled. Clear all bits in the INTEN register, i.e. INTENCLR = 0xFFFFFFFF. Explicitly configure the peripheral being enabled. Do not rely on inherited configuration from the disabled peripheral. 5. Enable the now configured peripheral. For a list of which peripherals that share an ID see Instantiation on page 24. 3.3.3 Peripheral registers Most peripherals feature an ENABLE register. Unless otherwise specified, the peripheral registers must be configured before enabling the peripheral. PSEL registers need to be set before a peripheral is enabled or started. Updating PSEL registers while the peripheral is running has no effect. In order to connect a peripheral to a different GPIO, the peripheral must be disabled, the PSEL register updated, and the peripheral re-enabled. It takes four CPU cycles between the PSEL register update and the connection between a peripheral and a GPIO becoming effective. Note: Note that the peripheral must be enabled before tasks and events can be used. Most of the register values are lost during System OFF or when a reset is triggered. Some registers will retain their values in System OFF or for some specific reset sources. These registers are marked as retained in the register description for a given peripheral. For more information on their behavior, see chapter Reset on page 56. 3.3.4 Bit set and clear Registers with multiple single-bit bit fields may implement the set-and-clear pattern. This pattern enables firmware to set and clear individual bits in a register without having to perform a read-modify-write operation on the main register. This pattern is implemented using three consecutive addresses in the register map, where the main register is followed by dedicated SET and CLR registers (in that exact order). In the main register, the SET register sets individual bits and the CLR register clears them. Writing '1' to a bit in the SET or CLR register will set or clear the same bit in the main register respectively. Writing '0' to a bit in the SET or CLR register has no effect. Reading the SET or CLR register returns the value of the main register. Note: The main register may not be visible and therefore not directly accessible in all cases. 3.3.5 Tasks Tasks are used to trigger actions in a peripheral, such as to start a particular behavior. A peripheral can implement multiple tasks with each task having a separate register in that peripheral's task register group. 4418_1315 v2.0 17 Product overview A task is triggered when firmware writes '1' to the task register, or when the peripheral itself or another peripheral toggles the corresponding task signal. See the figure Peripheral interface on page 16. 3.3.6 Events Events are used to notify peripherals and the CPU about events that have happened, for example a state change in a peripheral. A peripheral may generate multiple events, where each event has a separate register in that peripheral's event register group. An event is generated when the peripheral itself toggles the corresponding event signal, and the event register is updated to reflect that the event has been generated, see figure Peripheral interface on page 16. An event register is cleared when a '0' is written to it by firmware. Events can be generated by the peripheral even when the event register is set to '1'. 3.3.7 Publish and subscribe Events and tasks from different peripherals can be connected together through the DPPI system using the PUBLISH and SUBSCRIBE registers in each peripheral. See Peripheral interface on page 16. An event can be published onto a DPPI channel by configuring the event's PUBLISH register. Similarly, a task can subscribe to a DPPI channel by configuring the task's SUBSCRIBE register. See DPPI - Distributed programmable peripheral interconnect on page 86 for details. 3.3.8 Shortcuts A shortcut is a direct connection between an event and a task within the same peripheral. If a shortcut is enabled, the associated task is automatically triggered when its associated event is generated. Using shortcuts is equivalent to making the connection outside the peripheral and through the DPPI. However, the propagation delay when using shortcuts is usually shorter than the propagation delay through the DPPI. Shortcuts are predefined, which means that their connections cannot be configured by firmware. Each shortcut can be individually enabled or disabled through the shortcut register, one bit per shortcut, giving a maximum of 32 shortcuts for each peripheral. 3.3.9 Interrupts All peripherals support interrupts which are generated by events. A peripheral only occupies one interrupt, and the interrupt number follows the peripheral ID. For example, the peripheral with ID=4 is connected to interrupt number 4 in the nested vectored interrupt controller (NVIC). Using registers INTEN, INTENSET, and INTENCLR, every event generated by a peripheral can be configured to generate that peripheral's interrupt. Multiple events can be enabled to generate interrupts simultaneously. To resolve the correct interrupt source, the event registers in the event group of peripheral registers will indicate the source. Some peripherals implement only INTENSET and INTENCLR registers, and the INTEN register is not available on those peripherals. See the individual peripheral chapters for details. In all cases, reading back the INTENSET or INTENCLR register returns the same information as in INTEN. Each event implemented in the peripheral is associated with a specific bit position in the INTEN, INTENSET, and INTENCLR registers. The relationship between tasks, events, shortcuts, and interrupts is illustrated in figure Peripheral interface on page 16. 4418_1315 v2.0 18 Product overview 3.3.9.1 Interrupt clearing and disabling Interrupts should always be cleared by writing '0' to the corresponding EVENT register. Until cleared, interrupts will immediately be re-triggered and cause software interrupt service routines to be executed repeatedly. Because the clearing of the EVENT register may take a number of CPU clock cycles, the program should perform a read from the EVENT register that has been cleared before exiting the interrupt service routine. This will ensure that the EVENT clearing has taken place before the interrupt service routine is exited. Care should be taken to ensure that the compiler does not remove the read operation as an optimization. Similarly, when disabling an interrupt inside an interrupt service routine, the program should perform a read from the INTEN or INTENCLR registers to ensure that the interrupt is disabled before exiting the interrupt service routine. 3.3.10 Secure/non-secure peripherals For some peripherals, the security configuration can change from secure to non-secure, or vice versa. Care must be taken when changing the security configuration of a peripheral, to prevent security information leakage and ensure correct operation. The following sequence should be followed, where applicable, when configuring and changing the security settings of a peripheral in the SPU — System protection unit on page 259: 1. 2. 3. 4. 5. 6. 7. Stop peripheral operation Disable the peripheral Remove pin connections Disable DPPI connections Clear sensitive registers (e.g. writing back default values) Change peripheral security setting in the SPU — System protection unit on page 259 Re-enable the peripheral Note: Changing security settings on a peripheral during runtime is not advisable. 4418_1315 v2.0 19 4 Application core 4.1 CPU The ARM Cortex-M33 processor has a 32-bit instruction set (Thumb-2 technology) that implements a superset of 16 and 32-bit instructions to maximize code density and performance. This processor implements several features that enable energy-efficient arithmetic and high-performance signal processing, including: • • • • • • • Digital signal processing (DSP) instructions Single-cycle multiply and accumulate (MAC) instructions Hardware divide 8- and 16-bit single instruction, multiple data (SIMD) instructions Single-precision floating-point unit (FPU) Memory Protection Unit (MPU) ARM TrustZone for ARMv8-M The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for the ARM Cortex processor series is implemented and available for the M33 CPU. Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handling events at configurable priority levels via the nested vectored interrupt controller (NVIC). Executing code from internal or external flash will have a wait state penalty. The instruction cache can be enabled to minimize flash wait states when fetching instructions. For more information on cache, see Cache on page 31. The section Electrical specification on page 21 shows CPU performance parameters including the wait states in different modes, CPU current and efficiency, and processing power and efficiency based on the CoreMark benchmark. 4.1.1 CPU and support module configuration The ARM Cortex-M33 processor has a number of CPU options and support modules implemented on the device. 4418_1315 v2.0 20 Application core Option / Module Description Implemented Core options NVIC Nested vectored interrupt controller PRIORITIES Priority bits 3 WIC Wake-up interrupt controller NO Endianness Memory system endianness Little endian DWT Data watchpoint and trace YES MPU_NS Number of non-secure memory protection unit (MPU) regions 16 MPU_S Number of secure MPU regions 16 SAU Number of security attribution unit (SAU) regions 0, see SPU for more information about Modules secure regions. FPU Floating-point unit YES DSP Digital signal processing extension YES ARMv8-M TrustZone ARMv8-M security extensions YES CPIF Co-processor interface NO ETM Embedded trace macrocell YES ITM Instrumentation trace macrocell YES MTB Micro trace buffer NO CTI Cross trigger interface YES BPU Breakpoint unit YES HTM AMBA AHB trace macrocell NO 4.1.2 Electrical specification 4.1.2.1 CPU performance The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU is executing the CoreMark benchmark. It includes power regulator and clock base currents. All other blocks are IDLE. Symbol Description Min. WFLASH CPU wait states, running from flash, cache disabled 0 Typ. Max. 4 WFLASHCACHE CPU wait states, running from flash, cache enabled 0 2 WRAM CPU wait states, running from RAM Units 0 CMFLASH CoreMark , running from flash, cache enabled 243 CoreMark CMFLASH/MHz CoreMark per MHz, running from flash, cache enabled 3.79 CoreMark/ CMFLASH/mA CoreMark per mA, running from flash, cache enabled, DC/ 110.45 1 MHz DC CoreMark/ mA 4.2 Memory The application microcontroller has embedded 1024 kB flash and 256 kB RAM for application code and data storage. As illustrated in Memory layout on page 22, both CPU and EasyDMA are able to access RAM via the AHB multilayer interconnect. See AHB multilayer interconnect on page 47 and EasyDMA on page 45 for more information about AHB multilayer interconnect and EasyDMA respectively. The LTE modem can access all application MCU memory, but typically a small portion of RAM is dedicated to data exchange between application MCU and the modem baseband controller. 1 Using IAR compiler 4418_1315 v2.0 21 Application core EasyDMA AHB master CPU ARM® Cortex®-M33 DMA bus System bus Modem Code bus Peripheral Section 3 RAM7 AHB slave APB2APB Section 2 Section 1 Section 0 Section 3 RAM6 AHB slave Section 2 Section 1 Section 0 Section 3 RAM5 AHB slave Section 2 Section 1 Section 0 Section 3 RAM4 AHB slave Section 2 Section 1 Section 0 Section 3 RAM3 AHB slave Section 2 Section 1 Section 0 Section 3 RAM2 AHB slave RAM1 AHB slave Section 2 Section 1 0x2003 4000 0x2003 2000 0x2003 0000 0x2002 E000 0x2002 C000 0x2002 A000 0x2002 8000 0x2002 6000 0x2002 4000 0x2002 2000 0x2002 0000 0x2001 E000 0x2001 C000 0x2001 A000 0x2001 8000 0x2001 6000 0x2001 4000 0x2000 E000 Section 2 Section 1 Section 2 Section 1 Page 255 0x2000 C000 0x2000 A000 0x2000 8000 0x2000 6000 0x2000 4000 0x2000 2000 0x2000 0000 0x000F F000 Cache AHB slave Page 3..254 0x0000 3000 Page 2 0x0000 2000 Page 1 0x0000 1000 Page 0 0x0000 0000 Figure 3: Memory layout RAM - Random access memory RAM can be read and written an unlimited number of times by the CPU and the EasyDMA. Each RAM AHB slave is connected to one or more RAM sections. See Memory layout on page 22 for more information. 22 0x2003 6000 Section 3 Section 0 4418_1315 v2.0 0x2003 8000 0x2001 2000 0x2001 0000 Section 3 AHB multilayer interconnect 0x2003 C000 0x2003 A000 Section 0 Section 0 RAM0 AHB slave 0x2003 E000 Application core The RAM blocks power states and retention states in System ON and System OFF modes are controlled by the VMC. Flash - Non-volatile memory Flash can be read an unlimited number of times by the CPU and is accessible via the AHB interface connected to the CPU, see Memory layout on page 22 for more information. There are restrictions on the number of times flash can be written and erased, and also on how it can be written. For more information, see Absolute maximum ratings on page 392. Writing to flash is managed by the nonvolatile memory controller (NVMC). 4.2.1 Memory map All memory and registers are found in the same address space, as illustrated in the device memory map below. 4418_1315 v2.0 23 Application core System address map Address map 0xFFFF FFFF Private peripheral bus 0xE000 0000 Device 0xC000 0000 ROM table MCU ROM table 0xE00F F000 0xE00F E000 Reserved (MTB) CTI ETM Reserved (TPIU) 0xE004 3000 0xE004 2000 0xE004 1000 0xE004 0000 SCS BPU DWT ITM 0xE000 E000 0xE000 2000 0xE000 1000 0xE000 0000 AHB peripherals 0x5080 0000 Device 0xA000 0000 RAM 0x8000 0000 RAM 0x6000 0000 Secure peripheral APB peripherals 0x5000 0000 Non-secure peripheral AHB peripherals APB peripherals 0x4000 0000 0X5000 0000 0x4080 0000 0x4000 0000 SRAM 0x2000 0000 Code 0x0000 0000 SRAM 0x2000 0000 UICR 0x00FF 8000 FICR 0x00FF 0000 FLASH 0x0000 0000 Figure 4: Memory map Some of the registers are retained (their values kept). Read more about retained registers in Retained registers on page 57 and Reset behavior on page 57. 4.2.2 Instantiation ID Base address Peripheral Instance Secure mapping DMA security Description 3 0x50003000 SPU SPU S System Protection Unit 4418_1315 v2.0 NA 24 Application core ID 4 5 5 6 8 8 8 8 8 9 9 9 9 9 10 10 10 10 10 11 11 11 11 11 13 14 15 Base address 0x50004000 0x40004000 0x50005000 0x40005000 0x50005000 0x40005000 0x50006000 0x50008000 0x40008000 0x50008000 0x40008000 0x50008000 0x40008000 0x50008000 0x40008000 0x50008000 0x40008000 0x50009000 0x40009000 0x50009000 0x40009000 0x50009000 0x40009000 0x50009000 0x40009000 0x50009000 0x40009000 0x5000A000 0x4000A000 0x5000A000 0x4000A000 0x5000A000 0x4000A000 0x5000A000 0x4000A000 0x5000A000 0x4000A000 0x5000B000 0x4000B000 0x5000B000 0x4000B000 0x5000B000 0x4000B000 0x5000B000 0x4000B000 0x5000B000 0x4000B000 0x5000D000 0x5000E000 0x4000E000 0x5000F000 0x4000F000 4418_1315 v2.0 Peripheral REGULATORS CLOCK POWER CTRLAPPERI SPIM SPIS TWIM TWIS UARTE SPIM SPIS TWIM TWIS UARTE SPIM SPIS TWIM TWIS UARTE SPIM SPIS TWIM TWIS UARTE GPIOTE SAADC TIMER Instance REGULATORS : S REGULATORS : NS CLOCK : S CLOCK : NS POWER : S POWER : NS CTRL_AP_PERI SPIM0 : S SPIM0 : NS SPIS0 : S SPIS0 : NS TWIM0 : S TWIM0 : NS TWIS0 : S TWIS0 : NS UARTE0 : S UARTE0 : NS SPIM1 : S SPIM1 : NS SPIS1 : S SPIS1 : NS TWIM1 : S TWIM1 : NS TWIS1 : S TWIS1 : NS UARTE1 : S UARTE1 : NS SPIM2 : S SPIM2 : NS SPIS2 : S SPIS2 : NS TWIM2 : S TWIM2 : NS TWIS2 : S TWIS2 : NS UARTE2 : S UARTE2 : NS SPIM3 : S SPIM3 : NS SPIS3 : S SPIS3 : NS TWIM3 : S TWIM3 : NS TWIS3 : S TWIS3 : NS UARTE3 : S UARTE3 : NS GPIOTE0 SAADC : S SAADC : NS TIMER0 : S TIMER0 : NS Secure mapping DMA security Description US NA Regulator configuration US NA Clock control US NA Power control S NA CTRL-AP-PERI US SA SPI master 0 US SA SPI slave 0 US SA Two-wire interface master 0 US SA Two-wire interface slave 0 US SA US SA SPI master 1 US SA SPI slave 1 US SA Two-wire interface master 1 US SA Two-wire interface slave 1 US SA US SA SPI master 2 US SA SPI slave 2 US SA Two-wire interface master 2 US SA Two-wire interface slave 2 US SA US SA SPI master 3 US SA SPI slave 3 US SA Two-wire interface master 3 US SA Two-wire interface slave 3 US SA S NA Secure GPIO tasks and events US SA Analog to digital converter US NA Timer 0 25 Universal asynchronous receiver/transmitter with EasyDMA 0 Universal asynchronous receiver/transmitter with EasyDMA 1 Universal asynchronous receiver/transmitter with EasyDMA 2 Universal asynchronous receiver/transmitter with EasyDMA 3 Application core ID 16 17 20 21 23 24 27 28 29 30 31 32 33 34 35 36 38 40 42 44 49 57 57 58 Base address 0x50010000 0x40010000 0x50011000 0x40011000 0x50014000 0x40014000 0x50015000 0x40015000 0x50017000 0x40017000 0x50018000 0x40018000 0x5001B000 0x4001B000 0x5001C000 0x4001C000 0x5001D000 0x4001D000 0x5001E000 0x4001E000 0x5001F000 0x4001F000 0x50020000 0x40020000 0x50021000 0x40021000 0x50022000 0x40022000 0x50023000 0x40023000 0x50024000 0x40024000 0x50026000 0x40026000 0x50028000 0x40028000 0x5002A000 0x4002A000 0x5002C000 0x4002C000 0x40031000 0x50039000 0x40039000 0x50039000 0x40039000 0x5003A000 0x4003A000 Peripheral TIMER TIMER RTC RTC DPPIC WDT EGU EGU EGU EGU EGU EGU PWM PWM PWM PWM PDM I2S IPC FPU GPIOTE KMU NVMC VMC Instance TIMER1 : S TIMER1 : NS TIMER2 : S TIMER2 : NS RTC0 : S RTC0 : NS RTC1 : S RTC1 : NS DPPIC : S DPPIC : NS WDT : S WDT : NS EGU0 : S EGU0 : NS EGU1 : S EGU1 : NS EGU2 : S EGU2 : NS EGU3 : S EGU3 : NS EGU4 : S EGU4 : NS EGU5 : S EGU5 : NS PWM0 : S PWM0 : NS PWM1 : S PWM1 : NS PWM2 : S PWM2 : NS PWM3 : S PWM3 : NS PDM : S PDM : NS I2S : S I2S : NS IPC : S IPC : NS FPU : S FPU : NS GPIOTE1 KMU : S KMU : NS NVMC : S NVMC : NS VMC : S VMC : NS Secure mapping DMA security Description US NA Timer 1 US NA Timer 2 US NA Real time counter 0 US NA Real time counter 1 SPLIT NA DPPI configuration US NA Watchdog timer US NA Event generator unit 0 US NA Event generator unit 1 US NA Event generator unit 2 US NA Event generator unit 3 US NA Event generator unit 4 US NA Event generator unit 5 US SA Pulse width modulation unit 0 US SA Pulse width modulation unit 1 US SA Pulse width modulation unit 2 US SA Pulse width modulation unit 3 US SA US SA Inter-IC Sound US NA Interprocessor communication US NA Floating-point unit NS NA Non Secure GPIO tasks and events SPLIT NA Key management unit SPLIT NA Non-volatile memory controller US NA Volatile memory controller Pulse density modulation (digital microphone) interface 64 0x50840000 CC_HOST_RGF CC_HOST_RGF S NSA Host platform interface 64 0x50840000 CRYPTOCELL CRYPTOCELL S NSA CryptoCell sub-system control interface SPLIT NA General purpose input and output 66 0x50842500 0x40842500 GPIO P0 : S P0 : NS N/A 0x00FF0000 FICR FICR S NA Factory information configuration N/A 0x00FF8000 UICR UICR S NA User information configuration 4418_1315 v2.0 26 Application core ID Base address N/A 0xE0080000 Peripheral Instance Secure mapping DMA security Description TAD TAD S Trace and debug control NA Table 4: Instantiation table 4.2.3 Peripheral access control capabilities Information about the peripheral access control capabilities can be found in the instantiation table. The instantiation table has two columns containing the information about access control capabilities for a peripheral: • Secure mapping: This column defines configuration capabilities for TrustZone-M secure attribute. • DMA security: This column indicates if the peripheral has DMA capabilities, and if DMA transfer can be assigned to a different security attribute than the peripheral itself. For details on options in secure mapping column and DMA security column, see the following tables respecitvely. Abbreviation Description NS Non-secure: This peripheral is always accessible as a non-secure peripheral. S Secure: This peripheral is always accessible as a secure peripheral. US User-selectable: Non-secure or secure attribute for this peripheral is defined by the PERIPHID[0].PERM register. SPLIT Both non-secure and secure: The same resource is shared by both secure and nonsecure code. Table 5: Secure mapping column options Abbreviation Description NA Not applicable: Peripheral has no DMA capability. NSA No separate attribute: Peripheral has DMA, and DMA transfers always have the same security attribute as assigned to the peripheral. SA Separate attribute: Peripheral has DMA, and DMA transfers can have a different security attribute than the one assigned to the peripheral. Table 6: DMA security column options 4.3 VMC — Volatile memory controller The volatile memory controller (VMC) provides power control of RAM blocks. Each of the available RAM blocks, which can contain multiple RAM sections, can be turned on or off independently in System ON mode, using the RAM[n]registers. These registers also control if a RAM block, or some of its sections, is retained in System OFF mode. See Memory chapter for more information about RAM blocks and sections. Note: Powering up a RAM block takes typically 10 cycles. Thus, it is recommended reading the POWER register before accessing a RAM block that has been recently powered on. 4418_1315 v2.0 27 Application core 4.3.1 Registers Base address Peripheral Instance 0x5003A000 VMC : S 0x4003A000 VMC VMC : NS Secure mapping DMA security Description Configuration US NA Volatile memory controller Table 7: Instances Register Offset RAM[n].POWER 0x600 Security Description RAMn power control register RAM[n].POWERSET 0x604 RAMn power control set register RAM[n].POWERCLR 0x608 RAMn power control clear register Table 8: Register overview 4.3.1.1 RAM[n].POWER (n=0..7) Address offset: 0x600 + (n × 0x10) RAMn power control register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E Reset 0x0000FFFF ID R/W Field A-D RW S[i]POWER (i=0..3) D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Keep RAM section Si of RAM n on or off in System ON mode All RAM sections will be switched off in System OFF mode E-H RW Off 0 Off On 1 On S[i]RETENTION (i=0..3) Keep retention on RAM section Si of RAM n when RAM section is switched off Off 0 Off On 1 On 4.3.1.2 RAM[n].POWERSET (n=0..7) Address offset: 0x604 + (n × 0x10) RAMn power control set register When read, this register will return the value of the POWER register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E Reset 0x0000FFFF ID R/W Field A-D W S[i]POWER (i=0..3) E-H W Value ID Value On 1 Description Keep RAM section Si of RAM n on or off in System ON mode On S[i]RETENTION (i=0..3) Keep retention on RAM section Si of RAM n when RAM section is switched off On 4418_1315 v2.0 D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 On 28 Application core 4.3.1.3 RAM[n].POWERCLR (n=0..7) Address offset: 0x608 + (n × 0x10) RAMn power control clear register When read, this register will return the value of the POWER register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E Reset 0x0000FFFF ID R/W Field A-D W S[i]POWER (i=0..3) E-H W D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Off 1 Description Keep RAM section Si of RAM n on or off in System ON mode Off S[i]RETENTION (i=0..3) Keep retention on RAM section Si of RAM n when RAM section is switched off Off 1 Off 4.4 NVMC — Non-volatile memory controller The non-volatile memory controller (NVMC) is used for writing and erasing of the internal flash memory and the user information configuration register (UICR). The NVMC is a split security peripheral. This means that when the NVMC is configured as non-secure, only a subset of the registers is available from the non-secure code. See SPU — System protection unit on page 259 and Registers on page 32 for more details. When the NVMC is configured to be a secure peripheral, only secure code has access. Before a write can be performed, the NVMC must be enabled for writing in CONFIG.WEN. Similarly, before an erase can be performed, the NVMC must be enabled for erasing in CONFIG.EEN, see CONFIG on page 33. The user must make sure that writing and erasing are not enabled at the same time. Failing to do so may result in unpredictable behavior. 4.4.1 Writing to flash When writing is enabled, in CONFIG register for secure region, or in CONFIGNS register for non-secure region, flash is written by writing a full 32-bit word to a word-aligned address in flash. Secure code has access to both secure and non-secure regions, by using the appropriate configuration of CONFIG and CONFIGNS registers. Non-secure code, in constrast, has access to non-secure regions only. Thus, non-secure code only needs CONFIGNS. The NVMC is only able to write '0' to erased bits in flash, that is bits set to '1'. It cannot write a bit back to '1'. As illustrated in Memory on page 21, flash is divided into multiple pages. The same address in flash can only be written nWRITE number of times before a page erase must be performed. Only full 32-bit words can be written to flash using the NVMC interface. To write less than 32 bits to flash, write the data as a word, and set all the bits that should remain unchanged in the word to '1'. Note that the restriction about the number of writes (see above) still applies in this case. The time it takes to write a word to flash is specified by tWRITE. If CPU executes code from flash while the NVMC is writing to flash, the CPU will be stalled. Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a bus fault. 4418_1315 v2.0 29 Application core 4.4.2 Erasing a secure page in flash When secure region erase is enabled (in CONFIG register), a flash page can be erased by writing 0xFFFFFFFF into the first 32-bit word in a flash page. Page erase is only applicable to the code area in the flash and does not work with UICR. After erasing a flash page, all bits in the page are set to '1'. The time it takes to erase a page is specified by tERASEPAGE. The CPU is stalled if the CPU executes code from the flash while the NVMC performs the erase operation. See Partial erase of a page in flash for information on splitting the erase time in smaller chunks. 4.4.3 Erasing a non-secure page in flash When non-secure region erase is enabled, a non-secure flash page can be erased by writing 0xFFFFFFFF into the first 32-bit word of the flash page. Page erase is only applicable to the code area in the flash and does not work with UICR. After erasing a flash page, all bits in the page are set to '1'. The time it takes to erase a page is specified by tERASEPAGE. The CPU is stalled if the CPU executes code from the flash while the NVMC performs the erase operation. 4.4.4 Writing to user information configuration registers (UICR) User information configuration registers (UICR) are written in the same way as flash. After UICR has been written, the new UICR configuration will only take effect after a reset. UICR is only accessible by secure code. Any write from non-secure code will be faulted. In order to lock the chip after uploading non-secure code, a simple sequence must be followed: 1. Block access to secure code by setting UICR register SECUREAPPROTECT on page 42 to protected 2. Use the WRITEUICRNS on page 35 register, via non-secure debugger, in order to set APPROTECT (APPROTECT is automatically written to 0x00000000 by the NVMC) UICR can only be written nWRITE number of times before an erase must be performed using ERASEALL. The time it takes to write a word to the UICR is specified by tWRITE. The CPU is stalled if the CPU executes code from the flash while the NVMC is writing to the UICR. 4.4.5 Erase all When erase is enabled, the whole flash and UICR can be erased in one operation by using the ERASEALL register. ERASEALL will not erase the factory information configuration registers (FICR). This functionality can be blocked by some configuration of the UICR protection bits, see the table NVMC protection (1 - Enabled, 0 - Disabled, X - Don't care) on page 31. The time it takes to perform an ERASEALL on page 33 command is specified by tERASEALL. The CPU is stalled if the CPU executes code from the flash while the NVMC performs the erase operation. 4.4.6 NVMC protection mechanisms This chapter describes the different protection mechanisms for the non-volatile memory. 4.4.6.1 NVMC blocking UICR integrity is assured through use of multiple levels of protection. UICR protection bits can be configured to allow or block certain operations. The table below shows the different status of UICR protection bits, and which operations are allowed or blocked. 4418_1315 v2.0 30 Application core UICR protection bit status SECUREAPPROTECT APPROTECT ERASEPROTECT NVMC protection CTRL-AP NVMC ERASEALL ERASEALL 0 0 0 Available Available 1 X 0 Available Blocked X 1 0 Available Blocked X X 1 Blocked Blocked Table 9: NVMC protection (1 - Enabled, 0 - Disabled, X - Don't care) Note: Erase can still be performed through CTRL-AP, regardless of the above settings. See CTRL-AP - Control access port on page 372 for more information. Uploading code with secure debugging blocked Non-secure code can program non-secure flash regions. In order to perform these operations, the NVMC has the following non-secure registers: CONFIGNS, READY and READYNEXT. Register CONFIGNS on page 34 works as the CONFIG register but it is used only for non-secure transactions. Both page erase and writing inside the flash require a write transaction (see Erasing a secure page in flash on page 30 or Erasing a non-secure page in flash on page 30). Because of this, the SPU — System protection unit on page 259 will guarantee that the non-secure code cannot write inside a secure page, since the transaction will never reach the NVMC controller. 4.4.6.2 NVMC power failure protection NVMC power failure protection is possible through use of power-fail comparator that is monitoring power supply. If the power-fail comparator is enabled, and the power supply voltage is below VPOF threshold, the powerfail comparator will prevent the NVMC from performing erase or write operations in non-volatile memory (NVM). If a power failure warning is present at the start of an NVM write or erase operation, the NVMC will block the operation and a bus error will be signalled. If a power failure warning occurs during an ongoing NVM write operation, the NVMC will try to finish the operation. And if the power failure warning persists, consecutive NVM write operations will be blocked by the NVMC, and a bus error will be signalled. If a power failure warning occurs during an NVM erase operation, the operation is aborted and a bus error is signalled. 4.4.7 Cache An instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC. See Memory map on page 23 for the location of flash. A cache hit is an instruction fetch from the cache, and it has a 0 wait-state delay. The number of waitstates for a cache miss, where the instruction is not available in the cache and needs to be fetched from flash, depends on the processor frequency, see CPU parameter W_FLASHCACHE. Enabling the cache can increase the CPU performance, and reduce power consumption by reducing the number of wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache draws current when enabled. If the reduction in average current due to reduced flash accesses is larger than the cache power requirement, the average current to execute the program code will be reduced. When disabled, the cache does not draw current and its content is not retained. 4418_1315 v2.0 31 Application core It is possible to enable cache profiling to analyze the performance of the cache for your program using the register ICACHECNF. When profiling is enabled, registers IHIT and IMISS are incremented for every instruction cache hit or miss respectively. 4.4.8 Registers Base address Peripheral Instance 0x50039000 NVMC : S NVMC 0x40039000 Secure mapping DMA security SPLIT NVMC : NS Description Configuration Non-volatile memory NA controller Table 10: Instances Register Offset Security Description READY 0x400 NS Ready flag READYNEXT 0x408 NS Ready flag CONFIG 0x504 S Configuration register ERASEALL 0x50C S Register for erasing all non-volatile user memory ERASEPAGEPARTIALCFG 0x51C S Register for partial erase configuration ICACHECNF 0x540 S I-code cache configuration register IHIT 0x548 S I-code cache hit counter IMISS 0x54C S I-code cache miss counter CONFIGNS 0x584 NS WRITEUICRNS 0x588 NS Non-secure APPROTECT enable register Table 11: Register overview 4.4.8.1 READY Address offset: 0x400 Ready flag Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000001 ID R/W Field A R READY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description NVMC is ready or busy Busy 0 NVMC is busy (on-going write or erase operation) Ready 1 NVMC is ready 4.4.8.2 READYNEXT Address offset: 0x408 Ready flag Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000001 ID R/W Field A R READYNEXT 4418_1315 v2.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description NVMC can accept a new write operation Busy 0 NVMC cannot accept any write operation Ready 1 NVMC is ready 32 Application core 4.4.8.3 CONFIG Address offset: 0x504 Configuration register Note: This register is one hot Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A Reset 0x00000000 ID R/W Field A RW WEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. Ren 0 Read only access Wen 1 Write enabled Een 2 Erase enabled PEen 4 Partial erase enabled 4.4.8.4 ERASEALL Address offset: 0x50C Register for erasing all non-volatile user memory Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W ERASEALL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Erase all non-volatile memory including UICR registers. Note that erasing must be enabled by setting CONFIG.WEN = Een before the non-volatile memory can be erased. NoOperation 0 No operation Erase 1 Start chip erase 4.4.8.5 ERASEPAGEPARTIALCFG Address offset: 0x51C Register for partial erase configuration Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A Reset 0x0000000A ID R/W Field A RW DURATION 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 Value ID Value Description Duration of the partial erase in milliseconds The user must ensure that the total erase time is long enough for a complete erase of the flash page 4.4.8.6 ICACHECNF Address offset: 0x540 4418_1315 v2.0 33 Application core I-code cache configuration register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CACHEEN B RW A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Cache enable Disabled 0 Disable cache. Invalidates all cache entries. Enabled 1 Enable cache Disabled 0 Disable cache profiling Enabled 1 Enable cache profiling CACHEPROFEN Cache profiling enable 4.4.8.7 IHIT Address offset: 0x548 I-code cache hit counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW HITS Value ID Value Description Number of cache hits Write zero to clear 4.4.8.8 IMISS Address offset: 0x54C I-code cache miss counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW MISSES Value ID Value Description Number of cache misses Write zero to clear 4.4.8.9 CONFIGNS Address offset: 0x584 Note: This register is one hot 4418_1315 v2.0 34 Application core Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000000 ID R/W Field A RW WEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. Ren 0 Read only access Wen 1 Write enabled Een 2 Erase enabled 4.4.8.10 WRITEUICRNS Address offset: 0x588 Non-secure APPROTECT enable register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B B B B B B B B B B B B B B B B B B B B B B B B B B B B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A W SET B W Value ID Value Set 1 Keyvalid 0xAFBE5A7 A Description Allow non-secure code to set APPROTECT Set value KEY Key to write in order to validate the write operation Key value 4.4.9 Electrical specification 4.4.9.1 Flash programming Symbol Description nWRITE Number of times a 32-bit word can be written before erase Min. Typ. Max. Units nENDURANCE Erase cycles per page tWRITE Time to write one 32-bit word 43 µs tERASEPAGE Time to erase one page 87 ms tERASEALL Time to erase all flash 173 ms 1.08 ms Max. Units 2 10,000 tERASEPAGEPARTIAL,setupSetup time for one partial erase 4.4.9.2 Cache size Symbol Description SizeICODE I-Code cache size Min. Typ. 2048 Bytes 4.5 FICR — Factory information configuration registers Factory information configuration registers (FICR) are pre-programmed in factory and cannot be erased by the user. These registers contain chip-specific information and configuration. 4418_1315 v2.0 35 Application core 4.5.1 Registers Base address Peripheral Instance Secure mapping DMA security Description 0x00FF0000 FICR S NA Factory information FICR Configuration configuration Table 12: Instances Register Offset INFO.DEVICEID[n] 0x204 Security Description Device identifier INFO.PART 0x20C Part code INFO.VARIANT 0x210 Part Variant, Hardware version and Production configuration INFO.PACKAGE 0x214 Package option INFO.RAM 0x218 RAM variant INFO.FLASH 0x21C Flash variant INFO.CODEPAGESIZE 0x220 Code memory page size INFO.CODESIZE 0x224 Code memory size INFO.DEVICETYPE 0x228 Device type TRIMCNF[n].ADDR 0x300 Address TRIMCNF[n].DATA 0x304 Data TRNG90B.BYTES 0xC00 Amount of bytes for the required entropy bits TRNG90B.RCCUTOFF 0xC04 Repetition counter cutoff TRNG90B.APCUTOFF 0xC08 Adaptive proportion cutoff TRNG90B.STARTUP 0xC0C Amount of bytes for the startup tests TRNG90B.ROSC1 0xC10 Sample count for ring oscillator 1 TRNG90B.ROSC2 0xC14 Sample count for ring oscillator 2 TRNG90B.ROSC3 0xC18 Sample count for ring oscillator 3 TRNG90B.ROSC4 0xC1C Sample count for ring oscillator 4 Table 13: Register overview 4.5.1.1 INFO.DEVICEID[n] (n=0..1) Address offset: 0x204 + (n × 0x4) Device identifier Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID R/W Field A R DEVICEID 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description 64 bit unique device identifier DEVICEID[0] contains the least significant bits of the device identifier. DEVICEID[1] contains the most significant bits of the device identifier. 4.5.1.2 INFO.PART Address offset: 0x20C Part code 4418_1315 v2.0 36 Application core Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID R/W Field A R PART Value ID Value N9160 0x9160 Description Part code nRF9160 4.5.1.3 INFO.VARIANT Address offset: 0x210 Part Variant, Hardware version and Production configuration Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x0FFFFFFF 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID R/W Field A R VARIANT Value ID Value Description Part Variant, Hardware version and Production configuration, encoded as ASCII AAAA 0x41414141 AAAA AAA0 0x41414130 AAA0 4.5.1.4 INFO.PACKAGE Address offset: 0x214 Package option Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00002000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A R PACKAGE Value ID Value CC 0x2000 Description Package option CCxx - 236 ball wlCSP 4.5.1.5 INFO.RAM Address offset: 0x218 RAM variant Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000100 ID R/W Field A R RAM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Value ID Value Description K256 0x100 256 kByte RAM Unspecified 0xFFFFFFFF Unspecified RAM variant 4.5.1.6 INFO.FLASH Address offset: 0x21C Flash variant 4418_1315 v2.0 37 Application core Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000400 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ID R/W Field A R FLASH Value ID Value K1024 0x400 Description Flash variant 1 MByte FLASH 4.5.1.7 INFO.CODEPAGESIZE Address offset: 0x220 Code memory page size Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00001000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A R CODEPAGESIZE Value ID Value Description Code memory page size 4.5.1.8 INFO.CODESIZE Address offset: 0x224 Code memory size Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000100 ID R/W Field A R CODESIZE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Value ID Value Description Code memory size in number of pages Total code space is: CODEPAGESIZE * CODESIZE 4.5.1.9 INFO.DEVICETYPE Address offset: 0x228 Device type Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID R/W Field A R DEVICETYPE Value ID Value Description Die 0x0000000 Device is an physical DIE FPGA 0xFFFFFFFF Device is an FPGA Device type 4.5.1.10 TRIMCNF[n].ADDR (n=0..255) Address offset: 0x300 + (n × 0x8) Address 4418_1315 v2.0 38 Application core Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID R/W Field A R Address Value ID Value Description Address 4.5.1.11 TRIMCNF[n].DATA (n=0..255) Address offset: 0x304 + (n × 0x8) Data Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID R/W Field A R Data 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Data 4.5.1.12 TRNG90B.BYTES Address offset: 0xC00 Amount of bytes for the required entropy bits Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID R/W Field A R BYTES Value ID Value Description Amount of bytes for the required entropy bits 4.5.1.13 TRNG90B.RCCUTOFF Address offset: 0xC04 Repetition counter cutoff Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID R/W Field A R RCCUTOFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Repetition counter cutoff 4.5.1.14 TRNG90B.APCUTOFF Address offset: 0xC08 Adaptive proportion cutoff Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID R/W Field A R APCUTOFF 4418_1315 v2.0 Value ID Value Description Adaptive proportion cutoff 39 Application core 4.5.1.15 TRNG90B.STARTUP Address offset: 0xC0C Amount of bytes for the startup tests Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID R/W Field A R STARTUP Value ID Value Description Amount of bytes for the startup tests 4.5.1.16 TRNG90B.ROSC1 Address offset: 0xC10 Sample count for ring oscillator 1 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID R/W Field A R ROSC1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Sample count for ring oscillator 1 4.5.1.17 TRNG90B.ROSC2 Address offset: 0xC14 Sample count for ring oscillator 2 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID R/W Field A R ROSC2 Value ID Value Description Sample count for ring oscillator 2 4.5.1.18 TRNG90B.ROSC3 Address offset: 0xC18 Sample count for ring oscillator 3 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID R/W Field A R ROSC3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Sample count for ring oscillator 3 4.5.1.19 TRNG90B.ROSC4 Address offset: 0xC1C Sample count for ring oscillator 4 4418_1315 v2.0 40 Application core Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID R/W Field A R ROSC4 Value ID Value Description Sample count for ring oscillator 4 4.6 UICR — User information configuration registers The user information configuration registers (UICRs) are non-volatile memory (NVM) registers for configuring user specific settings. For information on writing UICR registers, see the NVMC — Non-volatile memory controller on page 29 and Memory on page 21 chapters. 4.6.1 Registers Base address Peripheral Instance Secure mapping DMA security Description 0x00FF8000 UICR S NA User information UICR Configuration configuration Table 14: Instances Register Offset APPROTECT 0x000 Security Description Access port protection XOSC32M 0x014 Oscillator control HFXOSRC 0x01C HFXO clock source selection HFXOCNT 0x020 HFXO startup counter SECUREAPPROTECT 0x02C Secure access port protection ERASEPROTECT 0x030 Erase protection OTP[n] 0x108 One time programmable memory KEYSLOT.CONFIG[n].DEST 0x400 Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) will be pushed by KMU. Note that this address must match that of a peripherals APB mapped write-only key registers, else the KMU can push this key value into an address range which the CPU can potentially read. KEYSLOT.CONFIG[n].PERM 0x404 KEYSLOT.KEY[n].VALUE[o] 0x800 Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. Table 15: Register overview 4.6.1.1 APPROTECT Address offset: 0x000 Access port protection 4418_1315 v2.0 41 Application core Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW PALL Value ID Value Description Blocks debugger read/write access to all CPU registers and memory mapped addresses Unprotected 0xFFFFFFFF Unprotected Protected 0x00000000 Protected 4.6.1.2 XOSC32M Address offset: 0x014 Oscillator control Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A Reset 0xFFFFFFCF ID R/W Field A RW CTRL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 Value ID Value Description Pierce current DAC control signals 4.6.1.3 HFXOSRC Address offset: 0x01C HFXO clock source selection Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0xFFFFFFFF ID R/W Field A RW HFXOSRC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description XTAL 1 32 MHz crystal oscillator TCXO 0 32 MHz temperature compensated crystal oscillator (TCXO) HFXO clock source selection 4.6.1.4 HFXOCNT Address offset: 0x020 HFXO startup counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0xFFFFFFFF ID R/W Field A RW HFXOCNT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description MinDebounceTime 0 Min debounce time = (0*64 us + 0.5 us) MaxDebounceTime 255 Max debounce time = (255*64 us + 0.5 us) HFXO startup counter. Total debounce time = HFXOCNT*64 us + 0.5 us 4.6.1.5 SECUREAPPROTECT Address offset: 0x02C Secure access port protection 4418_1315 v2.0 42 Application core Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW PALL Value ID Value Description Blocks debugger read/write access to all secure CPU registers and secure memory mapped addresses Unprotected 0xFFFFFFFF Unprotected Protected 0x00000000 Protected 4.6.1.6 ERASEPROTECT Address offset: 0x030 Erase protection Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID R/W Field A RW PALL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Blocks NVMC ERASEALL and CTRLAP ERASEALL functionality Unprotected 0xFFFFFFFF Unprotected Protected 0x00000000 Protected 4.6.1.7 OTP[n] (n=0..189) Address offset: 0x108 + (n × 0x4) One time programmable memory Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF ID R/W Field A RW1 LOWER 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Lower half word Note: Can only be written to a non 0xFFFF value once. B RW1 UPPER Upper half word Note: Can only be written to a non 0xFFFF value once. 4.6.1.8 KEYSLOT.CONFIG[n].DEST (n=0..127) Address offset: 0x400 + (n × 0x8) Destination address where content of the key value registers (KEYSLOT.KEYn.VALUE[0-3]) will be pushed by KMU. Note that this address must match that of a peripherals APB mapped write-only key registers, else the KMU can push this key value into an address range which the CPU can potentially read. Note: Writing/reading this register requires the KMU SELECTKEYSLOT register to be set to n+1. 4418_1315 v2.0 43 Application core Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID R/W Field A RW DEST Value ID Value Description Secure APB destination address 4.6.1.9 KEYSLOT.CONFIG[n].PERM (n=0..127) Address offset: 0x404 + (n × 0x8) Define permissions for the key slot. Bits 0-15 and 16-31 can only be written when equal to 0xFFFF. Note: Writing/reading this register requires the KMU SELECTKEYSLOT register to be set to n+1. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID D Reset 0xFFFFFFFF ID R/W Field A RW WRITE B C RW RW C B A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description Write permission for key slot Disabled 0 Disable write to the key value registers Enabled 1 Enable write to the key value registers READ Read permission for key slot Disabled 0 Disable read from key value registers Enabled 1 Enable read from key value registers PUSH Push permission for key slot Disabled 0 Enabled 1 Disable pushing of key value registers over secure APB, but can be read if field READ is Enabled Enable pushing of key value registers over secure APB. Register KEYSLOT.CONFIGn.DEST must contain a valid destination address! D RW STATE Revocation state for the key slot Note that it is not possible to undo a key revocation by writing the value '1' to this field Revoked 0 Key value registers can no longer be read or pushed Active 1 Key value registers are readable (if enabled) and can be pushed (if enabled) 4.6.1.10 KEYSLOT.KEY[n].VALUE[o] (n=0..127) (o=0..3) Address offset: 0x800 + (n × 0x10) + (o × 0x4) Define bits [31+o*32:0+o*32] of value assigned to KMU key slot. Note: Writing/reading this register requires the KMU SELECTKEYSLOT register to be set to n+1. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID R/W Field A RW VALUE 4418_1315 v2.0 Value ID Value Description Define bits [31+o*32:0+o*32] of value assigned to KMU key slot 44 Application core 4.7 EasyDMA EasyDMA is a module implemented by some peripherals to gain direct access to Data RAM. EasyDMA is an AHB bus master similar to CPU and is connected to the AHB multilayer interconnect for direct access to Data RAM. EasyDMA is not able to access flash. A peripheral can implement multiple EasyDMA instances to provide dedicated channels. For example, for reading and writing of data between the peripheral and RAM. This concept is illustrated in EasyDMA example on page 45. RAM AHB Multilayer Peripheral READER AHB RAM EasyDMA WRITER RAM AHB Peripheral Core EasyDMA Figure 5: EasyDMA example An EasyDMA channel is implemented in the following way, but some variations may occur: READERBUFFER_SIZE 5 WRITERBUFFER_SIZE 6 uint8_t readerBuffer[READERBUFFER_SIZE] __at__ 0x20000000; uint8_t writerBuffer[WRITERBUFFER_SIZE] __at__ 0x20000005; // Configuring the READER channel MYPERIPHERAL->READER.MAXCNT = READERBUFFER_SIZE; MYPERIPHERAL->READER.PTR = &readerBuffer; // Configure the WRITER channel MYPERIPHERAL->WRITER.MAXCNT = WRITEERBUFFER_SIZE; MYPERIPHERAL->WRITER.PTR = &writerBuffer; This example shows a peripheral called MYPERIPHERAL that implements two EasyDMA channels - one for reading called READER, and one for writing called WRITER. When the peripheral is started, it is assumed that the peripheral will perform the following tasks: • Read 5 bytes from the readerBuffer located in RAM at address 0x20000000 • Process the data • Write no more than 6 bytes back to the writerBuffer located in RAM at address 0x20000005 The memory layout of these buffers is illustrated in EasyDMA memory layout on page 46. 4418_1315 v2.0 45 Application core 0x20000000 readerBuffer[0] readerBuffer[1] readerBuffer[2] readerBuffer[3] 0x20000004 readerBuffer[4] writerBuffer[0] writerBuffer[1] writerBuffer[2] 0x20000008 writerBuffer[3] writerBuffer[4] writerBuffer[5] Figure 6: EasyDMA memory layout The WRITER.MAXCNT register should not be specified larger than the actual size of the buffer (writerBuffer). Otherwise, the channel would overflow the writerBuffer. Once an EasyDMA transfer is completed, the AMOUNT register can be read by the CPU to see how many bytes were transferred. For example, CPU can read MYPERIPHERAL->WRITER.AMOUNT register to see how many bytes WRITER wrote to RAM. Note: The PTR register of a READER or WRITER must point to a valid memory region before use. The reset value of a PTR register is not guaranteed to point to valid memory. See Memory on page 21 for more information about the different memory regions and EasyDMA connectivity. 4.7.1 EasyDMA error handling Some errors may occur during DMA handling. If READER.PTR or WRITER.PTR is not pointing to a valid memory region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 21 for more information about the different memory regions. If several AHB bus masters try to access the same AHB slave at the same time, AHB bus congestion might occur. An EasyDMA channel is an AHB master. Depending on the peripheral, the peripheral may either stall and wait for access to be granted, or lose data. 4.7.2 EasyDMA array list EasyDMA is able to operate in Array List mode. The Array List mode is implemented in channels where the LIST register is available. The array list does not provide a mechanism to explicitly specify where the next item in the list is located. Instead, it assumes that the list is organized as a linear array where items are located one after the other in RAM. 4418_1315 v2.0 46 Application core The EasyDMA Array List can be implemented by using the data structure ArrayList_type as illustrated in the code example below using a READER EasyDMA channel as an example: #define BUFFER_SIZE 4 typedef struct ArrayList { uint8_t buffer[BUFFER_SIZE]; } ArrayList_type; ArrayList_type ReaderList[3] __at__ 0x20000000; MYPERIPHERAL->READER.MAXCNT = BUFFER_SIZE; MYPERIPHERAL->READER.PTR = &ReaderList; MYPERIPHERAL->READER.LIST = MYPERIPHERAL_READER_LIST_ArrayList; The data structure only includes a buffer with size equal to the size of READER.MAXCNT register. EasyDMA uses the READER.MAXCNT register to determine when the buffer is full. READER.PTR = &ReaderList 0x20000000 : ReaderList[0] buffer[0] buffer[1] buffer[2] buffer[3] 0x20000004 : ReaderList[1] buffer[0] buffer[1] buffer[2] buffer[3] 0x20000008 : ReaderList[2] buffer[0] buffer[1] buffer[2] buffer[3] Figure 7: EasyDMA array list 4.8 AHB multilayer interconnect On the AHB multilayer interconnect, the application CPU and all EasyDMA instances are AHB bus masters while RAM, cache and peripherals are AHB slaves. External MCU subsystems can be seen both as master and slave on the AHB multilayer interconnect. Multiple AHB masters can access slave resources within the AHB multilayer interconnect as illustrated in Memory on page 21. Access rights to each of the AHB slaves are resolved using the natural priority of the different bus masters in the system. 4418_1315 v2.0 47 5 Power and clock management 5.1 Functional description The power and clock management system automatically ensures maximum power efficiency. The nRF9160 provides a total of three power modes; two internal (automatically handled by the device), and one external (driven by the ENABLE pin and overriding internal ones). The core of the automatic power and clock management is the power management unit (PMU) illustrated in the image below. nRF9160 VDD Power management IC (PMIC) Application core ENABLE PMU Clock sources LTE modem Memory Peripherals Figure 8: Power management unit When the device is powered and enabled, the PMU automatically tracks the power and clock resources required by the different components in the system. It then starts/stops and chooses operation modes in supply regulators and clock sources, without user interaction, to achieve the lowest power consumption possible. 5.1.1 Power management The two internal modes are handled by the power management unit (PMU) , whereas the external is handled by the user via the ENABLE pin. The System Disabled mode provides a way to override the PMU by manipulating voltages presented to the ENABLE pin. The PMU steers system-wide clock and power in order to provide the power modes - System ON and System OFF. Under the various modes, internal blocks are automatically powered by the PMU as required by the application. 5.1.1.1 System Disabled mode The entire device can be powered down by presenting the appropriate voltage to the externally available ENABLE pin. 4418_1315 v2.0 48 Power and clock management The nRF9160 provides a feature to be able disable power throughout the entire device externally. This can be useful when the device is operating as slave processor where it does not need to be powered on at all times, then it is possible to avoid unnecesary current leaking by driving the ENABLE pin to low. The nRF9160 will not start if is not enabled. Moreover, a change from disable to enable, will result in a poweron-reset behavior inside the device. Note: VDD_GPIO input must be driven low when device is disabled, failing to do so could result in increased leakage. For more information, see VDD_GPIO considerations in Operating conditions on page 391. Note: In case the System Disabled mode is not used, ENABLE must be connected to VDD. Pin Value Power status description Low Disabled Device's internal power regulator disabled High Enabled Device's internal power regulator enabled Table 16: ENABLE pin configuration 5.1.1.2 System OFF mode System OFF is the deepest internal power saving mode the system can enter. In this mode, the core system functionality is powered down and ongoing tasks terminated, and only the reset and the wakeup functions are available and responsive. The device is put into System OFF mode using the REGULATORS register interface. When in System OFF mode, one of the following signals/actions will wake up the device: 1. DETECT signal, generated by the GPIO peripheral 2. RESET 3. start of debug session When the device wakes up from System OFF mode, a system reset is performed. One or more RAM blocks can be retained in System OFF mode depending on the settings in the RAM[n].POWER registers in VMC. RAM[n].POWER are retained registers, see Reset behavior on page 57. Note that these registers are usually overwritten by the startup code provided with the nRF application examples. Before entering System OFF mode, the user must make sure that all on-going EasyDMA transactions have completed. This can be accomplished by making sure that EasyDMA enabled peripherals have stopped and END events from them received. The LTE modem also needs to be stopped, by issuing a command through the modem API, before entering System OFF mode. Once the command is issued, one should wait for the modem to respond that it actually has stopped, as there may be a delay until modem is disconnected from the network. 5.1.1.2.1 Emulated System OFF mode If the device is in debug interface mode, System OFF will be emulated to secure that all required resources needed for debugging are available during System OFF. See Overview on page 369 chapter for more information. Required resources needed for debugging include the following key components: Overview on page 369, CLOCK — Clock control on page 70, POWER — Power control on page 64, NVMC — Non-volatile memory controller on page 29, CPU on page 20, flash, and RAM. Since the CPU is kept on in emulated System OFF mode, it is required to add an infinite loop directly after entering System OFF, to prevent the CPU from executing code that normally should not be executed. 4418_1315 v2.0 49 Power and clock management 5.1.1.3 System ON mode System ON is the power mode entered after a power-on reset. While in System ON, the system can reside in one of two sub modes: • Low power • Constant latency The low power mode is default after power-on reset. In low power mode, whenever no application or wireless activity takes place, function blocks like the application CPU, LTE modem and all peripherals are in IDLE state. That particular state is referred to as System ON IDLE. In this state, all function blocks retain their state and configuration, so they are ready to become active once configured by the CPU. If any application or modem activity occurs, the system leaves the System ON IDLE state. Once a given activity in a function block is completed, the system automatically returns to IDLE, retaining its configuration. As long as the system resides in low power mode, the PMU ensures that the appropriate regulators and clock sources are started or stopped based on the needs of the function blocks active at any given time. This automatic power management can be overridden by switching to constant latency mode. In this mode, the CPU wakeup latency and the PPI task response are constant and kept at a minimum. This is secured by keeping a set of base resources that are always enabled. The advantage of having a constant and predictable latency will be at the cost of having significantly increased power consumption compared to the low power mode. The constant latency mode is enabled by triggering the CONSTLAT task (TASKS_CONSTLAT on page 64). While the system is in constant latency mode, the low power mode can be enabled by triggering LOWPWR task (TASKS_LOWPWR on page 65). To reduce power consumption while in System ON IDLE, RAM blocks can be turned off in System ON mode while enabling the retention of these RAM blocks in RAM[n].POWER registers in VMC. RAM[n].POWER are retained registers, see Reset behavior on page 57. Note that these registers are usually overwritten by the startup code provided with the nRF application examples. 5.1.1.4 Registers 5.1.1.5 Electrical specification 5.1.1.5.1 ENABLE pin voltage requirements Symbol Description Min. VSYSTEM_DISABLED_ON Operational voltage to enforce System-Disabled power Typ. Max. 0.8*VDD Units V mode. VSYSTEM_DISABLED_OFF Operational voltage to cancel System-Disabled power 0.4 V mode. 5.1.2 Power supply The nRF9160 has a single main power supply VDD, and the internal components are powered by integrated voltage regulators. The PMU manages these regulators automatically, no voltage regulator control needs to be included in application firmware. 5.1.2.1 General purpose I/O supply The input/output (I/O) drivers of P0.00 - P0.31 pins are supplied independently of VDD through VDD_GPIO. This enables easy match to signal voltage levels in the printed circuit board design. 4418_1315 v2.0 50 Power and clock management nRF91 GPIO External supply ... VDD_GPIO P0.00 P0.01 P0.30 P0.31 Figure 9: GPIO supply input (VDD_GPIO) The I/Os are supplied via VDD_GPIO pin as shown in figure above. VDD_GPIO pin supports voltage levels within range given in table Operating conditions on page 391 5.1.3 Power supply monitoring Power monitor solutions are available in the device, in order to survey the VDD (battery voltage). 5.1.3.1 Power supply supervisor The power supply supervisor enables monitoring of the connected power supply. Two functionalities are implemented: • Power-on reset (POR): Generates a reset when the supply is applied to the device, and ensures that the device starts up in a known state • Brownout reset (BOR): Generates a reset when the supply drops below the minimum voltage required for safe operations Two BOR levels are used: • VBOROFF, used in System OFF • VBORON, used in System ON The power supply supervisor is illustrated in the image below. VDD C Power-on reset R VBOR Figure 10: Power supply supervisor 4418_1315 v2.0 51 Brownout reset Power and clock management 5.1.3.2 Battery monitoring on VDD A battery voltage (VDD) monitoring capability is provided via a modem API Note: For details regarding the modem API, please refer to nRF Connect SDK document and nRF91 AT Commands, Command Reference Guide document. 5.1.3.3 Registers 5.1.3.4 Electrical specification 5.1.3.4.1 Device startup times Symbol Description tPOR Time in power-on reset after VDD has reached 3V, ENABLE Min. Typ. Max. 1.2 Units ms is tied to VDD. tPINR The maximum time taken to pull up the nRESET pin and .. .. .. release reset after power-on reset. Dependent on the pin capacitive load (C)2: t=TRC; Typical: T=2 R=13 kΩ; Max: T=5 R=16 kΩ. tPINR,500nF C=500 nF 13 40 ms tPINR,10uF C=10 µF 260 800 ms tR2ON Time from reset to ON (CPU execute) 127 µs tOFF2ON Time from OFF to CPU execute 73 µs tWFE2CPU Time from WFE to CPU execute 70 µs tWFI2CPU Time from WFI to CPU execute 69 µs tEVTSET,CL1 Time from HW event to PPI event in constant latency 0.1 0.1 µs 0.1 0.7 µs 200 ms 250 ms 7.5 s 90 s 1.6 s System ON mode tEVTSET,CL0 Time from HW event to PPI event in low power System ON mode tLTEMODEM,TYP LTE modem typical startup time. Time from application core powering up the modem until the modem is ready to receive the first AT command. tLTEMODEM,WORSTCASE LTE modem worst case startup time. Time from application core powering up the modem until the modem is ready to receive the first AT command, with modem FW variable elements included. tLTEMODEM,FOTA LTE modem startup time after modem FOTA update. Time from application core powering up the modem after a modem FOTA update until the modem is ready to receive the first AT command. tLTEMODEM,FOTAREJECT LTE modem startup time after a rejected modem FOTA update. Time from application core powering up the modem after a rejected modem FOTA update until the modem is ready to receive the first AT command. Modem will revert back to original FW image. tLTEMODEM,STOP,TYP LTE modem typical shutdown time. Time from application core calling bsd_shutdown command until bsd_shutdown returns. 2 To decrease the maximum time a device could be held in reset, a strong external pull-up resistor can be used. 4418_1315 v2.0 52 Power and clock management Symbol Description Min. Typ. tLTEMODEM,STOP,WORSTCASE LTE modem worst case shutdown time. Time from Max. Units 79 s Max. Units application core calling bsd_shutdown command until bsd_shutdown returns, with modem FW variable elements included. 5.1.3.4.2 Power supply supervisor Symbol Description VBOR Brownout reset voltage threshold. VPOR Voltage threshold at which the device enters power-on Min. Typ. 2.00 V 2.15 V reset (POR) when VDD is ramping up. 5.1.4 Clock management The clock control system can source the system clocks from a range of high and low frequency oscillators, and distribute them to modules based upon a module's individual requirements. Clock generation and distribution is handled automatically by PMU to optimize current consumption. Listed here are the available clock signal sources: • • • • 64 MHz oscillator (HFINT) 64 MHz high accuracy oscillator (HFXO) 32.768 kHz RC oscillator (LFRC) 32.768 kHz high accuracy oscillator (LFXO) The clock and oscillator resources are configured and controlled via the CLOCK peripheral as illustrated below. 4418_1315 v2.0 53 Power and clock management Clock and oscillator control unit PCLK1M HFXO oscillator (high accuracy) PCLK16M HFCLK clock control PCLK32M HCLK HFINT oscillator (low accuracy) LFRC RC oscillator LFXO oscillator LFCLKSTART LFCLK clock control CLOCK PCLK32KI LFCLKSTARTED LFCLKSTOP LFCLKSRC HFCLKSTOP HFCLKSTART HFCLKCTRL HFCLKSTARTED Figure 11: Clock and oscillator setup 5.1.4.1 HFCLK clock controller The HFCLK clock controller provides several clocks in the system. These are as follows: • • • • HCLK: 64 MHz CPU clock PCLK1M: 1 MHz peripheral clock PCLK16M: 16 MHz peripheral clock PCLK32M: 32 MHz peripheral clock The HFCLK controller uses the following high frequency clock (HFCLK) sources: • 64 MHz oscillator (HFINT) • 64 MHz high accuracy oscillator (HFXO) For illustration, see Clock and oscillator setup on page 54. The HFCLK controller will automatically provide the clock(s) requested by the system. If the system does not request any clocks from the HFCLK controller, the controller will switch off all its clock sources and enter a power saving mode. The HFINT source will be used when HFCLK is requested and HFXO has not been started. The HFXO is started by triggering the HFCLKSTART task and stopped using the HFCLKSTOP task. A HFCLKSTARTED event will be generated when the HFXO has started and its frequency is stable. 5.1.4.2 LFCLK clock controller The system supports several low frequency clock sources. 4418_1315 v2.0 54 Power and clock management As illustrated in Clock and oscillator setup on page 54, the system supports the following low frequency clock sources: • LFRC: 32.768 kHz RC oscillator • LFXO: 32.768 kHz high accuracy oscillator The LFCLK clock controller and all LFCLK clock sources are always switched off when in System OFF mode. The LFCLK clock is started by first selecting the preferred clock source in the LFCLKSRC on page 77 register and then triggering the LFCLKSTART task. LFXO is highly recommended as the LFCLK clock source, since the LFRC has a large frequency variation. Note: The LTE modem requires using LFXO as the LFCLK source. Switching between LFCLK clock sources can be done without stopping the LFCLK clock. A LFCLK clock source which is running prior to triggering the LFCLKSTART task will continue to run until the selected clock source has been available. After that the clock sources will be switched. Switching between clock sources will never introduce a glitch but it will stretch a clock pulse by 0.5 to 1.0 clock cycle (i.e. will delay rising edge by 0.5 to 1.0 clock cycle). Note: If the watchdog timer (WDT) is running, the default LFCLK clock source (LFRC - see LFCLKSRC on page 77) is started automatically (LFCLKSTART task doesn't have to be triggered). A LFCLKSTARTED event will be generated when the selected LFCLK clock source has started. Note: When selecting LFXO as clock source for the first time, LFRC quality is provided until LFXO is stable. A LFCLKSTOP task will stop global requesting of the LFCLK clock. However, if any system component (e.g. WDT, modem) requires the LFCLK, the clock won't be stopped. The LFCLKSTOP task should only be triggered after the STATE field in the LFCLKSTAT register indicates a LFCLK running-state. 5.1.4.2.1 32.768 kHz RC oscillator (LFRC) The default source of the low frequency clock (LFCLK) is the 32.768 kHz RC oscillator (LFRC). The LFRC frequency will be affected by variation in temperature. 5.1.4.3 Registers 5.1.4.4 Electrical specification 5.1.4.4.1 64 MHz internal oscillator (HFINT) Symbol Description fNOM_HFINT Nominal output frequency Min. Typ. 64 fTOL_HFINT Frequency tolerance +-1 tSTART_HFINT Startup time 3.2 Max. Units MHz +-5 % µs 5.1.4.4.2 64 MHz high accuracy oscillator (HFXO) Symbol Description fNOM_HFXO Nominal output frequency 64 MHz fTOL_HFXO Frequency tolerance +-1 ppm tSTART_HFXO Startup time TBA ms 4418_1315 v2.0 Min. 55 Typ. Max. Units Power and clock management 5.1.4.4.3 32.768 kHz high accuracy oscillator (LFXO) Symbol Description fNOM_LFXO Frequency Min. Typ. 32.768 Max. Units kHz fTOL_LFXO Frequency tolerance +-20 ppm tSTART_LFXO Startup time 200 ms 5.1.4.4.4 32.768 kHz RC oscillator (LFRC) Symbol Description fNOM_LFRC Nominal frequency Min. Typ. 32.768 Max. Units kHz fTOL_LFRC Frequency tolerance 30 % tSTART_LFRC Startup time 600 µs 5.1.5 Reset There are multiple reset sources that may trigger a reset of the system. After a reset the CPU can query the RESETREAS (reset reason register) to find out which source generated the reset. 5.1.5.1 Power-on reset The power-on reset generator initializes the system at power-on. The system is held in reset state until the supply has reached the minimum operating voltage and the internal voltage regulators have started. 5.1.5.2 Pin reset A pin reset is generated when the physical reset pin (nRESET) on the device is pulled low. To ensure that reset is issued correctly, the reset pin should be held low for time given in Pin reset on page 58 . nRESET pin has an always-on internal pull-up resistor connected to nRF9160 internal voltage typically of 2.2 V level. This is illustrated in the figure below. The value of the pull-up resistor is given in Pin reset on page 58. Note: Driving nRESET high with a voltage lower than 2.2V will result in additional leakage. nRF91 2.2V R nReset pin reset Figure 12: Pin reset internal generation 5.1.5.3 Wakeup from System OFF mode reset The device is reset when it wakes up from System OFF mode. The Debug access port is not reset following a wake up from System OFF mode if the device is in debug interface mode, see Overview on page 369 chapter for more information. 4418_1315 v2.0 56 Power and clock management 5.1.5.4 Soft reset A soft reset is generated when the SYSRESETREQ bit of the application interrupt and reset control register (AIRCR register) in the ARM core is set. 5.1.5.5 Watchdog reset A watchdog reset is generated when the watchdog timer (WDT) times out. See WDT — Watchdog timer on page 354 chapter for more information. 5.1.5.6 Brownout reset The brownout reset generator puts the system in reset state if the supply voltage drops below the brownout reset threshold. 5.1.5.7 Retained registers A retained register is a register that will retain its value in System OFF mode, and through a reset depending on reset source. See individual peripheral chapters for information of which registers are retained for the different peripherals. 5.1.5.8 Reset behavior Reset behavior depends on the reset source. The reset behavior is summarized in the table below. Reset source Reset target CPU Modem Debug3 SWJ-DP Not retained Retained RAM 4 RAM WDT x x Soft reset x x Wakeup from System OFF x x x6 x x Watchdog reset 7 x x x x x Pin reset x x x x x Brownout reset x x x x x x x Power-on reset x x x x x x x CPU lockup 5 RESETREAS 4 mode reset x x Table 17: Reset behavior for the main components Note: The RAM is never reset but its content may be corrupted after reset in the cases given in the table above. 3 4 5 6 7 All debug components excluding SWJ-DP. See Overview on page 369 chapter for more information about the different debug components in the system. RAM can be configured to be retained using registers in VMC — Volatile memory controller on page 27 Reset from CPU lockup is disabled if the device is in debug interface mode. CPU lockup is not possible in System OFF. The debug components will not be reset if the device is in debug interface mode. Watchdog reset is not available in System OFF. 4418_1315 v2.0 57 Power and clock management Reset source Reset target Regular peripheral GPIO, SPU NVMC registers CPU lockup 5 Soft reset x x x x x x Wakeup from System OFF mode reset x 7 NVMC REGULATORS, POWER.GPREGRET WAITSTATENUM IFCREADDELAY OSCILLATORS x Watchdog reset x x x x Pin reset x x x x Brownout reset x x x x x x Power-on reset x x x x x x Table 18: Reset behavior for the retained registers 5.1.5.9 Registers 5.1.5.10 Electrical specification 5.1.5.10.1 Pin reset Symbol Description Min. tHOLDRESET Hold time for reset pin when doing a pin reset 5 RPULL-UP Value of the internal pull-up resistor Typ. Max. Units µs 13 kΩ 5.2 Current consumption As the system is being constantly tuned by the PMU described in Functional description on page 48, estimating the current consumption of an application can be challenging if the designer is not able to perform measurements directly on the hardware. To facilitate the estimation process, a set of current consumption scenarios are provided to show the typical current drawn from the VDD supply. Each scenario specifies a set of operations and conditions applying to the given scenario. Current consumption scenarios, common conditions on page 59 shows a set of common conditions used in all scenarios, unless otherwise is stated in the description of a given scenario. Similarly, Current consumption scenarios, common conditions for LTE modem on page 59 describes the conditions used for the modem current consumption specifications. All scenarios are listed in Electrical specification on page 59 Peripherals typically share one or more power sources. This results in a current consumption that does not scale linearly with the number of peripherals enabled. For example, the current consumption for an application with two peripherals enabled, is not the sum of the currents reported by their individual peripherals. 4418_1315 v2.0 58 Power and clock management Condition Value Supply 3.7 V Temperature 25 °C CPU WFI (wait for interrupt)/WFE (wait for event) sleep Peripherals All idle8 Clock Not running RAM No retention Cache enabled Yes Table 19: Current consumption scenarios, common conditions Condition Cat-M1 and Cat-NB1 HD FDD mode Good channel, RF cable, no errors in DL/UL communication Network response times at minimum Output power at antenna port, single-ended 50 Ω Modem eDRX current consumption quoted with UICC that allows UICC supply shut down at eDRX intervals. 9 10 11 Modem PSM TAU event energy is measured from the modem PSM wake-up until end of RX inactivity time All LTE modem current consumption numbers include application core idle mode consumption Table 20: Current consumption scenarios, common conditions for LTE modem 5.2.1 Electrical specification 5.2.1.1 Current consumption during System Disabled Symbol Description ISYSTEM_DISABLED ENABLE and VDD_GPIO pins grounded 8 9 10 11 Min. Typ. 150 Max. Units nA Except for currents reported for a given peripheral. Peripheral's currents are estimated during momentary transmission. Required UICC restart current consumption is included. If the used UICC does not support supply shut down, then UICC will remain in clock stop mode. Depending on the used UICC a clock stop current of typ. 20-60uA@3.7V needs to be added to get the total average consumption. Minimum UICC supply shut down interval and clock stop mode current consumption must be obtained from the UICC supplier. 4418_1315 v2.0 59 Power and clock management 5.2.1.2 Sleep Symbol Description IMCUOFF0 MCU off, modem off, no RAM retention, wake on GPIO and Min. Typ. Max. Units 1.4 µA reset IMCUON0 MCU on IDLE, modem off, RTC off 1.8 µA IMCUON1 MCU on IDLE, modem off, RTC on 2.2 µA 5.2.1.3 Application CPU active current consumption Symbol Description ICPU0_FLASH CPU running CoreMark @64 MHz from flash, clock = HFINT, Min. Typ. Max. Units 2.20 mA ICOREMARK_PER_MA_FLASH CoreMark per mA, executing from flash, CoreMark=243 110.45 CoreMark/ ICPU0_RAM 2.19 mA 107.31 CoreMark/ cache enabled mA CPU running CoreMark @64 MHz from RAM, clock = HFINT ICOREMARK_PER_MA_RAMCoreMark per mA, executing from RAM, CoreMark=235 mA 5.2.1.4 I2S Symbol Description II2S0 I2S transferring data left-channel (mono) @ 16 bit x 16 kHz Min. Typ. Max. Units 0.69 mA 1.65 mA (CONFIG.MCKFREQ = 32MDIV8, CONFIG.RATIO = 256X), Clock = HFINT II2S1 I2S transferring data left-channel (mono) @ 16 bit x 16 kHz (CONFIG.MCKFREQ = 32MDIV8, CONFIG.RATIO = 256X), Clock = HFXO 5.2.1.5 PDM Symbol Description IPDM PDM receiving and processing data 16KHz, with FREQ = Min. Typ. Max. Units 0.71 mA 1.67 mA 1.28MHz, MODE.OPERATION = mono IPDM PDM receiving and processing data 16KHz, with FREQ = 1.28MHz, MODE.OPERATION = mono, clock HFXO 5.2.1.6 PWM Symbol Description IPWM0 PWM running @ 125 kHz, fixed duty cycle Min. Typ. 623.97 Max. Units µA IPWM1 PWM running @ 16 MHz, fixed duty cycle 723.1 µA 5.2.1.7 SAADC Symbol Description Min. ISAADC_HFXO SAADC sampling @ 16 ksps, with high accuracy clock HFXO, Typ. Max. Units 1288 µA 297.7 µA acquisition time = 20 µs ISAADC_HFINT SAADC sampling @ 16 ksps, with low accuracy clock HFINT, acquisition time = 20 µs 4418_1315 v2.0 60 Power and clock management 5.2.1.8 TIMER Symbol Description ITIMER0 TIMER running @ 1 MHz Min. Typ. 503.7 Max. Units µA ITIMER1 TIMER running @ 16 MHz 556.3 µA 5.2.1.9 SPIM Symbol Description Min. Typ. Max. Units ISPIM0 SPIM transferring data @ 2 Mbps, Clock = HFINT 0.63 mA ISPIM1 SPIM transferring data @ 2 Mbps, Clock = HFXO 1.58 mA ISPIM2 SPIM transferring data @ 8 Mbps, Clock = HFINT 0.67 mA ISPIM3 SPIM transferring data @ 8 Mbps, Clock = HFXO 1.62 mA 5.2.1.10 SPIS Symbol Description ISPIS_2M SPIS receiving data @ 2 Mbps, Clock=HFINT Min. Typ. 0.63 Max. Units mA ISPIS_2MXO SPIS receiving data @ 2 Mbps, Clock=HFXO 1.58 mA ISPIS_8M SPIS receiving data @ 8 Mbps, Clock=HFINT 0.67 mA ISPIS_8MXO SPIS receiving data @ 8 Mbps, Clock=HFXO 1.62 mA 5.2.1.11 TWIM Symbol Description ITWIM_100 TWIM running @ 100 kbps, Clock=HFINT Min. Typ. 0.61 Max. Units mA ITWIM_400 TWIM running @ 400 kbps, Clock = HFINT 0.61 mA ITWIM_100XO TWIM running @ 100 kbps, Clock = HFXO 1.56 mA ITWIM_400XO TWIM running @ 400 kbps, Clock = HFXO 1.56 mA 5.2.1.12 TWIS Symbol Description ITWIS,RUN_100 TWIS transferring data @ 100 kbps, Clock=HFINT Min. Typ. 0.60 Max. Units mA ITWIS1,RUN_400 TWIS transferring data @ 400 kbps, Clock=HFINT 0.60 mA ITWIS,RUN_100XO TWIS transferring data @ 100 kbps, Clock = HFXO 1.55 mA ITWIS,RUN_400XO TWIS transferring data @ 400 kbps, Clock = HFXO 1.55 mA 5.2.1.13 UARTE Symbol Description IUARTE,1M UARTE transferring data @ 1200 bps Min. Typ. 819.2 Max. Units mA IUARTE,115K UARTE transferring data @ 115200 bps 620.6 mA 5.2.1.14 WDT Symbol Description IWDT WDT started 4418_1315 v2.0 Min. Typ. 2.50 61 Max. Units µA Power and clock management 5.2.1.15 Modem current consumption For estimating particular use cases, see nRF9160 Online Power Profiler for LTE 4418_1315 v2.0 62 Power and clock management Symbol Description B13 B20 B3 B4 Units (typ.) (typ.) (typ.) (typ.) 2.7 2.7 2.7 2.7 µA Sleep current consumption, Cat-M1 and Cat-NB1 IPSM PSM floor current PSM TAU event energy and duration, Cat-M1 EPSM_TAU Pout 23 dBm, QPSK, resource blocks 6, TBS index 9, UICC included 105 - - - mJ TPSM_TAU Pout 23 dBm, QPSK, resource blocks 6, TBS index 9, UICC included 1.5 - - - s Pout 23 dBm, QPSK, UICC included; UL: 12SC, MCS Index 5 Resource Units 1, Repetitions 1; DL, 12SC, 550 - - - mJ - - - s PSM TAU event energy and duration, Cat-NB1 EPSM_TAU MCS Index 6, Subframes 3, Repetitions 1 TPSM_TAU Pout 23 dBm, QPSK, UICC included; UL: 12SC, MCS Index 5 Resource Units 1, Repetitions 1; DL, 12SC, 2.7 MCS Index 6, Subframes 3, Repetitions 1 Average current consumption, radio resource control (RRC) mode, Cat-M1 IEDRX eDRX average current, 81.92 s, one PO/PTW, PTW = 2.56 s 18 18 18 18 µA IIEDRX Idle eDRX average current, 655 s, one PO/PTW, PTW = 2.56 s 6 6 6 6 µA IRMC_0DBM Uplink 180 kbit/s, Pout 0 dBm, RMC settings as per 3GPP TS 36.521-1 Annex A.2 45 45 45 45 mA IRMC_10DBM Uplink 180 kbit/s, Pout 10 dBm, RMC settings as per 3GPP TS 36.521-1 Annex A.2 50 50 55 55 mA IRMC_23DBM Uplink 180 kbit/s, Pout 23 dBm, RMC settings as per 3GPP TS 36.521-1 Annex A.2 100 105 115 115 mA Average current consumption, radio resource control (RRC) mode, Cat-NB1 IEDRX eDRX average current, 81.92 s, one PO/PTW, PTW = 2.56 s 37 37 37 37 µA IIEDRX Idle eDRX average current, 655 s, one PO/PTW, PTW = 2.56 s 9 9 9 9 µA IRMC_0DBM Pout 0 dBm, QPSK, 1SC, 15 kHz, TX 33% RX 33% ("balanced TX and RX"), RMC settings as per 3GPP TS 35 35 40 40 mA 40 45 45 45 mA 95 105 110 110 mA 50 50 55 55 mA 65 65 75 75 mA 190 190 225 225 mA 36.101 Annex A.2.4 IRMC_10DBM Pout 10 dBm, QPSK, 1SC, 15 kHz, TX 33% RX 33% ("balanced TX and RX"), RMC settings as per 3GPP TS 36.101 Annex A.2.4 IRMC_23DBM Pout 23 dBm, QPSK, 1SC, 15 kHz, TX 33% RX 33% ("balanced TX and RX"), RMC settings as per 3GPP TS 36.101 Annex A.2.4 IRMC_0DBM Pout 0 dBm, BPSK, 1SC, 3.75 kHz, TX 80% RX 10% ("TX intensive"), RMC settings as per 3GPP TS 36.101 Annex A.2.4 IRMC_10DBM Pout 10 dBm, BPSK, 1SC, 3.75 kHz, TX 80% RX 10% ("TX intensive"), RMC settings as per 3GPP TS 36.101 Annex A.2.4 IRMC_23DBM Pout 23 dBm, BPSK, 1SC, 3.75 kHz, TX 80% RX 10% ("TX intensive"), RMC settings as per 3GPP TS 36.101 Annex A.2.4 Peak current consumption, nominal operating conditions, Cat-M1 ITX_0DBM TX subframe, Pout 0 dBm 60 60 65 65 mA ITX_10DBM TX subframe, Pout 10 dBm 80 85 90 90 mA ITX_23DBM TX subframe, Pout 23 dBm 255 275 295 290 mA IRX_-90DBM RX subframe, Pin -90 dBm 45 45 45 45 mA ITX_TRANSIENT TX transient 35 35 35 35 mA/µs Peak current consumption, nominal operating conditions, Cat-NB1 ITX_0DBM TX subframe, Pout 0 dBm 55 60 65 65 mA ITX_10DBM TX subframe, Pout 10 dBm 75 85 90 85 mA ITX_23DBM TX subframe, Pout 23 dBm 230 255 275 275 mA IRX_-90DBM RX subframe, Pin -90 dBm 35 35 35 35 mA ITX_TRANSIENT TX transient 35 35 35 35 mA/µs Peak current consumption, extreme operating conditions, Cat-M1 ITX_PEAK TX subframe, Pout >21 dBm, Ant VSWR3 330 355 360 360 mA ITX_PEAK TX subframe, Pout >20 dBm, Ant VSWR3, Vbat 3.5 V, Temp 85 °C 355 390 375 375 mA ITX_PEAK TX subframe, Pout >20 dBm, Ant VSWR3, Vbat 3.0 V, Temp 85 °C 415 415 435 435 mA Peak current consumption, extreme operating conditions, Cat-NB1 ITX_PEAK TX subframe, Pout >21 dBm, Ant VSWR3 280 310 325 325 mA ITX_PEAK TX subframe, Pout >20 dBm, Ant VSWR3, Vbat 3.5 V, Temp 85 °C 315 350 365 365 mA ITX_PEAK TX subframe, Pout >20 dBm, Ant VSWR3, Vbat 3.0 V, Temp 85 °C 370 405 425 425 mA 4418_1315 v2.0 63 Power and clock management 5.2.1.16 GPS current consumption Symbol Description IGPS_CONTINUOUS Continuous tracking, typical peak current without power Min. Typ. Max. Units 44.9 mA IGPS_CONTINUOUS_PSM Continuous tracking, power saving mode 9.6 mA IGPS_SINGLE 2.5 mA saving mode Single shot, one fix every 2 minutes 5.3 Register description 5.3.1 POWER — Power control The POWER module provides an interface to tasks, events, interrupt and reset related configuration settings of the power management unit. Note: Registers INTEN on page 67, INTENSET on page 67, and INTENCLR on page 68 are the same registers (at the same address) as corresponding registers in CLOCK — Clock control on page 70. 5.3.1.1 Registers Base address Peripheral Instance 0x50005000 POWER : S 0x40005000 POWER POWER : NS Secure mapping DMA security Description US NA Power control Table 21: Instances Register Offset TASKS_CONSTLAT 0x78 Security Description Enable constant latency mode. TASKS_LOWPWR 0x7C Enable low power mode (variable latency) SUBSCRIBE_CONSTLAT 0xF8 Subscribe configuration for task CONSTLAT SUBSCRIBE_LOWPWR 0xFC Subscribe configuration for task LOWPWR EVENTS_POFWARN 0x108 Power failure warning EVENTS_SLEEPENTER 0x114 CPU entered WFI/WFE sleep EVENTS_SLEEPEXIT 0x118 CPU exited WFI/WFE sleep PUBLISH_POFWARN 0x188 Publish configuration for event POFWARN PUBLISH_SLEEPENTER 0x194 Publish configuration for event SLEEPENTER PUBLISH_SLEEPEXIT 0x198 Publish configuration for event SLEEPEXIT INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt RESETREAS 0x400 Reset reason POWERSTATUS 0x440 Modem domain power status GPREGRET[n] 0x51C General purpose retention register Table 22: Register overview 5.3.1.1.1 TASKS_CONSTLAT Address offset: 0x78 Enable constant latency mode. 4418_1315 v2.0 64 Configuration Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_CONSTLAT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description Enable constant latency mode. Trigger task 5.3.1.1.2 TASKS_LOWPWR Address offset: 0x7C Enable low power mode (variable latency) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_LOWPWR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description Enable low power mode (variable latency) Trigger task 5.3.1.1.3 SUBSCRIBE_CONSTLAT Address offset: 0xF8 Subscribe configuration for task CONSTLAT Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that task CONSTLAT will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 5.3.1.1.4 SUBSCRIBE_LOWPWR Address offset: 0xFC Subscribe configuration for task LOWPWR Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that task LOWPWR will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 5.3.1.1.5 EVENTS_POFWARN Address offset: 0x108 Power failure warning 4418_1315 v2.0 65 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_POFWARN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Power failure warning 5.3.1.1.6 EVENTS_SLEEPENTER Address offset: 0x114 CPU entered WFI/WFE sleep Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_SLEEPENTER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated CPU entered WFI/WFE sleep 5.3.1.1.7 EVENTS_SLEEPEXIT Address offset: 0x118 CPU exited WFI/WFE sleep Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_SLEEPEXIT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated CPU exited WFI/WFE sleep 5.3.1.1.8 PUBLISH_POFWARN Address offset: 0x188 Publish configuration for event POFWARN Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that event POFWARN will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 5.3.1.1.9 PUBLISH_SLEEPENTER Address offset: 0x194 Publish configuration for event SLEEPENTER 4418_1315 v2.0 66 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that event SLEEPENTER will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 5.3.1.1.10 PUBLISH_SLEEPEXIT Address offset: 0x198 Publish configuration for event SLEEPEXIT Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that event SLEEPEXIT will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 5.3.1.1.11 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E D Reset 0x00000000 ID R/W Field A RW POFWARN D E RW RW A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Enable or disable interrupt for event POFWARN SLEEPENTER Enable or disable interrupt for event SLEEPENTER SLEEPEXIT Enable or disable interrupt for event SLEEPEXIT 5.3.1.1.12 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E D Reset 0x00000000 ID R/W Field A RW POFWARN 4418_1315 v2.0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event POFWARN 67 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E D Reset 0x00000000 ID D E R/W RW RW Field A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled SLEEPENTER Write '1' to enable interrupt for event SLEEPENTER SLEEPEXIT Write '1' to enable interrupt for event SLEEPEXIT 5.3.1.1.13 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E D Reset 0x00000000 ID R/W Field A RW POFWARN D E RW RW A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event POFWARN SLEEPENTER Write '1' to disable interrupt for event SLEEPENTER SLEEPEXIT Write '1' to disable interrupt for event SLEEPEXIT 5.3.1.1.14 RESETREAS Address offset: 0x400 Reset reason Note: Unless cleared, the RESETREAS register will be cumulative. A field is cleared by writing '1' to it. If none of the reset sources are flagged, this indicates that the chip was reset from the on-chip reset generator, which will indicate a power-on reset or a brownout reset. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID G F E Reset 0x00000000 ID R/W Field A RW RESETPIN 4418_1315 v2.0 D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Reset from pin reset detected 68 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID G F E Reset 0x00000000 ID B C R/W RW RW Field D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotDetected 0 Not detected Detected 1 Detected NotDetected 0 Not detected Detected 1 Detected DOG Reset from global watchdog detected OFF Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO D RW NotDetected 0 Not detected Detected 1 Detected DIF Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode E F G RW RW RW NotDetected 0 Not detected Detected 1 Detected SREQ Reset from AIRCR.SYSRESETREQ detected NotDetected 0 Not detected Detected 1 Detected NotDetected 0 Not detected Detected 1 Detected NotDetected 0 Not detected Detected 1 Detected LOCKUP Reset from CPU lock-up detected CTRLAP Reset triggered through CTRL-AP 5.3.1.1.15 POWERSTATUS Address offset: 0x440 Modem domain power status Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A R LTEMODEM 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description LTE modem domain status OFF 0 LTE modem domain is powered off ON 1 LTE modem domain is powered on 5.3.1.1.16 GPREGRET[n] (n=0..1) Address offset: 0x51C + (n × 0x4) General purpose retention register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x00000000 ID R/W Field A RW GPREGRET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description General purpose retention register This register is a retained register 4418_1315 v2.0 69 Power and clock management 5.3.2 CLOCK — Clock control The CLOCK module provides one of the interfaces to power and clock management configuration settings. Through CLOCK module it is able to configure the following: • • • • • LFCLK clock source setup LFCLK and HFCLK status Tasks and events Interrupts Reset Note: Registers INTEN on page 74, INTENSET on page 74, and INTENCLR on page 74 are the same registers (at the same address) as corresponding registers in POWER — Power control on page 64. 5.3.2.1 Registers Base address Peripheral Instance 0x50005000 CLOCK : S 0x40005000 CLOCK CLOCK : NS Secure mapping DMA security Description US NA Clock control Configuration Table 23: Instances Register Offset TASKS_HFCLKSTART 0x000 Security Description Start HFCLK source TASKS_HFCLKSTOP 0x004 Stop HFCLK source TASKS_LFCLKSTART 0x008 Start LFCLK source TASKS_LFCLKSTOP 0x00C Stop LFCLK source SUBSCRIBE_HFCLKSTART 0x080 Subscribe configuration for task HFCLKSTART SUBSCRIBE_HFCLKSTOP 0x084 Subscribe configuration for task HFCLKSTOP SUBSCRIBE_LFCLKSTART 0x088 Subscribe configuration for task LFCLKSTART SUBSCRIBE_LFCLKSTOP 0x08C Subscribe configuration for task LFCLKSTOP EVENTS_HFCLKSTARTED 0x100 HFCLK oscillator started EVENTS_LFCLKSTARTED 0x104 LFCLK started PUBLISH_HFCLKSTARTED 0x180 Publish configuration for event HFCLKSTARTED PUBLISH_LFCLKSTARTED 0x184 Publish configuration for event LFCLKSTARTED INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt INTPEND 0x30C Pending interrupts HFCLKRUN 0x408 Status indicating that HFCLKSTART task has been triggered HFCLKSTAT 0x40C The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has LFCLKRUN 0x414 Status indicating that LFCLKSTART task has been triggered LFCLKSTAT 0x418 The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART been started (STATE) task and if the source has been started (STATE) LFCLKSRCCOPY 0x41C Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered LFCLKSRC 0x518 Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register. Table 24: Register overview 4418_1315 v2.0 70 Power and clock management 5.3.2.1.1 TASKS_HFCLKSTART Address offset: 0x000 Start HFCLK source Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_HFCLKSTART 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description Start HFCLK source Trigger task 5.3.2.1.2 TASKS_HFCLKSTOP Address offset: 0x004 Stop HFCLK source Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_HFCLKSTOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description Stop HFCLK source Trigger task 5.3.2.1.3 TASKS_LFCLKSTART Address offset: 0x008 Start LFCLK source Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_LFCLKSTART 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description Start LFCLK source Trigger task 5.3.2.1.4 TASKS_LFCLKSTOP Address offset: 0x00C Stop LFCLK source Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_LFCLKSTOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description Stop LFCLK source Trigger task 5.3.2.1.5 SUBSCRIBE_HFCLKSTART Address offset: 0x080 4418_1315 v2.0 71 Power and clock management Subscribe configuration for task HFCLKSTART Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that task HFCLKSTART will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 5.3.2.1.6 SUBSCRIBE_HFCLKSTOP Address offset: 0x084 Subscribe configuration for task HFCLKSTOP Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that task HFCLKSTOP will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 5.3.2.1.7 SUBSCRIBE_LFCLKSTART Address offset: 0x088 Subscribe configuration for task LFCLKSTART Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that task LFCLKSTART will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 5.3.2.1.8 SUBSCRIBE_LFCLKSTOP Address offset: 0x08C Subscribe configuration for task LFCLKSTOP 4418_1315 v2.0 72 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that task LFCLKSTOP will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 5.3.2.1.9 EVENTS_HFCLKSTARTED Address offset: 0x100 HFCLK oscillator started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_HFCLKSTARTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated HFCLK oscillator started 5.3.2.1.10 EVENTS_LFCLKSTARTED Address offset: 0x104 LFCLK started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_LFCLKSTARTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated LFCLK started 5.3.2.1.11 PUBLISH_HFCLKSTARTED Address offset: 0x180 Publish configuration for event HFCLKSTARTED Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event HFCLKSTARTED will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 5.3.2.1.12 PUBLISH_LFCLKSTARTED Address offset: 0x184 4418_1315 v2.0 73 Power and clock management Publish configuration for event LFCLKSTARTED Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event LFCLKSTARTED will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 5.3.2.1.13 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B A Reset 0x00000000 ID R/W Field A RW HFCLKSTARTED B RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable interrupt for event HFCLKSTARTED Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable LFCLKSTARTED Enable or disable interrupt for event LFCLKSTARTED 5.3.2.1.14 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B A Reset 0x00000000 ID R/W Field A RW HFCLKSTARTED B RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event HFCLKSTARTED LFCLKSTARTED Write '1' to enable interrupt for event LFCLKSTARTED 5.3.2.1.15 INTENCLR Address offset: 0x308 Disable interrupt 4418_1315 v2.0 74 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B A Reset 0x00000000 ID R/W Field A RW HFCLKSTARTED B RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event HFCLKSTARTED LFCLKSTARTED Write '1' to disable interrupt for event LFCLKSTARTED 5.3.2.1.16 INTPEND Address offset: 0x30C Pending interrupts Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B A Reset 0x00000000 ID R/W Field A R HFCLKSTARTED B R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotPending 0 Read: Not pending Pending 1 Read: Pending NotPending 0 Read: Not pending Pending 1 Read: Pending Read pending status of interrupt for event HFCLKSTARTED LFCLKSTARTED Read pending status of interrupt for event LFCLKSTARTED 5.3.2.1.17 HFCLKRUN Address offset: 0x408 Status indicating that HFCLKSTART task has been triggered Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A R STATUS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotTriggered 0 Task not triggered Triggered 1 Task triggered HFCLKSTART task triggered or not 5.3.2.1.18 HFCLKSTAT Address offset: 0x40C The register shows if HFXO has been requested by triggering HFCLKSTART task and if it has been started (STATE) 4418_1315 v2.0 75 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A R SRC B R A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description HFINT 0 HFINT - 64 MHz on-chip oscillator HFXO 1 HFXO - 64 MHz clock derived from external 32 MHz crystal oscillator NotRunning 0 HFXO has not been started or HFCLKSTOP task has been triggered Running 1 HFXO has been started (HFCLKSTARTED event has been generated) Active clock source STATE HFCLK state 5.3.2.1.19 LFCLKRUN Address offset: 0x414 Status indicating that LFCLKSTART task has been triggered Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A R STATUS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotTriggered 0 Task not triggered Triggered 1 Task triggered LFCLKSTART task triggered or not 5.3.2.1.20 LFCLKSTAT Address offset: 0x418 The register shows which LFCLK source has been requested (SRC) when triggering LFCLKSTART task and if the source has been started (STATE) Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A R SRC B R A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description RFU 0 Reserved for future use LFRC 1 32.768 kHz RC oscillator LFXO 2 32.768 kHz crystal oscillator NotRunning 0 Running 1 Active clock source STATE LFCLK state Requested LFCLK source has not been started or LFCLKSTOP task has been triggered Requested LFCLK source has been started (LFCLKSTARTED event has been generated) 5.3.2.1.21 LFCLKSRCCOPY Address offset: 0x41C Copy of LFCLKSRC register, set after LFCLKSTART task has been triggered 4418_1315 v2.0 76 Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000001 ID R/W Field A R SRC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description RFU 0 Reserved for future use LFRC 1 32.768 kHz RC oscillator LFXO 2 32.768 kHz crystal oscillator Clock source 5.3.2.1.22 LFCLKSRC Address offset: 0x518 Clock source for the LFCLK. LFCLKSTART task starts starts a clock source selected with this register. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000001 ID R/W Field A RW SRC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description RFU 0 Reserved for future use (equals selecting LFRC) LFRC 1 32.768 kHz RC oscillator LFXO 2 32.768 kHz crystal oscillator Clock source 5.3.3 REGULATORS — Voltage regulators control The REGULATORS module provides an interface to certain configuration settings of on-chip voltage regulators. 5.3.3.1 Registers Base address Peripheral Instance Secure mapping DMA security Description US NA Regulator configuration REGULATORS : 0x50004000 0x40004000 REGULATORS S REGULATORS : NS Table 25: Instances Register Offset SYSTEMOFF 0x500 Security Description System OFF register DCDCEN 0x578 Enable DC/DC mode of the main voltage regulator. Table 26: Register overview 5.3.3.1.1 SYSTEMOFF Address offset: 0x500 System OFF register 4418_1315 v2.0 77 Configuration Power and clock management Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W SYSTEMOFF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Enable 1 Description Enable System OFF mode Enable System OFF mode 5.3.3.1.2 DCDCEN Address offset: 0x578 Enable DC/DC mode of the main voltage regulator. Note: DCDCEN must be set to 1 (enabled) before the LTE modem is started. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW DCDCEN 4418_1315 v2.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable DC/DC converter Disabled 0 DC/DC mode is disabled Enabled 1 DC/DC mode is enabled 78 6 Peripherals 6.1 CRYPTOCELL — ARM TrustZone CryptoCell 310 ARM TrustZone CryptoCell 310 (CRYPTOCELL) is a security subsystem which provides root of trust (RoT) and cryptographic services for a device. Flash Data RAM CRYPTOCELL library CRYPTOCELL workspace ARM Cortex CPU AHB multilayer SRAM TRNG Always-on domain Control interface Engine control logic SRAM Public key accelerator engine DMA Data routing AES HASH AHB-APB bridge ChaCha CRYPTOCELL APB Figure 13: Block diagram for CRYPTOCELL The following cryptographic features are provided: • True random number generator (TRNG) compliant with NIST 800-90B, AIS-31, and FIPS 140-2 • Pseudorandom number generator (PRNG) using underlying AES engine compliant with NIST 800-90A • RSA public key cryptography • Up to 2048-bit key size • PKCS#1 v2.1/v1.5 • Optional CRT support • Elliptic curve cryptography (ECC) • NIST FIPS 186-4 recommended curves using pseudorandom parameters, up to 521 bits: • Prime field: P-192, P-224, P-256, P-384, P-521 • SEC 2 recommended curves using pseudorandom parameters, up to 521 bits: • Prime field: secp160r1, secp192r1, secp224r1, secp256r1, secp384r1, secp521r1 • Koblitz curves using fixed parameters, up to 256 bits: 4418_1315 v2.0 79 Peripherals • Prime field: secp160k1, secp192k1, secp224k1, secp256k1 • Edwards/Montgomery curves: • Ed25519, Curve25519 • ECDH/ECDSA support • Secure remote password protocol (SRP) • Up to 3072-bit operations • Hashing functions • SHA-1, SHA-2 up to 256 bits • Keyed-hash message authentication code (HMAC) • AES symmetric encryption • General purpose AES engine (encrypt/decrypt, sign/verify) • 128-bit key size • Supported encryption modes: ECB, CBC, CMAC/CBC-MAC, CTR, CCM/CCM* (CCM* is a minor variation of CCM) • ChaCha20/Poly1305 symmetric encryption • Supported key size: 128 and 256 bits • Authenticated encryption with associated data (AEAD) mode 6.1.1 Usage The CRYPTOCELL state is controlled via a register interface. The cryptographic functions of CRYPTOCELL are accessible by using a software library provided in the device SDK, not directly via a register interface. To enable CRYPTOCELL, use register ENABLE on page 82. Note: Keeping the CRYPTOCELL subsystem enabled will prevent the device from reaching the System ON, All Idle state. 6.1.2 Always-on (AO) power domain The CRYPTOCELL subsystem has an internal always-on (AO) power domain for retaining device secrets when CRYPTOCELL is disabled. The following information is retained by the AO power domain: • 4 bits indicating the configured CRYPTOCELL lifecycle state (LCS) • 1 bit indicating if the hard-coded RTL key, KPRTL (see RTL key on page 81), is available for use • 128-bit device root key, KDR (see Device root key on page 81) A reset from any reset source will erase the content in the AO power domain. 6.1.3 Lifecycle state (LCS) Lifecycle refers to multiple states a device goes through during its lifetime. Two valid lifecycle states are offered for the device - debug and secure. The CRYPTOCELL subsystem lifecycle state (LCS) is controlled through register HOST_IOT_LCS on page 85. A valid LCS is configured by writing either value Debug or Secure into the LCS field of this register. A correctly configured LCS can be validated by reading back the read-only field LCS_IS_VALID from the abovementioned register. The LCS_IS_VALID field value will change from Invalid to Valid once a valid LCS value has been written. 4418_1315 v2.0 80 Peripherals LCS field value LCS_IS_VALID field value Secure Invalid Secure Valid Description Default reset value indicating that LCS has not been configured. LCS set to secure mode, and LCS is valid. Registers HOST_IOT_KDR[0..3] can only be written once per reset cycle. Any additional writes will be ignored. Debug Valid LCS set to debug mode, and LCS is valid. Registers HOST_IOT_KDR[0..3] can be written multiple times. Table 27: Lifecycle states 6.1.4 Cryptographic key selection The CRYPTOCELL subsystem can be instructed to operate on different cryptographic keys. Through register HOST_CRYPTOKEY_SEL on page 83, the following key types can be selected for cryptographic operations: • RTL key KPRTL • Device root key KDR • Session key KPRTL and KDR are configured as part of the CRYPTOCELL initialization process, while session keys are provided by the application through the software library API. 6.1.4.1 RTL key The ARM TrustZone CryptoCell 310 contains one hard-coded RTL key referred to as KPRTL. This key is set to the same value for all devices with the same part code in the hardware design and cannot be changed. The KPRTL key can be requested for use in cryptographic operations by the CRYPTOCELL, without revealing the key value itself. Access to use of KPRTL in cryptographic operations can be disabled until next reset by writing to register HOST_IOT_KPRTL_LOCK on page 84. If a locked KPRTL key is requested for use, a zero vector key will be routed to the AES engine instead. 6.1.4.2 Device root key The device root key KDR is a 128-bit AES key programmed into the CRYPTOCELL subsystem using firmware. It is retained in the AO power domain until the next reset. Once configured, it is possible to perform cryptographic operations using the the CRYPTOCELL subsystem where KDR is selected as key input without having access to the key value itself. The KDR key value must be written to registers HOST_IOT_KDR[0..3]. These 4 registers are write-only if LCS is set to debug mode, and write-once if LCS is set to secure mode. The KDR key value is successfully retained when the read-back value of register HOST_IOT_KDR0 on page 84 changes to 1. 6.1.5 Direct memory access (DMA) The CRYPTOCELL subsystem implements direct memory access (DMA) for accessing memory without CPU intervention. Any data stored in memory type(s) not accessible by the DMA engine must be copied to SRAM before it can be processed by the CRYPTOCELL subsystem. Maximum DMA transaction size is limited to 216-1 bytes. 6.1.6 Standards ARM TrustZone CryptoCell 310 (CRYPTOCELL) supports a number of cryptography standards. 4418_1315 v2.0 81 Peripherals Algorithm family Identification code Document title TRNG NIST SP 800-90B Recommendation for the Entropy Sources Used for Random Bit Generation AIS-31 A proposal for: Functionality classes and evaluation methodology for physical random number generators FIPS 140-2 Security Requirements for Cryptographic Modules PRNG NIST SP 800-90A Recommendation for Random Number Generation Using Deterministic Random Bit Generators Stream cipher Chacha ChaCha, a variant of Salsa20, Daniel J. Bernstein, January 28th 2008 MAC Poly1305 The Poly1305-AES message-authentication code, Daniel J. Bernstein Cryptography in NaCl, Daniel J. Bernstein Key agreement SRP The Secure Remote Password Protocol, Thomas Wu, November 11th 1997 AES FIPS-197 Advanced Encryption Standard (AES) NIST SP 800-38A Recommendation for Block Cipher Modes of Operation - Methods and Techniques NIST SP 800-38B Recommendation for Block Cipher Modes of Operation: The CMAC Mode for Authentication NIST SP 800-38C Recommendation for Block Cipher Modes of Operation: The CCM Mode for Authentication and Confidentiality ISO/IEC 9797-1 AES CBC-MAC per ISO/IEC 9797-1 MAC algorithm 1 IEEE 802.15.4-2011 IEEE Standard for Local and metropolitan area networks - Part 15.4: Low-Rate Wireless Personal Area Networks (LR-WPANs), Annex B.4: Specification of generic CCM* mode of operation Hash FIPS 180-3 Secure Hash Standard (SHA1, SHA-224, SHA-256) RFC2104 HMAC: Keyed-Hashing for Message Authentication RSA PKCS#1 Public-Key Cryptography Standards (PKCS) #1: RSA Cryptography Specifications v1.5/2.1 Diffie-Hellman ANSI X9.42 Public Key Cryptography for the Financial Services Industry: Agreement of Symmetric Keys Using Discrete Logarithm Cryptography ECC PKCS#3 Diffie-Hellman Key-Agreement Standard ANSI X9.63 Public Key Cryptography for the Financial Services Industry - Key Agreement and Key Transport Using Elliptic Curve Cryptography IEEE 1363 Standard Specifications for Public-Key Cryptography ANSI X9.62 Public Key Cryptography For The Financial Services Industry: The Elliptic Curve Digital Signature Algorithm (ECDSA) Edwards-curve, Ed25519: high-speed high-security signatures, Daniel J. Bernstein, Niels Duif, Tanja Lange, Ed25519 Peter Schwabe, and Bo-Yin Yang Curve25519 Montgomery curve, Curve25519: new Diffie-Hellman speed records, Daniel J. Bernstein FIPS 186-4 Digital Signature Standard (DSS) SEC 2 Recommended Elliptic Curve Domain Parameters, Certicom Research NIST SP 800-56A rev. 2 Recommendation for Pair-Wise Key Establishment Schemes Using Discrete Logarithm Cryptography Table 28: CRYPTOCELL cryptography standards 6.1.7 Registers Base address Peripheral Instance Secure mapping DMA security Description 0x50840000 CRYPTOCELL S NSA CryptoCell sub-system control CRYPTOCELL interface Table 29: Instances Register Offset ENABLE 0x500 Security Description Enable CRYPTOCELL subsystem Table 30: Register overview 6.1.7.1 ENABLE Address offset: 0x500 4418_1315 v2.0 82 Configuration Peripherals Enable CRYPTOCELL subsystem Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 CRYPTOCELL subsystem disabled Enabled 1 CRYPTOCELL subsystem enabled. Enable or disable the CRYPTOCELL subsystem When enabled the CRYPTOCELL subsystem can be initialized and controlled through the CryptoCell firmware API. 6.1.8 Host interface This chapter describes host registers used to control the CRYPTOCELL subsystem behavior. 6.1.8.1 HOST_RGF block The HOST_RGF block contains registers for configuring LCS and device root key KDR, in addition to selecting which cryptographic key is connected to the AES engine. 6.1.8.1.1 Registers Base address Peripheral 0x50840000 Instance Secure mapping CC_HOST_RGF CC_HOST_RGF S DMA security Description NSA Host platform interface Configuration Table 31: Instances Register Offset HOST_CRYPTOKEY_SEL 0x1A38 Security Description AES hardware key select HOST_IOT_KPRTL_LOCK 0x1A4C This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. HOST_IOT_KDR0 0x1A50 This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. HOST_IOT_KDR1 0x1A54 This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. HOST_IOT_KDR2 0x1A58 HOST_IOT_KDR3 0x1A5C This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. HOST_IOT_LCS 0x1A60 Controls lifecycle state (LCS) for CRYPTOCELL subsystem Table 32: Register overview 6.1.8.1.1.1 HOST_CRYPTOKEY_SEL Address offset: 0x1A38 AES hardware key select Note: If the HOST_IOT_KPRTL_LOCK register is set, and the HOST_CRYPTOKEY_SEL register set to 1, then the HW key that is connected to the AES engine is zero 4418_1315 v2.0 83 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000000 ID R/W Field A RW HOST_CRYPTOKEY_SEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description K_DR 0 Use device root key K_DR from CRYPTOCELL AO power domain K_PRTL 1 Use hard-coded RTL key K_PRTL Session 2 Use provided session key Select the source of the HW key that is used by the AES engine 6.1.8.1.1.2 HOST_IOT_KPRTL_LOCK Address offset: 0x1A4C This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW HOST_IOT_KPRTL_LOCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description This register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain. Disabled 0 K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL Enabled 1 K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead. 6.1.8.1.1.3 HOST_IOT_KDR0 Address offset: 0x1A50 This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID R/W Field A RW HOST_IOT_KDR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write: K_DR bits 31:0. Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain. Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain. 6.1.8.1.1.4 HOST_IOT_KDR1 Address offset: 0x1A54 This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. 4418_1315 v2.0 84 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A W HOST_IOT_KDR1 Value ID Value Description K_DR bits 63:32 6.1.8.1.1.5 HOST_IOT_KDR2 Address offset: 0x1A58 This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID R/W Field A W HOST_IOT_KDR2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description K_DR bits 95:64 6.1.8.1.1.6 HOST_IOT_KDR3 Address offset: 0x1A5C This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID R/W Field A W HOST_IOT_KDR3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description K_DR bits 127:96 6.1.8.1.1.7 HOST_IOT_LCS Address offset: 0x1A60 Controls lifecycle state (LCS) for CRYPTOCELL subsystem Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000002 ID R/W Field A RW LCS B RW A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Value ID Value Description Debug 0 CC310 operates in debug mode Secure 2 CC310 operates in secure mode Lifecycle state value. This field is write-once per reset. LCS_IS_VALID Read-only field. Indicates if CRYPTOCELL LCS has been successfully configured since last reset. 4418_1315 v2.0 Invalid 0 Valid LCS not yet retained in the CRYPTOCELL AO power domain Valid 1 Valid LCS successfully retained in the CRYPTOCELL AO power domain 85 Peripherals 6.2 DPPI - Distributed programmable peripheral interconnect The distributed programmable peripheral interconnect (DPPI) enables peripherals to interact autonomously with each other by using tasks and events, without any intervention from the CPU. DPPI allows precise synchronization between peripherals when real-time application constraints exist, and eliminates the need for CPU involvement to implement behavior which can be predefined using the DPPI. Note: For more information on tasks, events, publish/subscribe, interrupts, and other concepts, see Peripheral interface on page 15. The DPPI has the following features: • Peripheral tasks can subscribe to channels • Peripheral events can be published on channels • Publish/subscribe pattern enabling multiple connection options that include the following: • • • • One-to-one One-to-many Many-to-one Many-to-many The DPPI consists of several PPIBus modules, which are connected to a fixed number of DPPI channels and a DPPI configuration (DPPIC). 4418_1315 v2.0 86 tasks[0:M-1] events[0:N-1] PPIBus Channel X-1 PeripheralCore Channel 2 Channel 0 Peripheral A Channel 1 Peripherals ppiBusProducer [0:X-1] ppiBusConsumer[0:X-1] Peripheral B CHENSET / CHENCLR DPPI configuration tasks[0:J-1] events[0:I-1] PeripheralCore ppiBusProducer [0:X-1] PPIBus ppiBusConsumer[0:X-1] Figure 14: DPPI overview 6.2.1 Subscribing to and publishing on channels The PPIBus can route peripheral events onto the channels (publishing), or route events from the channels into peripheral tasks (subscribing). All peripherals include the following: • One subscribe register per task • One publish register per event Publish and subscribe registers use a channel index field to determine the channel to which the event is published or tasks subscribed. In addition, there is an enable bit for the subscribe and publish registers that needs to be enabled before the subscription or publishing takes effect. Writing non-existing channel index (CHIDX) numbers into a peripheral's publish or subscribe registers will yield unexpected results. One event can trigger multiple tasks by subscribing different tasks to the same channel. Similarly, one task can be triggered by multiple events by publishing different events to the same channel. For advanced use cases, multiple events and multiple tasks can connect to the same channel forming a many-to-many connection. If multiple events are published on the same channel at the same time, the events are merged and only one event is routed through the DPPI. How peripheral events are routed onto different channels based on publish registers is illustrated in the following figure. 4418_1315 v2.0 87 Peripherals event[0] event[N-1] PeripheralCore PPIBus EN PUB[0] EN PUB[N-1] ppiBusProducer[X-1] CHIDX ppiBusProducer[0] CHIDX Figure 15: DPPI events flow The following figure illustrates how peripheral tasks are triggered from different channels based on subscribe registers. 4418_1315 v2.0 88 ppiBusConsumer[X-1] ppiBusConsumer[1] ppiBusConsumer[0] Peripherals PPIBus SUB[0] SUB[M-1] CHIDX CHIDX EN task[0] task[M-1] EN PeripheralCore Figure 16: DPPI tasks flow 6.2.2 DPPI configuration (DPPIC) Enabling and disabling of channels globally is handled through the DPPI configuration (DPPIC). Connection (connect/disconnect) between a channel and a peripheral is handled locally by the PPIBus. There are two ways of enabling and disabling global channels using the DPPI configuration: • Enable or disable channels individually using registers CHEN, CHENSET, and CHENCLR. • Enable or disable channels in channel groups using the groups' tasks ENABLE and DISABLE. It needs to be defined which channels belong to which channel groups before these tasks are triggered. Note: ENABLE tasks are prioritized over DISABLE tasks. When a channel belongs to two or more groups, for example group m and n, and the tasks CHG[m].EN and CHG[n].DIS occur simultaneously (m and n can be equal or different), the CHG[m].EN task on that channel is prioritized. The DPPI configuration tasks (for example CHG[0].EN) can be triggered through DPPI like any other task, which means they can be linked to a DPPI channel through the subscribe registers. In order to write to CHG[x], the corresponding CHG[x].EN and CHG[x].DIS subscribe registers must be disabled. Writes to CHG[x] are ignored if any of the two subscribe registers are enabled. 6.2.3 Connection examples DPPI offers several connection options. Examples are given for how to create one-to-one and many-tomany connections. 4418_1315 v2.0 89 Peripherals One-to-one connection This example shows how to create a one-to-one connection between TIMER compare register and SAADC start task. The channel configuration is set up first. TIMER0 will publish its COMPARE0 event on channel 0, and SAADC will subscribe its START task to events on the same channel. After that, the channel is enabled through the DPPIC. NRF_TIMER0->PUBLISH_COMPARE0 = (DPPI_PUB_CHIDX_Ch0) | NRF_SAADC->SUBSCRIBE_START (DPPI_PUB_EN_Msk); = (DPPI_SUB_CHIDX_Ch0) | (DPPI_SUB_EN_Msk); NRF_DPPIC->CHENSET = (DPPI_CHENSET_CH0_Set = 3 mA 1.7 V tRF,15pF Rise/fall time, standard drive mode, 10-90%, 15 pF load1 6 9 19 ns tRF,25pF 1 10 13 30 ns 1 25 61 ns Rise/fall time, standard drive mode, 10-90%, 25 pF load tRF,50pF Rise/fall time, standard drive mode, 10-90%, 50 pF load 18 tHRF,15pF Rise/Fall time, high drive mode, 10-90%, 15 pF load1 2 4 8 ns tHRF,25pF Rise/Fall time, high drive mode, 10-90%, 25 pF load1 3 5 11 ns tHRF,50pF 1 Rise/Fall time, high drive mode, 10-90%, 50 pF load 5 8 19 ns RPU Pull-up resistance 11 13 16 kΩ RPD Pull-down resistance 11 13 16 kΩ CPAD Pad capacitance 3 pF 6.5 GPIOTE — GPIO tasks and events The GPIO tasks and events (GPIOTE) module provides functionality for accessing GPIO pins using tasks and events. Each GPIOTE channel can be assigned to one pin. A GPIOTE block enables GPIOs to generate events on pin state change which can be used to carry out tasks through the PPI system. A GPIO can also be driven to change state on system events using the PPI system. Tasks and events are briefly introduced in Peripheral interface on page 15, and GPIO is described in more detail in GPIO — General purpose input/output on page 97. Low power detection of pin state changes is possible when in System ON or System OFF. Instance Number of GPIOTE channels GPIOTE 8 Table 39: GPIOTE properties Up to three tasks can be used in each GPIOTE channel for performing write operations to a pin. Two tasks are fixed (SET and CLR), and one (OUT) is configurable to perform following operations: • Set • Clear • Toggle 1 Rise and fall times based on simulations 4418_1315 v2.0 106 Peripherals An event can be generated in each GPIOTE channel from one of the following input conditions: • Rising edge • Falling edge • Any change 6.5.1 Pin events and tasks The GPIOTE module has a number of tasks and events that can be configured to operate on individual GPIO pins. The tasks SET[n], CLR[n], and OUT[n] can write to individual pins, and events IN[n] can be generated from input changes of individual pins. The SET task will set the pin selected in GPIOTE.CONFIG[n].PSEL to high. The CLR task will set the pin low. The effect of the OUT task on the pin is configurable in CONFIG[n].POLARITY. It can set the pin high, set it low, or toggle it. Tasks and events are configured using the CONFIG[n] registers. One CONFIG[n] register is associated with a set of SET[n], CLR[n], and OUT[n] tasks and IN[n] events. As long as a SET[n], CLR[n], and OUT[n] task or an IN[n] event is configured to control pin n, the pin's output value will only be updated by the GPIOTE module. The pin's output value, as specified in the GPIO, will be ignored as long as the pin is controlled by GPIOTE. Attempting to write to the pin as a normal GPIO pin will have no effect. When the GPIOTE is disconnected from a pin, the associated pin gets the output and configuration values specified in the GPIO module, see MODE field in CONFIG[n] register. When conflicting tasks are triggered simultaneously (i.e. during the same clock cycle) in one channel, the priority of the tasks is as described in the following table. Priority Task 1 OUT 2 CLR 3 SET Table 40: Task priorities When setting the CONFIG[n] registers, MODE=Disabled does not have the same effect as MODE=Task and POLARITY=None. In the latter case, a CLR or SET task occurring at the exact same time as OUT will end up with no change on the pin, based on the priorities described in the table above. When a GPIOTE channel is configured to operate on a pin as a task, the initial value of that pin is configured in the OUTINIT field of CONFIG[n]. 6.5.2 Port event PORT is an event that can be generated from multiple input pins using the GPIO DETECT signal. The event will be generated on the rising edge of the DETECT signal. See GPIO — General purpose input/ output on page 97 for more information about the DETECT signal. The GPIO DETECT signal will not wake the system up again if the system is put into System ON IDLE while the DETECT signal is high. Clear all DETECT sources before entering sleep. If the LATCH register is used as a source, a new rising edge will be generated on DETECT if any bit in LATCH is still high after clearing all or part of the register. This could occur if one of the PINx.DETECT signals is still high, for example. See Pin sense mechanism on page 99 for more information. Setting the system to System OFF while DETECT is high will cause a wakeup from System OFF reset. 4418_1315 v2.0 107 Peripherals This feature can be used to wake up the CPU from a WFI or WFE type sleep in System ON when all peripherals and the CPU are idle, meaning the lowest power consumption in System ON mode. To prevent spurious interrupts from the PORT event while configuring the sources, the following steps must be performed: 1. 2. 3. 4. Disable interrupts on the PORT event (through INTENCLR.PORT). Configure the sources (PIN_CNF[n].SENSE). Clear any potential event that could have occurred during configuration (write 0 to EVENTS_PORT). Enable interrupts (through INTENSET.PORT). 6.5.3 Tasks and events pin configuration Each GPIOTE channel is associated with one physical GPIO pin through the CONFIG.PSEL field. When Event mode is selected in CONFIG.MODE, the pin specified by CONFIG.PSEL will be configured as an input, overriding the DIR setting in GPIO. Similarly, when Task mode is selected in CONFIG.MODE, the pin specified by CONFIG.PSEL will be configured as an output overriding the DIR setting and OUT value in GPIO. When Disabled is selected in CONFIG.MODE, the pin specified by CONFIG.PSEL will use its configuration from the PIN[n].CNF registers in GPIO. CONFIG.MODE must be disabled in order to be able to change the value of the PSEL field. Note: A pin can only be assigned to one GPIOTE channel at a time. Failing to do so may result in unpredictable behavior. 6.5.4 Registers Base address Peripheral Instance Secure mapping DMA security Description 0x5000D000 GPIOTE GPIOTE0 S NA Secure GPIO tasks and events 0x40031000 GPIOTE GPIOTE1 NS NA Non Secure GPIO tasks and Configuration events Table 41: Instances Register Offset TASKS_OUT[n] 0x000 Security Description TASKS_SET[n] 0x030 Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. TASKS_CLR[n] 0x060 Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. SUBSCRIBE_OUT[n] 0x080 Subscribe configuration for task OUT[n] SUBSCRIBE_SET[n] 0x0B0 Subscribe configuration for task SET[n] SUBSCRIBE_CLR[n] 0x0E0 Subscribe configuration for task CLR[n] EVENTS_IN[n] 0x100 Event generated from pin specified in CONFIG[n].PSEL EVENTS_PORT 0x17C Event generated from multiple input GPIO pins with SENSE mechanism enabled PUBLISH_IN[n] 0x180 Publish configuration for event IN[n] PUBLISH_PORT 0x1FC Publish configuration for event PORT INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt CONFIG[n] 0x510 Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. Table 42: Register overview 6.5.4.1 TASKS_OUT[n] (n=0..7) Address offset: 0x000 + (n × 0x4) 4418_1315 v2.0 108 Peripherals Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_OUT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY. Trigger 1 Trigger task 6.5.4.2 TASKS_SET[n] (n=0..7) Address offset: 0x030 + (n × 0x4) Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_SET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high. Trigger 1 Trigger task 6.5.4.3 TASKS_CLR[n] (n=0..7) Address offset: 0x060 + (n × 0x4) Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_CLR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low. Trigger 1 Trigger task 6.5.4.4 SUBSCRIBE_OUT[n] (n=0..7) Address offset: 0x080 + (n × 0x4) Subscribe configuration for task OUT[n] Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN 4418_1315 v2.0 A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that task OUT[n] will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 109 Peripherals 6.5.4.5 SUBSCRIBE_SET[n] (n=0..7) Address offset: 0x0B0 + (n × 0x4) Subscribe configuration for task SET[n] Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that task SET[n] will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.5.4.6 SUBSCRIBE_CLR[n] (n=0..7) Address offset: 0x0E0 + (n × 0x4) Subscribe configuration for task CLR[n] Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that task CLR[n] will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.5.4.7 EVENTS_IN[n] (n=0..7) Address offset: 0x100 + (n × 0x4) Event generated from pin specified in CONFIG[n].PSEL Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_IN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Event generated from pin specified in CONFIG[n].PSEL NotGenerated 0 Event not generated Generated 1 Event generated 6.5.4.8 EVENTS_PORT Address offset: 0x17C Event generated from multiple input GPIO pins with SENSE mechanism enabled 4418_1315 v2.0 110 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_PORT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Event generated from multiple input GPIO pins with SENSE mechanism enabled NotGenerated 0 Event not generated Generated 1 Event generated 6.5.4.9 PUBLISH_IN[n] (n=0..7) Address offset: 0x180 + (n × 0x4) Publish configuration for event IN[n] Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event IN[n] will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.5.4.10 PUBLISH_PORT Address offset: 0x1FC Publish configuration for event PORT Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event PORT will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.5.4.11 INTENSET Address offset: 0x304 Enable interrupt 4418_1315 v2.0 111 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID I Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A-H RW IN[i] (i=0..7) I RW H G F E D C B A Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event IN[i] PORT Write '1' to enable interrupt for event PORT 6.5.4.12 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID I Reset 0x00000000 ID R/W Field A-H RW IN[i] (i=0..7) I RW H G F E D C B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event IN[i] Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled PORT Write '1' to disable interrupt for event PORT Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.5.4.13 CONFIG[n] (n=0..7) Address offset: 0x510 + (n × 0x4) Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E Reset 0x00000000 ID R/W Field A RW MODE D D B B B B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Disabled 0 Event 1 Description Mode Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. Event mode The pin specified by PSEL will be configured as an input and the IN[n] event will be generated if operation specified in POLARITY occurs on the pin. 4418_1315 v2.0 112 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E Reset 0x00000000 ID R/W Field D D B B B B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Task 3 Task mode The GPIO specified by PSEL will be configured as an output and triggering the SET[n], CLR[n] or OUT[n] task will perform the operation specified by POLARITY on the pin. When enabled as a task the GPIOTE module will acquire the pin and the pin can no longer be written as a regular output pin from the GPIO module. B RW PSEL D RW POLARITY [0..31] GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. None 0 LoToHi 1 HiToLo 2 Toggle 3 Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. E RW OUTINIT When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. Low 0 Task mode: Initial value of pin before task triggering is low High 1 Task mode: Initial value of pin before task triggering is high 6.5.5 Electrical specification 6.6 IPC — Interprocessor communication The interprocessor communication (IPC) peripheral is used to send and receive events between MCUs in the system. 4418_1315 v2.0 113 Peripherals IPC channel M NVIC IPC channel 2 Cortex-M IPC channel 1 System-bus IPC channel 0 MCU subsystem 0 IRQ eventOut[0..N] IPC0 eventIn[0..N] MCU subsystem 1 System-bus Cortex-M NVIC IRQ eventOut[0..K] IPC1 eventIn[0..K] Figure 20: IPC block diagram Functional description IPC block diagram on page 114 illustrates the interprocessor communication (IPC) peripheral. In a multiMCU system, each MCU has one dedicated IPC peripheral. The IPC peripheral can be used to send and receive events to and from other IPC peripherals. An instance of the IPC peripheral can have multiple SEND tasks and RECEIVE events. A single SEND task can be configured to signal an event on one or more IPC channels, and a RECEIVE event can be configured to listen on one or more IPC channels. The IPC channels that are triggered in a SEND task can be configured through the SEND_CNF registers, and the IPC channels that trigger a RECEIVE event are configured through the RECEIVE_CNF registers. The figure below illustrates how the SEND_CNF and RECEIVE_CNF registers work. Both the SEND task and the RECEIVE event can be connected to all IPC channels. 4418_1315 v2.0 114 TASK_SEND[0] TASK_SEND[N] IPC channel X IPC channel 0 Peripherals eventOut0 eventOut N EVENTS_RECEIVE[0] eventIn1 EVENTS_RECEIVE[N] eventIn N Figure 21: IPC registers SEND_CNF and RECEIVE_CNF A SEND task can be viewed as broadcasting events onto one or more IPC channels, and a RECEIVE event can be seen as subscribing to a subset of IPC channels. It is possible for multiple IPCs to trigger events onto the same channel at the same time. When two or more events on the same channel occur within tIPC, the events may be merged into a single event seen from the IPC receiver. One of the events can therefore be lost. To prevent this, the user must ensure that events on the same IPC channel do not occur within tIPC of each other. When implementing firmware data structures, such as queues or mailboxes, this can be done by using one channel for acknowledgements. An IPC event often does not contain any data itself, it is used to signal other MCUs that something has occurred. Data can be shared through shared memory, for example in the form of a software implemented mailbox, or command/event queues. It is up to software to assign a logical functionality to an IPC channel. For instance, one IPC channel can be used to signal that a command is ready to be executed, and any processor in the system can subscribe to that particular channel and decode/execute the command. General purpose memory The GPMEM registers can be used freely to store information. These registers are accessed like any other of the IPC peripheral's registers. 6.6.1 IPC and PPI connections The IPC SEND tasks and RECEIVE events can be connected through PPI channels. This makes it possible to relay events from peripherals in one MCU to another, without CPU involvement. Figure below illustrates a timer COMPARE event that is relayed from one MCU to IPC using PPI, then back into a timer CAPTURE event in another MCU. 4418_1315 v2.0 115 Peripherals MCU 0 PPI channel 0 MCU 1 PPI channel 0 IPC channel 0 PUBLISH_COMPARE[0] TASKS_CAPTURE[0] TIMER TIMER IPC SUBSCRIBE_SEND[0] IPC PUBLISH_RECEIVE[0] Figure 22: Example of PPI and IPC connections 6.6.2 Registers Base address Peripheral Instance 0x5002A000 IPC : S 0x4002A000 IPC Secure mapping DMA security US IPC : NS Description Configuration Interprocessor NA communication Table 43: Instances Register Offset TASKS_SEND[n] 0x000 Security Description Trigger events on IPC channel enabled in SEND_CNF[n] SUBSCRIBE_SEND[n] 0x080 Subscribe configuration for task SEND[n] EVENTS_RECEIVE[n] 0x100 Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] PUBLISH_RECEIVE[n] 0x180 Publish configuration for event RECEIVE[n] INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt INTPEND 0x30C Pending interrupts SEND_CNF[n] 0x510 Send event configuration for TASKS_SEND[n] RECEIVE_CNF[n] 0x590 Receive event configuration for EVENTS_RECEIVE[n] GPMEM[n] 0x610 General purpose memory Table 44: Register overview 6.6.2.1 TASKS_SEND[n] (n=0..7) Address offset: 0x000 + (n × 0x4) Trigger events on IPC channel enabled in SEND_CNF[n] Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_SEND 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description Trigger events on IPC channel enabled in SEND_CNF[n] Trigger task 6.6.2.2 SUBSCRIBE_SEND[n] (n=0..7) Address offset: 0x080 + (n × 0x4) Subscribe configuration for task SEND[n] 4418_1315 v2.0 116 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that task SEND[n] will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.6.2.3 EVENTS_RECEIVE[n] (n=0..7) Address offset: 0x100 + (n × 0x4) Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_RECEIVE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Event received on one or more of the enabled IPC channels in RECEIVE_CNF[n] NotGenerated 0 Event not generated Generated 1 Event generated 6.6.2.4 PUBLISH_RECEIVE[n] (n=0..7) Address offset: 0x180 + (n × 0x4) Publish configuration for event RECEIVE[n] Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event RECEIVE[n] will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.6.2.5 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E D C B A Reset 0x00000000 ID R/W Field A-H RW RECEIVE[i] (i=0..7) 4418_1315 v2.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Enable or disable interrupt for event RECEIVE[i] 117 Peripherals 6.6.2.6 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E D C B A Reset 0x00000000 ID R/W Field A-H RW RECEIVE[i] (i=0..7) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event RECEIVE[i] 6.6.2.7 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E D C B A Reset 0x00000000 ID R/W Field A-H RW RECEIVE[i] (i=0..7) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event RECEIVE[i] 6.6.2.8 INTPEND Address offset: 0x30C Pending interrupts Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E D C B A Reset 0x00000000 ID R/W Field A-H R RECEIVE[i] (i=0..7) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Read pending status of interrupt for event RECEIVE[i] NotPending 0 Read: Not pending Pending 1 Read: Pending 6.6.2.9 SEND_CNF[n] (n=0..7) Address offset: 0x510 + (n × 0x4) Send event configuration for TASKS_SEND[n] 4418_1315 v2.0 118 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A-H RW CHEN[i] (i=0..7) Value ID Value Description Disable 0 Disable broadcast Enable 1 Enable broadcast Enable broadcasting on IPC channel i 6.6.2.10 RECEIVE_CNF[n] (n=0..7) Address offset: 0x590 + (n × 0x4) Receive event configuration for EVENTS_RECEIVE[n] Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E D C B A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A-H RW CHEN[i] (i=0..7) Value ID Value Description Disable 0 Disable events Enable 1 Enable events Enable subscription to IPC channel i 6.6.2.11 GPMEM[n] (n=0..3) Address offset: 0x610 + (n × 0x4) General purpose memory Retained only in System ON mode Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW GPMEM Value ID Value Description General purpose memory 6.6.3 Electrical specification 6.6.3.1 IPC Electrical Specification Symbol Description tIPC Time window during which IPC events can be merged Min. Typ. Max. Units 165 µs 6.7 I2S — Inter-IC sound interface The I2S (Inter-IC Sound) module, supports the original two-channel I2S format, and left or right-aligned formats. It implements EasyDMA for sample transfer directly to and from RAM without CPU intervention. The I2S peripheral has the following main features: • Master and Slave mode • Simultaneous bi-directional (TX and RX) audio streaming • Original I2S and left- or right-aligned format 4418_1315 v2.0 119 Peripherals • 8, 16 and 24-bit sample width • Low-jitter Master Clock generator • Various sample rates PSEL.MCK PSEL.LRCK PSEL.SCK PSEL.SDIN PSEL.SDOUT I2S CONFIG.MCKEN Master clock generator MCK CONFIG.MCKFREQ Div CONFIG.RATIO CONFIG.FORMAT Div SDIN SCK LRCK CONFIG.ALIGN Serial tranceiever TXD.PTR RXD.PTR RXTXD.MAXCNT EasyDMA SDOUT CONFIG.MODE RAM Figure 23: I2S master 6.7.1 Mode The I2S protocol specification defines two modes of operation, Master and Slave. The I2S mode decides which of the two sides (Master or Slave) shall provide the clock signals LRCK and SCK, and these signals are always supplied by the Master to the Slave. 6.7.2 Transmitting and receiving The I2S module supports both transmission (TX) and reception (RX) of serial data. In both cases the serial data is shifted synchronously to the clock signals SCK and LRCK. TX data is written to the SDOUT pin on the falling edge of SCK, and RX data is read from the SDIN pin on the rising edge of SCK. The most significant bit (MSB) is always transmitted first. Note: When starting a transmission in master mode, two frames (two left-and-right sample pairs) of value zero will be transmitted after triggering the START task, prior to the RXTXD.MAXCNT samples specified by the TXD.PTR pointer. TX and RX are available in both Master and Slave modes and can be enabled/disabled independently in the CONFIG.TXEN on page 134 and CONFIG.RXEN on page 134. Transmission and/or reception is started by triggering the START task. When started and transmission is enabled (in CONFIG.TXEN on page 134), the TXPTRUPD event will be generated for every RXTXD.MAXCNT on page 137 number of transmitted data words (containing one or more samples). 4418_1315 v2.0 120 Peripherals Similarly, when started and reception is enabled (in CONFIG.RXEN on page 134), the RXPTRUPD event will be generated for every RXTXD.MAXCNT on page 137 received data words. RXTXD.MAXCNT Left 0 Right 0 Left 1 RIght 1 Left 2 Right 2 Left 3 A A A A C C C Right 3 C Left 4 E B B B B D D D D F RXPTRUPD TXPTRUPD RXPTRUPD RXPTRUPD TXPTRUPD RXD.PTR = H TXD.PTR = G RXD.PTR = F TXD.PTR = E TXD.PTR = C RXD.PTR = D START TXD.PTR = A RXD.PTR = B CPU TXPTRUPD LRCK SCK SDIN SDOUT RXTXD.MAXCNT Figure 24: Transmitting and receiving. CONFIG.FORMAT = Aligned, CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Stereo, RXTXD.MAXCNT = 1. 6.7.3 Left right clock (LRCK) The Left Right Clock (LRCK), often referred to as "word clock", "sample clock" or "word select" in I2S context, is the clock defining the frames in the serial bit streams sent and received on SDOUT and SDIN, respectively. In I2S mode, each frame contains one left and right sample pair, with the left sample being transferred during the low half period of LRCK followed by the right sample being transferred during the high period of LRCK. In Aligned mode, each frame contains one left and right sample pair, with the left sample being transferred during the high half period of LRCK followed by the right sample being transferred during the low period of LRCK. Consequently, the LRCK frequency is equivalent to the audio sample rate. When operating in Master mode, the LRCK is generated from the MCK, and the frequency of LRCK is then given as: LRCK = MCK / CONFIG.RATIO LRCK always toggles around the falling edge of the serial clock SCK. 6.7.4 Serial clock (SCK) The serial clock (SCK), often referred to as the serial bit clock, pulses once for each data bit being transferred on the serial data lines SDIN and SDOUT. When operating in Master mode the SCK is generated from the MCK, and the frequency of SCK is then given as: SCK = 2 * LRCK * CONFIG.SWIDTH The falling edge of the SCK falls on the toggling edge of LRCK. When operating in Slave mode SCK is provided by the external I2S master. 4418_1315 v2.0 121 Peripherals 6.7.5 Master clock (MCK) The master clock (MCK) is the clock from which LRCK and SCK are derived when operating in Master mode. The MCK is generated by an internal MCK generator. This generator always needs to be enabled when in Master mode, but the generator can also be enabled when in Slave mode. Enabling the generator when in slave mode can be useful in the case where the external Master is not able to generate its own master clock. The MCK generator is enabled/disabled in the register CONFIG.MCKEN on page 134, and the generator is started or stopped by the START or STOP tasks. In Master mode the LRCK and the SCK frequencies are closely related, as both are derived from MCK and set indirectly through CONFIG.RATIO on page 135 and CONFIG.SWIDTH on page 136. When configuring these registers, the user is responsible for fulfilling the following requirements: 1. SCK frequency can never exceed the MCK frequency, which can be formulated as: CONFIG.RATIO >= 2 * CONFIG.SWIDTH 2. The MCK/LRCK ratio shall be a multiple of 2 * CONFIG.SWIDTH, which can be formulated as: Integer = (CONFIG.RATIO / (2 * CONFIG.SWIDTH)) The MCK signal can be routed to an output pin (specified in PSEL.MCK) to supply external I2S devices that require the MCK to be supplied from the outside. When operating in Slave mode, the I2S module does not use the MCK and the MCK generator does not need to be enabled. RATIO = MCK LRCK MCK LRCK SWIDTH SCK Figure 25: Relation between RATIO, MCK and LRCK. Desired LRCK CONFIG.SWIDTH CONFIG.RATIO CONFIG.MCKFREQ MCK [Hz] [Hz] LRCK [Hz] LRCK error [%] 16000 16Bit 32X 32MDIV63 507936.5 15873.0 -0.8 16000 16Bit 64X 32MDIV31 1032258.1 16129.0 0.8 16000 16Bit 256X 32MDIV8 4000000.0 15625.0 -2.3 32000 16Bit 32X 32MDIV31 1032258.1 32258.1 0.8 32000 16Bit 64X 32MDIV16 2000000.0 31250.0 -2.3 44100 16Bit 32X 32MDIV23 1391304.3 43478.3 -1.4 44100 16Bit 64X 32MDIV11 2909090.9 45454.5 3.1 Table 45: Configuration examples 6.7.6 Width, alignment and format The CONFIG.SWIDTH register primarily defines the sample width of the data written to memory. In master mode, it then also sets the amount of bits per frame. In Slave mode it controls padding/trimming if required. Left, right, transmitted, and received samples always have the same width. The CONFIG.FORMAT 4418_1315 v2.0 122 Peripherals register specifies the position of the data frames with respect to the LRCK edges in both Master and Slave modes. When using I2S format, the first bit in a half-frame (containing one left or right sample) gets sampled on the second rising edge of the SCK after a LRCK edge. When using Aligned mode, the first bit in a half-frame gets sampled on the first rising edge of SCK following a LRCK edge. For data being received on SDIN the sample value can be either right or left-aligned inside a half-frame, as specified in CONFIG.ALIGN on page 136. CONFIG.ALIGN on page 136 affects only the decoding of the incoming samples (SDIN), while the outgoing samples (SDOUT) are always left-aligned (or justified). When using left-alignment, each half-frame starts with the MSB of the sample value (both for data being sent on SDOUT and received on SDIN). When using right-alignment, each half-frame of data being received on SDIN ends with the LSB of the sample value, while each half-frame of data being sent on SDOUT starts with the MSB of the sample value (same as for left-alignment). In Master mode, the size of a half-frame (in number of SCK periods) equals the sample width (in number of bits), and in this case the alignment setting does not care as each half-frame in any case will start with the MSB and end with the LSB of the sample value. In slave mode, however, the sample width does not need to equal the frame size. This means you might have extra or fewer SCK pulses per half-frame than what the sample width specified in CONFIG.SWIDTH requires. In the case where we use left-alignment and the number of SCK pulses per half-frame is higher than the sample width, the following will apply: • For data received on SDIN, all bits after the LSB of the sample value will be discarded. • For data sent on SDOUT, all bits after the LSB of the sample value will be 0. In the case where we use left-alignment and the number of SCK pulses per frame is lower than the sample width, the following will apply: • Data sent and received on SDOUT and SDIN will be truncated with the LSBs being removed first. In the case where we use right-alignment and the number of SCK pulses per frame is higher than the sample width, the following will apply: • For data received on SDIN, all bits before the MSB of the sample value will be discarded. • For data sent on SDOUT, all bits after the LSB of the sample value will be 0 (same behavior as for leftalignment). In the case where we use right-alignment and the number of SCK pulses per frame is lower than the sample width, the following will apply: • Data received on SDIN will be sign-extended to "sample width" number of bits before being written to memory. • Data sent on SDOUT will be truncated with the LSBs being removed first (same behavior as for leftalignment). frame LRCK left right left SCK SDIN or SDOUT Figure 26: I2S format. CONFIG.SWIDTH equalling half-frame size. 4418_1315 v2.0 123 Peripherals frame LRCK right left left SCK SDATA Figure 27: Aligned format. CONFIG.SWIDTH equalling half-frame size. 6.7.7 EasyDMA The I2S module implements EasyDMA for accessing internal Data RAM without CPU intervention. The source and destination pointers for the TX and RX data are configured in TXD.PTR on page 137 and RXD.PTR on page 137. The memory pointed to by these pointers will only be read or written when TX or RX are enabled in CONFIG.TXEN on page 134 and CONFIG.RXEN on page 134. The addresses written to the pointer registers TXD.PTR on page 137 and RXD.PTR on page 137 are double-buffered in hardware, and these double buffers are updated for every RXTXD.MAXCNT on page 137 words (containing one or more samples) read/written from/to memory. The events TXPTRUPD and RXPTRUPD are generated whenever the TXD.PTR and RXD.PTR are transferred to these double buffers. If TXD.PTR on page 137 is not pointing to the Data RAM region when transmission is enabled, or RXD.PTR on page 137 is not pointing to the Data RAM region when reception is enabled, an EasyDMA transfer may result in a HardFault and/or memory corruption. See Memory on page 21 for more information about the different memory regions. Due to the nature of I2S, where the number of transmitted samples always equals the number of received samples (at least when both TX and RX are enabled), one common register RXTXD.MAXCNT on page 137 is used for specifying the sizes of these two memory buffers. The size of the buffers is specified in a number of 32-bit words. Such a 32-bit memory word can either contain four 8-bit samples, two 16-bit samples or one right-aligned 24-bit sample sign extended to 32 bit. In stereo mode (CONFIG.CHANNELS=Stereo), the samples are stored as "left and right sample pairs" in memory. Figure Memory mapping for 8 bit stereo. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Stereo. on page 124, Memory mapping for 16 bit stereo. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Stereo. on page 125 and Memory mapping for 24 bit stereo. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Stereo. on page 125 show how the samples are mapped to memory in this mode. The mapping is valid for both RX and TX. In mono mode (CONFIG.CHANNELS=Left or Right), RX sample from only one channel in the frame is stored in memory, the other channel sample is ignored. Illustrations Memory mapping for 8 bit mono. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Left. on page 125, Memory mapping for 16 bit mono, left channel only. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Left. on page 125 and Memory mapping for 24 bit mono, left channel only. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Left. on page 126 show how RX samples are mapped to memory in this mode. For TX, the same outgoing sample read from memory is transmitted on both left and right in a frame, resulting in a mono output stream. 31 24 23 16 15 8 7 0 x.PTR Right sample 1 Left sample 1 Right sample 0 Left sample 0 x.PTR + 4 Right sample 3 Left sample 3 Right sample 2 Left sample 2 Right sample n-1 Left sample n-1 Right sample n-2 Left sample n-2 x.PTR + (n*2) - 4 Figure 28: Memory mapping for 8 bit stereo. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Stereo. 4418_1315 v2.0 124 Peripherals 31 24 23 16 15 8 7 0 x.PTR Left sample 3 Left sample 2 Left sample 1 Left sample 0 x.PTR + 4 Left sample 7 Left sample 6 Left sample 5 Left sample 4 Left sample n-1 Left sample n-2 Left sample n-3 Left sample n-4 x.PTR + n - 4 Figure 29: Memory mapping for 8 bit mono. CONFIG.SWIDTH = 8Bit, CONFIG.CHANNELS = Left. 31 16 15 0 x.PTR Right sample 0 Left sample 0 x.PTR + 4 Right sample 1 Left sample 1 Right sample n - 1 Left sample n - 1 x.PTR + (n*4) - 4 Figure 30: Memory mapping for 16 bit stereo. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Stereo. 31 16 15 0 x.PTR Left sample 1 Left sample 0 x.PTR + 4 Left sample 3 Left sample 2 Left sample n - 1 Left sample n - 2 x.PTR + (n*2) - 4 Figure 31: Memory mapping for 16 bit mono, left channel only. CONFIG.SWIDTH = 16Bit, CONFIG.CHANNELS = Left. 31 23 0 x.PTR Sign ext. Left sample 0 x.PTR + 4 Sign ext. Right sample 0 x.PTR + (n*8) - 8 Sign ext. Left sample n - 1 x.PTR + (n*8) - 4 Sign ext. Right sample n - 1 Figure 32: Memory mapping for 24 bit stereo. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Stereo. 4418_1315 v2.0 125 Peripherals 31 23 0 x.PTR Sign ext. Left sample 0 x.PTR + 4 Sign ext. Left sample 1 x.PTR + (n*4) - 4 Sign ext. Left sample n - 1 Figure 33: Memory mapping for 24 bit mono, left channel only. CONFIG.SWIDTH = 24Bit, CONFIG.CHANNELS = Left. 6.7.8 Module operation Described here is a typical operating procedure for the I2S module. 1. Configure the I2S module using the CONFIG registers // Enable reception NRF_I2S->CONFIG.RXEN = (I2S_CONFIG_RXEN_RXEN_Enabled CONFIG.TXEN = (I2S_CONFIG_TXEN_TXEN_Enabled CONFIG.MCKEN = (I2S_CONFIG_MCKEN_MCKEN_Enabled CONFIG.MCKFREQ = I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 CONFIG.RATIO = I2S_CONFIG_RATIO_RATIO_256X CONFIG.SWIDTH = I2S_CONFIG_SWIDTH_SWIDTH_16Bit CONFIG.ALIGN = I2S_CONFIG_ALIGN_ALIGN_Left CONFIG.FORMAT = I2S_CONFIG_FORMAT_FORMAT_I2S CONFIG.CHANNELS = I2S_CONFIG_CHANNELS_CHANNELS_Stereo PSEL.MCK = (0 EVENTS_TXPTRUPD { } != 0) NRF_I2S->TXD.PTR = my_next_tx_buf; NRF_I2S->EVENTS_TXPTRUPD = 0; if(NRF_I2S->EVENTS_RXPTRUPD != 0) { } NRF_I2S->RXD.PTR = my_next_rx_buf; NRF_I2S->EVENTS_RXPTRUPD = 0; 4418_1315 v2.0 127 Peripherals 6.7.9 Pin configuration The MCK, SCK, LRCK, SDIN and SDOUT signals associated with the I2S module are mapped to physical pins according to the pin numbers specified in the PSEL.x registers. These pins are acquired whenever the I2S module is enabled through the register ENABLE on page 133. When a pin is acquired by the I2S module, the direction of the pin (input or output) will be configured automatically, and any pin direction setting done in the GPIO module will be overridden. The directions for the various I2S pins are shown below in GPIO configuration before enabling peripheral (master mode) on page 128 and GPIO configuration before enabling peripheral (slave mode) on page 128. To secure correct signal levels on the pins when the system is in OFF mode, and when the I2S module is disabled, these pins must be configured in the GPIO peripheral directly. I2S signal I2S pin Direction Output value MCK As specified in PSEL.MCK Output 0 LRCK As specified in PSEL.LRCK Output 0 SCK As specified in PSEL.SCK Output 0 SDIN As specified in PSEL.SDIN Input Not applicable SDOUT As specified in PSEL.SDOUT Output 0 Comment Table 46: GPIO configuration before enabling peripheral (master mode) I2S signal I2S pin Direction Output value MCK As specified in PSEL.MCK Output 0 LRCK As specified in PSEL.LRCK Input Not applicable SCK As specified in PSEL.SCK Input Not applicable SDIN As specified in PSEL.SDIN Input Not applicable SDOUT As specified in PSEL.SDOUT Output 0 Comment Table 47: GPIO configuration before enabling peripheral (slave mode) 6.7.10 Registers Base address Peripheral Instance 0x50028000 I2S : S 0x40028000 I2S I2S : NS Secure mapping DMA security Description US SA Inter-IC Sound Configuration Table 48: Instances Register Offset TASKS_START 0x000 Security Description Starts continuous I2S transfer. Also starts MCK generator when this is enabled. TASKS_STOP 0x004 Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED SUBSCRIBE_START 0x080 Subscribe configuration for task START SUBSCRIBE_STOP 0x084 Subscribe configuration for task STOP EVENTS_RXPTRUPD 0x104 The RXD.PTR register has been copied to internal double-buffers. When the I2S module is event to be generated. started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. EVENTS_STOPPED 0x108 I2S transfer stopped. EVENTS_TXPTRUPD 0x114 The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. 4418_1315 v2.0 128 Peripherals Register Offset Security Description PUBLISH_RXPTRUPD 0x184 Publish configuration for event RXPTRUPD PUBLISH_STOPPED 0x188 Publish configuration for event STOPPED PUBLISH_TXPTRUPD 0x194 Publish configuration for event TXPTRUPD INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt ENABLE 0x500 Enable I2S module. CONFIG.MODE 0x504 I2S mode. CONFIG.RXEN 0x508 Reception (RX) enable. CONFIG.TXEN 0x50C Transmission (TX) enable. CONFIG.MCKEN 0x510 Master clock generator enable. CONFIG.MCKFREQ 0x514 Master clock generator frequency. CONFIG.RATIO 0x518 MCK / LRCK ratio. CONFIG.SWIDTH 0x51C Sample width. CONFIG.ALIGN 0x520 Alignment of sample within a frame. CONFIG.FORMAT 0x524 Frame format. CONFIG.CHANNELS 0x528 Enable channels. RXD.PTR 0x538 Receive buffer RAM start address. TXD.PTR 0x540 Transmit buffer RAM start address. RXTXD.MAXCNT 0x550 Size of RXD and TXD buffers. PSEL.MCK 0x560 Pin select for MCK signal. PSEL.SCK 0x564 Pin select for SCK signal. PSEL.LRCK 0x568 Pin select for LRCK signal. PSEL.SDIN 0x56C Pin select for SDIN signal. PSEL.SDOUT 0x570 Pin select for SDOUT signal. Table 49: Register overview 6.7.10.1 TASKS_START Address offset: 0x000 Starts continuous I2S transfer. Also starts MCK generator when this is enabled. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_START 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Starts continuous I2S transfer. Also starts MCK generator when this is enabled. Trigger 1 Trigger task 6.7.10.2 TASKS_STOP Address offset: 0x004 Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. 4418_1315 v2.0 129 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_STOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated. Trigger 1 Trigger task 6.7.10.3 SUBSCRIBE_START Address offset: 0x080 Subscribe configuration for task START Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that task START will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.7.10.4 SUBSCRIBE_STOP Address offset: 0x084 Subscribe configuration for task STOP Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that task STOP will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.7.10.5 EVENTS_RXPTRUPD Address offset: 0x104 The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_RXPTRUPD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin. 4418_1315 v2.0 NotGenerated 0 Event not generated Generated 1 Event generated 130 Peripherals 6.7.10.6 EVENTS_STOPPED Address offset: 0x108 I2S transfer stopped. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_STOPPED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated I2S transfer stopped. 6.7.10.7 EVENTS_TXPTRUPD Address offset: 0x114 The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_TXPTRUPD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin. NotGenerated 0 Event not generated Generated 1 Event generated 6.7.10.8 PUBLISH_RXPTRUPD Address offset: 0x184 Publish configuration for event RXPTRUPD Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that event RXPTRUPD will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.7.10.9 PUBLISH_STOPPED Address offset: 0x188 Publish configuration for event STOPPED 4418_1315 v2.0 131 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that event STOPPED will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.7.10.10 PUBLISH_TXPTRUPD Address offset: 0x194 Publish configuration for event TXPTRUPD Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event TXPTRUPD will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.7.10.11 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F Reset 0x00000000 ID R/W Field B RW RXPTRUPD C F RW RW C B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Enable or disable interrupt for event RXPTRUPD STOPPED Enable or disable interrupt for event STOPPED Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable TXPTRUPD Enable or disable interrupt for event TXPTRUPD 6.7.10.12 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F Reset 0x00000000 ID R/W Field B RW RXPTRUPD 4418_1315 v2.0 C B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event RXPTRUPD 132 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F Reset 0x00000000 ID C F R/W RW RW Field C B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled STOPPED Write '1' to enable interrupt for event STOPPED TXPTRUPD Write '1' to enable interrupt for event TXPTRUPD 6.7.10.13 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F Reset 0x00000000 ID R/W Field B RW RXPTRUPD C F RW RW C B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event RXPTRUPD STOPPED Write '1' to disable interrupt for event STOPPED TXPTRUPD Write '1' to disable interrupt for event TXPTRUPD 6.7.10.14 ENABLE Address offset: 0x500 Enable I2S module. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW ENABLE 4418_1315 v2.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Enable I2S module. 133 Peripherals 6.7.10.15 CONFIG.MODE Address offset: 0x504 I2S mode. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW MODE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Master 0 Slave 1 Description I2S mode. Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx 6.7.10.16 CONFIG.RXEN Address offset: 0x508 Reception (RX) enable. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW RXEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Reception (RX) enable. Disabled 0 Enabled 1 Reception disabled and now data will be written to the RXD.PTR address. Reception enabled. 6.7.10.17 CONFIG.TXEN Address offset: 0x50C Transmission (TX) enable. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000001 ID R/W Field A RW TXEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Disabled 0 Enabled 1 Description Transmission (TX) enable. Transmission disabled and now data will be read from the RXD.TXD address. Transmission enabled. 6.7.10.18 CONFIG.MCKEN Address offset: 0x510 Master clock generator enable. 4418_1315 v2.0 134 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000001 ID R/W Field A RW MCKEN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Disabled 0 Enabled 1 Description Master clock generator enable. Master clock generator disabled and PSEL.MCK not connected(available as GPIO). Master clock generator running and MCK output on PSEL.MCK. 6.7.10.19 CONFIG.MCKFREQ Address offset: 0x514 Master clock generator frequency. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x20000000 ID R/W Field A RW MCKFREQ 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Master clock generator frequency. 32MDIV8 0x20000000 32 MHz / 8 = 4.0 MHz 32MDIV10 0x18000000 32 MHz / 10 = 3.2 MHz 32MDIV11 0x16000000 32 MHz / 11 = 2.9090909 MHz 32MDIV15 0x11000000 32 MHz / 15 = 2.1333333 MHz 32MDIV16 0x10000000 32 MHz / 16 = 2.0 MHz 32MDIV21 0x0C000000 32 MHz / 21 = 1.5238095 32MDIV23 0x0B000000 32 MHz / 23 = 1.3913043 MHz 32MDIV30 0x08800000 32 MHz / 30 = 1.0666667 MHz 32MDIV31 0x08400000 32 MHz / 31 = 1.0322581 MHz 32MDIV32 0x08000000 32 MHz / 32 = 1.0 MHz 32MDIV42 0x06000000 32 MHz / 42 = 0.7619048 MHz 32MDIV63 0x04100000 32 MHz / 63 = 0.5079365 MHz 32MDIV125 0x020C0000 32 MHz / 125 = 0.256 MHz 6.7.10.20 CONFIG.RATIO Address offset: 0x518 MCK / LRCK ratio. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A Reset 0x00000006 ID R/W Field A RW RATIO 4418_1315 v2.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Value ID Value Description 32X 0 LRCK = MCK / 32 48X 1 LRCK = MCK / 48 64X 2 LRCK = MCK / 64 96X 3 LRCK = MCK / 96 128X 4 LRCK = MCK / 128 192X 5 LRCK = MCK / 192 256X 6 LRCK = MCK / 256 384X 7 LRCK = MCK / 384 512X 8 LRCK = MCK / 512 MCK / LRCK ratio. 135 Peripherals 6.7.10.21 CONFIG.SWIDTH Address offset: 0x51C Sample width. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000001 ID R/W Field A RW SWIDTH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description 8Bit 0 8 bit. 16Bit 1 16 bit. 24Bit 2 24 bit. Sample width. 6.7.10.22 CONFIG.ALIGN Address offset: 0x520 Alignment of sample within a frame. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW ALIGN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Left 0 Left-aligned. Right 1 Right-aligned. Alignment of sample within a frame. 6.7.10.23 CONFIG.FORMAT Address offset: 0x524 Frame format. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW FORMAT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description I2S 0 Original I2S format. Aligned 1 Alternate (left- or right-aligned) format. Frame format. 6.7.10.24 CONFIG.CHANNELS Address offset: 0x528 Enable channels. 4418_1315 v2.0 136 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A Reset 0x00000000 ID R/W Field A RW CHANNELS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Stereo 0 Stereo. Left 1 Left only. Right 2 Right only. Enable channels. 6.7.10.25 RXD.PTR Address offset: 0x538 Receive buffer RAM start address. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID R/W Field A RW PTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. 6.7.10.26 TXD.PTR Address offset: 0x540 Transmit buffer RAM start address. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID R/W Field A RW PTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. 6.7.10.27 RXTXD.MAXCNT Address offset: 0x550 Size of RXD and TXD buffers. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A Reset 0x00000000 ID R/W Field A RW MAXCNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Size of RXD and TXD buffers in number of 32 bit words. 6.7.10.28 PSEL.MCK Address offset: 0x560 Pin select for MCK signal. 4418_1315 v2.0 137 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID R/W Field A RW PIN C RW CONNECT Value ID A A A A A Value Description [0..31] Pin number Connection Disconnected 1 Disconnect Connected 0 Connect 6.7.10.29 PSEL.SCK Address offset: 0x564 Pin select for SCK signal. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF ID R/W Field A RW PIN C RW CONNECT A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description [0..31] Pin number Connection Disconnected 1 Disconnect Connected 0 Connect 6.7.10.30 PSEL.LRCK Address offset: 0x568 Pin select for LRCK signal. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF ID R/W Field A RW PIN C RW CONNECT A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description [0..31] Pin number Connection Disconnected 1 Disconnect Connected 0 Connect 6.7.10.31 PSEL.SDIN Address offset: 0x56C Pin select for SDIN signal. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID R/W Field A RW PIN C RW CONNECT 4418_1315 v2.0 Value ID A A A A A Value Description [0..31] Pin number Connection Disconnected 1 Disconnect Connected 0 Connect 138 Peripherals 6.7.10.32 PSEL.SDOUT Address offset: 0x570 Pin select for SDOUT signal. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID R/W Field A RW PIN Value ID C RW CONNECT A A A A A Value Description [0..31] Pin number Connection Disconnected 1 Disconnect Connected 0 Connect 6.7.11 Electrical specification 6.7.11.1 I2S timing specification Symbol Description Min. tS_SDIN SDIN setup time before SCK rising 20 Typ. Max. Units ns tH_SDIN SDIN hold time after SCK rising 15 ns tS_SDOUT SDOUT setup time after SCK falling 40 ns tH_SDOUT SDOUT hold time before SCK falling 6 tSCK_LRCK SCLK falling to LRCK edge -5 fMCK ns 0 5 ns MCK frequency 4000 kHz fLRCK LRCK frequency 48 kHz fSCK SCK frequency 2000 kHz DCCK Clock duty cycle (MCK, LRCK, SCK) 55 % 45 tSCK_LRCK LRCK SCK tS_SDIN tH_SDIN SDIN tH_SDOUT tS_SDOUT SDOUT Figure 34: I2S timing diagram 6.8 KMU — Key management unit The key management unit (KMU) enforces access policies to a subset region of user information configuration register (UICR). This subset region is used for storing cryptographic key values inside the key slots, which the CPU has no access to. In total there are 128 key slots available, where each key slot can store one 128-bit key value together with an access policy and a destination address for the key value. Multiple key slots can be combined in order to support key sizes larger than 128 bits. The access policy of a key slot governs if and how a key value can 4418_1315 v2.0 139 Peripherals be used, while the destination address determines where in the memory map the KMU pushes the key value upon a request from the CPU. Key slots can be configured to be pushed directly into write-only key registers in cryptographic accelerators, like e.g. CryptoCell, without exposing the key value itself to the CPU. This enables the CPU to use the key values stored inside the key slots for cryptographic operations without being exposed to the key value. Access to the KMU, and the key slots in the UICR, is only allowed from secure mode. 6.8.1 Functional view From a functional view the UICR is divided into two different regions, one-time programmable (OTP) memory and key storage. UICR offset 0x1000 User information configuration register (UICR) infopage Regular UICR OTP Functional view Key storage User defined Key headers Part specific instantiation Key values Permission legend: KEYSLOT. CONFIG[0] KEYSLOT. CONFIG[n] (…) KEYSLOT. KEY[0] (…) Write-once per halfword limitation, always readable KEYSLOT. KEY[n] Write-once per halfword limitation, always readable DEST VALUE[0] PERM STATE PUSH READ VALUE[1] VALUE[2] VALUE[3] Write-once per halfword limitation, restricted usage and readability based on key header configuration WRITE Finite-state machine (FSM) Access control Figure 35: Memory map overview OTP One-time programmable (OTP) memory is typically used for holding values that are written once, and then never to be changed again throughout the product lifetime. The OTP region of UICR is emulated by placing a write-once per halfword limitation on registers defined here. Key storage The key storage region contains multiple key slots, where each slot consists of a key header and an associated key value. The key value is limited to 128 bits. Any key size greater than 128 bits must be divided and distributed over multiple key slot instances. Key headers are allocated an address range of 0x400 in the UICR memory map, allowing a total of 128 keys to be addressable inside the key storage region. Note: The use of the key storage region in UICR should be limited to keys with a certain life span, and not per-session derived keys where the CPU is involved in the key exchange. 6.8.2 Access control Access control to the underlying UICR infopage in flash is enforced by a hardware finite-state machine (FSM). The FSM can allow or block transactions, depending both on the security of the transaction (secure or non-secure) and on the type of register being written and/or read. 4418_1315 v2.0 140 Peripherals Access type Key headers Key values Read Allowed Restricted Write Restricted Restricted Table 50: Access control Any restricted access requires an explicit key slot selection through the KMU register interface. Any illegal access to restricted key slot registers will be blocked and word 0xDEADDEAD will be returned on the AHB. The OTP region has individual access control behavior, while access control to the key storage region is configured on a per key slot basis. The KMU FSM operates on only one key slot instance at a time, and the permissions and the usage restriction for a key value associated with a key slot can be configured individually. Note: Even if the KMU can be configured as non-secure, all non-secure transactions will be blocked. 6.8.3 Protecting the UICR content The UICR content can be protected against device-internal NVMC.ERASEALL requests, in addition to device-external ERASEALL requests, through the CTRL-AP interface. This feature is useful if the firmware designers want to prevent the OTP region from being erased. Since enabling this step will permanently disable erase for the UICR, the procedure requires an implementation defined 32-bit word to be written into the UICR's ERASEPROTECT register. In case of a field return handling, it is still possible to erase the UICR even if the ERASEPROTECT is set. If this functionality is desired, the secure boot code must implement a secure communication channel over the CTRL-AP mailbox interface. Upon successful authentication of the external party, the secure boot code can temporarily re-enable the CTRL-AP ERASEALL functionality. 6.8.4 Usage This section describes the specific KMU and UICR behavior in more detail, to help the reader get a better overview of KMU's features and the intended usage. 6.8.4.1 OTP The OTP region of the UICR contains a user-defined static configuration of the device. The KMU emulates the OTP functionality by placing a write-once per halfword limitation of registers defined in this region, i.e. only halfwords containing all '1's can be written. An OTP write transaction must consist of a full 32-bit word. Both halfwords can either be written simultaneously or one at a time. The KMU FSM will block any write to a halfword in the OTP region, if the initial value of this halfword is not 0xFFFF. When writing halfwords one at a time, the non-active halfword must be masked as 0xFFFF, otherwise the request will be blocked. For example, writing 0x1234XXXX to an OTP destination address which already contains the value 0xFFFFAABB, must be configured as 0x1234FFFF. The OTP destination address will contain the value 0x1234AABB after both write transactions have been processed. The KMU will also only allow secure AHB write transactions into the OTP region of the UICR. Any AHB write transaction to this region that does not satisfy the above requirements will be ignored, and the STATUS.BLOCKED register will be set to '1'. 6.8.4.2 Key storage The key storage region of the UICR can contain multiple keys of different type, including symmetrical keys, hashes, public/private key pairs and other device secrets. One of the key features of the KMU, is that these 4418_1315 v2.0 141 Peripherals device secrets can be installed and made available for use in cryptographic operations without revealing the actual secret values. Keys in this region will typically have a certain life span. The region is not designed to be used for persession derived keys where the non-secure side (i.e. application) is participating in the key exchange. All key storage is done through the concept of multiple key slots, where each key slot instance consists of one key header and an associated key value. Each key header supports the configuration of usage permissions and an optional secure destination address. The key header secure destination address option enables the KMU to push the associated key value over a dedicated secure APB to a pre-configured secure location within the memory map. Such locations typically include a write-only key register of the hardware cryptograhic accelerator, allowing the KMU to distribute keys within the system without compromising the key values. One key slot instance can store a key value of maximum 128 bits. If a key size exceeds this limit, the key value itself must be split over multiple key slot instances. The following usage and read permissions scheme is applicable for each key slot: State Push Active (1) Enabled (1) Active (1) Enabled (1) Active (1) Enabled (1) Active (1) Disabled Revoked Read Write Description Enabled Enabled Default flash erase value. Key slot cannot be pushed, write is enabled. (1) (1) Enabled Disabled (1) (0) Disabled Disabled (0) (0) Enabled Disabled (0) (1) (0) - - - Key slot is active, push is enabled. Key slot VALUE registers can be read, but write is disabled. Key slot is active, push is enabled. Read and write to key slot VALUE registers are disabled. Key slot is active, push is disabled. Key slot VALUE registers can be read, but write is disabled. Key slot is revoked. Cannot be read or pushed over secure APB regardless of the permission settings. (0) Table 51: Valid key slot permission schemes 6.8.4.2.1 Selecting a key slot The KMU FSM is designed to process only one key slot at a time, effectively operating as a memory protection unit for the key storage region. Whenever a key slot is selected, the KMU will allow access to writing, reading, and/or pushing the associated key value according to the selected slot configuration. A key slot must be selected prior to use, by writing the key slot ID into the KMU SELECTKEYSLOT register. Because the reset value of this register is 0x00000000, there is no key slot associated with ID=0 and no slot is selected by default. All key slots are addressed using IDs from 1 to 128. SELECTED status is set when a key slot is selected, and a read or write acccess to that keyslot occurs. BLOCKED status is set when any illegal access to key slot registers is detected. When the use of the particular key slot is stopped, the key slot selection in SELECTKEYSLOT must be set back to '0'. By default, all KMU key slots will consist of a 128-bit key value of '1's, where the key headers have no secure destination address, or any usage and read restrictions. 6.8.4.2.2 Writing to a key slot Writing a key slot into UICR is a five-step process. 1. Select which key slot the KMU shall operate on by writing the desired key slot ID into KMU>SELECTKEYSLOT. The selected key slot must be empty in order to add a new entry to UICR. 2. If the key value shall be pushable over secure APB, the destination address of the recipient must be configured in register KEYSLOT.CONFIG[ID-1].DEST. 4418_1315 v2.0 142 Peripherals 3. Write the 128-bit key value into KEYSLOT.KEY[ID-1].VALUE[0-3]. 4. Write the desired key slot permissions into KEYSLOT.CONFIG[ID-1].PERM, including any applicable usage restrictions. 5. Select key slot 0. In case the total key size is greater than 128 bits, the key value itself must be split into 128-bit segments and written to multiple key slot instances. Steps 1 through 5 above must be repeated for the entire key size. Note: If a key slot is configured as readable, and KEYSLOT.CONFIG[ID-1].DEST is not to be used, it is recommended to disable the push bit in KEYSLOT.CONFIG[ID-1].PERM when configuring key slot permissions. Note: A key value distributed over multiple key slots should use the same key slot configuration in its key headers, but the secure destination address for each key slot instance must be incremented by 4 words (128 bits) for each key slot instance spanned. Note: Write to flash must be enabled in NVMC->CONFIG prior to writing keys to flash, and subsequently disabled once writing is complete. Steps 1 through 5 above will be blocked if any of the following violations are detected: • • • • No key slot selected Non-empty key slot selected NVM destination address not empty AHB write to KEYSLOT.KEY[ID-1].VALUE[0-3] registers not belonging to selected key slot 6.8.4.2.3 Reading a key value Key slots that are configured as readable can have their key value read directly from the UICR memory map by the CPU. Readable keys are typically used during the secure boot sequence, where the CPU is involved in falsifying or verifying the integrity of the system. Since the CPU is involved in this decision process, it makes little sense not to trust the CPU having access to the actual key value but ultimately trust the decision of the integrity check. Another use-case for readable keys is if the key type in question does not have a HW peripheral in the platform that is able to accept such keys over secure APB. Reading a key value from the UICR is a three-step process: 1. Select the key slot which the KMU shall operate on by writing the desired key slot ID into KMU>SELECTKEYSLOT. 2. If STATE and READ permission requirements are fulfilled as defined in KEYSLOT.CONFIG[ID-1].PERM, the key value can be read from region KEYSLOT.KEY[ID-1].VALUE[0-3] for selected key slot. 3. Select key slot 0. Step 2 will be blocked and word 0xDEADDEAD will be returned on AHB if any of the following violations are detected: • • • • No key slot selected Key slot not configured as readable Key slot is revoked AHB read to KEYSLOT.KEY[ID-1].VALUE[0-3] registers not belonging to selected key slot 4418_1315 v2.0 143 Peripherals 6.8.4.2.4 Push over secure APB Key slots that are configured as non-readable cannot be read by the CPU regardless of the mode the system is in, and must be pushed over secure APB in order to use the key value for cryptographic operations. The secure APB destination address is set in the key slot configuration DEST register. Such destination addresses are typically write-only key registers in a hardware cryptographic accelerators memory map. The secure APB allows key slots to be utilized by the software side, without exposing the key value itself. APB APB Secure APB NVMC FICR 2:1 MUX 2:1 MUX Write-only key registers Write-only key registers Peripheral[0] Peripheral[n] UICR AHB EVENTS_KEYSLOT_PUSHED SELECTKEYSLOT NVMC TASKS_PUSH_KEYSLOT KMU APB Figure 36: Tasks and events pattern for key slots Pushing a key slot over secure APB is a four-step process: 1. Select the key slot on which the KMU shall operate by writing the desired key slot ID into KMU>SELECTKEYSLOT. 2. Start TASKS_PUSH_KEYSLOT to initiate a secure APB transaction, writing the 128-bit key value associated with the selected key slot into address defined in KEYSLOT.CONFIG[ID-1].DEST. 3. After completing the secure APB transaction, the 128-bit key value is ready for use by the peripheral and EVENTS_KEYSLOT_PUSHED is triggered. 4. Select key slot 0. Note: If a key value is distributed over multiple key slots due to its key size, exceeding the maximum 128-bit key value limitation, then each distributed key slot must be pushed individually in order to transfer the entire key value over secure APB. Step 3 will trigger other events than EVENTS_KEYSLOT_PUSHED if the following violations are detected: • EVENTS_KEYSLOT_ERROR: • • • • If no key slot is selected If a key slot has no destination address configured If when pushing a key slot, flash or peripheral returns an error If pushing a key slot when push permissions are disabled 4418_1315 v2.0 144 Peripherals • If attempting to push a key slot with default permissions • EVENTS_KEYSLOT_REVOKED if a key slot is marked as revoked in its key header configuration 6.8.4.2.5 Revoking the key slots All key slots within the key storage area can be marked as revoked. To revoke any key slots, write to the STATE field in the KEYSLOT.CONFIG[ID-1].PERM register. The following rules apply to keys that have been revoked: 1. Key slots that have the PUSH field enabled in PERM register can no longer be pushed. If a revoked key slot is selected and task TASKS_PUSH_KEYSLOT is started, the event EVENTS_KEYSLOT_REVOKED is triggered. 2. Key slots that have the READ field enabled in PERM register can no longer be read. Any read operation to a revoked key value will return word 0xDEADDEAD. 3. Previously pushed key values stored in a peripheral write-only key register are not affected by key revocation. If secure code wants to enforce that a revoked key is no longer usable by a peripheral for cryptographic operations, the secure code should disable or reset the peripheral in question. 6.8.4.3 STATUS register The KMU uses a STATUS register to indicate its status of operation. The SELECTED bit will be asserted whenever the currently selected key slot is successfully read from or written to. All read or write operations to other key slots than what is currently selected in KMU->SELECTKEYSLOT will assert the BLOCKED bit. The BLOCKED bit will also be asserted if the KMU fails to select a key slot, or if a request has been blocked due to an access violation. Normal operation using the KMU should never trigger the BLOCKED bit. If this bit is triggered during the development phase, it indicates that the code is using the KMU incorrectly. The STATUS register is reset every time register SELECTKEYSLOT is written. 6.8.5 Registers Base address Peripheral Instance 0x50039000 KMU : S 0x40039000 KMU KMU : NS Secure mapping DMA security Description SPLIT NA Key management unit Configuration Table 52: Instances Register Offset Security Description TASKS_PUSH_KEYSLOT 0x0000 Push a key slot over secure APB EVENTS_KEYSLOT_PUSHED 0x100 Key slot successfully pushed over secure APB EVENTS_KEYSLOT_REVOKED 0x104 Key slot has been revoked and cannot be tasked for selection EVENTS_KEYSLOT_ERROR 0x108 No key slot selected, no destination address defined, or error during push operation INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt INTPEND 0x30C Pending interrupts STATUS 0x40C Status bits for KMU operation SELECTKEYSLOT 0x500 Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started Table 53: Register overview 4418_1315 v2.0 145 Peripherals 6.8.5.1 TASKS_PUSH_KEYSLOT Address offset: 0x0000 Push a key slot over secure APB Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_PUSH_KEYSLOT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description Push a key slot over secure APB Trigger task 6.8.5.2 EVENTS_KEYSLOT_PUSHED Address offset: 0x100 Key slot successfully pushed over secure APB Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID A RW EVENTS_KEYSLOT_PUSHED Value Description Key slot successfully pushed over secure APB NotGenerated 0 Event not generated Generated 1 Event generated 6.8.5.3 EVENTS_KEYSLOT_REVOKED Address offset: 0x104 Key slot has been revoked and cannot be tasked for selection Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID A RW EVENTS_KEYSLOT_REVOKED Value Description Key slot has been revoked and cannot be tasked for selection NotGenerated 0 Event not generated Generated 1 Event generated 6.8.5.4 EVENTS_KEYSLOT_ERROR Address offset: 0x108 No key slot selected, no destination address defined, or error during push operation Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID A RW EVENTS_KEYSLOT_ERROR Value Description No key slot selected, no destination address defined, or error during push operation 4418_1315 v2.0 NotGenerated 0 Event not generated Generated 1 Event generated 146 Peripherals 6.8.5.5 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B A Reset 0x00000000 ID R/W Field A RW KEYSLOT_PUSHED B C RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Enable or disable interrupt for event KEYSLOT_PUSHED KEYSLOT_REVOKED Enable or disable interrupt for event KEYSLOT_REVOKED KEYSLOT_ERROR Enable or disable interrupt for event KEYSLOT_ERROR 6.8.5.6 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B A Reset 0x00000000 ID R/W Field A RW KEYSLOT_PUSHED B C RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to enable interrupt for event KEYSLOT_PUSHED Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled KEYSLOT_REVOKED Write '1' to enable interrupt for event KEYSLOT_REVOKED Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled KEYSLOT_ERROR Write '1' to enable interrupt for event KEYSLOT_ERROR Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.8.5.7 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B A Reset 0x00000000 ID R/W Field A RW KEYSLOT_PUSHED 4418_1315 v2.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Clear 1 Description Write '1' to disable interrupt for event KEYSLOT_PUSHED Disable 147 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B A Reset 0x00000000 ID B C R/W RW RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled KEYSLOT_REVOKED Write '1' to disable interrupt for event KEYSLOT_REVOKED KEYSLOT_ERROR Write '1' to disable interrupt for event KEYSLOT_ERROR 6.8.5.8 INTPEND Address offset: 0x30C Pending interrupts Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B A Reset 0x00000000 ID R/W Field A R KEYSLOT_PUSHED B C R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotPending 0 Read: Not pending Pending 1 Read: Pending NotPending 0 Read: Not pending Pending 1 Read: Pending Read pending status of interrupt for event KEYSLOT_PUSHED KEYSLOT_REVOKED Read pending status of interrupt for event KEYSLOT_REVOKED KEYSLOT_ERROR Read pending status of interrupt for event KEYSLOT_ERROR NotPending 0 Read: Not pending Pending 1 Read: Pending 6.8.5.9 STATUS Address offset: 0x40C Status bits for KMU operation This register is reset and re-written by the KMU whenever SELECTKEYSLOT is written Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B A Reset 0x00000000 ID R/W Field A R SELECTED B R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 No key slot ID selected by KMU Enabled 1 Key slot ID successfully selected by KMU Disabled 0 No access violation detected Enabled 1 Access violation detected and blocked Key slot ID successfully selected by the KMU BLOCKED 4418_1315 v2.0 Violation status 148 Peripherals 6.8.5.10 SELECTKEYSLOT Address offset: 0x500 Select key slot to be read over AHB or pushed over secure APB when TASKS_PUSH_KEYSLOT is started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A Reset 0x00000000 ID R/W Field A RW ID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Select key slot ID to be read over AHB, or pushed over secure APB, when TASKS_PUSH_KEYSLOT is started. NOTE: ID=0 is not a valid key slot ID. The 0 ID should be used when the KMU is idle or not in use. NOTE: Index N in UICR->KEYSLOT.KEY[N] and UICR>KEYSLOT.CONFIG[N] corresponds to KMU key slot ID=N+1. 6.9 PDM — Pulse density modulation interface The pulse density modulation (PDM) module enables input of pulse density modulated signals from external audio frontends, for example, digital microphones. The PDM module generates the PDM clock and supports single-channel or dual-channel (left and right) data input. Data is transferred directly to RAM buffers using EasyDMA. Listed here are the main features for PDM: • • • • • Up to two PDM microphones configured as a left/right pair using the same data input 16 kHz output sample rate, 16-bit samples EasyDMA support for sample buffering HW decimation filters Selectable ratio of 64 or 80 between PDM_CLK and output sample rate The PDM module illustrated below is interfacing up to two digital microphones with the PDM interface. EasyDMA is implemented to relieve the real-time requirements associated with controlling of the PDM slave from a low priority CPU execution context. It also includes all the necessary digital filter elements to produce pulse code modulation (PCM) samples. The PDM module allows continuous audio streaming. Bandpass and decimation (left) PDM to PCM Bandpass and decimation (right) RAM Sampling DIN PDM to PCM EasyDMA Master clock generator CLK Figure 37: PDM module 6.9.1 Master clock generator The master clock generator's PDMCLKCTRL register allows adjusting the PDM clock's frequency. The master clock generator does not add any jitter to the HFCLK source chosen. It is recommended (but not mandatory) to use the Xtal as HFCLK source. 4418_1315 v2.0 149 Peripherals 6.9.2 Module operation By default, bits from the left PDM microphone are sampled on PDM_CLK falling edge, and bits for the right are sampled on the rising edge of PDM_CLK, resulting in two bitstreams. Each bitstream is fed into a digital filter which converts the PDM stream into 16-bit PCM samples, then filters and down-samples them to reach the appropriate sample rate. The EDGE field in the MODE register allows swapping left and right, so that left will be sampled on rising edge, and right on falling. The PDM module uses EasyDMA to store the samples coming out from the filters into one buffer in RAM. Depending on the mode chosen in the OPERATION field in the MODE register, memory either contains alternating left and right 16-bit samples (Stereo), or only left 16-bit samples (Mono). To ensure continuous PDM sampling, it is up to the application to update the EasyDMA destination address pointer as the previous buffer is filled. The continuous transfer can be started or stopped by sending the START and STOP tasks. STOP becomes effective after the current frame has finished transferring, which will generate the STOPPED event. The STOPPED event indicates that all activity in the module is finished, and that the data is available in RAM (EasyDMA has finished transferring as well). Attempting to restart before receiving the STOPPED event may result in unpredictable behavior. 6.9.3 Decimation filter In order to convert the incoming data stream into PCM audio samples, a decimation filter is included in the PDM interface module. The input of the filter is the two-channel PDM serial stream (with left channel on clock high, right channel on clock low). Depending on the RATIO selected, its output is 2 × 16-bit PCM samples at a sample rate either 64 times or 80 times (depending on the RATIO register) lower than the PDM clock rate. The filter stage of each channel is followed by a digital volume control, to attenuate or amplify the output samples in a range of -20 dB to +20 dB around the default (reset) setting, defined by GPDM,default. The gain is controlled by the GAINL and GAINR registers. As an example, if the goal is to achieve 2500 RMS output samples (16-bit) with a 1 kHz 90 dBA signal into a -26 dBFS sensitivity PDM microphone, do the following: • Sum the PDM module's default gain ( GPDM,default ) and the gain introduced by the microphone and acoustic path of his implementation (an attenuation would translate into a negative gain) • Adjust GAINL and GAINR by the above summed amount. Assuming that only the PDM module influences the gain, GAINL and GAINR must be set to -GPDM,default dB to achieve the requirement. With GPDM,default=3.2 dB, and as GAINL and GAINR are expressed in 0.5 dB steps, the closest value to program would be 3.0 dB, which can be calculated as: GAINL = GAINR = (DefaultGain - (2 * 3)) Remember to check that the resulting values programmed into GAINL and GAINR fall within MinGain and MaxGain. 6.9.4 EasyDMA Samples will be written directly to RAM, and EasyDMA must be configured accordingly. The address pointer for the EasyDMA channel is set in SAMPLE.PTR register. If the destination address set in SAMPLE.PTR is not pointing to the Data RAM region, an EasyDMA transfer may result in a HardFault or RAM corruption. See Memory on page 21 for more information about the different memory regions. DMA supports Stereo (Left+Right 16-bit samples) and Mono (Left only) data transfer, depending on the setting in the OPERATION field in the MODE register. The samples are stored little endian. 4418_1315 v2.0 150 Peripherals MODE.OPERATION Bits per sample Stereo 32 (2x16) Mono 16 Result stored per RAM Physical RAM allocated Result boundary indexes Note word (32-bit words) in RAM L+R ceil(SAMPLE.MAXCNT/2) R0=[31:16]; L0=[15:0] 2xL ceil(SAMPLE.MAXCNT/2) L1=[31:16]; L0=[15:0] Default Table 54: DMA sample storage The destination buffer in RAM consists of one block, the size of which is set in SAMPLE.MAXCNT register. Format is number of 16-bit samples. The physical RAM allocated is always: (RAM allocation, in bytes) = SAMPLE.MAXCNT * 2; (but the mapping of the samples depends on MODE.OPERATION. If OPERATION=Stereo, RAM will contain a succession of left and right samples. If OPERATION=Mono, RAM will contain a succession of left only samples. For a given value of SAMPLE.MAXCNT, the buffer in RAM can contain half the stereo sampling time as compared to the mono sampling time. The PDM acquisition can be started by the START task, after the SAMPLE.PTR and SAMPLE.MAXCNT registers have been written. When starting the module, it will take some time for the filters to start outputting valid data. Transients from the PDM microphone itself may also occur. The first few samples (typically around 50) might hence contain invalid values or transients. It is therefore advised to discard the first few samples after a PDM start. As soon as the STARTED event is received, the firmware can write the next SAMPLE.PTR value (this register is double-buffered), to ensure continuous operation. When the buffer in RAM is filled with samples, an END event is triggered. The firmware can start processing the data in the buffer. Meanwhile, the PDM module starts acquiring data into the new buffer pointed to by SAMPLE.PTR, and sends a new STARTED event, so that the firmware can update SAMPLE.PTR to the next buffer address. 6.9.5 Hardware example PDM can be configured with a single microphone (mono), or with two microphones. When a single microphone is used, connect the microphone clock to CLK, and data to DIN. Vdd L/R nRFxxxxx CLK CLK DATA DIN CLK DIN Figure 38: Example of a single PDM microphone, wired as left Vdd L/R nRFxxxxx CLK CLK DATA DIN CLK DIN Figure 39: Example of a single PDM microphone, wired as right Note that in a single-microphone (mono) configuration, depending on the microphone’s implementation, either the left or the right channel (sampled at falling or rising CLK edge respectively) will contain reliable data. 4418_1315 v2.0 151 Peripherals If two microphones are used, one of them has to be set as left, the other as right (L/R pin tied high or to GND on the respective microphone). It is strongly recommended to use two microphones of exactly the same brand and type so that their timings in left and right operation match. Vdd L/R nRFxxxxx CLK CLK DATA DIN Vdd CLK L/R DATA CLK DIN Figure 40: Example of two PDM microphones 6.9.6 Pin configuration The CLK and DIN signals associated to the PDM module are mapped to physical pins according to the configuration specified in the PSEL.CLK and PSEL.DIN registers respectively. If the CONNECT field in any PSEL register is set to Disconnected, the associated PDM module signal will not be connected to the required physical pins, and will not operate properly. The PSEL.CLK and PSEL.DIN registers and their configurations are only used as long as the PDM module is enabled, and retained only as long as the device is in System ON mode. See POWER — Power control on page 64 for more information about power modes. When the peripheral is disabled, the pins will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n] register. To ensure correct behavior in the PDM module, the pins used by the PDM module must be configured in the GPIO peripheral as described in GPIO configuration before enabling peripheral on page 152 before enabling the PDM module. This is to ensure that the pins used by the PDM module are driven correctly if the PDM module itself is temporarily disabled or the device temporarily enters System OFF. This configuration must be retained in the GPIO for the selected I/Os as long as the PDM module is supposed to be connected to an external PDM circuit. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. PDM signal PDM pin Direction Output value CLK As specified in PSEL.CLK Output 0 DIN As specified in PSEL.DIN Input Not applicable Comment Table 55: GPIO configuration before enabling peripheral 6.9.7 Registers Base address Peripheral Instance 0x50026000 PDM : S 0x40026000 PDM PDM : NS Secure mapping US DMA security Description Pulse density modulation SA (digital microphone) interface Table 56: Instances Register Offset TASKS_START 0x000 Starts continuous PDM transfer TASKS_STOP 0x004 Stops PDM transfer SUBSCRIBE_START 0x080 Subscribe configuration for task START 4418_1315 v2.0 Security Description 152 Configuration Peripherals Register Offset Security Description SUBSCRIBE_STOP 0x084 Subscribe configuration for task STOP EVENTS_STARTED 0x100 PDM transfer has started EVENTS_STOPPED 0x104 PDM transfer has finished EVENTS_END 0x108 The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after PUBLISH_STARTED 0x180 Publish configuration for event STARTED PUBLISH_STOPPED 0x184 Publish configuration for event STOPPED PUBLISH_END 0x188 Publish configuration for event END INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt ENABLE 0x500 PDM module enable register PDMCLKCTRL 0x504 PDM clock generator control MODE 0x508 Defines the routing of the connected PDM microphones' signals GAINL 0x518 Left output gain adjustment GAINR 0x51C Right output gain adjustment RATIO 0x520 Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL PSEL.CLK 0x540 Pin number configuration for PDM CLK signal PSEL.DIN 0x544 Pin number configuration for PDM DIN signal SAMPLE.PTR 0x560 RAM address pointer to write samples to with EasyDMA SAMPLE.MAXCNT 0x564 Number of samples to allocate memory for in EasyDMA mode a STOP task has been received) to Data RAM accordingly. Table 57: Register overview 6.9.7.1 TASKS_START Address offset: 0x000 Starts continuous PDM transfer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_START 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description Starts continuous PDM transfer Trigger task 6.9.7.2 TASKS_STOP Address offset: 0x004 Stops PDM transfer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_STOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description Stops PDM transfer Trigger task 6.9.7.3 SUBSCRIBE_START Address offset: 0x080 4418_1315 v2.0 153 Peripherals Subscribe configuration for task START Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that task START will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.9.7.4 SUBSCRIBE_STOP Address offset: 0x084 Subscribe configuration for task STOP Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that task STOP will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.9.7.5 EVENTS_STARTED Address offset: 0x100 PDM transfer has started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_STARTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated PDM transfer has started 6.9.7.6 EVENTS_STOPPED Address offset: 0x104 PDM transfer has finished Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_STOPPED 4418_1315 v2.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated PDM transfer has finished 154 Peripherals 6.9.7.7 EVENTS_END Address offset: 0x108 The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_END 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM NotGenerated 0 Event not generated Generated 1 Event generated 6.9.7.8 PUBLISH_STARTED Address offset: 0x180 Publish configuration for event STARTED Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event STARTED will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.9.7.9 PUBLISH_STOPPED Address offset: 0x184 Publish configuration for event STOPPED Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event STOPPED will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.9.7.10 PUBLISH_END Address offset: 0x188 Publish configuration for event END 4418_1315 v2.0 155 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that event END will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.9.7.11 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B A Reset 0x00000000 ID R/W Field A RW STARTED B C RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable interrupt for event STARTED Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable STOPPED Enable or disable interrupt for event STOPPED END Enable or disable interrupt for event END 6.9.7.12 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B A Reset 0x00000000 ID R/W Field A RW STARTED B C RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event STARTED STOPPED Write '1' to enable interrupt for event STOPPED END Write '1' to enable interrupt for event END 6.9.7.13 INTENCLR Address offset: 0x308 4418_1315 v2.0 156 Peripherals Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C B A Reset 0x00000000 ID R/W Field A RW STARTED B C RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Write '1' to disable interrupt for event STARTED Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled STOPPED Write '1' to disable interrupt for event STOPPED Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled END Write '1' to disable interrupt for event END Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.9.7.14 ENABLE Address offset: 0x500 PDM module enable register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Enable or disable PDM module 6.9.7.15 PDMCLKCTRL Address offset: 0x504 PDM clock generator control Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x08400000 ID R/W Field A RW FREQ 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description 1000K 0x08000000 PDM_CLK = 32 MHz / 32 = 1.000 MHz Default 0x08400000 PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for PDM_CLK frequency configuration. RATIO=Ratio64. 1067K 0x08800000 PDM_CLK = 32 MHz / 30 = 1.067 MHz 1231K 0x09800000 PDM_CLK = 32 MHz / 26 = 1.231 MHz 1280K 0x0A000000 PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80. 1333K 4418_1315 v2.0 0x0A800000 PDM_CLK = 32 MHz / 24 = 1.333 MHz 157 Peripherals 6.9.7.16 MODE Address offset: 0x508 Defines the routing of the connected PDM microphones' signals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B A Reset 0x00000000 ID R/W Field A RW OPERATION 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Stereo 0 Mono 1 Description Mono or stereo operation Sample and store one pair (left + right) of 16-bit samples per RAM word R=[31:16]; L=[15:0] Sample and store two successive left samples (16 bits each) per RAM word L1=[31:16]; L0=[15:0] B RW EDGE Defines on which PDM_CLK edge left (or mono) is sampled LeftFalling 0 Left (or mono) is sampled on falling edge of PDM_CLK LeftRising 1 Left (or mono) is sampled on rising edge of PDM_CLK 6.9.7.17 GAINL Address offset: 0x518 Left output gain adjustment Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A Reset 0x00000028 ID R/W Field A RW GAINL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 Value ID Value Description Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust MinGain 0x00 -20 dB gain adjustment (minimum) DefaultGain 0x28 0 dB gain adjustment MaxGain 0x50 +20 dB gain adjustment (maximum) 6.9.7.18 GAINR Address offset: 0x51C Right output gain adjustment 4418_1315 v2.0 158 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A Reset 0x00000028 ID R/W Field A RW GAINR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 Value ID Value Description Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) MinGain 0x00 -20 dB gain adjustment (minimum) DefaultGain 0x28 0 dB gain adjustment MaxGain 0x50 +20 dB gain adjustment (maximum) 6.9.7.19 RATIO Address offset: 0x520 Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW RATIO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Ratio64 0 Ratio of 64 Ratio80 1 Ratio of 80 Selects the ratio between PDM_CLK and output sample rate 6.9.7.20 PSEL.CLK Address offset: 0x540 Pin number configuration for PDM CLK signal Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF ID R/W Field A RW PIN C RW CONNECT A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description [0..31] Pin number Connection Disconnected 1 Disconnect Connected 0 Connect 6.9.7.21 PSEL.DIN Address offset: 0x544 Pin number configuration for PDM DIN signal Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ID R/W Field A RW PIN C RW CONNECT 4418_1315 v2.0 Value ID A A A A A Value Description [0..31] Pin number Connection Disconnected 1 Disconnect Connected 0 Connect 159 Peripherals 6.9.7.22 SAMPLE.PTR Address offset: 0x560 RAM address pointer to write samples to with EasyDMA Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW SAMPLEPTR Value ID Value Description Address to write PDM samples to over DMA Note: See the memory chapter for details about which memories are available for EasyDMA. 6.9.7.23 SAMPLE.MAXCNT Address offset: 0x564 Number of samples to allocate memory for in EasyDMA mode Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW BUFFSIZE Value ID Value Description [0..32767] Length of DMA RAM allocation in number of samples 6.9.8 Electrical specification 6.9.8.1 PDM Electrical Specification Symbol Description fPDM,CLK,64 PDM clock speed. PDMCLKCTRL = Default (Setting needed Min. Typ. Max. Units 1.032 MHz 1.28 MHz for 16 MHz sample frequency @ RATIO = Ratio64) fPDM,CLK,80 PDM clock speed. PDMCLKCTRL = 1280K (Setting needed for 16 MHz sample frequency @ RATIO = Ratio80) tPDM,JITTER Jitter in PDM clock output TdPDM,CLK PDM clock duty cycle tPDM,DATA Decimation filter delay tPDM,cv Allowed clock edge to data valid tPDM,ci Allowed (other) clock edge to data invalid 0 ns tPDM,s Data setup time at fPDM,CLK=1.024 MHz or 1.280 MHz 65 ns tPDM,h Data hold time at fPDM,CLK=1.024 MHz or 1.280 MHz 0 GPDM,default Default (reset) absolute gain of the PDM module 4418_1315 v2.0 40 50 ns 60 % 5 ms 125 ns ns 3.2 160 20 dB Peripherals tPDM,CLK CLK tPDM,cv tPDM,s tPDM,h=tPDM,ci DIN (L) tPDM,cv tPDM,s tPDM,h=tPDM,ci DIN(R) Figure 41: PDM timing diagram 6.10 PWM — Pulse width modulation The pulse with modulation (PWM) module enables the generation of pulse width modulated signals on GPIO. The module implements an up or up-and-down counter with four PWM channels that drive assigned GPIOs. The following are the main features of a PWM module: • • • • • Programmable PWM frequency Up to four PWM channels with individual polarity and duty cycle values Edge or center-aligned pulses across PWM channels Multiple duty cycle arrays (sequences) defined in RAM Autonomous and glitch-free update of duty cycle values directly from memory through EasyDMA (no CPU involvement) • Change of polarity, duty cycle, and base frequency possibly on every PWM period • RAM sequences can be repeated or connected into loops Sequence 0 DATA RAM STARTED STOPPED EasyDMA START Sequence 1 PWM STOP SEQSTART[0] SEQSTART[1] SEQ[n].REFRESH SEQSTARTED[0] SEQSTARTED[1] SEQEND[0] SEQEND[1] Decoder NEXTSTEP Carry/Reload COMP0 PSEL.OUT[0] COMP1 PSEL.OUT[1] COMP2 PSEL.OUT[2] COMP3 PSEL.OUT[3] Wave Counter PWM_CLK COUNTERTOP PRESCALER Figure 42: PWM module 6.10.1 Wave counter The wave counter is responsible for generating the pulses at a duty cycle that depends on the compare values, and at a frequency that depends on COUNTERTOP. There is one common 15-bit counter with four compare channels. Thus, all four channels will share the same period (PWM frequency), but can have individual duty cycle and polarity. The polarity is set by a 4418_1315 v2.0 161 Peripherals value read from RAM (see figure Decoder memory access modes on page 165). Whether the counter counts up, or up and down, is controlled by the MODE register. The timer top value is controlled by the COUNTERTOP register. This register value, in conjunction with the selected PRESCALER of the PWM_CLK, will result in a given PWM period. A COUNTERTOP value smaller than the compare setting will result in a state where no PWM edges are generated. OUT[n] is held high, given that the polarity is set to FallingEdge. All compare registers are internal and can only be configured through decoder presented later. COUNTERTOP can be safely written at any time. Sampling follows the START task. If DECODER.LOAD=WaveForm, the register value is ignored and taken from RAM instead (see section Decoder with EasyDMA on page 165 for more details). If DECODER.LOAD is anything else than the WaveForm, it is sampled following a STARTSEQ[n] task and when loading a new value from RAM during a sequence playback. The following figure shows the counter operating in up mode (MODE=PWM_MODE_Up), with three PWM channels with the same frequency but different duty cycle: COUNTERTOP COMP1 COMP0 OUT[0] OUT[1] Figure 43: PWM counter in up mode example - FallingEdge polarity The counter is automatically reset to zero when COUNTERTOP is reached and OUT[n] will invert. OUT[n] is held low if the compare value is 0 and held high if set to COUNTERTOP, given that the polarity is set to 4418_1315 v2.0 162 Peripherals FallingEdge. Counter running in up mode results in pulse widths that are edge-aligned. The following is the code for the counter in up mode example: uint16_t pwm_seq[4] = {PWM_CH0_DUTY, PWM_CH1_DUTY, PWM_CH2_DUTY, PWM_CH3_DUTY}; NRF_PWM0->PSEL.OUT[0] = (first_pin PSEL.OUT[0] = (first_pin PSEL.OUT[0] = (first_pin LOOP = (16000 DECODER = (PWM_LOOP_CNT_Disabled SEQ[0].PTR = (PWM_DECODER_LOAD_Common SEQ[0].CNT (PWM_DECODER_MODE_RefreshCount TASKS_SEQSTART[0] = 1; To completely stop the PWM generation and force the associated pins to a defined state, a STOP task can be triggered at any time. A STOPPED event is generated when the PWM generation has stopped at the end of the currently running PWM period, and the pins go into their idle state as defined in GPIO OUT register. 4418_1315 v2.0 166 Peripherals PWM generation can then only be restarted through a SEQSTART[n] task. SEQSTART[n] will resume PWM generation after having loaded the first value from the RAM buffer defined in the SEQ[n].PTR register. The following table indicates when specific registers get sampled by the hardware. Care should be taken when updating these registers to avoid that values are applied earlier than expected. Register Taken into account by hardware Recommended (safe) update SEQ[n].PTR When sending the SEQSTART[n] task After having received the SEQSTARTED[n] event SEQ[n].CNT When sending the SEQSTART[n] task After having received the SEQSTARTED[n] event SEQ[0].ENDDELAY When sending the SEQSTART[0] task Before starting sequence [0] through a SEQSTART[0] task Every time a new value from sequence [0] has been loaded from When no more value from sequence [0] gets loaded from RAM RAM and gets applied to the Wave Counter (indicated by the (indicated by the SEQEND[0] event) PWMPERIODEND event) At any time during sequence [1] (which starts when the SEQSTARTED[1] event is generated) SEQ[1].ENDDELAY When sending the SEQSTART[1] task Before starting sequence [1] through a SEQSTART[1] task Every time a new value from sequence [1] has been loaded from When no more value from sequence [1] gets loaded from RAM RAM and gets applied to the Wave Counter (indicated by the (indicated by the SEQEND[1] event) PWMPERIODEND event) At any time during sequence [0] (which starts when the SEQSTARTED[0] event is generated) SEQ[0].REFRESH When sending the SEQSTART[0] task Before starting sequence [0] through a SEQSTART[0] task Every time a new value from sequence [0] has been loaded from At any time during sequence [1] (which starts when the RAM and gets applied to the Wave Counter (indicated by the SEQSTARTED[1] event is generated) PWMPERIODEND event) SEQ[1].REFRESH When sending the SEQSTART[1] task Before starting sequence [1] through a SEQSTART[1] task Every time a new value from sequence [1] has been loaded from At any time during sequence [0] (which starts when the RAM and gets applied to the Wave Counter (indicated by the SEQSTARTED[0] event is generated) PWMPERIODEND event) COUNTERTOP MODE In DECODER.LOAD=WaveForm: this register is ignored. Before starting PWM generation through a SEQSTART[n] task In all other LOAD modes: at the end of current PWM period After a STOP task has been triggered, and the STOPPED event has (indicated by the PWMPERIODEND event) been received. Immediately Before starting PWM generation through a SEQSTART[n] task After a STOP task has been triggered, and the STOPPED event has been received. DECODER Immediately Before starting PWM generation through a SEQSTART[n] task After a STOP task has been triggered, and the STOPPED event has been received. PRESCALER Immediately Before starting PWM generation through a SEQSTART[n] task After a STOP task has been triggered, and the STOPPED event has been received. LOOP Immediately Before starting PWM generation through a SEQSTART[n] task After a STOP task has been triggered, and the STOPPED event has been received. PSEL.OUT[n] Immediately Before enabling the PWM instance through the ENABLE register Table 58: When to safely update PWM registers Note: SEQ[n].REFRESH and SEQ[n].ENDDELAY are ignored at the end of a complex sequence, indicated by a LOOPSDONE event. The reason for this is that the last value loaded from RAM is maintained until further action from software (restarting a new sequence, or stopping PWM generation). 4418_1315 v2.0 167 Peripherals The following figure shows a more complex example using the register LOOP on page 182. SEQ[0].CNT=2, SEQ[1].CNT=3, SEQ[0].REFRESH=1, SEQ[1].REFRESH=0, SEQ[0].ENDDELAY=1, SEQ[1].ENDDELAY=0, LOOP.CNT=1 SEQ[0].PTR Event/Tasks SEQSTART[0] P O COMPARE L P O COMPARE L PWM clock period (continued below) SEQSTARTED[0] SEQEND[0] SEQ[1].PTR 1 PWM period SEQ[0].ENDDELAY=1 (continuation) P O COMPARE L P O COMPARE L PWM generation maintains last played value Event/Tasks SEQSTARTED[1] SEQEND[1] LOOPSDONE Figure 47: Example using two sequences In this case, an automated playback takes place, consisting of SEQ[0], delay 0, SEQ[1], delay 1, then again SEQ[0], etc. The user can choose to start a complex playback with SEQ[0] or SEQ[1] through sending the SEQSTART[0] or SEQSTART[1] task. The complex playback always ends with delay 1. The two sequences 0 and 1 are defined by the addresses of value tables in RAM (pointed to by SEQ[n].PTR) and the buffer size (SEQ[n].CNT). The rate at which a new value is loaded is defined individually for each sequence by SEQ[n].REFRESH. The chaining of sequence 1 following the sequence 0 is implicit, the LOOP.CNT register allows the chaining of sequence 1 to sequence 0 for a determined number of times. In other words, it allows to repeat a complex sequence a number of times in a fully automated way. In the following code example, sequence 0 is defined with SEQ[0].REFRESH set to 1, meaning that a new PWM duty cycle is pushed every second PWM period. This complex sequence is started with the SEQSTART[0] task, so SEQ[0] is played first. Since SEQ[0].ENDDELAY=1 there will be one PWM period delay between last period on sequence 0 and the first period on sequence 1. Since SEQ[1].ENDDELAY=0 there is no delay 1, so SEQ[0] would be started immediately after the end of SEQ[1]. However, as LOOP.CNT is 4418_1315 v2.0 168 Peripherals 1, the playback stops after having played SEQ[1] only once, and both SEQEND[1] and LOOPSDONE are generated (their order is not guaranteed in this case). NRF_PWM0->PSEL.OUT[0] = (first_pin DECODER = (1 SEQ[0].PTR = (PWM_DECODER_LOAD_Common SEQ[0].CNT (PWM_DECODER_MODE_RefreshCount SEQ[1].PTR NRF_PWM0->SEQ[1].CNT = ((uint32_t)(seq1_ram) SEQ[1].ENDDELAY = 0; NRF_PWM0->TASKS_SEQSTART[0] = 1; The decoder can also be configured to asynchronously load new PWM duty cycle. If the DECODER.MODE register is set to NextStep, then the NEXTSTEP task will cause an update of internal compare registers on the next PWM period. The following figures provide an overview of each part of an arbitrary sequence, in various modes (LOOP.CNT=0 and LOOP.CNT>0). In particular, the following are represented: • • • • • Initial and final duty cycle on the PWM output(s) Chaining of SEQ[0] and SEQ[1] if LOOP.CNT>0 Influence of registers on the sequence Events generated during a sequence DMA activity (loading of next value and applying it to the output(s)) 4418_1315 v2.0 169 4418_1315 v2.0 170 1 Figure 49: Complex sequence (LOOP.CNT>0) starting with SEQ[0] SEQ[1].ENDDELAY SEQ[1].CNT SEQ[0].ENDDELAY SEQ[0].CNT SEQ[1].CNT SEQ[0].ENDDELAY (LOOP.CNT - 1) ... EVENTS_SEQSTARTED[1] EVENTS_SEQEND[1] EVENTS_LOOPSDONE EVENTS_SEQEND[0] EVENTS_SEQSTARTED[0] EVENTS_SEQSTARTED[1] EVENTS_SEQEND[1] EVENTS_SEQEND[0] SEQ[0].CNT SEQ[1].ENDDELAY SEQ[1].CNT SEQ[0].ENDDELAY LOOP.CNT EVENTS_SEQSTARTED[0] EVENTS_SEQSTARTED[1] EVENTS_SEQEND[1] SEQ[0].CNT Loop counter EVENTS_SEQEND[0] TASKS_SEQSTART[0] EVENTS_SEQSTARTED[0] EVENTS_SEQEND[0] TASKS_SEQSTART[0] EVENTS_SEQSTARTED[0] SEQ[0].ENDDELAY SEQ[0].CNT Peripherals 100% duty cycle last loaded duty cycle maintained Previously loaded duty cycle New value load 0% duty cycle Figure 48: Single shot (LOOP.CNT=0) Note: The single-shot example also applies to SEQ[1]. Only SEQ[0] is represented for simplicity. 100% duty cycle Previously loaded duty cycle last loaded duty cycle maintained New value load 0% duty cycle 1 SEQ[1].CNT SEQ[0].ENDDELAY SEQ[0].CNT SEQ[1].CNT SEQ[0].ENDDELAY (LOOP.CNT - 1) ... SEQ[0].CNT SEQ[1].CNT SEQ[1].ENDDELAY LOOP.CNT Loop counter SEQ[1].ENDDELAY Peripherals 100% duty cycle Previously loaded duty cycle last loaded duty cycle maintained 0% duty cycle EVENTS_SEQSTARTED[1] EVENTS_SEQEND[1] EVENTS_LOOPSDONE EVENTS_SEQEND[0] EVENTS_SEQSTARTED[0] EVENTS_SEQSTARTED[1] EVENTS_SEQEND[1] EVENTS_SEQEND[0] EVENTS_SEQSTARTED[0] TASKS_SEQSTART[1] EVENTS_SEQSTARTED[1] EVENTS_SEQEND[1] New value load Figure 50: Complex sequence (LOOP.CNT>0) starting with SEQ[1] Note: If a sequence is in use in a simple or complex sequence, it must have a length of SEQ[n].CNT > 0. This example shows how the PWM module can be configured to repeat a single sequence until stopped. NRF_PWM0->PSEL.OUT[0] = (first_pin DECODER = (1 TASKS_SEQSTART[1] = 1; 4418_1315 v2.0 171 Peripherals 6.10.3 Limitations The previous compare value is repeated if the PWM period is shorter than the time it takes for the EasyDMA to retrieve from RAM and update the internal compare registers. This is to ensure a glitch-free operation even for very short PWM periods. Only SEQ[1] can trigger the LOOPSDONE event upon completion, not SEQ[0]. This requires looping to be enabled (LOOP > 0) and SEQ[1].CNT > 0 when sequence playback starts. 6.10.4 Pin configuration The OUT[n] (n=0..3) signals associated with each PWM channel are mapped to physical pins according to the configuration of PSEL.OUT[n] registers. If PSEL.OUT[n].CONNECT is set to Disconnected, the associated PWM module signal will not be connected to any physical pins. The PSEL.OUT[n] registers and their configurations are used as long as the PWM module is enabled and the PWM generation active (wave counter started). They are retained only as long as the device is in System ON mode (see the POWER section for more information about power modes). To ensure correct behavior in the PWM module, the pins that are used must be configured in the GPIO peripheral in the following way before the PWM module is enabled: PWM signal PWM pin Direction Output value Comment OUT[n] As specified in PSEL.OUT[n] Output 0 Idle state defined in GPIO OUT (n=0..3) register Table 59: Recommended GPIO configuration before starting PWM generation The idle state of a pin is defined by the OUT register in the GPIO module, to ensure that the pins used by the PWM module are driven correctly. If PWM generation is stopped by triggering a STOP task, the PWM module itself is temporarily disabled or the device temporarily enters System OFF. This configuration must be retained in the GPIO for the selected pins (I/Os) for as long as the PWM module is supposed to be connected to an external PWM circuit. Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in unpredictable behavior. 6.10.5 Registers Base address Peripheral Instance 0x50021000 PWM0 : S 0x40021000 0x50022000 0x40022000 0x50023000 0x40023000 0x50024000 0x40024000 PWM PWM PWM PWM PWM0 : NS PWM1 : S PWM1 : NS PWM2 : S PWM2 : NS PWM3 : S PWM3 : NS Secure mapping DMA security Description US SA Pulse width modulation unit 0 US SA Pulse width modulation unit 1 US SA Pulse width modulation unit 2 US SA Pulse width modulation unit 3 Configuration Table 60: Instances Register Offset TASKS_STOP 0x004 Security Description Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback 4418_1315 v2.0 172 Peripherals Register Offset TASKS_SEQSTART[n] 0x008 Security Description Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. TASKS_NEXTSTEP 0x010 Steps by one value in the current sequence on all enabled channels if SUBSCRIBE_STOP 0x084 Subscribe configuration for task STOP SUBSCRIBE_SEQSTART[n] 0x088 Subscribe configuration for task SEQSTART[n] SUBSCRIBE_NEXTSTEP 0x090 Subscribe configuration for task NEXTSTEP EVENTS_STOPPED 0x104 Response to STOP task, emitted when PWM pulses are no longer generated EVENTS_SEQSTARTED[n] 0x108 First PWM period started on sequence n EVENTS_SEQEND[n] 0x110 Emitted at end of every sequence n, when last value from RAM has been applied to wave DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. counter EVENTS_PWMPERIODEND 0x118 Emitted at the end of each PWM period EVENTS_LOOPSDONE 0x11C Concatenated sequences have been played the amount of times defined in LOOP.CNT PUBLISH_STOPPED 0x184 Publish configuration for event STOPPED PUBLISH_SEQSTARTED[n] 0x188 Publish configuration for event SEQSTARTED[n] PUBLISH_SEQEND[n] 0x190 Publish configuration for event SEQEND[n] PUBLISH_PWMPERIODEND 0x198 Publish configuration for event PWMPERIODEND PUBLISH_LOOPSDONE 0x19C Publish configuration for event LOOPSDONE SHORTS 0x200 Shortcuts between local events and tasks INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt ENABLE 0x500 PWM module enable register MODE 0x504 Selects operating mode of the wave counter COUNTERTOP 0x508 Value up to which the pulse generator counter counts PRESCALER 0x50C Configuration for PWM_CLK DECODER 0x510 Configuration of the decoder LOOP 0x514 Number of playbacks of a loop SEQ[n].PTR 0x520 Beginning address in RAM of this sequence SEQ[n].CNT 0x524 Number of values (duty cycles) in this sequence SEQ[n].REFRESH 0x528 Number of additional PWM periods between samples loaded into compare register SEQ[n].ENDDELAY 0x52C Time added after the sequence PSEL.OUT[n] 0x560 Output pin select for PWM channel n Table 61: Register overview 6.10.5.1 TASKS_STOP Address offset: 0x004 Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_STOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback Trigger 4418_1315 v2.0 1 Trigger task 173 Peripherals 6.10.5.2 TASKS_SEQSTART[n] (n=0..1) Address offset: 0x008 + (n × 0x4) Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_SEQSTART 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running. Trigger 1 Trigger task 6.10.5.3 TASKS_NEXTSTEP Address offset: 0x010 Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_NEXTSTEP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running. Trigger 1 Trigger task 6.10.5.4 SUBSCRIBE_STOP Address offset: 0x084 Subscribe configuration for task STOP Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that task STOP will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.10.5.5 SUBSCRIBE_SEQSTART[n] (n=0..1) Address offset: 0x088 + (n × 0x4) Subscribe configuration for task SEQSTART[n] 4418_1315 v2.0 174 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that task SEQSTART[n] will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.10.5.6 SUBSCRIBE_NEXTSTEP Address offset: 0x090 Subscribe configuration for task NEXTSTEP Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that task NEXTSTEP will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.10.5.7 EVENTS_STOPPED Address offset: 0x104 Response to STOP task, emitted when PWM pulses are no longer generated Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_STOPPED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Response to STOP task, emitted when PWM pulses are no longer generated NotGenerated 0 Event not generated Generated 1 Event generated 6.10.5.8 EVENTS_SEQSTARTED[n] (n=0..1) Address offset: 0x108 + (n × 0x4) First PWM period started on sequence n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_SEQSTARTED 4418_1315 v2.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated First PWM period started on sequence n 175 Peripherals 6.10.5.9 EVENTS_SEQEND[n] (n=0..1) Address offset: 0x110 + (n × 0x4) Emitted at end of every sequence n, when last value from RAM has been applied to wave counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_SEQEND 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Emitted at end of every sequence n, when last value from RAM has been applied to wave counter NotGenerated 0 Event not generated Generated 1 Event generated 6.10.5.10 EVENTS_PWMPERIODEND Address offset: 0x118 Emitted at the end of each PWM period Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW EVENTS_PWMPERIODEND Value ID Value Description Emitted at the end of each PWM period NotGenerated 0 Event not generated Generated 1 Event generated 6.10.5.11 EVENTS_LOOPSDONE Address offset: 0x11C Concatenated sequences have been played the amount of times defined in LOOP.CNT This event triggers after the last SEQ[1] completion of the loop, and only if looping was enabled (LOOP > 0) when the sequence playback was started. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_LOOPSDONE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Concatenated sequences have been played the amount of times defined in LOOP.CNT This event triggers after the last SEQ[1] completion of the loop, and only if looping was enabled (LOOP > 0) when the sequence playback was started. NotGenerated 0 Event not generated Generated 1 Event generated 6.10.5.12 PUBLISH_STOPPED Address offset: 0x184 Publish configuration for event STOPPED 4418_1315 v2.0 176 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that event STOPPED will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.10.5.13 PUBLISH_SEQSTARTED[n] (n=0..1) Address offset: 0x188 + (n × 0x4) Publish configuration for event SEQSTARTED[n] Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event SEQSTARTED[n] will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.10.5.14 PUBLISH_SEQEND[n] (n=0..1) Address offset: 0x190 + (n × 0x4) Publish configuration for event SEQEND[n] Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event SEQEND[n] will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.10.5.15 PUBLISH_PWMPERIODEND Address offset: 0x198 Publish configuration for event PWMPERIODEND Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN 4418_1315 v2.0 Value ID A A A A A A A A Value Description [255..0] DPPI channel that event PWMPERIODEND will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 177 Peripherals 6.10.5.16 PUBLISH_LOOPSDONE Address offset: 0x19C Publish configuration for event LOOPSDONE This event triggers after the last SEQ[1] completion of the loop, and only if looping was enabled (LOOP > 0) when the sequence playback was started. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that event LOOPSDONE will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.10.5.17 SHORTS Address offset: 0x200 Shortcuts between local events and tasks Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID E D C B A Reset 0x00000000 ID R/W Field A RW SEQEND0_STOP B C D E RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Shortcut between event SEQEND[0] and task STOP Disabled 0 Disable shortcut Enabled 1 Enable shortcut Disabled 0 Disable shortcut Enabled 1 Enable shortcut SEQEND1_STOP Shortcut between event SEQEND[1] and task STOP LOOPSDONE_SEQSTART0 Shortcut between event LOOPSDONE and task SEQSTART[0] Disabled 0 Disable shortcut Enabled 1 Enable shortcut LOOPSDONE_SEQSTART1 Shortcut between event LOOPSDONE and task SEQSTART[1] Disabled 0 Disable shortcut Enabled 1 Enable shortcut LOOPSDONE_STOP Shortcut between event LOOPSDONE and task STOP Disabled 0 Disable shortcut Enabled 1 Enable shortcut 6.10.5.18 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E D C B Reset 0x00000000 ID R/W Field B RW STOPPED 4418_1315 v2.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enable or disable interrupt for event STOPPED 178 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E D C B Reset 0x00000000 ID C-D E-F G H R/W RW RW RW RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable SEQSTARTED[i] (i=0..1) Enable or disable interrupt for event SEQSTARTED[i] SEQEND[i] (i=0..1) Enable or disable interrupt for event SEQEND[i] Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable PWMPERIODEND Enable or disable interrupt for event PWMPERIODEND LOOPSDONE Enable or disable interrupt for event LOOPSDONE This event triggers after the last SEQ[1] completion of the loop, and only if looping was enabled (LOOP > 0) when the sequence playback was started. Disabled 0 Disable Enabled 1 Enable 6.10.5.19 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E D C B Reset 0x00000000 ID R/W Field B RW STOPPED C-D E-F G H RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event STOPPED SEQSTARTED[i] (i=0..1) Write '1' to enable interrupt for event SEQSTARTED[i] SEQEND[i] (i=0..1) Write '1' to enable interrupt for event SEQEND[i] PWMPERIODEND Write '1' to enable interrupt for event PWMPERIODEND LOOPSDONE Write '1' to enable interrupt for event LOOPSDONE This event triggers after the last SEQ[1] completion of the loop, and only if looping was enabled (LOOP > 0) when the sequence playback was started. 4418_1315 v2.0 Set 1 Enable Disabled 0 Read: Disabled 179 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E D C B Reset 0x00000000 ID R/W Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enabled 1 Read: Enabled 6.10.5.20 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID H G F E D C B Reset 0x00000000 ID R/W Field B RW STOPPED C-D E-F G H RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event STOPPED SEQSTARTED[i] (i=0..1) Write '1' to disable interrupt for event SEQSTARTED[i] SEQEND[i] (i=0..1) Write '1' to disable interrupt for event SEQEND[i] PWMPERIODEND Write '1' to disable interrupt for event PWMPERIODEND LOOPSDONE Write '1' to disable interrupt for event LOOPSDONE This event triggers after the last SEQ[1] completion of the loop, and only if looping was enabled (LOOP > 0) when the sequence playback was started. Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.10.5.21 ENABLE Address offset: 0x500 PWM module enable register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW ENABLE 4418_1315 v2.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disabled Enabled 1 Enable Enable or disable PWM module 180 Peripherals 6.10.5.22 MODE Address offset: 0x504 Selects operating mode of the wave counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW UPDOWN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Up 0 Up counter, edge-aligned PWM duty cycle UpAndDown 1 Up and down counter, center-aligned PWM duty cycle Selects up mode or up-and-down mode for the counter 6.10.5.23 COUNTERTOP Address offset: 0x508 Value up to which the pulse generator counter counts Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A Reset 0x000003FF ID R/W Field A RW COUNTERTOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Value ID Value Description [3..32767] Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used. 6.10.5.24 PRESCALER Address offset: 0x50C Configuration for PWM_CLK Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A Reset 0x00000000 ID R/W Field A RW PRESCALER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description DIV_1 0 Divide by 1 (16 MHz) DIV_2 1 Divide by 2 (8 MHz) DIV_4 2 Divide by 4 (4 MHz) DIV_8 3 Divide by 8 (2 MHz) DIV_16 4 Divide by 16 (1 MHz) DIV_32 5 Divide by 32 (500 kHz) DIV_64 6 Divide by 64 (250 kHz) DIV_128 7 Divide by 128 (125 kHz) Prescaler of PWM_CLK 6.10.5.25 DECODER Address offset: 0x510 Configuration of the decoder 4418_1315 v2.0 181 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW LOAD B RW A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Common 0 1st half word (16-bit) used in all PWM channels 0..3 Grouped 1 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 Individual 2 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 WaveForm 3 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP How a sequence is read from RAM and spread to the compare register MODE Selects source for advancing the active sequence RefreshCount 0 NextStep 1 SEQ[n].REFRESH is used to determine loading internal compare registers NEXTSTEP task causes a new value to be loaded to internal compare registers 6.10.5.26 LOOP Address offset: 0x514 Number of playbacks of a loop Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A Reset 0x00000000 ID R/W Field A RW CNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Disabled 0 Description Number of playbacks of pattern cycles Looping disabled (stop at the end of the sequence) 6.10.5.27 SEQ[n].PTR (n=0..1) Address offset: 0x520 + (n × 0x20) Beginning address in RAM of this sequence Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID R/W Field A RW PTR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Beginning address in RAM of this sequence Note: See the memory chapter for details about which memories are available for EasyDMA. 6.10.5.28 SEQ[n].CNT (n=0..1) Address offset: 0x524 + (n × 0x20) Number of values (duty cycles) in this sequence 4418_1315 v2.0 182 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A Reset 0x00000000 ID R/W Field A RW CNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Disabled 0 Description Number of values (duty cycles) in this sequence Sequence is disabled, and shall not be started as it is empty 6.10.5.29 SEQ[n].REFRESH (n=0..1) Address offset: 0x528 + (n × 0x20) Number of additional PWM periods between samples loaded into compare register Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000001 ID R/W Field A RW CNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Number of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) Continuous 0 Update every PWM period 6.10.5.30 SEQ[n].ENDDELAY (n=0..1) Address offset: 0x52C + (n × 0x20) Time added after the sequence Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID R/W Field A RW CNT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Time added after the sequence in PWM periods 6.10.5.31 PSEL.OUT[n] (n=0..3) Address offset: 0x560 + (n × 0x4) Output pin select for PWM channel n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID C Reset 0xFFFFFFFF ID R/W Field A RW PIN C RW CONNECT A A A A A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Value ID Value Description [0..31] Pin number Connection Disconnected 1 Disconnect Connected 0 Connect 6.11 RTC — Real-time counter The real-time counter (RTC) module provides a generic, low-power timer on the low frequency clock source (LFCLK). 4418_1315 v2.0 183 Peripherals RTC START PRESCALER STOP COUNTER TICK CLEAR OVRFLW TRIGOVRFLW CC[0:n] CAPTURE[0:n] COMPARE[0:n] LFCLK 32.768 kHz Figure 51: RTC block diagram The RTC module features a 24-bit COUNTER, a 12-bit (1/X) prescaler, compare registers, and a tick event generator. 6.11.1 Clock source The RTC will run off the LFCLK. When started, the RTC will automatically request the LFCLK source with RC oscillator if the LFCLK is not already running. See CLOCK — Clock control on page 70 for more information about clock sources. 6.11.2 Resolution versus overflow and the prescaler The relationship between the prescaler, counter resolution, and overflow is summarized in the following table. Prescaler Counter resolution Overflow 0 30.517 μs 512 seconds 28-1 7812.5 μs 131072 seconds 212-1 125 ms 582.542 hours Table 62: RTC resolution versus overflow The counter increment frequency is given by the following equation: fRTC [kHz] = 32.768 / (PRESCALER + 1 ) The PRESCALER register can only be written when the RTC is stopped. The prescaler is restarted on tasks START, CLEAR and TRIGOVRFLW. That is, the prescaler value is latched to an internal register () on these tasks. Examples: 1. Desired COUNTER frequency 100 Hz (10 ms counter period) PRESCALER = round(32.768 kHz / 100 Hz) - 1 = 327 fRTC = 99.9 Hz 10009.576 μs counter period 4418_1315 v2.0 184 Peripherals 2. Desired COUNTER frequency 8 Hz (125 ms counter period) PRESCALER = round(32.768 kHz / 8 Hz) – 1 = 4095 fRTC = 8 Hz 125 ms counter period 6.11.3 Counter register The internal register increments on LFCLK when the internal PRESCALER register () is 0x00. is reloaded from the PRESCALER register. If enabled, the TICK event occurs on each increment of the COUNTER. PCLK16M LFCLK TICK PRESC 0x000 0x000 0x000 0x000 0x000 0x000000 0x000001 0x000002 0x000003 Figure 52: Timing diagram - COUNTER_PRESCALER_0 PCLK16M LFCLK TICK PRESC 0x001 0x000 0x001 0x000 0x000000 0x001 0x000001 Figure 53: Timing diagram - COUNTER_PRESCALER_1 6.11.3.1 Reading the counter register To read the COUNTER register, the internal value is sampled. To ensure that the is safely sampled (considering that an LFCLK transition may occur during a read), the CPU and core memory bus are halted for PCLK16M cycles. In addition, the read takes the CPU two PCLK16M cycles, resulting in the COUNTER register read taking maximum six PCLK16M clock cycles. 6.11.4 Overflow An OVRFLW event is generated on COUNTER register overflow (overflowing from 0xFFFFFF to 0). The TRIGOVRFLW task will set the COUNTER value to 0xFFFFF0, to allow software test of the overflow condition. Note: The OVRFLW event is disabled by default. 4418_1315 v2.0 185 Peripherals 6.11.5 Tick event The TICK event enables low-power tickless RTOS implementation, as it optionally provides a regular interrupt source for an RTOS with no need for use of the ARM SysTick feature. Using the TICK event, rather than the SysTick, allows the CPU to be powered down while keeping RTOS scheduling active. Note: The TICK event is disabled by default. 6.11.6 Event control To optimize the RTC power consumption, events in the RTC can be individually disabled to prevent PCLK16M and HFCLK from being requested when those events are triggered. This is managed using the EVTEN register. This means that the RTC implements a slightly different task and event system compared to the standard system described in Peripheral interface on page 15. The RTC task and event system is illustrated in the following figure. Task signal from PPI RTC write TASK OR task RTC core event EVTEN m INTEN m EVENT m IRQ signal to NVIC Event signal to PPI Figure 54: Tasks, events, and interrupts in the RTC 6.11.7 Compare The RTC implements one COMPARE event for every available compare register. When the COUNTER is incremented and then becomes equal to the value specified in the register CC[n], the corresponding compare event COMPARE[n] is generated. When writing a CC[n] register, the RTC COMPARE event exhibits several behaviors. See the following figures for more information. If a CC value is 0 when a CLEAR task is set, this will not trigger a COMPARE event. 4418_1315 v2.0 186 Peripherals PCLK16M LFCLK 0x000 X 0x000000 CLEAR CC[0] 0x000000 COMPARE[0] 0 Figure 55: Timing diagram - COMPARE_CLEAR If a CC value is N and the COUNTER value is N when the START task is set, this will not trigger a COMPARE event. PCLK16M LFCLK 0x000 N N+1 START CC[0] N COMPARE[0] 0 Figure 56: Timing diagram - COMPARE_START A COMPARE event occurs when a CC value is N, and the COUNTER value transitions from N-1 to N. PCLK16M LFCLK 0x000 N-2 N-1 CC[0] COMPARE[0] N N+1 N 0 1 Figure 57: Timing diagram - COMPARE If the COUNTER value is N, writing N+2 to a CC register is guaranteed to trigger a COMPARE event at N+2. 4418_1315 v2.0 187 Peripherals PCLK16M LFCLK 0x000 N-1 N N+1 N+2 > 62.5 ns CC[0] X N+2 COMPARE[0] 0 1 Figure 58: Timing diagram - COMPARE_N+2 If the COUNTER value is N, writing N or N+1 to a CC register may not trigger a COMPARE event. PCLK16M LFCLK 0x000 N-2 N-1 N N+1 >= 0 ns CC[0] X N+1 COMPARE[0] 0 Figure 59: Timing diagram - COMPARE_N+1 If the COUNTER value is N, and the current CC value is N+1 or N+2 when a new CC value is written, a match may trigger on the previous CC value before the new value takes effect. If the current CC value is greater than N+2 when the new value is written, there will be no event due to the old value. PCLK16M LFCLK 0x000 N-2 N-1 N N+1 >= 0 ns CC[0] N COMPARE[0] X 0 1 Figure 60: Timing diagram - COMPARE_N-1 6.11.8 Task and event jitter/delay Jitter or delay in the RTC, is due to the peripheral clock being a low frequency clock (LFCLK), which is not synchronous to the faster PCLK16M. Registers in the peripheral interface that are part of the PCLK16M domain, have a set of mirrored registers in the LFCLK domain. For example, the COUNTER value accessible from the CPU is in the PCLK16M domain, and is latched on a read from an internal COUNTER register in the LFCLK domain. The COUNTER register 4418_1315 v2.0 188 Peripherals is modified each time the RTC ticks. The registers are synchronised between the two clock domains (PCLK16M and LFCLK). CLEAR and STOP (and TRIGOVRFLW, which is not shown) will be delayed as long as it takes for the peripheral to clock a falling edge and a rising edge of the LFCLK. This is between 15.2585 μs and 45.7755 μs – rounded to 15 μs and 46 μs for the remainder of the section. PCLK16M CLEAR LFCLK 0x000 X X+1 0x000000 0x000001 0 or more PCLK16M cycles after CLEARa = ~15 µs 1 or more PCLK16M cycles before CLEARb Figure 61: Timing diagram - DELAY_CLEAR When a STOP task is triggered, the PCLK16M domain will immediately prevent the generation of any EVENTS from the RTC. However, as seen in the following figure, the COUNTER value can still increment one final time. PCLK16M STOP LFCLK 0x000 X X+1 0 or more PCLK16M cycles after STOPa = ~15 µs 1 or more PCLK16M cycles before Figure 62: Timing diagram - DELAY_STOP The START task will start the RTC. Assuming that the LFCLK was previously running and stable, the first increment of COUNTER (and instance of TICK event) will be typically after 30.5 μs +/-15 μs. Additional delay will occur if the RTC is started before the LFCLK is running, see CLOCK — Clock control on page 70 for LFLK startup times. The software should therefore wait for the first TICK if it has to make sure that the RTC is running. Sending a TRIGOVRFLW task sets the COUNTER to a value close to overflow. However, since the update of COUNTER relies on a stable LFCLK, sending this task while LFCLK is not running will also add additional delay as previously described. The figures show the smallest and largest delays on the START task, appearing as a +/-15 μs jitter on the first COUNTER increment. 4418_1315 v2.0 189 Peripherals PCLK16M First tick LFCLK PRESC 0x000 COUNTER X X+1 X+2 X+3 >= ~15 µs 0 or more PCLK16M cycles before START Figure 63: Timing diagram - JITTER_STARTPCLK16M First tick LFCLK PRESC 0x000 COUNTER X X+1 X+2 LFCLK startup time START Figure 64: Timing diagram - JITTER_START+ The following tables summarize jitter introduced for tasks and events. Any 32.768 kHz clock jitter will come in addition to these numbers. Task Delay CLEAR, START, STOP, TRIGOVRFLOW +15 to 46 μs Table 63: RTC jitter magnitudes on tasks Operation/Function Jitter START to COUNTER increment COMPARE to COMPARE ± 15 μs ± 62.5 ns 12 Table 64: RTC jitter magnitudes on events 6.11.9 Registers Base address Peripheral Instance 0x50014000 RTC0 : S 0x40014000 0x50015000 0x40015000 RTC RTC RTC0 : NS RTC1 : S RTC1 : NS Secure mapping DMA security Description US NA Real time counter 0 US NA Real time counter 1 Table 65: Instances 12 Assumes RTC runs continuously between these events. 4418_1315 v2.0 190 Configuration Peripherals Register Offset Security Description TASKS_START 0x000 Start RTC counter TASKS_STOP 0x004 Stop RTC counter TASKS_CLEAR 0x008 Clear RTC counter TASKS_TRIGOVRFLW 0x00C Set counter to 0xFFFFF0 SUBSCRIBE_START 0x080 Subscribe configuration for task START SUBSCRIBE_STOP 0x084 Subscribe configuration for task STOP SUBSCRIBE_CLEAR 0x088 Subscribe configuration for task CLEAR SUBSCRIBE_TRIGOVRFLW 0x08C Subscribe configuration for task TRIGOVRFLW EVENTS_TICK 0x100 Event on counter increment EVENTS_OVRFLW 0x104 Event on counter overflow EVENTS_COMPARE[n] 0x140 Compare event on CC[n] match PUBLISH_TICK 0x180 Publish configuration for event TICK PUBLISH_OVRFLW 0x184 Publish configuration for event OVRFLW PUBLISH_COMPARE[n] 0x1C0 Publish configuration for event COMPARE[n] INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt EVTEN 0x340 Enable or disable event routing EVTENSET 0x344 Enable event routing EVTENCLR 0x348 Disable event routing COUNTER 0x504 Current counter value PRESCALER 0x508 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is CC[n] 0x540 stopped. Compare register n Table 66: Register overview 6.11.9.1 TASKS_START Address offset: 0x000 Start RTC counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_START 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Start RTC counter Trigger 1 Trigger task 6.11.9.2 TASKS_STOP Address offset: 0x004 Stop RTC counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_STOP 4418_1315 v2.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description Stop RTC counter Trigger task 191 Peripherals 6.11.9.3 TASKS_CLEAR Address offset: 0x008 Clear RTC counter Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_CLEAR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description Clear RTC counter Trigger task 6.11.9.4 TASKS_TRIGOVRFLW Address offset: 0x00C Set counter to 0xFFFFF0 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_TRIGOVRFLW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description Set counter to 0xFFFFF0 Trigger task 6.11.9.5 SUBSCRIBE_START Address offset: 0x080 Subscribe configuration for task START Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that task START will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.11.9.6 SUBSCRIBE_STOP Address offset: 0x084 Subscribe configuration for task STOP Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN 4418_1315 v2.0 A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that task STOP will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 192 Peripherals 6.11.9.7 SUBSCRIBE_CLEAR Address offset: 0x088 Subscribe configuration for task CLEAR Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that task CLEAR will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.11.9.8 SUBSCRIBE_TRIGOVRFLW Address offset: 0x08C Subscribe configuration for task TRIGOVRFLW Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that task TRIGOVRFLW will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.11.9.9 EVENTS_TICK Address offset: 0x100 Event on counter increment Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_TICK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Event on counter increment NotGenerated 0 Event not generated Generated 1 Event generated 6.11.9.10 EVENTS_OVRFLW Address offset: 0x104 Event on counter overflow 4418_1315 v2.0 193 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_OVRFLW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Event on counter overflow 6.11.9.11 EVENTS_COMPARE[n] (n=0..3) Address offset: 0x140 + (n × 0x4) Compare event on CC[n] match Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_COMPARE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated Compare event on CC[n] match 6.11.9.12 PUBLISH_TICK Address offset: 0x180 Publish configuration for event TICK Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that event TICK will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.11.9.13 PUBLISH_OVRFLW Address offset: 0x184 Publish configuration for event OVRFLW Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event OVRFLW will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.11.9.14 PUBLISH_COMPARE[n] (n=0..3) Address offset: 0x1C0 + (n × 0x4) 4418_1315 v2.0 194 Peripherals Publish configuration for event COMPARE[n] Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event COMPARE[n] will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.11.9.15 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E D C Reset 0x00000000 ID R/W Field A RW TICK B C-F RW RW B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event TICK OVRFLW Write '1' to enable interrupt for event OVRFLW COMPARE[i] (i=0..3) Write '1' to enable interrupt for event COMPARE[i] 6.11.9.16 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E D C Reset 0x00000000 ID R/W Field A RW TICK B C-F RW RW Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Write '1' to disable interrupt for event TICK OVRFLW Write '1' to disable interrupt for event OVRFLW COMPARE[i] (i=0..3) 4418_1315 v2.0 B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Write '1' to disable interrupt for event COMPARE[i] Disable 195 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E D C Reset 0x00000000 ID R/W Field B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.11.9.17 EVTEN Address offset: 0x340 Enable or disable event routing Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E D C Reset 0x00000000 ID R/W Field A RW TICK B C-F RW RW B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Enable or disable event routing for event TICK OVRFLW Enable or disable event routing for event OVRFLW COMPARE[i] (i=0..3) Enable or disable event routing for event COMPARE[i] Disabled 0 Disable Enabled 1 Enable 6.11.9.18 EVTENSET Address offset: 0x344 Enable event routing Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E D C Reset 0x00000000 ID R/W Field A RW TICK B C-F RW RW Value ID Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Write '1' to enable event routing for event TICK OVRFLW Write '1' to enable event routing for event OVRFLW COMPARE[i] (i=0..3) Write '1' to enable event routing for event COMPARE[i] 6.11.9.19 EVTENCLR Address offset: 0x348 Disable event routing 4418_1315 v2.0 B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 196 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID F E D C Reset 0x00000000 ID R/W Field A RW TICK B C-F RW RW B A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Write '1' to disable event routing for event TICK OVRFLW Write '1' to disable event routing for event OVRFLW COMPARE[i] (i=0..3) Write '1' to disable event routing for event COMPARE[i] 6.11.9.20 COUNTER Address offset: 0x504 Current counter value Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID R/W Field A R COUNTER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Counter value 6.11.9.21 PRESCALER Address offset: 0x508 12-bit prescaler for counter frequency (32768/(PRESCALER+1)). Must be written when RTC is stopped. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A Reset 0x00000000 ID R/W Field A RW PRESCALER 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Prescaler value 6.11.9.22 CC[n] (n=0..3) Address offset: 0x540 + (n × 0x4) Compare register n Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 ID R/W Field A RW COMPARE 4418_1315 v2.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Compare value 197 Peripherals 6.11.10 Electrical specification 6.12 SAADC — Successive approximation analog-todigital converter The SAADC is a differential successive approximation register (SAR) analog-to-digital converter. Listed here are the main features of SAADC: • 8/10/12-bit resolution, 14-bit resolution with oversampling • Multiple analog inputs: • AIN0 to AIN7 pins • VDD_GPIO pin • Up to eight input channels: • • • • • • • • • • • One channel per single-ended input and two channels per differential input • Scan mode can be configured with both single-ended channels and differential channels • Each channel can be configured to select any of the above analog inputs Full scale input range (0 to VDD_GPIO) Sampling triggered via a task from software or a PPI channel for full flexibility on sample frequency source from low-power 32.768 kHz RTC or more accurate 1/16 MHz timers One-shot conversion mode to sample a single channel Scan mode to sample a series of channels in sequence with configurable sample delay Support for direct sample transfer to RAM using EasyDMA Interrupts on single sample and full buffer events Samples stored as 16-bit two’s complement values for differential and single-ended sampling Continuous sampling without the need of an external timer Internal resistor string On-the-fly limit checking 6.12.1 Overview The ADC supports up to eight external analog input channels. It can be operated in One-shot mode with sampling under software control, or Continuous mode with a programmable sampling rate. The analog inputs can be configured as eight single-ended inputs, four differential inputs or a combination of these. Each channel can be configured to select: • AIN0 to AIN7 pins • VDD_GPIO pin Channels can be sampled individually in one-shot or continuous sampling modes, or, using scan mode, multiple channels can be sampled in sequence. Channels can also be oversampled to improve noise performance. 4418_1315 v2.0 198 Peripherals PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A CH[X].CONFIG PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A CH[X].PSELP NC AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VDD_GPIO ADC RAM MUX RESULT P RESP RESULT GAIN NC AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 VDD_GPIO RESULT SAR core EasyDMA RESULT RESULT RESULT N RESN RESULT RESULT MUX RESULT.PTR START SAMPLE VDD_GPIO Internal reference REFSEL STARTED END STOPPED STOP CH[X].PSELN PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A PSEL_A Figure 65: Simplified ADC block diagram Internally, the ADC is always a differential analog-to-digital converter, but by default it is configured with single-ended input in the MODE field of the CH[n].CONFIG register. In single-ended mode, the negative input will be shorted to ground internally. The assumption in single-ended mode is that the internal ground of the ADC is the same as the external ground that the measured voltage is referred to. The ADC is thus sensitive to ground bounce on the PCB in single-ended mode. If this is a concern we recommend using differential measurement. 6.12.2 Digital output The output result of the ADC depends on the settings in the CH[n].CONFIG and RESOLUTION registers as follows: RESULT = [V(P) – V(N) ] * GAIN/REFERENCE * 2(RESOLUTION - m) where V(P) is the voltage at input P V(N) is the voltage at input N GAIN is the selected gain setting m is the mode setting. Use m=0 if CONFIG.MODE=SE, or m=1 if CONFIG.MODE=Diff REFERENCE is the selected reference voltage The result generated by the ADC will deviate from the expected due DC errors like offset, gain, differential non-linearity (DNL), and integral non-linearity (INL). See Electrical specification for details on these parameters. The result can also vary due to AC errors like non-linearities in the GAIN block, settling errors 4418_1315 v2.0 199 Peripherals due to high source impedance and sampling jitter. For battery measurement, the DC errors are most noticeable. The ADC has a wide selection of gains controlled in the GAIN field of the CH[n].CONFIG register. If CH[n].CONFIG.REFSEL=0, the input range of the ADC core is nominally ±0.6 V differential and the input must be scaled accordingly. The ADC has a temperature dependent offset. If the ADC is to operate over a large temperature range, we recommend running CALIBRATEOFFSET at regular intervals. The CALIBRATEDONE event will be fired when the calibration has been completed. Note that the DONE and RESULTDONE events will also be generated. 6.12.3 Analog inputs and channels Up to eight analog input channels, CH[n](n=0..7), can be configured. Any one of the available channels can be enabled for the ADC to operate in one-shot mode. If more than one CH[n] is configured, the ADC enters scan mode. An analog input is selected as a positive converter input if CH[n].PSELP is set, setting CH[n].PSELP also enables the particular channel. An analog input is selected as a negative converter input if CH[n].PSELN is set. The CH[n].PSELN register will have no effect unless differential mode is enabled, see MODE field in CH[n].CONFIG register. If more than one of the CH[n].PSELP registers is set, the device enters scan mode. Input selections in scan mode are controlled by the CH[n].PSELP and CH[n].PSELN registers, where CH[n].PSELN is only used if the particular scan channel is specified as differential, see MODE field in CH[n].CONFIG register. 6.12.4 Operation modes The ADC input configuration supports one-shot mode, continuous mode and scan mode. Note: Scan mode and oversampling cannot be combined. The ADC indicates a single ongoing conversion via the register STATUS on page 219. During scan mode, oversampling, or continuous modes, more than a single conversion take place in the ADC. As consequence, the value reflected in STATUS register will toggle at the end of each single conversion. 6.12.4.1 One-shot mode One-shot operation is configured by enabling only one of the available channels defined by CH[n].PSELP, CH[n].PSELN, and CH[n].CONFIG registers. Upon a SAMPLE task, the ADC starts to sample the input voltage. The CH[n].CONFIG.TACQ controls the acquisition time. A DONE event signals that one sample has been taken. In this mode, the RESULTDONE event has the same meaning as DONE when no oversampling takes place. Note that both events may occur before the actual value has been transferred into RAM by EasyDMA. For more information, see EasyDMA on page 202. 6.12.4.2 Continuous mode Continuous sampling can be achieved by using the internal timer in the ADC, or triggering the SAMPLE task from one of the general purpose timers through the PPI system. Care shall be taken to ensure that the sample rate fulfils the following criteria, depending on how many channels are active: fSAMPLE < 1/(tACQ + tconv) 4418_1315 v2.0 200 Peripherals The SAMPLERATE register can be used as a local timer instead of triggering individual SAMPLE tasks. When SAMPLERATE.MODE is set to Timers, it is sufficient to trigger SAMPLE task only once in order to start the SAADC and triggering the STOP task will stop sampling. The SAMPLERATE.CC field controls the sample rate. The SAMPLERATE timer mode cannot be combined with SCAN mode, and only one channel can be enabled in this mode. A DONE event signals that one sample has been taken. In this mode, the RESULTDONE event has the same meaning as DONE when no oversampling takes place. Note that both events may occur before the actual value has been transferred into RAM by EasyDMA. 6.12.4.3 Oversampling An accumulator in the ADC can be used to average noise on the analog input. In general, oversampling improves the signal-to-noise ratio (SNR). Oversampling, however, does not improve the integral nonlinearity (INL), or differential non-linearity (DNL). Oversampling and scan should not be combined, since oversampling and scan will average over input channels. The accumulator is controlled in the OVERSAMPLE register. The SAMPLE task must be set 2OVERSAMPLE number of times before the result is written to RAM. This can be achieved by: • Configuring a fixed sampling rate using the local timer or a general purpose timer and the PPI system to trigger a SAMPLE task • Triggering SAMPLE 2OVERSAMPLE times from software • Enabling BURST mode CH[n].CONFIG.BURST can be enabled to avoid setting SAMPLE task 2OVERSAMPLE times. With BURST = 1 the ADC will sample the input 2OVERSAMPLE times as fast as it can (actual timing: = number of channels enabled. For more information about the scan mode, see Scan mode on page 201. 6.12.6 Resistor ladder The ADC has an internal resistor string for positive and negative input. See Resistor ladder for positive input (negative input is equivalent, using RESN instead of RESP) on page 204. The resistors are controlled in the CH[n].CONFIG.RESP and CH[n].CONFIG.RESN registers. 4418_1315 v2.0 203 Peripherals RESP = Pullup R Output Input R RESP = Pulldown Figure 69: Resistor ladder for positive input (negative input is equivalent, using RESN instead of RESP) 6.12.7 Reference The ADC can use two different references, controlled in the REFSEL field of the CH[n].CONFIG register. These are: • Internal reference • VDD_GPIO as reference The internal reference results in an input range of ±0.6 V on the ADC core. VDD_GPIO as reference results in an input range of ±VDD_GPIO/4 on the ADC core. The gain block can be used to change the effective input range of the ADC. Input range = (+- 0.6 V or +-VDD_GPIO/4)/Gain For example, choosing VDD_GPIO as reference, single ended input (grounded negative input), and a gain of 1/4 the input range will be: Input range = (VDD_GPIO/4)/(1/4) = VDD_GPIO With internal reference, single ended input (grounded negative input), and a gain of 1/6 the input range will be: Input range = (0.6 V)/(1/6) = 3.6 V The AIN0-AIN7 inputs cannot exceed VDD_GPIO, or be lower than VSS. 6.12.8 Acquisition time To sample the input voltage, the ADC connects a capacitor to the input. For illustration, see Simplified ADC sample network on page 205. The acquisition time indicates how long the capacitor is connected, see TACQ field in CH[n].CONFIG register. The required acquisition time depends on the source (Rsource) resistance. For high source resistance the acquisition time should be increased, see Acquisition time on page 205. 4418_1315 v2.0 204 Peripherals ADC Rsource TACQ Figure 70: Simplified ADC sample network TACQ [µs] Maximum source resistance [kOhm] 3 10 5 40 10 100 15 200 20 400 40 800 Table 67: Acquisition time 6.12.9 Limits event monitoring A channel can be event monitored by configuring limit register CH[n].LIMIT. If the conversion result is higher than the defined high limit, or lower than the defined low limit, the appropriate event will get fired. VIN CH[n].LIMIT.HIGH CH[n].LIMIT.LOW t EVENTS_CH[n].LIMITL EVENTS_CH[n].LIMITH EVENTS_CH[n].LIMITH EVENTS_CH[n].LIMITH events Figure 71: Example of limits monitoring on channel 'n' 4418_1315 v2.0 205 Peripherals Note that when setting the limits, CH[n].LIMIT.HIGH shall always be higher than or equal to CH[n].LIMIT.LOW . In other words, an event can be fired only when the input signal has been sampled outside of the defined limits. It is not possible to fire an event when the input signal is inside a defined range by swapping high and low limits. The comparison to limits always takes place, there is no need to enable it. If comparison is not required on a channel, the software shall simply ignore the related events. In that situation, the value of the limits registers is irrelevant, so it does not matter if CH[n].LIMIT.LOW is lower than CH[n].LIMIT.HIGH or not. 6.12.10 Registers Base address Peripheral Instance 0x5000E000 SAADC : S 0x4000E000 SAADC SAADC : NS Secure mapping DMA security Description US SA Analog to digital converter Configuration Table 68: Instances Register Offset Security Description TASKS_START 0x000 Start the ADC and prepare the result buffer in RAM TASKS_SAMPLE 0x004 Take one ADC sample, if scan is enabled all channels are sampled TASKS_STOP 0x008 Stop the ADC and terminate any on-going conversion TASKS_CALIBRATEOFFSET 0x00C Starts offset auto-calibration SUBSCRIBE_START 0x080 Subscribe configuration for task START SUBSCRIBE_SAMPLE 0x084 Subscribe configuration for task SAMPLE SUBSCRIBE_STOP 0x088 Subscribe configuration for task STOP SUBSCRIBE_CALIBRATEOFFSET 0x08C Subscribe configuration for task CALIBRATEOFFSET EVENTS_STARTED 0x100 The ADC has started EVENTS_END 0x104 The ADC has filled up the Result buffer EVENTS_DONE 0x108 A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. EVENTS_RESULTDONE 0x10C A result is ready to get transferred to RAM. EVENTS_CALIBRATEDONE 0x110 Calibration is complete EVENTS_STOPPED 0x114 The ADC has stopped EVENTS_CH[n].LIMITH 0x118 Last results is equal or above CH[n].LIMIT.HIGH EVENTS_CH[n].LIMITL 0x11C Last results is equal or below CH[n].LIMIT.LOW PUBLISH_STARTED 0x180 Publish configuration for event STARTED PUBLISH_END 0x184 Publish configuration for event END PUBLISH_DONE 0x188 Publish configuration for event DONE PUBLISH_RESULTDONE 0x18C Publish configuration for event RESULTDONE PUBLISH_CALIBRATEDONE 0x190 Publish configuration for event CALIBRATEDONE PUBLISH_STOPPED 0x194 Publish configuration for event STOPPED PUBLISH_CH[n].LIMITH 0x198 Publish configuration for event CH[n].LIMITH PUBLISH_CH[n].LIMITL 0x19C Publish configuration for event CH[n].LIMITL INTEN 0x300 Enable or disable interrupt INTENSET 0x304 Enable interrupt INTENCLR 0x308 Disable interrupt STATUS 0x400 Status ENABLE 0x500 Enable or disable ADC CH[n].PSELP 0x510 Input positive pin selection for CH[n] CH[n].PSELN 0x514 Input negative pin selection for CH[n] CH[n].CONFIG 0x518 Input configuration for CH[n] CH[n].LIMIT 0x51C High/low limits for event monitoring a channel RESOLUTION 0x5F0 Resolution configuration 4418_1315 v2.0 206 Peripherals Register Offset OVERSAMPLE 0x5F4 Security Description Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. SAMPLERATE 0x5F8 Controls normal or continuous sample rate RESULT.PTR 0x62C Data pointer RESULT.MAXCNT 0x630 Maximum number of buffer words to transfer RESULT.AMOUNT 0x634 Number of buffer words transferred since last START Table 69: Register overview 6.12.10.1 TASKS_START Address offset: 0x000 Start the ADC and prepare the result buffer in RAM Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_START 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Start the ADC and prepare the result buffer in RAM Trigger 1 Trigger task 6.12.10.2 TASKS_SAMPLE Address offset: 0x004 Take one ADC sample, if scan is enabled all channels are sampled Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_SAMPLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description Take one ADC sample, if scan is enabled all channels are sampled Trigger task 6.12.10.3 TASKS_STOP Address offset: 0x008 Stop the ADC and terminate any on-going conversion Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A W TASKS_STOP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Trigger 1 Description Stop the ADC and terminate any on-going conversion Trigger task 6.12.10.4 TASKS_CALIBRATEOFFSET Address offset: 0x00C Starts offset auto-calibration 4418_1315 v2.0 207 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A W TASKS_CALIBRATEOFFSET Value ID Trigger Value Description Starts offset auto-calibration 1 Trigger task 6.12.10.5 SUBSCRIBE_START Address offset: 0x080 Subscribe configuration for task START Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that task START will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.12.10.6 SUBSCRIBE_SAMPLE Address offset: 0x084 Subscribe configuration for task SAMPLE Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that task SAMPLE will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.12.10.7 SUBSCRIBE_STOP Address offset: 0x088 Subscribe configuration for task STOP Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that task STOP will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.12.10.8 SUBSCRIBE_CALIBRATEOFFSET Address offset: 0x08C 4418_1315 v2.0 208 Peripherals Subscribe configuration for task CALIBRATEOFFSET Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that task CALIBRATEOFFSET will subscribe to Disabled 0 Disable subscription Enabled 1 Enable subscription 6.12.10.9 EVENTS_STARTED Address offset: 0x100 The ADC has started Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_STARTED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated The ADC has started 6.12.10.10 EVENTS_END Address offset: 0x104 The ADC has filled up the Result buffer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_END 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated The ADC has filled up the Result buffer 6.12.10.11 EVENTS_DONE Address offset: 0x108 A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. 4418_1315 v2.0 209 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_DONE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM. NotGenerated 0 Event not generated Generated 1 Event generated 6.12.10.12 EVENTS_RESULTDONE Address offset: 0x10C A result is ready to get transferred to RAM. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_RESULTDONE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated A result is ready to get transferred to RAM. 6.12.10.13 EVENTS_CALIBRATEDONE Address offset: 0x110 Calibration is complete Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID A RW EVENTS_CALIBRATEDONE Value Description Calibration is complete NotGenerated 0 Event not generated Generated 1 Event generated 6.12.10.14 EVENTS_STOPPED Address offset: 0x114 The ADC has stopped Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW EVENTS_STOPPED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NotGenerated 0 Event not generated Generated 1 Event generated The ADC has stopped 6.12.10.15 EVENTS_CH[n].LIMITH (n=0..7) Address offset: 0x118 + (n × 0x8) 4418_1315 v2.0 210 Peripherals Last results is equal or above CH[n].LIMIT.HIGH Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW LIMITH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Last results is equal or above CH[n].LIMIT.HIGH NotGenerated 0 Event not generated Generated 1 Event generated 6.12.10.16 EVENTS_CH[n].LIMITL (n=0..7) Address offset: 0x11C + (n × 0x8) Last results is equal or below CH[n].LIMIT.LOW Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW LIMITL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Last results is equal or below CH[n].LIMIT.LOW NotGenerated 0 Event not generated Generated 1 Event generated 6.12.10.17 PUBLISH_STARTED Address offset: 0x180 Publish configuration for event STARTED Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event STARTED will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.12.10.18 PUBLISH_END Address offset: 0x184 Publish configuration for event END Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN 4418_1315 v2.0 A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event END will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 211 Peripherals 6.12.10.19 PUBLISH_DONE Address offset: 0x188 Publish configuration for event DONE Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that event DONE will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.12.10.20 PUBLISH_RESULTDONE Address offset: 0x18C Publish configuration for event RESULTDONE Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that event RESULTDONE will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.12.10.21 PUBLISH_CALIBRATEDONE Address offset: 0x190 Publish configuration for event CALIBRATEDONE Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event CALIBRATEDONE will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.12.10.22 PUBLISH_STOPPED Address offset: 0x194 Publish configuration for event STOPPED 4418_1315 v2.0 212 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW CHIDX B RW EN Value ID A A A A A A A A Value Description [255..0] DPPI channel that event STOPPED will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.12.10.23 PUBLISH_CH[n].LIMITH (n=0..7) Address offset: 0x198 + (n × 0x8) Publish configuration for event CH[n].LIMITH Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event CH[n].LIMITH will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.12.10.24 PUBLISH_CH[n].LIMITL (n=0..7) Address offset: 0x19C + (n × 0x8) Publish configuration for event CH[n].LIMITL Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CHIDX B RW EN A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [255..0] DPPI channel that event CH[n].LIMITL will publish to Disabled 0 Disable publishing Enabled 1 Enable publishing 6.12.10.25 INTEN Address offset: 0x300 Enable or disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 ID R/W Field A RW STARTED B RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Enable or disable interrupt for event STARTED END 4418_1315 v2.0 Enable or disable interrupt for event END 213 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 ID R/W Field C RW DONE D E F G H I J K L M N O P Q R S RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Enable or disable interrupt for event DONE RESULTDONE Enable or disable interrupt for event RESULTDONE CALIBRATEDONE Enable or disable interrupt for event CALIBRATEDONE STOPPED Enable or disable interrupt for event STOPPED Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable CH0LIMITH Enable or disable interrupt for event CH0LIMITH CH0LIMITL Enable or disable interrupt for event CH0LIMITL CH1LIMITH Enable or disable interrupt for event CH1LIMITH CH1LIMITL Enable or disable interrupt for event CH1LIMITL Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable CH2LIMITH Enable or disable interrupt for event CH2LIMITH CH2LIMITL Enable or disable interrupt for event CH2LIMITL CH3LIMITH Enable or disable interrupt for event CH3LIMITH CH3LIMITL Enable or disable interrupt for event CH3LIMITL Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable CH4LIMITH Enable or disable interrupt for event CH4LIMITH CH4LIMITL Enable or disable interrupt for event CH4LIMITL CH5LIMITH Enable or disable interrupt for event CH5LIMITH CH5LIMITL Enable or disable interrupt for event CH5LIMITL Disabled 0 Disable Enabled 1 Enable Disabled 0 CH6LIMITH 4418_1315 v2.0 Enable or disable interrupt for event CH6LIMITH Disable 214 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 ID T U V R/W RW RW RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enabled 1 Enable CH6LIMITL Enable or disable interrupt for event CH6LIMITL Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable Disabled 0 Disable Enabled 1 Enable CH7LIMITH Enable or disable interrupt for event CH7LIMITH CH7LIMITL Enable or disable interrupt for event CH7LIMITL 6.12.10.26 INTENSET Address offset: 0x304 Enable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 ID R/W Field A RW STARTED B C D E F G H RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to enable interrupt for event STARTED END Write '1' to enable interrupt for event END DONE Write '1' to enable interrupt for event DONE RESULTDONE Write '1' to enable interrupt for event RESULTDONE CALIBRATEDONE Write '1' to enable interrupt for event CALIBRATEDONE STOPPED Write '1' to enable interrupt for event STOPPED CH0LIMITH Write '1' to enable interrupt for event CH0LIMITH CH0LIMITL 4418_1315 v2.0 Write '1' to enable interrupt for event CH0LIMITL 215 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 ID I J K L M N O P Q R S T R/W RW RW RW RW RW RW RW RW RW RW RW RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Set 1 Enable Disabled 0 Read: Disabled CH1LIMITH Write '1' to enable interrupt for event CH1LIMITH CH1LIMITL Write '1' to enable interrupt for event CH1LIMITL CH2LIMITH Write '1' to enable interrupt for event CH2LIMITH CH2LIMITL Write '1' to enable interrupt for event CH2LIMITL CH3LIMITH Write '1' to enable interrupt for event CH3LIMITH CH3LIMITL Write '1' to enable interrupt for event CH3LIMITL CH4LIMITH Write '1' to enable interrupt for event CH4LIMITH CH4LIMITL Write '1' to enable interrupt for event CH4LIMITL CH5LIMITH Write '1' to enable interrupt for event CH5LIMITH CH5LIMITL Write '1' to enable interrupt for event CH5LIMITL CH6LIMITH Write '1' to enable interrupt for event CH6LIMITH CH6LIMITL 4418_1315 v2.0 Write '1' to enable interrupt for event CH6LIMITL 216 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 ID U V R/W RW RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Enabled 1 Read: Enabled CH7LIMITH Write '1' to enable interrupt for event CH7LIMITH Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled CH7LIMITL Write '1' to enable interrupt for event CH7LIMITL Set 1 Enable Disabled 0 Read: Disabled Enabled 1 Read: Enabled 6.12.10.27 INTENCLR Address offset: 0x308 Disable interrupt Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 ID R/W Field A RW STARTED B C D E F G H RW RW RW RW RW RW RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Write '1' to disable interrupt for event STARTED END Write '1' to disable interrupt for event END DONE Write '1' to disable interrupt for event DONE RESULTDONE Write '1' to disable interrupt for event RESULTDONE CALIBRATEDONE Write '1' to disable interrupt for event CALIBRATEDONE STOPPED Write '1' to disable interrupt for event STOPPED CH0LIMITH Write '1' to disable interrupt for event CH0LIMITH CH0LIMITL 4418_1315 v2.0 Write '1' to disable interrupt for event CH0LIMITL Disable 217 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 ID I J K L M N O P Q R S T R/W RW RW RW RW RW RW RW RW RW RW RW RW Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled CH1LIMITH Write '1' to disable interrupt for event CH1LIMITH CH1LIMITL Write '1' to disable interrupt for event CH1LIMITL CH2LIMITH Write '1' to disable interrupt for event CH2LIMITH CH2LIMITL Write '1' to disable interrupt for event CH2LIMITL CH3LIMITH Write '1' to disable interrupt for event CH3LIMITH CH3LIMITL Write '1' to disable interrupt for event CH3LIMITL CH4LIMITH Write '1' to disable interrupt for event CH4LIMITH CH4LIMITL Write '1' to disable interrupt for event CH4LIMITL CH5LIMITH Write '1' to disable interrupt for event CH5LIMITH CH5LIMITL Write '1' to disable interrupt for event CH5LIMITL CH6LIMITH Write '1' to disable interrupt for event CH6LIMITH CH6LIMITL 4418_1315 v2.0 Write '1' to disable interrupt for event CH6LIMITL 218 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID V U T S R Q P O N M L K J I H G F E D C B A Reset 0x00000000 ID R/W Field U RW CH7LIMITH V RW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Clear 1 Disable Disabled 0 Read: Disabled Enabled 1 Read: Enabled Write '1' to disable interrupt for event CH7LIMITH CH7LIMITL Write '1' to disable interrupt for event CH7LIMITL 6.12.10.28 STATUS Address offset: 0x400 Status Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A R STATUS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Status Ready 0 ADC is ready. No on-going conversion. Busy 1 ADC is busy. Single conversion in progress. 6.12.10.29 ENABLE Address offset: 0x500 Enable or disable ADC Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A Reset 0x00000000 ID R/W Field A RW ENABLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Disabled 0 Disable ADC Enabled 1 Enable ADC Enable or disable ADC When enabled, the ADC will acquire access to the analog input pins specified in the CH[n].PSELP and CH[n].PSELN registers. 6.12.10.30 CH[n].PSELP (n=0..7) Address offset: 0x510 + (n × 0x10) Input positive pin selection for CH[n] Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A Reset 0x00000000 ID R/W Field A RW PSELP 4418_1315 v2.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Analog positive input channel 219 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A Reset 0x00000000 ID R/W Field 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NC 0 Not connected AnalogInput0 1 AIN0 AnalogInput1 2 AIN1 AnalogInput2 3 AIN2 AnalogInput3 4 AIN3 AnalogInput4 5 AIN4 AnalogInput5 6 AIN5 AnalogInput6 7 AIN6 AnalogInput7 8 AIN7 VDDGPIO 9 VDD_GPIO 6.12.10.31 CH[n].PSELN (n=0..7) Address offset: 0x514 + (n × 0x10) Input negative pin selection for CH[n] Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A Reset 0x00000000 ID R/W Field A RW PSELN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description NC 0 Not connected AnalogInput0 1 AIN0 AnalogInput1 2 AIN1 AnalogInput2 3 AIN2 AnalogInput3 4 AIN3 AnalogInput4 5 AIN4 AnalogInput5 6 AIN5 AnalogInput6 7 AIN6 AnalogInput7 8 AIN7 VDD_GPIO 9 VDD_GPIO Analog negative input, enables differential channel 6.12.10.32 CH[n].CONFIG (n=0..7) Address offset: 0x518 + (n × 0x10) Input configuration for CH[n] Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID G Reset 0x00020000 ID R/W Field A RW RESP B RW E E E D C C C B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Bypass 0 Bypass resistor ladder Pulldown 1 Pull-down to GND Pullup 2 Pull-up to VDD_GPIO VDD1_2 3 Set input at VDD_GPIO/2 Bypass 0 Bypass resistor ladder Pulldown 1 Pull-down to GND Positive channel resistor control RESN 4418_1315 v2.0 F Negative channel resistor control 220 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID G Reset 0x00020000 ID C D E F R/W RW RW RW RW Field F E E E D C C C B B A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Pullup 2 Pull-up to VDD_GPIO VDD1_2 3 Set input at VDD_GPIO/2 Gain1_6 0 1/6 Gain1_5 1 1/5 Gain1_4 2 1/4 Gain1_3 3 1/3 Gain1_2 4 1/2 Gain1 5 1 Gain2 6 2 Gain4 7 4 Internal 0 Internal reference (0.6 V) VDD1_4 1 VDD_GPIO/4 as reference 3us 0 3 us 5us 1 5 us 10us 2 10 us 15us 3 15 us 20us 4 20 us 40us 5 40 us GAIN Gain control REFSEL Reference control TACQ Acquisition time, the time the ADC uses to sample the input voltage MODE Enable differential mode SE 0 Diff 1 Single ended, PSELN will be ignored, negative input to ADC shorted to GND G RW Differential BURST Enable burst mode Disabled 0 Burst mode is disabled (normal operation) Enabled 1 Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. 6.12.10.33 CH[n].LIMIT (n=0..7) Address offset: 0x51C + (n × 0x10) High/low limits for event monitoring a channel Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B B B B B B B B B B B B B B B B A A A A A A A A A A A A A A A A Reset 0x7FFF8000 ID R/W Field A RW B RW 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description LOW [-32768 to +32767] Low level limit HIGH [-32768 to +32767] High level limit 6.12.10.34 RESOLUTION Address offset: 0x5F0 Resolution configuration 4418_1315 v2.0 221 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A Reset 0x00000001 ID R/W Field A RW VAL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Value ID Value Description Set the resolution 8bit 0 8 bit 10bit 1 10 bit 12bit 2 12 bit 14bit 3 14 bit 6.12.10.35 OVERSAMPLE Address offset: 0x5F4 Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A Reset 0x00000000 ID R/W Field A RW OVERSAMPLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description Bypass 0 Bypass oversampling Over2x 1 Oversample 2x Over4x 2 Oversample 4x Over8x 3 Oversample 8x Over16x 4 Oversample 16x Over32x 5 Oversample 32x Over64x 6 Oversample 64x Over128x 7 Oversample 128x Over256x 8 Oversample 256x Oversample control 6.12.10.36 SAMPLERATE Address offset: 0x5F8 Controls normal or continuous sample rate Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID B Reset 0x00000000 ID R/W Field A RW CC B RW MODE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value ID Value Description [80..2047] Capture and compare value. Sample rate is 16 MHz/CC Select mode for sample rate control Task 0 Rate is controlled from SAMPLE task Timers 1 Rate is controlled from local timer (use CC to control the rate) 6.12.10.37 RESULT.PTR Address offset: 0x62C Data pointer 4418_1315 v2.0 A A A A A A A A A A A 222 Peripherals Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW PTR Value ID Value Description Data pointer Note: See the memory chapter for details about which memories are available for EasyDMA. 6.12.10.38 RESULT.MAXCNT Address offset: 0x630 Maximum number of buffer words to transfer Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field A RW MAXCNT Value ID Value Description Maximum number of buffer words to transfer 6.12.10.39 RESULT.AMOUNT Address offset: 0x634 Number of buffer words transferred since last START Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID A A A A A A A A A A A A A A A Reset 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ID R/W Field Value ID A R AMOUNT Value Description Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. 6.12.11 Electrical specification 6.12.11.1 SAADC Electrical Specification Symbol Description Min. Typ. DNL10 Differential non-linearity, 10-bit resolution -0.95
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