ES8374

ES8374 FEATURES Low Power Mono Audio CODEC DAC • • System • • • • • • • • • High performance and low power multibit delta-sigma audio ADC and DAC I2S/PCM master or slave serial data port Two pairs of analog input with differential input option Mono analog output 256/384Fs, USB 12/24 MHz, fractional PLL for wide range of system clocks Standard audio clock output Sophisticated analog input and output routing, mixing and gain GPIO I2C interface • • • • Low Power • • • ADC • • • • • • • 24-bit, 8 to 96 kHz sampling frequency 95 dB signal to noise ratio, -85 dB THD+N 1.25W@8Ω/5V or 1.8W@4Ω/4.2V mono class D speaker driver Dynamic range compression Headphone and external mic detection Pop and click noise suppression 3.3V to 5V operation 32 mW playback; 42 mW playback and record Low standby current APPLICATIONS 24-bit, 8 to 96 kHz sampling frequency 95 dB signal to noise ratio, -85 dB THD+N Low noise pre-amplifier Noise reduction filters Auto level control (ALC) and noise gate Support analog and digital microphone Microphone bias • • • • Car DV IP Camera DVR, NVR Surveillance ORDERING INFORMATION ES8374 -40°C ~ +85°C QFN-28 1 Everest Semiconductor Confidential ES8374 1. BLOCK DIAGRAM LIN2 LIN1 PGA 2 PGA RIN1 RIN2 DSDIN ASDOUT SCLK DLRCK CDATA CCLK CE IC GPIO1 GPIO2 MCLK Clock Mgr/PLL GPIO I S/PCM Mono ADC 2 ADC ALC DAC DRC Noise Filter Mixer Mono DAC HP Driver MONOOUT LIN2 LIN1 Class D Driver Analog Reference Power Supply MICBIAS ADCVREF DACVREF VMID DVDD PVDD DGND AVDD AGND SPKVDD SPKGND Revision 9 Mic Bias SPKP SPKN 2 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8374 RIN2 LIN2 RIN1 LIN1/DMIC_SDA GPIO1 CE CDATA 2. PIN OUT AND DESCRIPTION 22 23 24 25 26 27 28 CCLK MCLK DGND GPIO2 PVDD DVDD SCLK 1 2 3 4 5 6 7 ES8374 21 20 19 18 17 16 15 MICBIAS VMID ADCVREF DACVREF AGND AVDD MONOOUT 14 13 12 11 10 9 8 SPKP SPKVDD SPKGND SPKN DSDIN LRCK ASDOUT NAME MCLK CDATA CCLK CE GPIO1 GPIO2 I/O DI DIO DI DI DIO DIO DESCRIPTION Master clock I2C data I2C clock I2C address GPIO (digital mic clock, jack detect, PLL out, interrupt) GPIO (PLL out, interrupt) ASDOUT DSDIN LRCK SCLK DO DI DIO DIO I2S/PCM serial data out I2S/PCM serial data in I2S/PCM left and right clock I2S/PCM bit clock LIN1/DMIC_SDA RIN1 LIN2 RIN2 AI AI AI AI Left analog input or digital mic data Right analog input Left analog input Right analog input MONOOUT SPKP SPKN AO AO AO Mono output Positive speaker out Negative speaker out MICBIAS ADCVRP DACVRP VMID Mic bias ADC reference filtering DAC reference filtering Common mode filtering DVDD PVDD DGND AVDD AGND SPKVDD SPKGND Digital core power supply Digital IO power supply Digital ground Analog power supply Analog ground Speaker driver power supply Speaker driver ground Revision 9 3 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8374 DCLK DMIC DOUT 3. TYPICAL APPLICATION CIRCUIT Mic2P 1uF Mic2N 1uF MICBIAS PVDD DVDD 3 29 DGND PGND 23 RIN2 22 24 LIN2 26 25 RIN1 AVDD 16 1uF AGND 17 21 1uF MICBIAS Everest VMID ES8374 SPKLP 5 6 LIN1/DMIC-SDA MCLK BCLK ASDOUT DLRCK ADSIN DMICLK/GPIO1 2 7 8 9 10 SPKLN * * 0.1uF 0.1uF CE CDATA CCLK SPKGND PVDD DVDD 27 28 1 SPKVDD CPU/DSP PLLout/GPIO2 4 1uF AGND * * * 20 ADCVREF 19 DACVREF 18 MONOOUT 15 * * AVDD AGND MICBIAS 1uF AGND 1uF AGND 1uF AGND MOUT_OUT 14 11 13 12 AGND AGND AGND Vbat * AGND 1uF AGND GND(SYS) 0R Speaker AGND In the layout, chip is treated as an analog device For the best performance,decoupling and filtering capacitors should be located as close to the device package as possible Additional parallel capacitors(typically 0.1 μF) can be used, larger value capacitors(typically 10 μF) would also help * 4. CLOCK MODES AND SAMPLING FREQUENCIES The device supports three types of clocking: standard audio clocks (256Fs, 384Fs, 512Fs, etc), USB clocks (12/24 MHz), and an on-chip 22-bit fractional PLL clock. According to the serial audio data sampling frequency (Fs), the device can work in two speed modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz. The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the system clock with specific rates. In master mode, LRCK and SCLK are derived internally from device master clock. 5. MICRO-CONTROLLER CONFIGURATION INTERFACE The device supports standard I2C micro-controller configuration interface. External microcontroller can completely configure the device through writing to internal configuration registers. I2C interface is a bi-directional serial bus that uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. The timing diagram for data transfer of this interface is given in Figure 1. Data are transmitted synchronously to SCL clock on the SDA line on a byte-by-byte basis. Each bit in a byte is sampled during SCL high with MSB bit being transmitted firstly. Each transferred Revision 9 4 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8374 byte is followed by an acknowledge bit from receiver to pull the SDA low. The transfer rate of this interface can be up to 400 kbps. Figure 1 Data Transfer for I2C Interface A master controller initiates the transmission by sending a “start” signal, which is defined as a high-to-low transition at SDA while SCL is high. The first byte transferred is the slave address. It is a seven-bit chip address followed by a RW bit. The chip address must be 001000x, where x equals AD0. The RW bit indicates the slave data transfer direction. Once an acknowledge bit is received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by the RW bit. The master can terminate the communication by generating a “stop” signal, which is defined as a low-to-high transition at SDA while SCL is high. In I2C interface mode, the registers can be written and read. The formats of “write” and “read” instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the register. Table 1 Write Data to Register in I2C Interface Mode Chip Address 001000 AD0 R/W 0 ACK Register Address RAM ACK Data to be written DATA Table 2 Read Data from Register in I2C Interface Mode Chip Address 001000 Chip Address 001000 AD0 AD0 R/W 0 R/W 1 ACK ACK Register Address RAM Data to be read Data 6. DIGITAL AUDIO INTERFACE The device provides many formats of serial audio data interface to the input of the DAC or output from the ADC through LRCK, BCLK (SCLK) and DACDAT/ADCDAT pins. These formats are I2S, left justified, right justified, DSP/PCM and TDM mode. DAC input DACDAT is sampled by the Revision 9 5 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8374 device on the rising edge of SCLK. ADC data is out at ADCDAT on the falling edge of SCLK. The relationship of SDATA (DACDAT/ADCDAT), SCLK and LRCK with these formats are shown through Figure 2 to Figure 6. 1 SCLK 1 SCLK SDATA 1 2 3 n-2 n-1 MSB n 1 LSB MSB 2 3 n-2 n-1 n LSB SCLK LEFT CHANNEL LRCK RIGHT CHANNEL Figure 2 I2S Serial Audio Data Format Up To 24-bit SDATA 1 2 3 n-2 n-1 MSB n 1 LSB MSB 2 3 n-2 n-1 n LSB SCLK LRCK LEFT CHANNEL RIGHT CHANNEL Figure 3 Left Justified Serial Audio Data Format Up To 24-bit Figure 4 DSP/PCM Mode A Figure 5 DSP/PCM Mode B Revision 9 6 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8374 7. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Continuous operation at or beyond these conditions may permanently damage the device. PARAMETER Analog Supply Voltage Level Digital Supply Voltage Level Input Voltage Range Operating Temperature Range Storage Temperature MIN -0.3V -0.3V DGND-0.3V -40°C -65°C MAX +5.5V +5.5V PVDD+0.3V +85°C +150°C RECOMMENDED OPERATING CONDITIONS PARAMETER AVDD SPKVDD 4Ω Speaker 8Ω Speaker DVDD PVDD (DVDD - input high level < 2V) MIN 3 TYP 3.3 MAX 5.5 3 3 3 1.6 4.2 5 3.3 3.3 5 5.5 5.5 5.5 UNIT V V V V ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: AVDD=3.3V, DVDD=3.3V, AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz or 96 KHz, MCLK/LRCK=256. PARAMETER ADC Performance Signal to Noise ratio (A-weigh) THD+N Gain Error Filter Frequency Response – Single Speed Passband Stopband Passband Ripple Stopband Attenuation Filter Frequency Response – Double Speed Passband Stopband Passband Ripple Stopband Attenuation Analog Input Full Scale Input Level Input Impedance Revision 9 MIN TYP MAX UNIT 85 -88 95 -85 98 -75 ±5 dB dB % 0.4535 Fs Fs dB dB 0 0.5465 50 0 0.5833 50 ±0.05 0.4167 ±0.005 Fs Fs dB dB Vrms KΩ 7 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8374 DAC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: AVDD=3.3V, DVDD=3.3V, AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz or 96 KHz, MCLK/LRCK=256. PARAMETER DAC Performance Signal to Noise ratio (A-weigh) THD+N Filter Frequency Response – Single Speed Passband Stopband Passband Ripple Stopband Attenuation Filter Frequency Response – Double Speed Passband Stopband Passband Ripple Stopband Attenuation Analog Output Full Scale Output Level MIN TYP MAX UNIT 83 -88 95 -85 98 -75 dB dB 0.4535 Fs Fs dB dB 0 0.5465 ±0.05 40 0 0.5833 0.4167 ±0.005 40 Fs Fs dB dB Vrms POWER CONSUMPTION CHARACTERISTICS PARAMETER Normal Operation Mode DVDD=3.3V, PVDD=3.3V, AVDD=3.3V: Play back Play back and record Power Down Mode DVDD=3.3V, PVDD=3.3V, AVDD=3.3V MIN TYP MAX UNIT mW 32 42 50 uA SERIAL AUDIO PORT SWITCHING SPECIFICATIONS PARAMETER MCLK frequency MCLK duty cycle LRCK frequency LRCK duty cycle SCLK frequency SCLK pulse width low SCLK Pulse width high SCLK falling to LRCK edge SCLK falling to SDOUT valid SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time Revision 9 Symbol MIN 40 40 TSCLKL TSCLKH TSLR TSDO TSDIS TSDIH 15 15 –10 0 10 10 MAX 51.2 60 200 60 26 10 UNIT MHz % KHz % MHz ns ns ns ns ns ns 8 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8374 Figure 6 Serial Audio Port Timing I2C SWITCHING SPECIFICATIONS PARAMETER SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL Fall Time SCL Symbol FSCL TTWID TTWSTH TTWCL TTWCH TTWSTS TTWDH TTWDS TTWR TTWF MIN 1.3 0.6 1.3 0.4 0.6 100 MAX 400 900 300 300 UNIT KHz us us us us us ns ns ns ns SDA TTWSTS TTWSTH TTWCL SCL TTWDH TTWID TTWDS TTWCH S TTWF TTWR P S Figure 7 I2C Timing Revision 9 9 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8374 8. PACKAGE Revision 9 10 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com Everest Semiconductor Confidential ES8374 9. CORPORATE INFORMATION Everest Semiconductor Co., Ltd. 苏州工业园区金鸡湖大道 1355 号国际科技园, 邮编 215021 Email: info@everest-semi.com Revision 9 11 September 2018 Latest datasheet: www.everest-semi.com or info@everest-semi.com