SPI-NAND
GD5F1GQ5xExxG
GD5F1GQ5xExxG
DATASHEET
1G-bit 2K+128BPageSize with E Version
1
SPI-NAND
GD5F1GQ5xExxG
Contents
1
FEATURE ........................................................................................................................................................... 4
2
GENERAL DESCRIPTION ............................................................................................................................... 5
2.1
VALID PART NUMBERS ........................................................................................................................................ 6
2.2
CONNECTION DIAGRAM ..................................................................................................................................... 7
2.3
PIN DESCRIPTION ................................................................................................................................................ 8
2.4
BLOCK DIAGRAM ................................................................................................................................................ 8
3
MEMORY MAPPING ......................................................................................................................................... 9
4
ARRAY ORGANIZATION ............................................................................................................................... 10
5
DEVICE OPERATION ..................................................................................................................................... 11
5.1
SPI MODES.......................................................................................................................................................... 11
5.2
HOLD MODE ....................................................................................................................................................... 12
5.3
WRITE PROTECTION............................................................................................................................................... 12
5.4
POWER OFF TIMING .............................................................................................................................................. 13
6
COMMANDS DESCRIPTION ......................................................................................................................... 14
7
WRITE OPERATIONS .................................................................................................................................... 16
8
9
7.1
WRITE ENABLE (WREN) (06H) .............................................................................................................................. 16
7.2
WRITE DISABLE (WRDI) (04H) ............................................................................................................................... 16
READ OPERATIONS ...................................................................................................................................... 17
8.1
PAGE READ .......................................................................................................................................................... 17
8.2
PAGE READ TO CACHE (13H) .................................................................................................................................. 18
8.3
READ FROM CACHE (03H OR 0BH) .......................................................................................................................... 19
8.4
READ FROM CACHE X2 (3BH) ................................................................................................................................. 20
8.5
READ FROM CACHE X4 (6BH) ................................................................................................................................. 21
8.6
READ FROM CACHE DUAL IO (BBH) ........................................................................................................................ 22
8.7
READ FROM CACHE QUAD IO (EBH) ........................................................................................................................ 23
8.8
READ FROM CACHE QUAD I/O DTR (EEH) ............................................................................................................... 24
8.9
READ ID (9FH)..................................................................................................................................................... 25
8.10
READ UID ........................................................................................................................................................... 26
8.11
READ PARAMETER PAGE ......................................................................................................................................... 27
PROGRAM OPERATIONS ............................................................................................................................. 32
9.1
PAGE PROGRAM ................................................................................................................................................... 32
9.2
PROGRAM LOAD (PL) (02H) ................................................................................................................................... 33
9.3
PROGRAM LOAD X4 (PL X4) (32H) .......................................................................................................................... 34
9.4
PROGRAM EXECUTE (PE) (10H) .............................................................................................................................. 35
9.5
INTERNAL DATA MOVE ........................................................................................................................................... 36
9.6
PROGRAM LOAD RANDOM DATA (84H) .................................................................................................................... 36
9.7
PROGRAM LOAD RANDOM DATA X4 (C4H/34H) ........................................................................................................ 37
2
SPI-NAND
GD5F1GQ5xExxG
10 ERASE OPERATIONS ................................................................................................................................... 38
10.1
11
BLOCK ERASE (D8H) ............................................................................................................................................. 38
RESET OPERATIONS .................................................................................................................................... 39
11.1
SOFT RESET (FFH) ................................................................................................................................................ 39
11.2
ENABLE POWER ON RESET (66H) AND POWER ON RESET (99H) .................................................................................... 40
12 FEATURE OPERATIONS ............................................................................................................................... 41
12.1
GET FEATURES (0FH) AND SET FEATURES (1FH) ......................................................................................................... 41
12.2
STATUS REGISTER AND DRIVER REGISTER.................................................................................................................... 45
12.3
OTP REGION ........................................................................................................................................................ 46
12.4
ASSISTANT BAD BLOCK MANAGEMENT ...................................................................................................................... 47
12.5
BLOCK PROTECTION ............................................................................................................................................... 48
12.6
POWER LOCK DOWN PROTECTION............................................................................................................................ 49
12.7
INTERNAL ECC...................................................................................................................................................... 50
13 POWER ON TIMING ....................................................................................................................................... 52
14 ABSOLUTE MAXIMUM RATINGS ................................................................................................................ 53
15 CAPACITANCE MEASUREMENT CONDITIONS ........................................................................................ 54
16 DC CHARACTERISTIC .................................................................................................................................. 55
17 AC CHARACTERISTICS................................................................................................................................ 56
18 PERFORMANCE AND TIMING ..................................................................................................................... 57
19 ORDERING INFORMATION .......................................................................................................................... 59
20 PACKAGE INFORMATION ............................................................................................................................ 60
21 REVISION HISTORY....................................................................................................................................... 63
3
SPI-NAND
1
GD5F1GQ5xExxG
FEATURE
◆
1Gb SLC NAND Flash
Advanced security Features
◆
- 8K-Byte OTP Region
◆
Organization
- Internal ECC On (ECC_EN=1, default):
Program/Erase/Read Speed
◆
Page Size：2048-Byte+64-Byte
- Page Program time: 400us typical
- Internal ECC Off (ECC_EN=0):
- Block Erase time: 3ms typical
Page Size：2048-Byte+128-Byte
- Page read time: 60us maximum
◆
Standard, Dual, Quad SPI,DTR
◆
Low Power Consumption
- Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
- 30mA maximum active current
- Dual SPI: SCLK, CS#, SIO0, SIO1, WP#, HOLD#
- 50uA maximum standby current
- Quad SPI: SCLK, CS#, SIO0, SIO1, SIO2, SIO3
- DTR(Double Transfer Rate) Read : SCLK, CS#, SIO0,
◆
SIO1, SIO2, SIO3
◆
Enhanced access performance
- 2Kbyte cache for fast random read
High Speed Clock Frequency
◆
- 3.3V: 133MHz for fast read with 30pF load
Advanced Feature for NAND
- Factory good block0
- 1.8V: 104MHz for fast read with 30pF load
- 3.3V: Quad I/O Data transfer up to 532 Mbits/s
◆
- 1.8V: Quad I/O Data transfer up to 416 Mbits/s
Reliability
- P/E cycles with ECC: 100K
- Data retention: 10 Years
◆
Software/Hardware Write Protection
- Write protect all/portion of memory via software
◆
- Register protection with WP# Pin
- 4bits /528byte
- Power Lock Down Protection
◆
Internal ECC
Single Power Supply Voltage
- Full voltage range for 1.8V: 1.7V ~ 2.0V
- Full voltage range for 3.3V: 2.7V ~ 3.6V
Note: (1) ECC is on default, which can be disable by user.
4
SPI-NAND
2
GD5F1GQ5xExxG
GENERAL DESCRIPTION
SPI (Serial Peripheral Interface) NAND Flash provides an ultra-cost effective while high density non-volatile memory
storage solution for embedded systems, based on an industry-standard NAND Flash memory core. It is an attractive
alternative to SPI-NOR and standard parallel NAND Flash, with advanced features, Total pin count is 8, including VCC and
GND
• Density is 1Gb
• Superior write performance and cost per bit over SPI-NOR
• Significant low cost than parallel NAND
This low-pin-count NAND Flash memory follows the industry-standard serial peripheral interface, and always remains the
same pin out from one density to another. The command sets resemble common SPI-NOR command sets, modified to
handle NAND specific functions and added new features. GigaDevice SPI NAND is an easy-to-integrate NAND Flash
memory, with specified designed features to ease host management:
• User-selectable internal ECC. ECC parity is generated internally during a page program operation. When a page
is read to the cache register, the ECC parity is detected and corrects the errors when necessary. The 64-bytes spare
area is available even when internal ECC enabled. The device outputs corrected data and returns an ECC error status.
• Internal data move or copy back with internal ECC. The device can be easily refreshed and manage garbage
collection task, without need of shift in and out of data.
• Power on Read with internal ECC. The device will automatically read first page of fist block to cache after power
on, then host can directly read data from cache for easy boot. Also the data is promised correct by internal ECC when
ECC enabled.
It is programmed and read in page-based operations, and erased in block-based operations. Data is transferred to or from
the NAND Flash memory array, page by page, to a data register and a cache register. The cache register is closest to I/O
control circuits and acts as a data buffer for the I/O data; the data register is closest to the memory array and acts as a
data buffer for the NAND Flash memory array operation. The cache register functions as the buffer memory to enable page
and random data READ/WRITE and copy back operations. These devices also use a SPI status register that reports the
status of device operation.
5
SPI-NAND
GD5F1GQ5xExxG
2.1 VALID PART NUMBERS
Please contact GigaDevice regional sales for the latest product selection and available form factors
Product Number
Density
Voltage
Package Type
Temperature
WSON8(8*6mm)
-40℃ to 85℃
WSON8(6*5mm)
-40℃ to 85℃
GD5F1GQ5REBIG
TFBGA24(5*5 Ball Array)
-40℃ to 85℃
GD5F1GQ5UEYIG
WSON8(8*6mm)
-40℃ to 85℃
WSON8(6*5mm)
-40℃ to 85℃
GD5F1GQ5UEBIG
TFBGA24(5*5 Ball Array)
-40℃ to 85℃
GD5F1GQ5REYFG*
WSON8(8*6mm)
-40℃ to 85℃
WSON8(6*5mm)
-40℃ to 85℃
TFBGA24(5*5 Ball Array)
-40℃ to 85℃
WSON8(8*6mm)
-40℃ to 85℃
WSON8(6*5mm)
-40℃ to 85℃
GD5F1GQ5UEBFG*
TFBGA24(5*5 Ball Array)
-40℃ to 85℃
GD5F1GQ5REYJG
WSON8(8*6mm)
-40℃ to 105℃
WSON8(6*5mm)
-40℃ to 105℃
GD5F1GQ5REBJG
TFBGA24(5*5 Ball Array)
-40℃ to 105℃
GD5F1GQ5UEYJG
WSON8(8*6mm)
-40℃ to 105℃
WSON8(6*5mm)
-40℃ to 105℃
TFBGA24(5*5 Ball Array)
-40℃ to 105℃
GD5F1GQ5REYIG
GD5F1GQ5REWIG
1.7V to 2.0V
GD5F1GQ5UEWIG
2.7V to 3.6V
GD5F1GQ5REWFG*
GD5F1GQ5REBFG*
GD5F1GQ5UEYFG*
GD5F1GQ5UEWFG*
GD5F1GQ5REWJG
GD5F1GQ5UEWJG
1.7V to 2.0V
1Gbit
2.7V to 3.6V
1.7V to 2.0V
2.7V to 3.6V
GD5F1GQ5UEBJG
Note: (1) Industrial+: F grade has implemented additional test flows to ensure higher product quality than I grade.
6
SPI-NAND
GD5F1GQ5xExxG
2.2 CONNECTION DIAGRAM
Figure 2-1. Connect Diagram
CS#
1
8
VCC
SO/
SIO1
2
7
HOLD#/
SIO3
WP#/
SIO2
3
6
SCLK
VSS
4
5
SI/
SIO0
Top View
8–LEAD WSON
Top View
A2
A3
A4
A5
NC
NC
NC
NC
B1
B2
B3
B4
B5
NC
SCLK
VSS
VCC
NC
C4
C5
C1
C2
C3
NC
CS#
NC
D1
D2
D3
NC
SO(IO1) SI(IO0)
WP#(IO2) NC
D4
D5
HOLD#
(IO3)
NC
E1
E2
E3
E4
E5
NC
NC
NC
NC
NC
24-BALL TFBGA (5x5 ball array)
7
SPI-NAND
GD5F1GQ5xExxG
2.3 PIN DESCRIPTION
Pin Name
I/O
Description
CS#
I
Chip Select input, active low
SO/SIO1
I/O
Serial Data Output / Serial Data Input Output 1
WP#/SIO2
I/O
Write Protect, active low / Serial Data Input Output 2
VSS
Ground
Ground
SI/SIO0
I/O
Serial Data Input / Serial Data Input Output 0
SCLK
I
Serial Clock input
HOLD#/SIO3
I/O
Hold Input/Serial Data Input Output 3
VCC
Supply
Power Supply
Not Connect, Not internal connection; can be driven or floated.
NC
2.4 BLOCK DIAGRAM
Figure 2-2. Block Diagram
SCLK
SI/SIO0
SO/SIO1
CS#
HOLD#/
SIO3
WP#/
SIO2
Serial NAND controller
Vcc
Vss
Cache
memory
Status register
8
NAND
memory
core
SPI-NAND
3
GD5F1GQ5xExxG
MEMORY MAPPING
For 1G
Blocks
RA
0
1
Pages
RA
0
1
Bytes
CA
0
1
2
1023
63
2
2175
Note:
1.
CA: Column Address. The 12-bit address is capable of addressing from 0 to 4095 bytes; however, only bytes 0
through 2175 are valid. Bytes 2176 through 4095 of each page are “out of bounds,” do not exist in the device,
and cannot be addressed.
2.
RA: Row Address. RAselects a page inside a block, and RAselects a block.
9
SPI-NAND
4
GD5F1GQ5xExxG
ARRAY ORGANIZATION
Table 3. Array Organization
Each device has
Each block has
Each page has
128M+8M
128K+8K
2K+128
bytes
1024 x 64
64
-
pages
1024
-
-
blocks
1Gb
Figure 3.Array Organization
Cache Register
2048
128
Data Register
2048
128
IO
1 page
= (2K + 128)bytes
1 block = (2K + 128)bytes x 64 pages
= (128K + 8K)bytes
Per device:
1G: 1024 Blocks
1 device:
For 1G: = (128K +8K)bytes x 1024 blocks
= 1Gb
1 block
Internal ECC = OFF
Cache Register
2048
64
Data Register
2048
64
IO
1 page
= (2K + 64)bytes
1 block = (2K + 64)bytes x 64 pages
= (128K + 4K)bytes
Per device:
1G: 1024 Blocks
1 device:
For 1G: = (128K +4K)bytes x 1024 blocks
= 1Gb
1 block
Internal ECC = ON
Note:
1.When Internal ECC is enabled，user can program the first 64 bytes of the entire 128 bytes spare area and the last 64
bytes of the whole spare area cannot be programed，user can read the entire 128 Byte spare area.
2.When Internal ECC is disabled，user can read and program the entire 128 bytes spare area.
10
SPI-NAND
5
GD5F1GQ5xExxG
DEVICE OPERATION
5.1 SPI Modes
SPI NAND supports two SPI modes:
• CPOL = 0, CPHA = 0 (Mode 0)
• CPOL = 1, CPHA = 1 (Mode 3)
Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK for both modes. All timing
diagrams shown in this data sheet are mode 0. See Figure 5-1 for more details.
Figure 5-1. SPI Modes Sequence Diagram
CPOL CPHA
0
0 SCLK
1
1
SCLK
SI
MSB
LSB
SO
MSB
LSB
CS#
Note: While CS# is HIGH, keep SCLK at VCC or GND (determined by mode 0 or mode 3). Do not toggle SCLK until CS#
is driven LOW.
We recommend that the user pull CS# to high when user don’t use SPI flash, otherwise the flash is always in the read state,
which is damage for flash.
When CS# is high and SCLK at VCC or GND state, the device is in idle state.
Standard SPI
SPI NAND Flash features a standard serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO).
Dual SPI
SPI NAND Flash supports Dual SPI operation when using the x2 and dual IO commands. These commands allow data to
be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI command the SI
and SO pins become bidirectional I/O pins: SIO0 and SIO1.
Quad SPI
SPI NAND Flash supports Quad SPI operation when using the x4 and Quad IO commands. These commands allow data
to be transferred to or from the device at four times the rate of the standard SPI. When using the Quad SPI command the
SI and SO pins become bidirectional I/O pins: SIO0 and SIO1, and WP# and HOLD# pins become SIO2 and SIO3.
11
SPI-NAND
GD5F1GQ5xExxG
DTR Quad SPI
The device supports DTR Quad SPI operation when using the “DTR Quad I/O Fast Read” command.
These command allow data to be transferred to or from the device at eight times the rate of the standard SPI, and data
output will be latched on both rising and falling edges of the serial clock. When using the DTR Quad SPI command the SI
and SO pins become bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3.
5.2 HOLD Mode
The HOLD# function is only available when QE=0, If QE=1, The HOLD# functions is disabled, the pin acts as
dedicated data I/O pin.
The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being
low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge
of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure 5-2. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
5.3 Write Protection
SPI NAND provides Hardware Protection Mode besides the Software Mode. Write Protect (WP#) prevents the block
lock bits (BP0, BP1, BP2 and INV, CMP) from being over written. If the BRWD bit is set to 1 and WP# is LOW, the block
protect bits cannot be altered.
To enable the Write Protection, the Quad Enable bit (QE) of feature (B0[0]) must be set to 0.
12
SPI-NAND
GD5F1GQ5xExxG
5.4 Power Off Timing
Please do not turn off the power before Write/Erase operation is complete. Avoid using the device when the battery is
low. Power shortage and/or power failure before Write/Erase operation is complete will cause loss of data and/or damage
to data.
13
SPI-NAND
6
GD5F1GQ5xExxG
COMMANDS DESCRIPTION
Table 6. Commands Set
Command Name
Byte1
Byte2
Byte3
Byte4
Write Enable
06H
Write Disable
04H
Get Features
0FH
A7-A0
D7-D0
Wrap(8)
Set Feature
1FH
A7-A0
D7-D0
Page Read (to cache)
13H
A23-A16
A15-A8
A7-A0
Read From Cache
03H/0BH
A15-A8
A7-A0(2)
Dummy(1)
D7-D0
A15-A8
A7-A0(2)
Dummy(1)
D7-D0
A15-A8
A7-A0(2)
Dummy(1)
D7-D0
A15-A8
A7-A0(2)
Dummy(9)
D7-D0
EBH
A15-A8
A7-A0(2)
Dummyx2(9)
D7-D0
EEH
A31-A24
A23-A16
A15-A8
A7-A0(2)
Read ID(4)
9FH
Dummy
MID
DID
Read parameter page
13H
00H
00H
04H
Read UID
13H
00H
00H
06H
Program Load
02H
A15-A8
A7-A0(3)
D7-D0
Next byte
Program Load x4
32H
A15-A8
A7-A0(3)
D7-D0
Next byte
Program Execute
10H
A23-A16
A15-A8
A7-A0
Program Load Random Data
84H(6)
A15-A8
A7-A0(3)
D7-D0
Next byte
Program Load Random Data x4
C4H/34H(6)
A15-A8
A7-A0(3)
D7-D0
Next byte
Block Erase(128K)
D8H
A23-A16
A15-A8
A7-A0
Reset(5)
FFH
Read From Cache x 2
Read From Cache x 4
Read From Cache Dual IO
Read From Cache Quad IO
Read From Cache Quad I/O
DTR
Enable Power on Reset
Power on
Reset(7)
3BH
6BH
BBH
66h
99h
14
Byte5
Byte6
Dummy
x8(1)
Byte 7
D7-D0
SPI-NAND
GD5F1GQ5xExxG
Note:
1. The dummy has 8 clock.
03H/0BH/3BH/6BH has 1 byte dummy.
EEH has 8 bytes dummy.
2. The A15-A0 (03H/0BH/3BH/6BH) has 16 clock, include 4 clock dummy.
The A15-A0 (BBH) has 8 clock, include 2 clock dummy.
The A15-A0 (EBH) has 4 clock, include 1 clock dummy.
The A31-A0 (EEH) has 4 clock, include 2.5 clock dummy.
3. The A15-A0 has 16 clock, include 4 clock dummy.
4. MID is Manufacture ID (C8h for GigaDevice), DID is Device ID.
5. Reset command:
• Reset will reset PAGE READ/PROGRAM/ERASE operation.
• Reset will reset status register bits P_FAIL/E_FAIL/WEL/OIP/ECCS/ECCSE.
6. Those commands are only available in Internal Data Move operation.
7. Power on reset:
Retrieve status register and data in cache to power on status.
8. The output would be updated by real-time, until CS# is driven high.
9. The dummy has 4 clock
BBh has 1bytes dummy
EBh has 2bytes dummy.
15
SPI-NAND
7
GD5F1GQ5xExxG
WRITE OPERATIONS
7.1 Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit
must be set prior to following operations that change the contents of the memory array:
• Page program
• OTP program/OTP protection
• Block erase
The WEL bit can be cleared after a reset command.
Figure 7-1. Write Enable Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
Command
SI
06H
High-Z
SO
7.2 Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The WEL bit is reset by following
condition:
• Page program
• OTP program/OTP protection
• Block erase
Figure 7-2. Write Disable Sequence Diagram
CS#
SCLK
SI
SO
0
1
2
3
4
5
Command
04H
High-Z
16
6
7
SPI-NAND
8
GD5F1GQ5xExxG
READ OPERATIONS
8.1 Page Read
The PAGE READ (13H) command transfers the data from the NAND Flash array to the cache register. The command
sequence is as follows:
• 13H (PAGE READ to cache)
• 0FH (GET FEATURES command to read the status)
• 03H or 0BH (Read from cache)/3BH (Read from cache x2)/6BH (Read from cache x4)/BBH (Read from cache
dual IO)/EBH (Read from cache Quad IO)/EEH (Read from cache Quad IO DTR)
The PAGE READ command requires a 24-bit address. After the block/page addresses are registered, the device starts
the transfer from the main array to the cache register, and is busy for tRD time. During this time, the GET FEATURE
(0FH) command can be issued to monitor the status. Followed the page read operation, the RANDOM DATA READ
(03H/0BH/3BH/6BH/BBH/EBH/EEH) command must be issued in order to read out the data from cache. When CS# is
pulled high this operation will be terminated. Refer waveforms to view the entire READ operation.
Note: (1) The command 6BH (Read from cache x4)/EBH (Read from cache Quad IO)/EEH (Read from cache Quad IO
DTR) is only available with the QE enable.
(2) When user read to the end of 64-Byte spare area, it won’t wrap around from the beginning boundary and an
additional 64Byte ECC code will be read. (Internal ECC enabled)
17
SPI-NAND
GD5F1GQ5xExxG
8.2 Page Read to Cache (13H)
The command page read to cache is read the data from flash array to cache register.
Figure 8-1. Page Read to cache Sequence Diagram
CS#
28 29 30 31
9 10
8
7
6
5
4
3
2
1
0
SCLK
24-bit address
Command
SI
0
1
2
3
23 22 21
13H
High-Z
SO
CS#
0
1
3
2
4
5
6
7
8
9 10 11 12 13 14 15
SLK
tCS
7
0FH
MSB
High-Z
SO
CS#
16 17 18 19 20 21 22 23 24
SCLK
SI
Data byte
SO
7
6
5
1 byte address
Get Feature
SI
4
3
2
1
0
7
MSB
18
6
5
4
3
2
1
0
SPI-NAND
GD5F1GQ5xExxG
8.3 Read From Cache (03H or 0BH)
The command sequence is shown below.
Figure 8-2. Read From Cache Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
22 23
SCLK
Command
SI
Dummy
03H or 0BH
0
0
A11- A0
3 2
0 0 11 10
1
0
High-Z
SO
CS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Dummy byte
SI
SO
7
6
5
4
3
2
1
0
7 6
MSB
19
Data byte 0
5 4 3 2 1
0
Data byte 1
7 6 5
MSB
SPI-NAND
GD5F1GQ5xExxG
8.4 Read From Cache x2 (3BH)
The command sequence is shown below.
Figure 8-3. Read From Cache x2 Sequence Diagram
CS#
0
1
2
3
4
5
6
7
9 10 11 12 13 14
8
22 23
SCLK
Dummy
Command
SI/SIO0
3BH
0
0 0
A11-A0
0 11 10
3
2
High-Z
SO/SIO1
CS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Dummy byte
SI/SIO0
SO/SIO1
7
6
5
4
3
2
1
0
6
4
2
0
6
4
2
0
6
4
2
Data byte 0 Data byte 1
7 5 3 1 7 5 3 1 7
5
3
MSB
MSB
20
1
0
SPI-NAND
GD5F1GQ5xExxG
8.5 Read From Cache x4 (6BH)
The Quad Enable bit (QE) of feature (B0[0]) must be set to enable the read from cache x4 command. The command
sequence is shown below.
Figure 8-4. Read From Cache x4 Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
22 23
SCLK
Command
SI(SIO0)
Dummy
6BH
0
SO(SIO1)
High-Z
WP#(SIO2)
High-Z
HOLD#(SIO3)
High-Z
CS#
0 0
A11- A0
0 11 10
3
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Dummy byte
7
6
5
4
3
2
1
0 4
0
4
0
4
0
4
0
4
SO(SIO1)
5
1
5
1
5
1
5
1
5
WP#(SIO2)
6
2
6
2
6
2
6
2
6
HOLD#(SIO3)
7 3 7 3 7 3 7 3 7
Byte0 Byte1 Byte2 Byte3
SI(SIO0)
21
2
1
0
SPI-NAND
GD5F1GQ5xExxG
8.6 Read From Cache Dual IO (BBH)
The Read from Cache Dual I/O command (BBH) is similar to the Read from Cache x2 command (3BH) but with the
capability to input the 4 Dummy bits, followed by a 12-bit column address for the starting byte address and 4 clock dummy
by SIO0 and SIO1, each bit being latched in during the rising edge of SCLK, then the cache contents are shifted out 2-bit
per clock cycle from SIO0 and SIO1. The first address byte can be at any location. The address is increased automatically
to the next higher address after each byte of data shifted out until the boundary rap bit.
Figure 8-5 Read From Cache Dual IO Sequence Diagram
CS#
0
SCLK
1
2
3
4
5 6
8
9 10 11 12 13 14 15 16 17 18 19
Dummy
A11-A0
0 0 10 8 6 4 2 0
Command
SI(SIO0)
7
BBH
SO(SIO1)
0
0 11 9
7
5
3 1
CS#
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
SCLK
SI(SIO0)
6
SO(SIO1) 7
4
2
0
6 4
0
6
4 2
0
6
4
2 0
6
5 3
Data
byte 0
1
7 5 3 1
Data
byte 1
7
5 3 1
Data
byte 2
7
5 3 1
Data
byte 3
7
2
22
Dummy
6
4
2
0
7
5
3
1
SPI-NAND
GD5F1GQ5xExxG
8.7 Read From Cache Quad IO (EBH)
The Read from Cache Quad IO command is similar to the Read from Cache x4 command but with the capability to input
the 4 dummy bits, followed a 12-bit column address for the starting byte address and 4 clock dummy by SIO0, SIO1, SIO3,
SIO4, each bit being latched in during the rising edge of SCLK, then the cache contents are shifted out 4-bit per clock cycle
from SIO0, SIO1, SIO2, SIO3. The first byte addressed can be at any location. The address is increased automatically to
the next higher address after each byte of data is shifted out until the boundary wrap bit. The Quad Enable bit (QE) of
feature (B0[0]) must be set to enable the read from cache quad IO command.
Figure 8-6 Read From Cache Quad IO Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
Dummy
0 8
4
0
4
0
4
0
4
0 4
0
4
SO(SIO1)
0
5
1
5
1
5
1
5
1 5
1
5
WP#(SIO2)
0 10 6
2
6
2
6
2
6
2 6
2
6
HOLD#(SIO3)
0 11 7
3
7
3
7
3
7
3 7
3
7
Command
SI(SIO0)
EBH
9
A11 - A0
23
Dummy
Byte0 Byte1
SPI-NAND
GD5F1GQ5xExxG
8.8 Read From Cache Quad I/O DTR (EEH)
The DTR Quad IO command enables Double Transfer Rate throughput on quad I/O of Serial Flash in read mode. A Quad
Enable (QE) bit of status Register must be set to “1” before sending the DTR Quad IO command. The address (interleave
on 4 I/O pins) is latched on both rising and falling edge of SCLK, and data (interleave on 4 I/O pins) shift out on both rising
and falling edge of SCLK. The 8-bit address can be latched-in at one clock, and 8-bit data can be read out at one clock,
which means four bits at rising edge of clock, the other four bits at falling edge of clock.
The first address Byte can be at any location. The address is automatically increased to the next higher address after each
Byte data is shifted out, so the whole page can be read out at a single DTR Quad IO command. The address counter rolls
over to 0 when the highest address has been reached.
Figure 8-7. Read From Cache Quad I/O DTR Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
8
9 10 11
Dummy
Command
SI(IO0)
7
EEH
19 20
Dummy
0 0 0 0 0 8 4 0
4 0 4 0
0 0 0 0 0 9 5 1
5 1 5 1
IO2
0 0 0 0 0 10 6 2
6 2 6 2
IO3
0 0 0 0 0 11 7 3
SO(IO1)
A11- A0
Note:
Please contact GigaDevice when there is a need to use the EEh command for DTR.
24
7 3 7 3
Byte 0Byte 1
SPI-NAND
GD5F1GQ5xExxG
8.9 Read ID (9FH)
The READ ID command is used to identify the NAND Flash device.
• With address 00H, the READ ID command outputs the Manufacturer ID and the device ID. See Table 8-1 for details.
Figure 8-8. Read ID Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
Command
SI
Dummy
9FH
7
6
5
4
3
2
1
High-Z
SO
CS#
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
SO
7
Manufacturer ID
6 5 4 3 2 1
MSB
Device ID
0
7
6
5
4
3
2
MSB
Table 8-1. READ ID Table
Part No
MID
DID1
GD5F1GQ5UExxG
C8H
51H
GD5F1GQ5RExxG
C8H
41H
25
1
0
0
SPI-NAND
GD5F1GQ5xExxG
8.10 Read UID
The Read Unique ID function is used to retrieve the 16 byte unique ID (UID) for the device. The unique ID when combined
with the device manufacturer shall be unique.
The UID data may be stored within the Flash array. To allow the host to determine if the UID is without bit errors, the UID
is returned with its complement. If the XOR of the UID and its bit-wise complement is all ones, then the UID is valid. To
accommodate robust retrieval of the UID in the case of bit errors, sixteen copies of the UID and the corresponding
complement are stored by the target. For example, reading bytes 32-63 returns to the host another copy of the UID and its
complement.
Bytes
Value
0-15
UID
16-31
UID complement (bit-wise)
Sequence is as follows:
1.
Use Set Feature command to set B0 register, to enable OTP_EN.
2.
Use Get Feature command to get data from B0 register and check if the OTP_EN is enable.
3.
Use page read to cache (13h) command with address 24’h000006h, read data from array to cache.
4.
Use 0FH (GET FEATURES command) read the status.
5.
User can use Read from cache command (03H/0BH), read 16 bytes UID from cache.
Figure 8-9. Read UID to cache and Get Feature command Sequence Diagram one
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24-bit address
13H
000006H
High-Z
SO
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SLK
tCS
0FH
7
MSB
High-Z
SO
CS#
16 17 18 19 20 21 22 23 24
SCLK
SI
Data byte
SO
7
6
5
1 byte address
Get Feature
SI
4
3
2
1
0
7
MSB
26
6
5
4
3
2
1
0
SPI-NAND
GD5F1GQ5xExxG
8.11 Read Parameter Page
The Read Parameter Page function retrieves the data structure that describes the chip’s organization, features, timing and
other behavioral parameters. This data structure enables the host processor to automatically recognize the SPI-NAND
Flash configuration of a device. A minimum of three copies of the parameter page are stored in the device. The Read from
Cache command can be used to change the location of data output.
Sequence is as follows:
1.
Use Set Feature command to set B0 register, to enable OTP_EN.
2.
Use Get Feature command to get data from B0 register and check if the OTP_EN is enable.
3.
Use Page Read to Cache (13h) command with address 24’h000004. Load parameter page from array to
cache.
4.
Use 0FH (GET FEATURES command) read the status
5.
User can use Read from cache command (03H/0BH), read parameter page from cache.
Figure 8-10. Read parameter page to cache and Get Feature command Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24-bit address
13H
000004H
High-Z
SO
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SLK
0FH
7
MSB
High-Z
SO
CS#
16 17 18 19 20 21 22 23 24
SCLK
SI
Data byte
SO
7
6
5
1 byte address
Get Feature
tCS
SI
4
3
2
1
0
7
MSB
27
6
5
4
3
2
1
0
SPI-NAND
GD5F1GQ5xExxG
Parameter page table as follow (1G)
Byte
O/M
Description
3.3V/1.8V
0-3
M
Parameter page signature
4FH
Byte 0: 4FH, “O”
4EH
Byte 1: 4EH, “N”
46H
Byte 2: 46H, “F”
49H
Byte 3: 49H, “I”
4-5
6-7
8-9
M
M
M
Revision number
00H
0-15 Reserved (0)
00H
Features supported
00H
0-15 Reserved (0)
00H
Reserved (0)
00H
00H
10-31
Reserved (0)
00H
…
00H
Manufacturer Information block
32-43
M
Device manufacturer (12 ASCII characters)“GIGADEVICE
”
47H
49H
47H
41H
44H
45H
56H
49H
43H
45H
20H
20H
44-63
M
Device model (20 ASCII characters)
47H
Device Model
ORGANIZATION
VCC RANGE
44H
“GD5F1GQ5U”
X4
2.7v ~ 3.6v
35H
“GD5F1GQ5R”
X4
1.7v ~ 2.0v
46H
31H
47H
51H
35H
55H/52H
20H
20H
20H
20H
20H
20H
28
SPI-NAND
GD5F1GQ5xExxG
20H
20H
20H
20H
20H
64
M
JEDEC manufacturer ID“C8”
C8H
65-66
O
Date code
00H
00H
67-79
Reserved
00H
00H
00H
Memory organization block
80-83
M
Number of data bytes per page
00H
08H
00H
00H
84-85
M
Number of spare bytes per page
80H
00H
86-89
M
Number of data bytes per partial page
00H
02H
00H
00H
90-91
M
Number of spare bytes per partial page
20H
00H
92-95
M
Number of pages per block
40H
00H
00H
00H
96-99
M
Number of blocks per logical unit (LUN)
00H
04H
00H
00H
100
M
Number of logical units (LUNs)
01H
101
M
Reserved
00H
102
M
Number of bits per cell
01H
103-104
M
Bad blocks maximum
14H
00H
105-106
M
Block endurance
01H
05H
107
M
Guaranteed valid blocks at beginning of target
01H
108-109
M
Block endurance for guaranteed valid blocks
00H
00H
29
SPI-NAND
GD5F1GQ5xExxG
110
M
Number of programs per page
04H
111
M
Partial programming attributes
00H
5-7 Reserved
4 1 = partial page layout is partial page data followed by partial page spare
1-3 Reserved
0 1 = partial page programming has constraints
112
M
Number of bits ECC correctability
00H
113
M
Number of interleaved address bits
00H
4-7 Reserved (0)
0-3 Number of interleaved address bits
114
O
Interleaved operation attributes
00H
4-7 Reserved (0)
3 Address restrictions for program cache
2 1 = program cache supported
1 1 = no block address restrictions
0 Overlapped / concurrent interleaving support
115-127
Reserved
00H
…
00H
Electrical parameters block
128
M
I/O capacitance
08H
129-130
M
IO clock support
00H
00H
131-132
O
Reserved (0)
00H
00H
133-134
M
tPROG Maximum page program time (us)
58H
02H
135-136
M
tBERS Maximum block erase time (us)
10H
27H
137-138
M
tR Maximum page read time (us)
3CH
00H
139-140
M
Reserved
00H
00H
141-163
Reserved
00H
Vendor block
164-165
M
166-253
254-255
M
Vendor specific Revision number
00H
Vendor specific
00H
Integrity CRC
Set on test
Redundant parameter pages
256-511
M
Value of bytes 0-255
512-767
M
Value of bytes 0-255
768+
O
Additional redundant parameter pages
30
SPI-NAND
GD5F1GQ5xExxG
Notes:
1.
“O” Stands for Optional, “M” for Mandatory
2.
The Integrity CRC (Cycling Redundancy Check) field is used to verify that the contents of the parameters page were transferred
correctly to the host. Please refer to ONFI 1.0 specifications for details. The CRC shall be calculated using the following 16-bit
generator polynomial: G(X) = X16 + X15 +X2 + 1，This polynomial in hex may be represented as 8005h.
3．The CRC value shall be initialized with a value of 4F4Eh before the calculation begins. There is no XOR applied to the final CRC value
after it is calculated. There is no reversal of the data bytes or the CRC calculated value.
Device Model
ORGANIZATION
VCC RANGE
CRC value
“GD5F1GQ5UxxG”
X4
2.7v ~ 3.6v
58H/F3H
“GD5F1GQ5RxxG”
X4
1.7v ~ 2.0v
80H/3EH
31
B254/B255
SPI-NAND
9
GD5F1GQ5xExxG
PROGRAM OPERATIONS
9.1 Page Program
The PAGE PROGRAM operation sequence programs 1 byte to whole page bytes of data within a page. The page program
sequence is as follows:
• 02H (PROGRAM LOAD)/32H (PROGRAM LOAD x4)
• 06H (WRITE ENABLE)
• 10H (PROGRAM EXECUTE)
• 0FH (GET FEATURE command to read the status)
Firstly, a PROGRAM LOAD (02H/32H) command is issued. PROGRAM LOAD consists of an 8-bit Op code, followed by 4
dummy bits and a 12-bit column address, then the data bytes to be programmed. The Program address should be in
sequential order in a block. The data bytes are loaded into a cache register that is whole page long. If more than one page
data are loaded, then those additional bytes are ignored by the cache register. The command sequence ends when CS#
goes from LOW to HIGH. Figure 9-1 shows the PROGRAM LOAD operation. Secondly, prior to performing the PROGRAM
EXECUTE operation, a WRITE ENABLE (06H) command must be issued. As with any command that changes the memory
contents, the WRITE ENABLE must be executed in order to set the WEL bit. If this command is not issued, then the rest
of the program sequence is ignored.
Note:
1.
The contents of Cache Register doesn’t reset when Program Random Load (84h) command and RESET (FFh)
command.
2.
When Program Execute (10h) command was issued just after Program Load (02h) command, the 0xFF is output to
the address that data was not loaded by Program Load (02h) command.
3.
When Program Execute (10h) command was issued just after Program Load Random Data (84h) command, the
contents of Cache Register is output to the NAND.
4.
The Program address should be in sequential order in a block.
5.
Program Load x4 is only available with the QE enable.
32
SPI-NAND
GD5F1GQ5xExxG
9.2 Program Load (PL) (02H)
The command sequence is shown below.
Figure 9-1. Program Load Sequence Diagram
CS#
0
1
2
3
4
5
6
7
9 10 11 12 13 14
8
22 23
SCLK
Dummy
Command
SI
02H
0
0
A11- A0
0 0 11 10
3
2
1
0
CS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Data byte 0
SI
7 6
MSB
5
4
3
Data byte 1
2
1
0 7
6
5
4
3
2
Data byte N
1
0
7
6
5
4
3
2
1
0
Note: When internal ECC disabled the Data Byte is 2176, when internal ECC enabled the Data Byte is 2112.
33
SPI-NAND
GD5F1GQ5xExxG
9.3 Program Load x4 (PL x4) (32H)
The Program Load x4 command (32H) is similar to the Program Load command (02H) but with the capability to input the
data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is shown below. The Quad Enable bit (QE)
of feature (B0[0]) must be set to enable the program load x4 command.
Figure 9-2. Program Load x4 Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCLK
Command
SI(SIO0)
0
0
0
Byte 0 Byte1
A11 - A0
Dummy
32H
0 11
1
0 4
0
4
0
4
0
4
0
SO(SIO1)
5
1
5
1
5
1
5
1
WP#(SIO2)
6
2
6
2
6
2
6
2
HOLD#(SIO3)
7
3
7
3
7
3
7
3
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Byte10Byte11
Byte
N
Byte
N+1
4
4
SI(SIO0)
4
SO(SIO1)
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
WP#(SIO2)
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
HOLD#(SIO3) 7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
4
0
0
0
Note: When internal ECC disabled the Data Byte is 2176, when internal ECC enabled the Data Byte is 2112.
34
SPI-NAND
GD5F1GQ5xExxG
9.4 Program Execute (PE) (10H)
After the data is loaded, a PROGRAM EXECUTE (10H) command must be issued to initiate the transfer of data from the
cache register to the main array. PROGRAM EXECUTE consists of an 8-bit Op code, followed by a 24-bit address. After
the page/block address is registered, the memory device starts the transfer from the cache register to the main array, and
is busy for tPROG time. This operation shown in Figure 9-3. During this busy time, the status register can be polled to
monitor the status of the operation (refer to Status Register). When the operation completes successfully, the next series
of data can be loaded with the PROGRAM LOAD command. The command sequence is shown below.
Figure 9-3. Program Execute Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24-bit address
10H
23 22 21
3
2
1
0
High-Z
SO
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
tCS
0FH
7
6
5
4
3
2
1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCLK
SI
Status register data out
SO
0
MSB
High-Z
SO
CS#
Status register address
get feature
SI
7
MSB
6
5
4
3
2
1
0
Status register data out
7
MSB
35
6
5
4
3
2
1
0
7
6
SPI-NAND
GD5F1GQ5xExxG
9.5 Internal Data Move
The INTERNAL DATA MOVE command sequence programs or replaces data in a page with existing data. The
INTERNAL DATA MOVE command sequence is as follows:
• 13H (PAGE READ to cache)
• Optional 84H/C4H/34H(PROGRAM LOAD RANDOM DATA)
• 06H (WRITE ENABLE)
• 10H (PROGRAM EXECUTE)
• 0FH (GET FEATURE command to read the status)
Prior to performing an internal data move operation, the target page content must be read out into the cache register by
issuing a PAGE READ (13H) command. The PROGRAM LOAD RANDOM DATA (84H/C4H) command can be issued, if
user wants to update bytes of data in the page. New data is loaded in the 12-bit column address. If the random data is
not sequential, another PROGRAM LOAD RANDOM DATA (84H/C4H) command must be issued with the new column
address. After the data is loaded, the WRITE ENABLE command must be issued, and then PROGRAMEXECUTE (10H)
command can be issued to start the programming operation.
9.6 Program Load Random Data (84H)
This command consists of an 8-bit Op code, followed by 4 dummy bits, and a 12-bit column address. New data is loaded
in the column address provided with the 12 bits. If the random data is not sequential, then another PROGRAM LOAD
RANDOM DATA (84H) command must be issued with a new column address, see Figure 9-4 for details. This command is
only available during internal data move sequence.
Figure 9-4. Program Load Random Data Sequence Diagram
CS#
0
1
2
3
4
5
6
7
9 10 11 12 13 14
8
22 23
SCLK
Command
SI
A11 - A0
Dummy
84H
0
0 0
0 11 10
3
2
1
0
CS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Data byte 0
SI
7 6
MSB
5
4
3
Data byte 1
2
1
0 7
6
5
4
3
2
36
Data byte N
1
0
7
6
5
4
3
2
1
0
SPI-NAND
GD5F1GQ5xExxG
9.7 Program Load Random Data x4 (C4H/34H)
The Program Load Random Data x4 command (C4H/34H) is similar to the Program Load Random Data command (84H)
but with the capability to input the data bytes by four pins: SIO0, SIO1, SIO2, and SIO3. The command sequence is shown
below. The Quad Enable bit (QE) of feature (B0[0]) must be set to enable for the program load random data x4 command.
See Figure 9-5 for details. Those two commands are only available during internal data move sequence.
Figure 9-5. Program Load Random Data x4 Sequence Diagram
CS#
0
1
2
3
4
5
6
7
9 10 11 12
8
22 23 24 25 26 27 28 29 30 31
SCLK
Command
SI(SIO0)
Dummy
C4H/34H
0
0
Byte 0 Byte 1
A11 - A0
0 0 11
1
0 4
0
4
0
4
0
4
0
SO(SIO1)
5
1
5
1
5
1
5
1
WP#(SIO2)
6
2
6
2
6
2
6
2
HOLD#(SIO3)
7
3
7
3
7
3
7
3
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Byte10Byte11
Byte N
SI(SIO0)
4
SO(SIO1)
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
5 1
WP#(SIO2)
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
6 2
HOLD#(SIO3) 7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
7 3
0
4
0
4
0
4
0
4
0
4
0
37
4
0
4
0
4
0
4
0
4
0
4
0
SPI-NAND
10
GD5F1GQ5xExxG
ERASE OPERATIONS
10.1 Block Erase (D8H)
The BLOCK ERASE (D8H) command is used to erase at the block level. The BLOCK ERASE command (D8H) operates
on one block at a time. The command sequence for the BLOCK ERASE operation is as follows:
• 06H (WRITE ENBALE command)
• D8H (BLOCK ERASE command)
• 0FH (GET FEATURES command to read the status register)
Prior to performing the BLOCK ERASE operation, a WRITE ENABLE (06H) command must be issued. As with any
command that changes the memory contents, the WRITE ENABLE command must be executed in order to set the WEL
bit. If the WRITE ENABLE command is not issued, then the rest of the erase sequence is ignored. A WRITE ENABLE
command must be followed by a BLOCK ERASE (D8H) command. This command requires a 24-bit address. After the
row address is registered, the control logic automatically controls timing and erase-verify operations. The device is busy
for tBERS time during the BLOCK ERASE operation. The GET FEATURES (0FH) command can be used to monitor the
status of the operation.
Figure 10. Block Erase Sequence Diagram
CS#
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
SCLK
Command
SI
24-bit address
D8H
23 22 21
3
2
1
0
High-Z
SO
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SLK
tCS
SI
0FH
7
6
5
4
3
2
1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCLK
SI
Status register data out
SO
0
MSB
High-Z
SO
CS#
Status register address
get feature
7
MSB
6
5
4
3
2
1
0
Status register data out
7
MSB
38
6
5
4
3
2
1
0
7
6
SPI-NAND
11
GD5F1GQ5xExxG
RESET OPERATIONS
11.1 Soft Reset (FFH)
The RESET (FFH) command stops all operations and the status. For example, in case of a program or erase or read
operation, the reset command can make the device enter the idle state.
Figure 11-1. Reset Sequence Diagram
CS#
0
1
2
3
4
5
6
7
SCLK
Command
SI
FFH
High-Z
SO
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SLK
SI
0FH
7
6
5
4
3
2
1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SCLK
SI
Status register data out
SO
0
MSB
High-Z
SO
CS#
Status register address
get feature
tCS
7
MSB
6
5
4
3
2
1
0
Status register data out
7
6
5
4
3
2
1
0
7
MSB
Note: The Register bit value after soft reset refers to Table 12-2.Register bit Descriptions.
39
6
SPI-NAND
GD5F1GQ5xExxG
11.2 Enable Power on Reset (66H) and Power on Reset (99H)
If the Power on Reset command is accepted, any on-going internal operation will be terminated and the device will return
to its default power-on state and lose all the current feature settings.
The “Enable Reset (66H)” and the “Reset (99H)” commands can be issued in SPI mode. The “Reset (99H)” command
sequence as follow: CS# goes low -> Sending Enable Reset command ->CS# goes high ->CS# goes low.->Sending Reset
command ->CS# goes high. Once the Reset command is accepted by the device, the device will take approximately tVSL
to reset. During this period, no command will be accepted.
Figure 11-2. Reset Sequence Diagram
CS#
0
1
2
3
4
5
6
7
0
1
2
3
4
5
SCLK
Command
SI
SO
Command
66H
99H
High-Z
40
High-Z
6
7
SPI-NAND
12
GD5F1GQ5xExxG
FEATURE OPERATIONS
12.1 Get Features (0FH) and Set Features (1FH)
The GET FEATURES (0FH) and SET FEATURES (1FH) commands are used to monitor the device status and alter the
device behavior. These commands use a 1-byte feature address to determine which feature is to be read or modified.
Feature such as OTP can be enabled or disabled by setting specific feature bits (shown in the below table).The status
register is mostly read, except WEL, which is a writable bit with the WRITE ENABLE (06H) command.
When a feature is set, it remains active until the device is power cycled or the feature is written to. Unless otherwise
specified in the following table, once the device is set, it remains set, even if a RESET (FFH) command is issued.
Table 12-1. Features Settings
Register
Addr.
Protection A0H
7
6
5
4
3
2
1
0
BRWD
Reserved
BP2
BP1
BP0
INV
CMP
Reserved
Feature
B0H
OTP_PRT
OTP_EN
Reserved
ECC_EN
BPL
Reserved
Reserved
QE
Status
C0H
Reserved
Reserved
ECCS1
ECCS0
P_FAIL
E_FAIL
WEL
OIP
Feature
D0H
Reserved
DS_IO[1]
DS_IO[0]
Reserved
Reserved
Reserved
Reserved
Reserved
Status
F0H
Reserved
Reserved
ECCSE1
ECCSE0
BPS
Reserved
Reserved
Reserved
Note:
1. If BRWD is enabled and WP# is LOW, then the block lock register cannot be changed.
2. If QE is enabled, the quad IO operations can be executed.
3. All the reserved bits must be held low when the feature is set.
4. These registers A0H/B0H/D0H are write/read type, and Registers C0H/F0H are read only.
5. The OTP_PRT is non-volatile, others bits are volatile.
6. The Register Bit default value after power-up refers to Table 12-2. Register Bit Descriptions.
7. The BPL bit is available on special order. Please contact GigaDevice for details.
41
SPI-NAND
GD5F1GQ5xExxG
Table 12-2. Status Register Bit Descriptions
Bit
Bit Name
After Power up
After Reset
or Power on
command
Reset(66H-99H)
(FFH)
Description
Block
BRWD
register
Which is used combined with WP#, If BRWD is high
0
No Change
write disable
BP2
enabled and WP# is LOW, then the Protection register
cannot be changed
1
BP1
Block
1
BP0
Protection
1
INV
bits
0
CMP
No Change
used combination, refer to chapter Block Protection
No Change
used combination, refer to chapter OTP Region
0
OTP_PRT
OTP Region
OTP_EN
bits
0
0
Before OTP Set
The device offers data corruption protection by offering
optional internal ECC. READs and PROGRAMs with
ECC_EN
ECC Enable
Latch
internal ECC can be enabled or disabled by setting feature
1
No Change
bit ECC_EN. ECC is enabled by default when device
powered on, so the default READ and PROGRAM
commands operate with internal ECC in the “active” state
when ECC enable.
BPL is for Power Lock Down Protection. Once the BPL bit
Block
BPL
Protection
Lock
sets as 1, the rest of the protection bits BP[0,2] , INV ,
0
No Change
default BPL is 0 after power-on-reset and this bit default is
register
QE
The Quad
Enable bit
CMP , BRWD can’t be changed until next power cycle. By
Power Lock Down Protection disable.
This bit indicates that whether the quad IO operations can
0
No Change
be executed.
If QE is set to 1, the quad IO operations can be executed.
ECCS provides ECC status as the following table.
ECCS and ECCSE are set to 00b either following a
ECCS1
0
ECCS0
0
ECCSE1
ECCSE0
ECC Status
Page 0 Status
RESET, or at the beginning of the READ. They are then
updated after the device completes a valid READ
operation.
0
ECCS and ECCSE are invalid if internal ECC is disabled
0
(via a SET FEATURES command to reset ECC_EN to 0).
After power-on RESET, ECC status is set to reflect the
contents of block 0, page 0.
42
SPI-NAND
GD5F1GQ5xExxG
This bit indicates that a program failure has occurred
(P_FAIL set to 1). It will also be set if the user attempts to
P_FAIL
Program Fail
0
program an invalid address or a protected region,
0
including the OTP area. This bit is cleared during the
PROGRAM EXECUTE command sequence or a RESET
command (P_FAIL = 0).
This bit indicates that an erase failure has occurred
(E_FAIL set to 1). It will also be set if the user attempts to
E_FAIL
Erase Fail
0
0
erase a locked region. This bit is cleared (E_FAIL = 0) at
the start of the BLOCK ERASE command sequence or the
RESET command.
This bit indicates the current status of the write enable
latch (WEL) and must be set (WEL = 1), prior to issuing a
WEL
Write Enable
Latch
0
PROGRAM EXECUTE or BLOCK ERASE command. It is
0
set by issuing the WRITE ENABLE command. WEL can
also be disabled (WEL = 0), by issuing the WRITE
DISABLE command.
This bit is set (OIP = 1 ) when a PROGRAM EXECUTE,
OIP
Operation In
Progress
0
PAGE READ, BLOCK ERASE, or RESET command is
0
executing, indicating the device is busy. When the bit is 0,
the interface is in the ready state.
DS_IO[1]
DS_IO[0]
Driven
Strength
register
0
0
No Change
Block
BPS
Protection
IO driver strength setting. Default is 00b.
Block protection status
1
No Change
Status
BPS is 1, selected block is protected
BPS is 0, selected block is unprotected.
43
SPI-NAND
GD5F1GQ5xExxG
Figure 12-1. Get Features Sequence Diagram
CS#
SCLK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
1 byte address
Command
SI
0FH
SO
7
6
5
4
3
2
1
0
Data byte
MSB
High-Z
7
6
5
4
3
2
1
0
MSB
Figure 12-2. Set Features Sequence Diagram
CS#
SCLK
SI
0
1
2
3
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Command
1FH
SO
4
Data byte
1 byte address
7 6
MSB
5
4
3
High-Z
44
2
1
0
7
MSB
6
5
4
3
2
1
0
SPI-NAND
GD5F1GQ5xExxG
12.2 Status Register and Driver Register
The NAND Flash device has an 8-bit status register that software can read during the device operation for operation state
query. The status register can be read by issuing the GET FEATURES (0FH)command, followed by the feature address
C0h (see FEATURE OPERATION). The Output Driver Register can be set and read by issuing the SET FEATURE (0FH)
and GET FEATURE command followed by the feature address D0h (see FEATURE OPERATION).
Table 12-3. ECC Error Bits Descriptions
Description
ECCS1
ECCS0
ECCSE1
ECCSE0
0
0
x
x
No bit errors were detected during the previous read algorithm
0
1
0
0
Bit errors(=1) were detected and corrected
0
1
0
1
Bit errors (=2) were detected and corrected.
0
1
1
0
Bit errors (=3) were detected and corrected.
0
1
1
1
Bit errors (=4) were detected and corrected.
1
1
x
x
Reserved
1
0
x
x
Bit errors greater than ECC capability(4 bits) and not corrected
Table 12-4. Driver Register Bits Descriptions
DS_IO[1]
DS_IO[0]
Driver Strength
0
0
100%
0
1
75%
1
0
50%
1
1
25%
45
SPI-NAND
GD5F1GQ5xExxG
12.3 OTP Region
The serial device offers a protected, One-Time Programmable NAND Flash memory area. 4 full pages are available on
the device. Customers can use the OTP area any way they want, like programming serial numbers, or other data, for
permanent storage. When delivered from factory, feature bit OTP_PRT is 0. To access the OTP feature, the user must
set feature bits OTP_EN/OTP_PRT by SET FEATURES command. When the OTP is ready for access, pages 00h–03H
can be programmed in sequential order by PROGRAM LOAD (02H) and PROGRAM EXECUTE (10H) commands ( when
not yet protected), and read out by PAGE READ (13H) command and output data by READ from CACHE
(03H/0BH/3BH/6BH/BBH/EBH). When ECC is enabled, data written in the OTP area is ECC protected.
Table 12-5.OTP States
OTP_PRT
OTP_EN
State
x
0
Normal Operation
0
1
Access OTP region, read and program data
1
1
1. When the device power on state OTP_PRT is 0, user can set feature bit OTP_PRT and
OTP_EN to 1, then issue PROGRAM EXECUTE (10H) to lock OTP, and after that OTP_PRT
will permanently remain 1.
2. When the device power on state OTP_PRT is 1, user can only read the OTP region data
Note: The OTP space cannot be erased and after it has been protected, it cannot be programmed again, please use this
function carefully.
Access to OTP data
• Issue the SET FEATURES command (1FH)
• Set feature bit OTP_EN
• Issue the PAGE PROGRAM (only when OTP_PRT is 0) or PAGE READ command
Protect OTP region
Only when the following steps are completed, the OTP_PRT will be set and users can get this feature out with 0FH
command.
• Issue the SET FEATURES command (1FH)
• Set feature bit OTP_EN and OTP_PRT
• 06H (WRITE ENABLE)
• Issue the PROGRAM EXECUTE (10H) command.
46
SPI-NAND
GD5F1GQ5xExxG
12.4 Assistant Bad Block Management
As a NAND Flash, the device may have blocks that are invalid when shipped from the factory, and a minimum number of
valid blocks (NVB) of the total available blocks are specified. An invalid block is one that contains at least one page that
has more bad bits than can be corrected by the minimum required ECC. Additional bad blocks may develop with use.
However, the total number of available blocks will not fall below NVB during the endurance life of the product.
Although NAND Flash memory devices may contain bad blocks, they can be used reliably in systems that provide badblock management and error-correction algorithms, which ensure data integrity. Internal circuitry isolates each block from
other blocks, so the presence of a bad block does not affect the operation of the rest of the NAND Flash array.
NAND Flash devices are shipped from the factory erased. The factory identifies invalid blocks before shipping by
programming the Bad Block Mark (00h) to the first spare area location in each bad block. This method is compliant with
ONFI Factory Defect Mapping requirements. See the following table for the bad-block mark.
System software should initially check the first spare area location for non-FFH data on the first page of each block prior to
performing any program or erase operations on the NAND Flash device. A bad-block table can then be created, enabling
system software to map around these areas. Factory testing is performed under worst-case conditions. Because invalid
blocks may be marginal, it may not be possible to recover the bad-block marking if the block is erased.
To simplify the system requirement and guard the data integration, GigaDevice SPI NAND provides assistant Management
options as below.
Table 12-6. Bad Block Mark information
Description
Requirement
Minimum number of valid blocks (NVB)
1004
Total available blocks per die
1024
First spare area location
Byte 2048
Bad-block mark
00h(use non FFH to check)
47
SPI-NAND
GD5F1GQ5xExxG
12.5 Block Protection
The block lock feature provides the ability to protect the entire device, or ranges of blocks, from the PROGRAM and ERASE
operations. After power-up, the device is in the “locked” state, i.e., feature bits BP0, BP1and BP2 are set to 1, INV, CMP
and BRWD are set to 0. To unlock all the blocks, or a range of blocks, the SET FEATURES command must be issued to
alter the state of protection feature bits. When BRWD is set and WP# is LOW, none of the writable protection feature bits
can be set. Also, when a PROGRAM/ERASE command is issued to a locked block, status bit OIP remains 0. When an
ERASE command is issued to a locked block, the erase failure, status bit E_FAIL set to 1. When a PROGRAM command
is issued to a locked block, program failure, status bit P_FAIL set to 1.
To enable the Write Protection (WP#), the Quad Enable bit (QE) of feature (B0[0]) must be set to 0.
Table 12-7. Block Lock Register Block Protect Bits
CMP
INV
BP2
BP1
BP0
Protect Row Address
Protect Rows
x
x
0
0
0
None
None—all unlocked
0
0
0
0
1
FC00h～FFFFH
Upper 1/64 locked
0
0
0
1
0
F800h～FFFFH
Upper 1/32 locked
0
0
0
1
1
F000h～FFFFH
Upper 1/16 locked
0
0
1
0
0
E000h～FFFFH
Upper 1/8 locked
0
0
1
0
1
C000h～FFFFH
Upper 1/4 locked
0
0
1
1
0
8000h～FFFFH
Upper 1/2 locked
x
x
1
1
1
0000h～FFFFH
All locked (default)
0
1
0
0
1
0000h～03FFH
Lower 1/64 locked
0
1
0
1
0
0000h～07FFH
Lower 1/32 locked
0
1
0
1
1
0000h～0FFFH
Lower 1/16 locked
0
1
1
0
0
0000h～1FFFH
Lower 1/8 locked
0
1
1
0
1
0000h～3FFFH
Lower 1/4 locked
0
1
1
1
0
0000h～7FFFH
Lower 1/2 locked
1
0
0
0
1
0000h～FBFFH
Lower 63/64 locked
1
0
0
1
0
0000h～F7FFH
Lower31/32 locked
1
0
0
1
1
0000h～EFFFH
Lower 15/16 locked
1
0
1
0
0
0000h～DFFFH
Lower7/8 locked
1
0
1
0
1
0000h～BFFFH
Lower3/4 locked
1
0
1
1
0
0000h～003FH
Block0
1
1
0
0
1
0400h～FFFFH
Upper 63/64 locked
1
1
0
1
0
0800h～FFFFH
Upper31/32 locked
1
1
0
1
1
1000h～FFFFH
Upper 15/16 locked
1
1
1
0
0
2000h～FFFFH
Upper7/8 locked
1
1
1
0
1
4000h～FFFFH
Upper3/4 locked
1
1
1
1
0
0000h～003FH
Block0
When WP# is not LOW, user can issue bellows commands to alter the protection states as want.
• Issue SET FEATURES register write (1FH)
• Issue the feature bit address (A0h) and the feature bits combination as the table
48
SPI-NAND
GD5F1GQ5xExxG
12.6 Power Lock Down Protection
The Power lock down protection prevent the block protection state from software modifications. After it is enabled, this
protection cannot be disabled by a software command. Also, BP[0,2] , INV , CMP and BRWD bits are protected from further
software change. Only another power cycle can disable the Power Lock Down Protection.
When the Hardware Protection is disabled during quad or x4 mode, Power Lock Down Protection can be used to prevent
a block protection state change.
To enable the Power Lock Down Protection, perform the following command sequence:
• Issue the SET FEATURES command (with address B0H) to set the feature bit BPL to 1:
Note: This feature is available on special order. Please contact GigaDevice for details.
49
SPI-NAND
GD5F1GQ5xExxG
12.7 Internal ECC
The device offers data corruption protection by offering optional internal ECC. READs and PROGRAMs with internal ECC
can be enabled or disabled by setting feature bit ECC_EN. ECC is enabled by default when device powered on, so the
default READ and PROGRAM commands operate with internal ECC in the “active” state when ECC enable.
To enable/disable ECC, perform the following command sequence:
• Issue the SET FEATURES command (1FH) to set the feature bit ECC_EN:
1.
To enable ECC, Set ECC_EN to 1.
2.
To disable ECC, Clear ECC_EN to 0.
During a PROGRAM operation, the device calculates an ECC code on the 2k page in the cache register, before the page
is written to the NAND Flash array.
During a READ operation, the page data is read from the array to the cache register, where the ECC code is calculated
and compared with the ECC code value read from the array. If error bits are detected, the error is corrected in the cache
register. Only corrected data is output on the I/O bus. The ECC status bit indicates whether or not the error correction was
successful. The ECC Protection table below shows the ECC protection scheme used throughout a page.
The ECC protection format as follow:
• User meta data I is not protected by internal ECC and User meta data II is protected by internal ECC.
Any data wrote to the ECC parity data area are ignored when ECC enabled.
Table 12-8. The Distribution of ECC Segment and Spare Area in a Page
Main Area(2KB)
Spare Area(128B)
User data
User meta data(I+II)
ECC Parity Data
Main0
Main1
Main2
Main3
Spare0
Spare1
Spare2
Spare3
Spare0
Spare1
Spare2
Spare3
(512B)
(512B)
(512B)
(512B)
(4B+12B)
(4B+12B)
(4B+12B)
(4B+12B)
(16B)
(16B)
(16B)
(16B)
50
SPI-NAND
GD5F1GQ5xExxG
Table 12-9. ECC Protection and Spare Area
Max Byte Address
Min Byte Address
ECC Protected
Area
Description
1FFH
000H
Yes
Main 0
User data 0
3FFH
200H
Yes
Main 1
User data 1
5FFH
400H
Yes
Main 2
User data 2
7FFH
600H
Yes
Main 3
User data 3
803H
800H
No
Spare 0
User meta 0 data I(1)
80FH
804H
Yes
Spare 0
User meta 0 data II
813H
810H
No
Spare 1
User meta 1 data I
81FH
814H
Yes
Spare 1
User meta 1 data II
823H
820H
No
Spare 2
User meta 2 data I
82FH
824H
Yes
Spare 2
User meta 2 data II
833H
830H
No
Spare 3
User meta 3 data I
83FH
834H
Yes
Spare 3
User meta 3 data II
84FH
840H
Yes
Spare 0
ECC Parity Data
85FH
850H
Yes
Spare 1
ECC Parity Data
86FH
860H
Yes
Spare 2
ECC Parity Data
87FH
870H
Yes
Spare 3
ECC Parity Data
Note
1.
800H is reserved for initial bad block mark, and please check the initial bad block mark with internal ECC off.
2.
When ECC is on, user cannot program the Address 840H~87FH but user can read the Address 840H~87FH.
3.
When ECC is off, the whole page area is open for user. And we recommend the user to provide external ECC
protection.
51
SPI-NAND
13
GD5F1GQ5xExxG
POWER ON TIMING
Figure 13. Power on Timing Sequence
Vcc(max)
Chip Selection is not allowed
Vcc(min)
tVSL
Device is fully
accessible
VWI
Time
Table 13. Power-On Timing and Write Inhibit Threshold for 1.8V/3.3V
Symbol
tVSL
VWI
Parameter
Min
VCC(min) To CS# Low
Write Inhibit Voltage
Max
1
ms
1.8V
1.4
3.3V
2.5
52
Unit
V
SPI-NAND
14
GD5F1GQ5xExxG
ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
-40 to 85
Ambient Operating Temperature
℃
-40 to 105
℃
Storage Temperature
-65 to 150
Applied Input / Output Voltage
-0.6 to VCC+0.4
V
VCC(3.3V)
-0.6 to 4.0
V
VCC(1.8V)
-0.6 to 2.5
V
Figure 14. Input Test Waveform and Measurement Level
Maximum Negative Overshoot Waveform
20ns
Maximum Positive Overshoot Waveform
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
53
20ns
SPI-NAND
15
GD5F1GQ5xExxG
CAPACITANCE MEASUREMENT CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
Conditions
CIN
Input Capacitance
6
pF
VIN=0V
COUT
Output Capacitance
8
pF
VOUT=0V
CL
Load Capacitance
30
Input Rise And Fall time
pF
5
ns
Input Pulse Voltage
0.1VCC to 0.8VCC
V
Input Timing Reference Voltage
0.2VCC to 0.7VCC
V
Output Timing Reference Voltage
0.5VCC
V
Figure 15. Input Test Waveform and Measurement Level
Input timing reference level
0.8VCC
0.7VCC
0.1VCC
0.2VCC
Output timing reference level
AC Measurement Level
Note: Input pulse rise and fall time are
工商网监
湘ICP备2023018690号
