2Pai Semi
Data Sheet
Enhanced ESD, 3.0 kV rms/6.0 kV rms
10Mbps Hexa-Channel Digital Isolators
π160M/π161M/π162M/π163M
FEATURES
Ultra low power consumption (1Mbps):
0.58mA/Channel
High data rate: π16xAxx: 600Mbps
π16xExx: 200Mbps
π16xMxx: 10Mbps
π16xUxx: 150kbps
High common-mode transient immunity: 75 kV/µs typical
High robustness to radiated and conducted noise
Low propagation delay:
8 ns typical for 5 V operation
9 ns typical for 3.3 V operation
Isolation voltages:
π16xx3x: AC 3000Vrms
π16xx6x: AC 6000Vrms
High ESD rating:
ESDA/JEDEC JS-001-2017
Human body model (HBM) ±8kV, all pins
Safety and regulatory approvals (Pending)：
UL certificate number: E494497
3000Vrms/6000Vrms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate number: 40047929
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 707V peak/1200V peak
CQC certification per GB4943.1-2011
3 V to 5.5 V level translation
AEC-Q100 qualification
Wide temperature range: -40°C to 125°C
16-lead, RoHS-compliant, (W)SOIC package
The π1xxxxx isolator data channels are independent and are
available in a variety of configurations with a withstand voltage
rating of 1.5 kV rms to 6.0 kV rms and the data rate from DC up
to 600Mbps (see the Ordering Guide). The devices operate with
the supply voltage on either side ranging from 3.0 V to 5.5 V,
providing compatibility with lower voltage systems as well as
enabling voltage translation functionality across the isolation
barrier. The fail-safe state is available in which the outputs
transition to a preset state when the input power supply is not
applied.
FUNCTIONAL BLOCK DIAGRAMS
ENERAL DESCRIPTION
Intelligent voltage divider technology (iDivider technology) is a
new generation digital isolator technology invented by 2PaiSEMI.
It uses the principle of capacitor voltage divider to transmit
voltage signal directly cross the isolator capacitor without signal
modulation and demodulation.
16
VDD2
2
15
VOA
VIB
3
14
VOB
VIC
4
13
VOC
VOD
5
12
VIE
6
11
VOE
VIF
7
10
VOF
GND1
8
9
GND2
VDD1
1
16
VDD2
VIA
2
15
VOA
VIB
3
14
VOB
VIC
4
13
VOC
VID
5
12
VOD
VIE
6
11
VOE
VOF
7
10
VIF
GND1
8
9
GND 2
VDD1
1
16
VDD2
VIA
2
15
VOA
VIB
3
14
VOB
VIC
4
13
VOC
VOD
π161XXX
π162XXX
VID
5
12
VOE
6
11
VOF
7
10
1
8
9
VDD1
1
16
VDD2
VIA
2
15
VOA
VIB
3
14
VOB
VIC
4
13
VOC
VOD
5
12
VID
VOE
6
11
V IE
VOF
7
10
VIF
GND 1
8
9
GND2
GND
General-purpose multichannel isolation
Industrial field bus isolation
The π1xxxxx is a 2PaiSemi digital isolators product family that
includes over hundreds of digital isolator products. By using
maturated standard semiconductor CMOS technology and
2PaiSEMI iDivider technology, these isolation components
provide outstanding performance characteristics and reliability
superior to alternatives such as optocoupler devices and other
integrated isolators.
1
VIA
VID
APPLICATIONS
π160XXX
VDD1
π163XXX
VIE
VIF
GND 2
Figure1. π160xxx/π161xxx/π162xxx/π163xxx functional Block Diagram
VDD1
VDD2
CIN
COUT
0.1uF
0.1 uF
1
2
3
4
5
6
7
8
VIN_A
VIN_B
VIN_C
VIN_D
VIN_E
VIN_F
GND 1
VDD1
VIA
VIB
VIC
VID
VIE
VIF
GND1
VDD2
VOA
VOB
VOC
VOD
VOE
VOF
GND2
16
15
14
13
12
11
10
9
VOUT_A
VOUT_B
VOUT_C
VOUT_D
VOUT_E
VOUT_F
GND2
Figure2. π160xxx Typical Application Circuit
Rev.1
Information furnished by 2Pai semi is believed to be accurate and reliable. However, no
responsibility is assumed by 2Pai semi for its use, nor for any infringements of patents or
other rights of third parties that may result from its use. Specifications subject to change
without notice. No license is granted by implication or otherwise under any patent or
patent rights of 2Pai semi.
Trademarks and registered trademarks are the property of their respective owners.
Room 308-309, No.22, Boxia Road, Pudong New District, Shanghai, 201203, China
021-50850681
2Pai Semiconductor Co., Limited. All rights reserved.
http://www.rpsemi.com/
π160M/π161M/π162M/π163M
Data Sheet
PIN CONFIGURATIONS AND FUNCTIONS
π160Mxx Pin Function Descriptions
Pin No.
Name
Description
1
VDD1
Supply Voltage for Isolator Side 1.
2
VIA
Logic Input A.
3
VIB
Logic Input B.
4
VIC
5
VDD1 1
16 VDD2
π160
15 VOA
VIA
2
VIB
3
14 VOB
Logic Input C.
VIC
4
13 VOC
VID
Logic Input D.
VID
5
6
VIE
Logic Input E.
6
VIF
Logic Input F.
VIE
7
8
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
9
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
10
VOF
Logic Output F.
11
VOE
Logic Output E.
12
VOD
Logic Output D.
13
VOC
Logic Output C.
14
VOB
Logic Output B.
15
VOA
Logic Output A.
16
VDD2
Supply Voltage for Isolator Side 2.
TOP VIEW
(Not to scale)
VIF 7
12 VOD
11 VOE
10 VOF
GND1 8
9 GND2
Figure3. π160Mxx Pin Configuration
Figure3. π160Mxx Pin Configuration
π161Mxx Pin Function Descriptions
Pin No.
Name
Description
1
VDD1
Supply Voltage for Isolator Side 1.
2
VIA
Logic Input A.
VIA
3
VIB
Logic Input B.
VIC
Logic Input C.
VIB 3
14 VOB
4
5
VID
Logic Input D.
VIC
13 VOC
6
VIE
Logic Input E.
VID 5
7
VOF
Logic Output F.
VIE
8
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
VOF 7
9
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
10
VIF
Logic Input F.
11
VOE
Logic Output E.
12
VOD
Logic Output D.
13
VOC
Logic Output C.
14
VOB
Logic Output B.
15
VOA
Logic Output A.
16
VDD2
Supply Voltage for Isolator Side 2.
VDD1 1
2
16 VDD2
π161
4
6
GND1 8
TOP VIEW
(Not to scale)
15 VOA
12 VOD
11 VOE
10 VIF
9 GND2
Figure4. π161Mxx Pin Configuration
Figure8. π121x6 Pin Configuration
Rev. 1 | Page 2 of 16
π160M/π161M/π162M/π163M
Data Sheet
π162Mxx Pin Function Descriptions
Pin No.
Name
Description
1
VDD1
Supply Voltage for Isolator Side 1.
2
VIA
Logic Input A.
VIA 2
3
VIB
Logic Input B.
VIB
3
14 VOB
4
VIC
Logic Input C.
VIC
4
VID
Logic Input D.
13 VOC
5
6
VOE
Logic Output E.
VID
5
7
VOF
Logic Output F.
VOE 6
8
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
VOF 7
9
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
GND1 8
10
VIF
Logic Input F.
11
VIE
Logic Input E.
12
VOD
Logic Output D.
13
VOC
Logic Output C.
14
VOB
Logic Output B.
15
VOA
Logic Output A.
16
VDD2
Supply Voltage for Isolator Side 2.
VDD1 1
16 VDD2
π162
TOP VIEW
(Not to scale)
15 VOA
12 VOD
11 VIE
10 VIF
9 GND2
Figure5. π162Mxx Pin Configuration
Figure9. π122x6 Pin Configuration
π163Mxx Pin Function Descriptions
Pin No.
Name
Description
1
VDD1
Supply Voltage for Isolator Side 1.
2
VIA
Logic Input A.
VIA
2
3
VIB
Logic Input B.
VIB
3
14 VOB
4
VIC
Logic Input C.
VIC
4
VOD
Logic Output D.
13 VOC
5
6
VOE
Logic Output E.
7
VOF
Logic Output F.
VOE 6
8
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
VOF 7
9
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
GND1 8
10
VIF
Logic Input F.
11
VIE
Logic Input E.
12
VID
Logic Input D.
13
VOC
Logic Output C.
14
VOB
Logic Output B.
15
VOA
Logic Output A.
16
VDD2
Supply Voltage for Isolator Side 2.
VDD1 1
VOD 5
16 VDD2
π163
TOP VIEW
(Not to scale)
15 VOA
12 VID
11 VIE
10 VIF
9 GND2
Figure6. π163Mxx Pin Configuration
Figure9. π122x6 Pin Configuration
Rev. 1 | Page 3 of 16
π160M/π161M/π162M/π163M
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 1. Absolute Maximum Ratings4
Parameter
Rating
Supply Voltages (VDD1-GND1, VDD2-GND2)
Input Voltages
−0.5 V to +7.0 V
(VIA, VIB)1
Output Voltages
−0.5 V to VDDx + 0.5 V
(VOA, VOB)1
−0.5 V to VDDx + 0.5 V
Average Output Current per Pin2 Side 1 Output Current (IO1)
−10 mA to +10 mA
Average Output Current per Pin2 Side 2 Output Current (IO2)
−10 mA to +10 mA
Common-Mode Transients
Immunity 3
−150 kV/µs to +150 kV/µs
Storage Temperature (TST) Range
−65°C to +150°C
Ambient Operating Temperature (TA) Range
−40°C to +125°C
Notes:
1 VDDx is the side voltage power supply VDD, where x = 1 or 2.
2 See Figure7 for the maximum rated current values for various temperatures.
3 See Figure21 for Common-mode transient immunity (CMTI) measurement.
4 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating
conditions for extended periods may affect product reliability.
RECOMMENDED OPERATING CONDITIONS
Table 2. Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
Min
VDDx 1
3
High Level Input Signal Voltage
VIH
0.7*VDDx
Low Level Input Signal Voltage
VIL
0
High Level Output Current
IOH
-6
Low Level Output Current
IOL
Maximum Data Rate
Typ
1
Max
Unit
5.5
V
VDDx
1
0.3*VDDx
V
1
V
mA
6
mA
0
10
Mbps
Junction Temperature
TJ
-40
150
°C
Ambient Operating Temperature
TA
-40
125
°C
Notes:
1 VDDx is the side voltage power supply VDD, where x = 1 or 2.
Truth Tables
Table 3. π160xxx/π161xxx/π162xxx/π163xxx Truth Table
Default Low
Default High
VOx Output1
VOx Output1
Test Conditions
/Comments
Powered2
Low
Low
Normal operation
Powered2
High
High
Normal operation
Open
Powered2
Powered2
Low
High
Default output
Don’t Care4
Unpowered3
Powered2
Low
High
Default output5
Don’t Care4
Powered2
Unpowered3
High Impedance
High Impedance
VIx Input1
VDDI State1
VDDO State1
Low
Powered2
High
Powered2
Notes:
1 VIx/VOx are the input/output signals of a given channel (A or B). VDDI/VDDO are the supply voltages on the input/output signal sides of this given channel.
Rev. 1 | Page 4 of 16
π160M/π161M/π162M/π163M
Data Sheet
2 Powered
means VDDx≥ 2.9 V
means VDDx < 2.3V
4 Input signal (VIx) must be in a low state to avoid powering the given VDDI1 through its ESD protection circuitry.
5 If the VDDI goes into unpowered status, the channel outputs the default logic signal after around 1us. If the VDDI goes into powered status, the channel outputs the input
status logic signal after around 1us.
3 Unpowered
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Table 4. Switching Specifications
VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, unless otherwise noted.
Parameter
Minimum Pulse Width
Symbol
Pulse Width Distortion4
Part to Part Propagation Delay
Skew4
Channel to Channel Propagation
Delay Skew4
Typ
PW
Maximum Data Rate
Propagation Delay Time1,4
Min
Max
100
10
tpHL, tpLH
PWD
Test Conditions/Comments
ns
Within pulse width distortion (PWD) limit
Mbps
Within PWD limit
5.5
8
12.5
ns
The different time between 50% input signal to
50% output signal 50% @ 5VDC supply
6.5
9
13.5
ns
@ 3.3VDC supply
0
0.3
0.8
ns
The max different time between tpHL and tpLH@
5VDC supply. And The value is | tpHL - tpLH |
0
0.3
0.8
ns
@ 3.3VDC supply
1
ns
The max different propagation delay time
between any two devices at the same
temperature, load and voltage @ 5VDC supply
1
ns
0
1
ns
0
0.8
ns
tPSK
tCSK
Unit
@ 3.3VDC supply
The max amount propagation delay time
differs between any two output channels in
the single device @ 5VDC supply.
@ 3.3VDC supply
Output Signal Rise/Fall Time4
tr/tf
1.5
Dynamic Input Supply Current per
Channel
IDDI (D)
9
µA
/Mbps
10% to 90% signal terminated 50，See
figure17.
Inputs switching, 50% duty cycle square wave,
CL = 0 pF @ 5VDC Supply
Dynamic Output Supply Current
per Channel
IDDO (D)
38
µA
/Mbps
Inputs switching, 50% duty cycle square wave,
CL = 0 pF @ 5VDC Supply
Dynamic Input Supply Current per
Channel
IDDI (D)
5
µA
/Mbps
Inputs switching, 50% duty cycle square wave,
CL = 0 pF @ 3.3VDC Supply
Dynamic Output Supply Current
per Channel
IDDO (D)
23
µA
/Mbps
Inputs switching, 50% duty cycle square wave,
CL = 0 pF @ 3.3VDC Supply
Common-Mode Transient
Immunity3
CMTI
75
kV/µs
VIN = VDDx2 or 0V, VCM = 1000 V
120
ps p-p
See the Jitter Measurement section
20
ps rms
See the Jitter Measurement section
±8
kV
All pins
Jitter
ESD（HBM - Human body
model）
ESD
ns
Notes:
1 tpLH = low-to-high propagation delay time, tpHL = high-to-low propagation delay time. See figure 18.
2V
DDx is the side voltage power supply VDD, where x = 1 or 2.
3 See Figure21 for Common-mode transient immunity (CMTI) measurement.
4 Output Signal Terminated 50
Rev. 1 | Page 5 of 16
π160M/π161M/π162M/π163M
Data Sheet
Table 5. DC Specifications
VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, unless otherwise noted.
Symbol
Rising Input Signal Voltage
Threshold
Falling Input Signal Voltage
Threshold
High Level Output Voltage
VIT+
Low Level Output Voltage
VOL
Input Current per Signal
Channel
VDDx1 Undervoltage Rising
Threshold
VDDx1 Undervoltage Falling
Threshold
VDDx1 Hysteresis
Min
Typ
Max
0.6*VDDx
1
0.7*VDDx
Unit
1
Test Conditions/Comments
V
VIT-
0.3* VDDX1
0.4* VDDX1
V
VOH 1
VDDx − 0.1
VDDx
V
−20 µA output current
VDDx − 0.2
VDDx − 0.1
V
−2 mA output current
0
0.1
V
20 µA output current
0.1
0.2
V
2 mA output current
0 V ≤ Signal voltage ≤ VDDX1
IIN
−10
0.5
10
µA
VDDxUV+
2.45
2.65
2.9
V
VDDxUV−
2.3
2.5
2.75
V
VDDxUVH
0.15
V
Notes:
1 VDDx is the side voltage power supply VDD, where x = 1 or 2.
Table 6. Quiescent Supply Current
VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, CL = 0 pF, unless otherwise noted.
Parameter
π160Mxx Quiescent Supply Current @ 5VDC Supply
@ 3.3VDC Supply
π161Mxx Quiescent Supply Current @ 5VDC Supply
@ 3.3VDC Supply
π162Mxx Quiescent Supply Current @ 5VDC Supply
@ 3.3VDC Supply
Symbol
Min
Typ
Max
Unit
Test Conditions
IDD1 (Q)
192
240
312
µA
0V Input signal
IDD2 (Q)
2342
2928
3806
µA
0V Input signal
IDD1 (Q)
473
591
768
µA
5V Input signal
IDD2 (Q)
2215
2769
3600
µA
5V Input signal
IDD1 (Q)
190
237
308
µA
0V Input signal
IDD2 (Q)
2316
2895
3764
µA
0V Input signal
IDD1 (Q)
348
435
566
µA
3.3V Input signal
IDD2 (Q)
2126
2658
3455
µA
3.3V Input signal
IDD1 (Q)
547
684
889
µA
0V Input signal
IDD2 (Q)
1981
2476
3219
µA
0V Input signal
IDD1 (Q)
751
939
1221
µA
5V Input signal
IDD2 (Q)
1913
2391
3108
µA
5V Input signal
IDD1 (Q)
541
676
879
µA
0V Input signal
IDD2 (Q)
1958
2448
3182
µA
0V Input signal
IDD1 (Q)
640
800
1040
µA
3.3V Input signal
IDD2 (Q)
1826
2282
2967
µA
3.3V Input signal
IDD1 (Q)
902
1128
1466
µA
0V Input signal
IDD2 (Q)
1619
2024
2631
µA
0V Input signal
IDD1 (Q)
IDD2 (Q)
1030
1610
1287
2013
1673
2617
µA
µA
5V Input signal
5V Input signal
IDD1 (Q)
892
1115
1450
µA
0V Input signal
IDD2 (Q)
1601
2001
2601
µA
0V Input signal
IDD1 (Q)
932
1165
1515
µA
3.3V Input signal
Rev. 1 | Page 6 of 16
π160M/π161M/π162M/π163M
Data Sheet
IDD2 (Q)
π163Mxx Quiescent Supply Current @ 5VDC Supply
@ 3.3VDC Supply
1525
1906
2478
µA
3.3V Input signal
IDD1 (Q)
1258
1572
2044
µA
0V Input signal
IDD2 (Q)
1258
1572
2044
µA
0V Input signal
IDD1 (Q)
IDD2 (Q)
1308
1308
1635
1635
2126
2126
µA
µA
5V Input signal
5V Input signal
IDD1 (Q)
1243
1554
2020
µA
0V Input signal
IDD2 (Q)
1243
1554
2020
µA
0V Input signal
IDD1 (Q)
1224
1530
1989
µA
3.3V Input signal
IDD2 (Q)
1224
1530
1989
µA
3.3V Input signal
Table 7. Total Supply Current vs. Data Throughput (CL = 0 pF)
VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, CL = 0 pF, unless otherwise noted.
Parameter
Symbol
π160Mxx Supply Current @ 5VDC
@ 3.3VDC
π161Mxx Supply Current @ 5VDC
@ 3.3VDC
π162Mxx Supply Current @ 5VDC
@ 3.3VDC
π163Mxx Supply Current @ 5VDC
@ 3.3VDC
150 Kbps
Min
Typ
Max
IDD1
0.42
IDD2
1 Mbps
Min
10 Mbps
Typ
Max
0.63
0.45
2.85
4.28
IDD1
0.33
IDD2
Min
Typ
Max
Unit
0.68
0.72
1.08
mA
3.06
4.59
5.28
7.92
mA
0.50
0.36
0.54
0.54
0.81
mA
2.79
4.19
2.91
4.37
4.29
6.44
mA
IDD1
0.82
1.23
0.88
1.32
1.45
2.18
mA
IDD2
2.44
3.66
2.62
3.93
4.49
6.74
mA
IDD1
0.74
1.11
0.78
1.17
1.13
1.70
mA
IDD2
2.38
3.57
2.48
3.72
3.63
5.45
mA
IDD1
1.22
1.83
1.31
1.97
2.18
3.27
mA
IDD2
2.03
3.05
2.18
3.27
3.70
5.55
mA
IDD1
1.15
1.73
1.20
1.80
1.72
2.58
mA
IDD2
1.97
2.96
2.05
3.08
2.97
4.46
mA
IDD1
1.62
2.43
1.74
2.61
2.91
4.37
mA
IDD2
1.62
2.43
1.74
2.61
2.91
4.37
mA
IDD1
1.56
2.34
1.62
2.43
2.31
3.47
mA
IDD2
1.56
2.34
1.62
2.43
2.31
3.47
mA
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 8. Insulation Specifications
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap
(Clearance)
Minimum External Tracking
(Creepage)
Minimum Internal Gap (Internal
Clearance)
Tracking Resistance (Comparative
Tracking Index)
Material Group
Symbol
Value
Unit
Test Conditions/Comments
π16xM3x
π16xM6x
3000
6000
L (CLR)
4
8
mm min
L (CRP)
4
8
mm min
11
21
µm min
Insulation distance through insulation
>400
>400
V
DIN IEC 112/VDE 0303 Part 1
II
II
CTI
V rms
Rev. 1 | Page 7 of 16
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Material Group (DIN VDE 0110, 1/89, Table 1)
π160M/π161M/π162M/π163M
Data Sheet
PACKAGE CHARACTERISTICS
Table 9. Package Characteristics
Parameter
Symbol
Typical Value
π16xM3x
π16xM6x
Unit
Test Conditions/Comments
Resistance (Input to Output)1
RI-O
10 11
10 11
Ω
Capacitance (Input to Output)1
CI-O
0.6
0.6
pF
@1MHz
CI
3
3
pF
@1MHz
θJA
76
45
°C/W
Thermocouple located at center
of package underside
Input
Capacitance2
IC Junction to Ambient Thermal
Resistance
Notes:
1The device is considered a 2-terminal device; SOIC-16 Pin 1 - Pin 8(WSOIC-16 Pin 1-Pin8) are shorted together as the one terminal, and SOIC-16 Pin 9 - Pin 16(WSOIC-16
Pin 9-Pin16) are shorted together as the other terminal.
2Testing from the input signal pin to ground.
REGULATORY INFORMATION
See Table 10 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross
isolation waveforms and insulation levels.
Table10. Regulatory
π16xM3x
Regulatory
UL
CSA
π16xM6x
Recognized under UL 1577
Recognized under UL 1577
Component Recognition Program1
Component Recognition Program1
Single Protection, 3000 V rms Isolation Voltage
Single Protection, 6000 V rms Isolation Voltage
File (E494497)
File (pending)
Approved under CSA Component Acceptance Notice 5A
Approved under CSA Component Acceptance Notice 5A
CSA 60950-1-07+A1+A2 and
CSA 60950-1-07+A1+A2 and
IEC 60950-1, second edition, +A1+A2:
IEC 60950-1, second edition, +A1+A2:
Basic insulation at 500 V rms (707 V peak)
Basic insulation at 845 V rms (1200 V peak)
Reinforced insulation at 250 V rms
Reinforced insulation at 422 V rms
(353 V peak)
(600 V peak)
File (pending)
VDE
CQC
DIN V VDE V 0884-10 (VDE V
File (pending)
0884-10):2006-122
DIN V VDE V 0884-10 (VDE V 0884-10):2006-122
Basic insulation, VIORM = 707 V peak, VIOSM = 4615 V peak
Basic insulation, VIORM = 1200 V peak, VIOSM = 7000 V peak
File (40047929)
File (pending)
Certified under
Certified under
CQC11-471543-2012
CQC11-471543-2012
GB4943.1-2011
GB4943.1-2011
Basic insulation at 500 V rms (707 V peak) working voltage
Basic insulation at 845 V rms (1200 V peak) working voltage
Reinforced insulation at
Reinforced insulation at
250 V rms (353 V peak)
422 V rms (600 V peak)
File (pending)
File (pending)
Notes:
1 In accordance with UL 1577, each π160M3x/π161M3x/π162M3x /π163M3xis proof tested by applying an insulation test voltage ≥ 3600 V rms for 1 sec; each
π160M6x/π161M6x/π162M6x /π163M6xis proof tested by applying an isulation test voltage ≥ 7200 V rms for 1 sec
2 In accordance with DIN V VDE V 0884-10, eachπ160M3x/π161M3x/π162M3x /π163M3x is proof tested by applying an insulation test voltage ≥ 1326 V peak for 1 sec
(partial discharge detection limit = 5 pC); each π160M6x/π161M6x/π162M6x /π163M6x is proof tested by ≥ 2250 V peak for 1 sec. The * marking branded on the
component designates DIN V VDE V 0884-10 approval.
Rev. 1 | Page 8 of 16
π160M/π161M/π162M/π163M
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance
of the safety data. The * marking on packages denotes DIN V VDE V 0884-10 approval.
Table 11. VDE Insulation Characteristics
Description
Test Conditions/Comments
Symbol
Characteristic
π16xx3x
π16xx6x
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
I to IV
I to IV
I to III
I to III
For Rated Mains Voltage ≤ 400 V rms
I to III
I to III
40/105/21
40/105/21
2
2
Unit
Installation Classification per DIN VDE 0110
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
VIORM
707
1200
V peak
VIORM × 1.875 = Vpd (m), 100% production
test, tini = tm = 1 sec, partial discharge <
5 pC
Vpd (m)
1326
2250
V peak
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10
sec, partial discharge < 5 pC
Vpd (m)
1061
1800
V peak
849
1440
V peak
VIOTM
4200
8500
V peak
4615
7000
V peak
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10
sec, partial discharge < 5 pC
Surge Isolation Voltage Basic
Basic insulation, 1.2 µs rise time, 50 µs,
50% fall time
VIOSM
Surge Isolation Voltage Reinforced
Reinforced insulation, 1.2 µs rise time,
50 µs, 50% fall time
VIOSM
Safety Limiting Values
Maximum value allowed in the event of
a failure (see Figure 7)
Maximum Junction Temperature
TS
Total Power Dissipation at 25°C
Insulation Resistance at TS
π16xM3x
VIO = 800 V
V peak
150
°C
PS
1.56
2.78
W
RS
>109
>109
Ω
π16xM6x
Figure7. Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per VDE
Rev. 1 | Page 9 of 16
150
π160M/π161M/π162M/π163M
3
12.0
2.9
Propagation Delay Time(nS)
Power Supply Undervoltage Threshold
Data Sheet
2.8
2.7
2.6
2.5
VDDxUV+(V）
VDDxUV−(V）
2.4
2.3
2.2
10.0
8.0
6.0
tpHL(ns)@3.3V
tpLH(ns)@3.3V
tpHL(ns)@5.0V
tpLH(ns)@5.0V
4.0
2.0
0.0
0
50
100
150
0
50
Free-Air Temperature ( °C)
2
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 3.3V Input
IDD2@ 3.3V Input
0.5
0
0
50
100
150
Free-Air Temperature ( °C)
π160Mxx Quiescent Supply Current
(mA)
π160Mxx Quiescent Supply Current
(mA)
Figure9. Propagation Delay Time vs. Free-Air Temperature
2.5
1
2
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 3.3V Input
IDD2@ 3.3V Input
1
0.5
0
0
50
100
2.5
2
1.5
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 5V Input
IDD2@ 5V Input
1
0.5
0
0
50
100
150
Free-Air Temperature ( °C)
Figure11. π160Mxx Quiescent Supply Current with 5.0V
Supply vs. Free-Air Temperature
150
Free-Air Temperature ( °C)
Figure12. π161Mxx Quiescent Supply Current with 3.3V
Supply vs. Free-Air Temperature
π161Mxx Quiescent Supply Current
(mA)
π161Mxx Quiescent Supply Current
(mA)
Figure10. π160Mxx Quiescent Supply Current with 3.3V
Supply vs. Free-Air Temperature
1.5
150
Free-Air Temperature ( °C)
Figure8. UVLO vs. Free-Air Temperature
1.5
100
2
1.5
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 5V Input
IDD2@ 5V Input
1
0.5
0
0
50
100
150
Free-Air Temperature ( °C)
Figure13. π161Mxx Quiescent Supply Current with 5.0V
Supply vs. Free-Air Temperature
Rev. 1 | Page 10 of 16
π160M/π161M/π162M/π163M
π162Mxx Quiescent Supply Current
(mA)
1.6
1.4
1.2
1
0.8
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 3.3V Input
IDD2@ 3.3V Input
0.6
0.4
0.2
0
0
50
100
150
Free-Air Temperature ( °C)
Figure14. π162Mxx Quiescent Supply Current with 3.3V
Supply vs. Free-Air Temperature
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 5V Input
IDD2@ 5V Input
0
50
100
150
Free-Air Temperature ( °C)
Figure15. π162Mxx Quiescent Supply Current with 5.0V
Supply vs. Free-Air Temperature
1.4
π163Mxx Quiescent Supply Current
(mA)
π162Mxx Quiescent Supply Current
(mA)
Data Sheet
1.2
1
0.8
@3.3V Supply with 0V Input
0.6
@3.3V Supply with 3.3V Input
0.4
@5V Supply with 0V Input
@5V Supply with 5V Input
0.2
0
0
50
100
150
Free-Air Temperature ( °C)
Figure16. π163Mxx Quiescent Supply Current vs. Free-Air
Temperature
VDDX
Figure17. Transition time waveform measurement
Figure18. Propagation delay time waveform measurement
Rev. 1 | Page 11 of 16
π160M/π161M/π162M/π163M
Data Sheet
APPLICATIONS INFORMATION
the closer the better. The return path will couple between the
nearest ground plane to the signal path. Keep suitable trace width
for controlled impedance transmission lines interconnect.
OVERVIEW
The π1xxxxx are 2PaiSemi digital isolators product family based
on 2PaiSEMI unique iDivider technology. Intelligent voltage
Divider technology (iDivider technology) is a new generation
digital isolator technology invented by 2PaiSEMI. It uses the
principle of capacitor voltage divider to transmit signal directly
cross the isolator capacitor without signal modulation and
demodulation. Compare to the traditional Opto-couple
technology, icoupler technology, OOK technology, iDivider is a
more essential and concise isolation signal transmit technology
which leads to greatly simplification on circuit design and
therefore significantly improves device performance, such as
lower power consumption, faster speed, enhanced antiinterference ability, lower noise.
By using maturated standard semiconductor CMOS technology
and the innovative iDivider design, these isolation components
provide outstanding performance characteristics and reliability
superior to alternatives such as optocoupler devices and other
integrated isolators. The π1xxxxx isolator data channels are
independent and are available in a variety of configurations with
a withstand voltage rating of 1.5 kV rms to 6.0 kV rms and the
data rate from DC up to 600Mbps (see the Ordering Guide).
The π160Mxx/π161Mxx/π162Mxx/π163Mxx are the outstanding
10 Mbps hexa-channel digital isolators with the enhanced ESD
capability. the devices transmit data across an isolation barrier by
layers of silicon dioxide isolation.
The devices operate with the supply voltage on either side
ranging from 3.0 V to 5.5 V, offering voltage translation of 3.3 V
and 5 V logic.
The π160Mxx/π161Mxx/π162Mxx/π163Mxx have very low
propagation delay and high speed. The input/output design
techniques allow logic and supply voltages over a wide range
from 3.0 V to 5.5 V, offering voltage translation of 3.3 V and 5 V
logic. The architecture is designed for high common-mode
transient immunity and high immunity to electrical noise and
magnetic interference.
To reduce the rise time degradation, keep the length of
input/output signal traces as short as possible, and route low
inductance loop for the signal path and It’s return path.
VDD1
VIA
VIB
VIC
VID/VOD
VIE/VOE
VIF/VOF
VDD2
VOA
VOB
VOC
VOD/VID
VOE/VIE
VOF/VIF
GND1
GND2
Figure19.Recommended Printed Circuit Board Layout
JITTER MEASUREMENT
The eye diagram shown in the figure18 provides the jitter
measurement
result
for
the
π160Mxx/π161Mxx/π162Mxx/π163Mxx.
The
Keysight
81160A pulse function arbitrary generator works as the data
source for the π160Mxx/π161Mxx/π162Mxx/π163Mxx, which
generates 10Mbps pseudo random bit sequence (PRBS). The
Keysight DSOS104A digital storage oscilloscope captures the
π160Mxx/π161Mxx/π162Mxx/π163Mxx output waveform and
recoveries the eye diagram with the SDA tools and eye diagram
analysis tools. The result shows a typical measurement 120ps
p-p jitter.
See the Ordering Guide for the model numbers that have the failsafe output state of low or high.
Figure20. π160Mxx/π161Mxx/π162Mxx/π163Mxx Eye Diagram
PCB LAYOUT
The low-ESR ceramic bypass capacitors must be connected
between VDD1 and GND1 and between VDD2 and GND2. The
bypass capacitors are placed on the PCB as close to the isolator
device as possible. The recommended bypass capacitor value is
between 0.1 μF and 10 μF. To enhance the robustness of a design,
the user may also include resistors (50–300 Ω) in series with the
inputs and outputs if the system is excessively noisy.
CMTI MEASUREMENT
To measure the Common-Mode Transient Immunity (CMTI) of
π1xxxxx isolator under specified common-mode pulse magnitude
Avoid reducing the isolation capability, Keep the space
underneath the isolator device free from metal such as planes,
pads, traces and vias.
To minimize the impedance of the signal return loop, keep the
solid ground plane directly underneath the high-speed signal path,
Rev. 1 | Page 12 of 16
Figure21. Common-mode transient immunity (CMTI) measurement
π160M/π161M/π162M/π163M
Data Sheet
(VCM) and specified slew rate of the common-mode pulse
(dVCM/dt) and other specified test or ambient conditions, The
common-mode pulse generator (G1) will be capable of providing
fast rising and falling pulses of specified magnitude and duration
of the common-mode pulse (VCM) and the maximum common-
mode slew rates (dVCM/dt) can be applied to π1xxxxx isolator
coupler under measurement. The common-mode pulse is applied
between one side ground GND1 and the other side ground GND2
of π1xxxxx isolator and shall be capable of providing positive
transients as well as negative transients.
OUTLINE DIMENSIONS
Figure22. 16-Lead Standard Small Outline Package [16-Lead SOIC_N]
Figure23. 16-Lead Wide Body Outline Package [16-Lead SOIC_W]
Rev. 1 | Page 13 of 16
π160M/π161M/π162M/π163M
Data Sheet
REEL INFORMATION
16-Lead SOIC_N
16-Lead SOIC_W
Rev. 1 | Page 14 of 16
π160M/π161M/π162M/π163M
Data Sheet
ORDERING GUIDE
Model Name
Temperature
Range
No. of
Inputs,
VDD1
Side
No. of
Inputs,
VDD2
Side
Withstand
Voltage
Rating (kV
rms)
FailSafe
Output
State
Package
Description
Package
Option
Quantity
π160M31
Pai160M31
−40°C to +125°C
6
0
3
High
16-Lead SOIC_N
S-16-N
2500 per reel
π160M30
Pai160M30
−40°C to +125°C
6
0
3
Low
16-Lead SOIC_N
S-16-N
2500 per reel
π161M31
Pai161M31
−40°C to +125°C
5
1
3
High
16-Lead SOIC_N
S-16-N
2500 per reel
π161M30
Pai161M30
−40°C to +125°C
5
1
3
Low
16-Lead SOIC_N
S-16-N
2500 per reel
π162M31
Pai162M31
−40°C to +125°C
4
2
3
High
16-Lead SOIC_N
S-16-N
2500 per reel
π162M30
Pai162M30
−40°C to +125°C
4
2
3
Low
16-Lead SOIC_N
S-16-N
2500 per reel
π163M31
Pai163M31
−40°C to +125°C
3
3
3
High
16-Lead SOIC_N
S-16-N
2500 per reel
π163M30
Pai163M30
−40°C to +125°C
3
3
3
Low
16-Lead SOIC_N
S-16-N
2500 per reel
π160M61
Pai160M61
−40°C to +125°C
6
0
6
High
16-Lead SOIC_W
S-16-W
1500 per reel
π160M60
Pai160M60
−40°C to +125°C
6
0
6
Low
16-Lead SOIC_W
S-16-W
1500 per reel
π161M61
Pai161M61
−40°C to +125°C
5
1
6
High
16-Lead SOIC_W
S-16-W
1500 per reel
π161M60
Pai161M60
−40°C to +125°C
5
1
6
Low
16-Lead SOIC_W
S-16-W
1500 per reel
π162M61
Pai162M61
−40°C to +125°C
4
2
6
High
16-Lead SOIC_W
S-16-W
1500 per reel
π162M60
Pai162M60
−40°C to +125°C
4
2
6
Low
16-Lead SOIC_W
S-16-W
1500 per reel
π163M61
Pai163M61
−40°C to +125°C
3
3
6
High
16-Lead SOIC_W
S-16-W
1500 per reel
π163M60
Pai163M60
−40°C to +125°C
3
3
6
Low
16-Lead SOIC_W
S-16-W
1500 per reel
Notes:
1 π16xxxxQ special for Auto, qualified for AEC-Q100
PART NUMBER NAMED RULE
π(1)(2)(0)(A)(3)(0)(S)
SeriesNumber:
1,2,3...
Total Channel Am ount:
N=N Channels N=1,2,3,4,5,6...
Reverse Channel Amount:
N=N Channels N=0,1,2,3...
Data Rate:A=600Mbps
E=200Mbps
M=10Mbps
U=150Kbps
Isolation Voltag es:
N=1
1.5KVrms AC
N=3
3KVrms AC
N=6
6KVrms AC
Fail-Safe Output Stat e:
0=Logic Low
1=Logic High
Optional：
S=SSOP Package
Q=AEC-Q100 Qualified
Notes:Pai16xxxx is equals to π16xxxx in the customer BOM
Rev. 1 | Page 15 of 16
π160M/π161M/π162M/π163M
Data Sheet
REVISION HISTORY
Revision
Updated
Date
Page
1
Devin
2018/09/19
All
2
Devin
2018/11/28
P1,P12
3
Devin
2019/09/08
P1,P13,
P15,P16
Change Record
Initial version
Changed CIN，COUT in Figure2 from 0.1uF to 1uF.
Changed the recommended bypass capacitor value from between 0.1 μF and 1 μF to
between 0.1 μF and 10 μF.
P1: Changed the address from ‘Room 19307, Building 8, No.498, GuoShouJing Road’ to
‘Room 308-309, No.22, Boxia Road’; Add iDivider technology description in General
Description.
Changed propagation delay for 5V from 7.5ns to 8ns.
Changed CMTI from 50KV/us to 75KV/us.
Changed CIN，COUT in Figure2 from 1uF to 0.1uF.
P13: Add iDivider technology description in overview.
P15: Updated 16-Lead SOIC_W reel drawing.
P16: Add character ‘S’ and ‘Q’ in part number named rule; Changed the SOIC_W
quantity from ‘1000 per reel’ to ‘1500 per reel’.
Rev. 1 | Page 16 of 16
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