M0519SD3AE

M0519 ARM® Cortex® -M0 32-bit Microcontroller NuMicro® Family M0519 Series Datasheet Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com Jul. 31, 2015 Page 1 of 69 Rev 1.01 M0519 DATASHEET The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. M0519 Table of Contents 1 GENERAL DESCRIPTION ....................................................................... 6 2 FEATURES ......................................................................................... 7 3 ABBREVIATIONS ................................................................................ 10 4 PARTS INFORMATION LIST AND PIN CONFIGURATION .............................. 12 4.1 NuMicro® M0519 Selection Guide..................................................................12 4.2 Pin Configuration......................................................................................13 4.3 Pin Description ........................................................................................16 5 BLOCK DIAGRAM ............................................................................... 23 6 FUNCTIONAL DESCRIPTION ................................................................. 24 M0519 DATASHEET 6.1 ARM® Cortex® -M0 Core..............................................................................24 6.2 System Manager ......................................................................................26 6.3 Clock Controller .......................................................................................35 6.4 Flash Memory Controller (FMC) ....................................................................38 6.5 General Purpose I/O (GPIO) ........................................................................39 6.6 Timer Controller (TIMER) ............................................................................40 6.7 Basic PWM Generator and Capture Timer (BPWM) ............................................41 6.8 Enhanced PWM Generator (EPWM) ..............................................................42 6.9 Enhanced Input Capture Timer (ECAP) ...........................................................43 6.10 Watchdog Timer (WDT)..............................................................................44 6.11 Window Watchdog Timer (WWDT) ................................................................45 6.12 Universal Asynchronous Receiver Transmitter (UART) ........................................46 6.13 I2C Serial Interface Controller (I²C) ................................................................47 6.14 Serial Peripheral Interface (SPI) ....................................................................48 6.15 Hardware Divider (HDIV) ............................................................................49 6.16 Enhanced Analog-to-Digital Converter (EADC) ..................................................50 6.17 Analog Comparator (ACMP) ........................................................................51 6.18 OP Amplifier (OPA) ...................................................................................52 ELECTRICAL CHARACTERISTICS .......................................................... 53 7 7.1 Absolute Maximum Ratings .........................................................................53 7.2 DC Electrical Characteristics ........................................................................54 7.3 AC Electrical Characteristics ........................................................................58 7.4 Analog Characteristics ...............................................................................60 Jul. 31, 2015 Page 2 of 69 Rev 1.01 M0519 7.5 PACKAGE DIMENSIONS ...................................................................... 65 8 9 Flash DC Electrical Characteristics ................................................................64 8.1 LQFP 100V (14x14x1.4 mm footprint 2.0mm) ...................................................65 8.2 LQFP 64S (7x7x1.4 mm footprint 2.0 mm) .......................................................66 8.3 LQFP 48L (7x7x1.4mm footprint 2.0mm) .........................................................67 REVISION HISTORY ............................................................................ 68 M0519 DATASHEET Jul. 31, 2015 Page 3 of 69 Rev 1.01 M0519 List of Figures ® Figure 4-1 NuMicro M0519 Selection Code ................................................................................. 12 ® Figure 4-2 NuMicro M0519VxxAE Series LQFP-100 Pin Diagram .............................................. 13 ® Figure 4-3 NuMicro M0519SxxAE Series LQFP-64 Pin Diagram ................................................ 14 ® Figure 4-4 NuMicro M0519LxxAE Series LQFP-48 Pin Diagram ................................................ 15 ® Figure 5-1 NuMicro M0519 Series Block Diagram ....................................................................... 23 Figure 6-1 Functional Controller Diagram ...................................................................................... 24 ® Figure 6-2 NuMicro M0519 Series Power Distribution Diagram .................................................. 27 Figure 6-3 Clock Generator Block Diagram ................................................................................... 36 Figure 6-4 Clock Generator Global View Diagram ......................................................................... 37 Figure 7–1 Typical Crystal Application Circuit ............................................................................... 58 M0519 DATASHEET Jul. 31, 2015 Page 4 of 69 Rev 1.01 M0519 List of Tables Table 6-1 Address Space Assignments for On-Chip Controllers ................................................... 29 Table 6-2 Exception Model ............................................................................................................ 32 Table 6-3 System Interrupt Map Vector Table ............................................................................... 33 Table 6-4 Vector Table ................................................................................................................... 34 Table 6-5 Clock Stable Count Value Table .................................................................................... 35 M0519 DATASHEET Jul. 31, 2015 Page 5 of 69 Rev 1.01 M0519 1 GENERAL DESCRIPTION ® ® ® The NuMicro M0519 Series 32-bit microcontroller is embedded with the newest ARM Cortex M0 core at a cost equivalent to traditional 8-bit microcontroller for industrial control and applications which need high performance. ® ® The NuMicro M0519 Series embedded with the Cortex -M0 core runs up to 72 MHz and supports a variety of industrial control and applications which need high CPU performance. The ® NuMicro M0519 Series provides 128K/64K bytes embedded flash, 4 Kbytes data flash, 8 Kbytes flash for the ISP, and 16K bytes embedded SRAM. This MCU includes advanced PWM function and input capture timer which are specially designed for motor driving application. It is also equipped with plenty of peripheral devices, such as Timers, Watchdog Timer, UART, SPI, I2C, PWM Timer, GPIO, 12-bit ADC, Low Voltage Detector and Brown-out detector. These useful ® functions make the NuMicro M0519 Series powerful for a wide range of applications. ® In addition, the NuMicro M0519 Series is equipped with ISP (In-System Programming), ICP (InCircuit Programming) functions and IAP (In-Application Programming) which allow user to update the program memory without removing the chip from the actual end product. M0519 DATASHEET Jul. 31, 2015 Page 6 of 69 Rev 1.01 M0519 2 FEATURES  Core ® ® ARM Cortex -M0 core running up to 72 MHz One 24-bit system timer Supports Low Power Sleep mode by WFI instructions Single-cycle 32-bit hardware multiplier Supports programmable 4 level priorities of Nested Vectored Interrupt Controller (NVIC) – Supports Serial Wire Debug (SWD) support with two watchpoints and four breakpoints  Built-in LDO for wide operating voltage ranged from 2.5V to 5.5V – – – – –  Memory 128K/64K bytes Flash for program memory (APROM) 4KB Flash for data memory (Data Flash) 8KB Flash for loader (LDROM) Supports In-system program (ISP) and In-application program (IAP) application code update – Supports 2-wired ICP update through SWD/ICE interface – Supports fast parallel programming mode by external programmer – 16K bytes embedded SRAM  Clock Control – – – – – Built-in 22.1184 MHz internal high speed RC oscillator (HIRC) for system operation (variation < 2% at -40˚C ~ +105˚C) – Built-in 10 kHz internal low speed RC oscillator (LIRC) for Watchdog Timer and wakeup operation – Built-in 4~24 MHz external high speed crystal oscillator (HXT) for precise timing operation – Supports one PLL up to 72 MHz for high performance system operation, sourced from HIRC and HXT – Supports clock output  Hardware divider M0519 DATASHEET – Supports signed 32-bit dividend, 16-bit divisor operation  GPIO port – Four I/O modes: – TTL/Schmitt trigger input selectable – Bit control available – I/O pin configured as interrupt source with edge/level trigger setting – Supports high driver and high sink current I/O (up to 16 mA at 5V) – INT0 and INT1 pins with individual interrupt vectors – Supports up to 82/51/38 GPIOs for LQFP100/64/48 respectively  Timers – Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter – Provides One-shot, Periodic, Toggle and Continuous Counting operation modes – Supports event counting function to count the event from external pin  Watchdog Timer – Supports multiple clock sources from LIRC(default selection) and HCLK/2048 – 8 selectable time-out period from 1.6ms ~ 26.0sec (depending on clock source) – Able to wake up from Power-down or Idle mode – Interrupt or reset selectable on watchdog time-out – Time-out reset delay period time can be selected  Window Watchdog Timer Jul. 31, 2015 Page 7 of 69 Rev 1.01 M0519 – Supports multiple clock sources from HCLK/2048 (default selection) and LIRC – Window set by 6-bit counter with 11-bit prescale – Able to wake up from Power-down or Idle mode  Basic PWM – 1 unit of 16-bit basic PWM, up to 2ch output – Alternative function as input capture timer  Enhanced PWM 2 units of 16-bit enhanced PWM, up to 6ch output with dead-zone control, brake and polarity control for motor drive – Default tri-state during any reset  Enhanced Input Capture – – Up to 2 units of 24-bit input capture – Each unit has 3 inputs: ECAPx_IC0, ECAPx_IC1 and ECAPx_IC2  UART M0519 DATASHEET – – – – – –  SPI Up to two 16550 compatible UART devices Programmable baud-rate generator Buffered receiving and transmitting, each with 16 bytes FIFO Supports flow control (TX, RX, CTS and RTS) Supports IrDA(SIR) function Supports RS-485 – – – – – – – 2  IC Up to three sets of SPI device Supports SPI master/slave mode Full duplex synchronous serial data transfer Variable length of transfer data from 8 to 32 bits MSB or LSB first data transfer Rx and Tx on both rising or falling edge of serial clock independently Supports Byte Suspend mode in 32-bit transmission – – – – – –  ADC Master/Slave up to 1 Mbit/s Bi-directional data transfer between masters and slaves Multi-master bus (no central master) Arbitration between simultaneously transmitting masters Programmable clocks allow versatile rate control Multiple address recognition (four slave address with mask option) – – – – – Two A/D converters Each ADC with up to 8 channel, 12-bit resolution with 10-bit accuracy 16 result registers Sampling rate up to 800ksps Two operating modes:  Single Sampling mode: Only one specified channel can be sampled at one time.  Simultaneous Sampling mode: Allowing two ADC channels to be sampled simultaneously. – Two converting result digital comparators – Conversion start by software, external pins, or linked with Timer 0~3 or PWM module  Up to three Analog Comparators  Up to two OPA (operational amplifier) Jul. 31, 2015 Page 8 of 69 Rev 1.01 M0519  Brown-out detector – 4 levels: 4.4V/3.7V/2.7V/2.2V – Optional brown-out interrupt or reset  Built-in LDO for Wide Operating Voltage Range: 2.5V to 5.5V  Low Voltage Reset  96-bit unique ID  Operating Temperature: -40℃~105℃  Develop tools: parallel writer or In-Circuit Programming (ICP) writer  Packages: – – All Green package (RoHS) LQFP 100/64/48-pin M0519 DATASHEET Jul. 31, 2015 Page 9 of 69 Rev 1.01 M0519 3 ABBREVIATIONS M0519 DATASHEET Acronym Description ACMP Analog Comparator Controller ADC Analog-to-Digital Converter AES Advanced Encryption Standard APB Advanced Peripheral Bus AHB Advanced High-Performance Bus BOD Brown-out Detection CAN Controller Area Network DAP Debug Access Port DES Data Encryption Standard EBI External Bus Interface EPWM Enhanced Pulse Width Modulation FIFO First In, First Out FMC Flash Memory Controller FPU Floating-point Unit GPIO General-Purpose Input/Output HCLK The Clock of Advanced High-Performance Bus HIRC 22.1184 MHz Internal High Speed RC Oscillator HXT 4~24 MHz External High Speed Crystal Oscillator IAP In Application Programming ICP In Circuit Programming ISP In System Programming LDO Low Dropout Regulator LIN Local Interconnect Network LIRC 10 kHz internal low speed RC oscillator (LIRC) MPU Memory Protection Unit NVIC Nested Vectored Interrupt Controller PCLK The Clock of Advanced Peripheral Bus PDMA Peripheral Direct Memory Access PLL Phase-Locked Loop PWM Pulse Width Modulation QEI Quadrature Encoder Interface SDIO Secure Digital Input/Output SPI Serial Peripheral Interface Jul. 31, 2015 Page 10 of 69 Rev 1.01 M0519 SPS Samples per Second TDES Triple Data Encryption Standard TMR Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID USB Universal Serial Bus WDT Watchdog Timer WWDT Window Watchdog Timer M0519 DATASHEET Jul. 31, 2015 Page 11 of 69 Rev 1.01 M0519 4 PARTS INFORMATION LIST AND PIN CONFIGURATION NuMicro® M0519 Selection Guide 4.1 4.1.1 NuMicro® M0519 Selection Guide Part Number APROM (KB) RAM (KB) Data Flash (KB) LDROM (KB) I/O Timer (32-Bit) UART SPI I2C LIN QEI Capture PWM ADC (12-Bit) OPA Comp. ISP/ICP/IAP Package Connectivity M0519LD3AE 64 16 4 8 38 4 2 1 1 2 - - 6 16 - 2 v LQFP48 M0519LE3AE 128 16 Config. 8 38 4 2 1 1 2 - - 6 16 - 2 v LQFP48 M0519SD3AE 64 16 4 8 51 4 2 2 1 2 - - 10 16 1 2 v LQFP64 M0519SE3AE 128 16 Config. 8 51 4 2 2 1 2 - - 10 16 1 2 v LQFP64 M0519VE3AE 128 16 Config. 8 82 4 2 3 1 2 - 6 14 16 2 3 v LQFP100 4.1.2 NuMicro® M0519 Naming Rule M0519 - X X X X E CPU core ARM Cortex M0 Temperature E: - 40 ℃ ~ +105℃ Package Type Version A: Version M0519 DATASHEET L: LQFP 48 (7x7) S: LQFP 64 (7x7) V: LQFP 100 (14x14) Flash ROM D: 64 KB Flash ROM E: 128 KB Flash ROM SRAM Size 3: 16KB SRAM ® Figure 4-1 NuMicro M0519 Selection Code Jul. 31, 2015 Page 12 of 69 Rev 1.01 M0519 VREF AVDD AVSS P8.0/OP0_P P8.1/OP0_N P8.2/OP0_O P6.0/ADC0_CH0 P6.1/ADC0_CH1 P6.2/ADC0_CH2 P6.3/ADC0_CH3 P6.4/ADC0_CH4/ACMP1_N P6.5/ADC0_CH5/ACMP1_P P6.6/ADC0_CH6 P6.7/ADC0_CH7 VDD VSS P8.6 P8.7/ACMP0_O P0.0/EPWM0_CH0/ECAP1_IC0 P0.1/EPWM0_CH1/ECAP1_IC1 P0.2/EPWM0_CH2/ECAP1_IC2 P0.3/EPWM0_CH3/STADC P5.5/CLKO P5.4/SPI2_SS P5.3/SPI2_CLK 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 LQFP 100-pin ADC1_CH7/P7.7 76 50 P5.2/SPI2_MISO/ACMP1_O ADC1_CH6/P7.6 77 49 P2.0/SPI2_MOSI/ACMP2_O ACMP2_P/ADC1_CH5/P7.5 78 48 P2.1/ECAP0_IC2 ACMP2_N/ADC1_CH4/P7.4 79 47 P2.2/ECAP0_IC1 ADC1_CH3/P7.3 80 46 P2.3/ECAP0_IC0 ADC1_CH2/P7.2 81 45 P0.4/EPWM0_CH4 ADC1_CH1/P7.1 82 44 P0.5/EPWM0_CH5 ADC1_CH0/P7.0 83 43 P0.6/EPWM0_BRAKE1 ACMP0_P/P8.4 84 42 P0.7/STADC ACMP0_N/P8.3 85 41 P2.4 OP1_O/P9.0 86 40 P2.5 OP1_N/P9.1 87 39 P2.6/SPI0_SS/UART1_nCTS OP1_P/P9.2 88 38 P2.7/SPI0_CLK/UART1_nRTS VDD 89 37 P5.1/SPI0_MISO/UART0_nCTS/I2C_SDA VSS 90 36 P5.0/SPI0_MOSI/UART0_nRTS/I2C_SCL P8.5 91 35 VSS EPWM1_BRAKE1/P9.3 92 34 VDD nRESET 93 33 P4.7/TM3 XT1_OUT 94 32 P3.1/UART0_TXD/ACMP0_O XT1_IN 95 31 P3.0/UART0_RXD/CLKO ICE_DAT 96 30 P1.0/EPWM1_CH0 ICE_CLK 97 29 P1.1/EPWM1_CH1 SPI1_CLK/P9.4 98 28 P4.6/TM2 SPI1_MISO/P9.5 99 27 P3.3/INT1 SPI1_MOSI/P9.6 100 26 P4.3 13 14 15 16 17 18 19 20 21 22 23 24 25 BPWM0_CH1/P5.7 BPWM0_CH0/P5.6 EPWM0_BRAKE0/P1.6 EPWM1_CH5/P1.5 EPWM1_CH4/P1.4 EPWM1_CH3/P1.3 EPWM1_CH2/P1.2 P4.4 P4.5 ECAP1_IC0/P4.0 ECAP1_IC1/P4.1 ECAP1_IC2/P4.2 9 LDO_CAP I2C_SDA/UART1_TXD/PA.0 8 EPWM1_BRAKE0/P1.7 12 7 INT0/P3.2 I2C_SCL/UART1_RXD/PA.1 6 I2C_SDA/TM0/P3.4 11 5 I2C_SCL/TM1/P3.5 VSS 4 P3.6 10 3 P3.7 VDD 2 M0519 DATASHEET 1 M0519VxxAE LQFP 100-pin PVSS 4.2.1 Pin Configuration SPI1_SS/P9.7 4.2 ® Figure 4-2 NuMicro M0519VxxAE Series LQFP-100 Pin Diagram Jul. 31, 2015 Page 13 of 69 Rev 1.01 M0519 VREF AVDD AVSS P8.0/OP0_P P8.1/OP0_N P8.2/OP0_O P6.0/ADC0_CH0 P6.1/ADC0_CH1 P6.2/ADC0_CH2 P6.3/ADC0_CH3 P6.4/ADC0_CH4/ACMP1_N P6.5/ADC0_CH5/ACMP1_P P6.6/ADC0_CH6 P6.7/ADC0_CH7 P5.4/SPI2_SS P5.3/SPI2_CLK 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LQFP 64-pin ADC1_CH7/P7.7 49 32 P5.2/SPI2_MISO/ACMP1_O ADC1_CH6/P7.6 50 31 P2.0/SPI2_MOSI/ACMP2_O ACMP2_P/ADC1_CH5/P7.5 51 30 P0.4/EPWM0_CH4 ACMP2_N/ADC1_CH4/P7.4 52 29 P0.5/EPWM0_CH5 ADC1_CH3/P7.3 53 28 P2.4 ADC1_CH2/P7.2 54 27 P2.5 ADC1_CH1/P7.1 55 26 P2.6/SPI0_SS/UART1_nCTS ADC1_CH0/P7.0 56 25 P2.7/SPI0_CLK/UART1_nRTS OP1_O/P9.0 57 24 P5.1/SPI0_MISO/UART0_nCTS/I2C_SDA OP1_N/P9.1 58 23 P5.0/SPI0_MOSI/UART0_nRTS/I2C_SCL OP1_P/P9.2 59 22 VSS nRESET 60 21 VDD XT1_OUT 61 20 P3.1/UART0_TXD XT1_IN 62 19 P3.0/UART0_RXD/CLKO ICE_DAT 63 18 P1.0/EPWM1_CH0 ICE_CLK 64 17 P1.1/EPWM1_CH1 13 14 15 16 EPWM1_CH5/P1.5 EPWM1_CH4/P1.4 EPWM1_CH3/P1.3 EPWM1_CH2/P1.2 9 I2C_SDA/UART1_TXD/PA.0 12 8 I2C_SCL/UART1_RXD/PA.1 EPWM0_BRAKE0/P1.6 7 VSS 11 6 VDD BPWM0_CH0/P5.6 5 LDO_CAP 10 4 EPWM1_BRAKE0/P1.7 BPWM0_CH1/P5.7 3 2 INT0/P3.2 1 M0519 DATASHEET I2C_SCL/T1/P3.5 M0519SxxAE LQFP 64-pin I2C_SDA/T0/P3.4 4.2.2 ® Figure 4-3 NuMicro M0519SxxAE Series LQFP-64 Pin Diagram Jul. 31, 2015 Page 14 of 69 Rev 1.01 M0519 AVDD AVSS P8.0/OP0_P P8.1/OP0_N P8.2/OP0_O P6.0/ADC0_CH0 P6.1/ADC0_CH1 P6.2/ADC0_CH2 P6.3/ADC0_CH3 P6.4/ADC0_CH4/ACMP1_N P6.5/ADC0_CH5/ACMP1_P P6.6/ADC0_CH6 36 35 34 33 32 31 30 29 28 27 26 25 LQFP 48-pin ADC1_CH7/P7.7 37 24 P6.7/ADC0_CH7 ADC1_CH6/P7.6 38 23 P0.7/STADC ACMP2_P/ADC1_CH5/P7.5 39 22 P2.6/SPI0_SS/UART1_nCTS ACMP2_N/ADC1_CH4/P7.4 40 21 P2.7/SPI0_CLK/UART1_nRTS ADC1_CH3/P7.3 41 20 P5.1/SPI0_MISO/UART0_nCTS/I2C_SDA ADC1_CH2/P7.2 42 19 P5.0/SPI0_MOSI/UART0_nRTS/I2C_SCL ADC1_CH1/P7.1 43 18 P3.1/UART0_TXD/ACMP0_O ADC1_CH0/P7.0 44 17 P3.0/UART0_RXD/CLKO OP1_O/P9.0 45 16 P1.5/EPWM1_CH5 OP1_N/P9.1 46 15 P1.4/EPWM1_CH4 OP1_P/P9.2 47 14 P1.3/EPWM1_CH3 nRESET 48 13 P1.2/EPWM1_CH2 1 2 3 4 5 6 7 8 9 10 11 12 XT1_IN XT1_OUT EPWM1_BRAKE0/P1.7 LDO_CAP VDD VSS I2C_SCL/UART1_RXD/PA.1 I2C_SDA/UART1_TXD/PA.0 BPWM0_CH1/P5.7 BPWM0_CH0/P5.6 M0519 DATASHEET ICE_CLK M0519LxxAE LQFP 48-pin ICE_DAT 4.2.3 ® Figure 4-4 NuMicro M0519LxxAE Series LQFP-48 Pin Diagram Jul. 31, 2015 Page 15 of 69 Rev 1.01 M0519 4.3 Pin Description Pin Number Pin Name 100- pin 64-pin 48-pin Pin Type[1] Description 10 6 34 7 VDD P POWER SUPPLY: Supply voltage Digital VDD for operation. 8 VSS P GROUND: Digital Ground potential. 61 21 89 11 7 35 60 22 90 LDO: LDO output pin 9 5 6 LDO_CAP P 1 - - PVSS P PLL GROUND: PLL Ground potential. 74 47 36 AVDD AP Power supply for internal analog circuit 73 46 35 AVSS AP Ground Pin for analog circuit 75 48 - VREF AP RESET: nRESET pin is a Schmitt trigger input pin for hardware device reset. A “Low” on this pin for 768 clock counter of Internal RC 22.1184 MHz while the system clock is running will reset the device. nRESET (ST) pin has an internal pull-up resistor allowing power-on reset by simply connecting an external capacitor to GND. Note: It needs to be connected with a 1uF capacitor. Voltage reference input for ADC Note: It needs to be connected with a 1uF capacitor. I M0519 DATASHEET 93 60 48 nRESET 94 61 4 XT1_OUT 95 62 3 XT1_IN 96 63 2 ICE_DAT I/O Serial Wired Debugger Data pin 97 64 1 ICE_CLK I Serial Wired Debugger Clock pin 57 56 55 - - - Jul. 31, 2015 - - O CRYSTAL OUT: This is the output pin from the internal inverting amplifier. It emits the inverted signal of XT1_IN. CRYSTAL IN: This is the input pin to the internal inverting amplifier. The system clock is from external crystal or resonator when FOSC[1:0] (ST) (CONFIG3[1:0]) are both logic 1 by default. I P0.0 I/O General purpose digital I/O pin PWM0_CH0 O PWM0 output of PWM Unit 0 ECAP1_IC0 I Input 0 of Enhanced Input Capture Unit 1 P0.1 I/O General purpose digital I/O pin PWM0_CH1 O PWM1 output of PWM Unit 0 ECAP1_IC1 I Input 1 of Enhanced Input Capture Unit 1 P0.2 I/O General purpose digital I/O pin PWM0_CH2 O PWM2 output of PWM Unit 0 - Page 16 of 69 Rev 1.01 M0519 Pin Number Pin Name 100- pin 64-pin 48-pin ECAP1_IC2 54 45 44 43 - 30 29 - - General purpose digital I/O pin PWM0_CH3 O PWM3 output of PWM Unit 0 STADC I ADC external trigger input P0.4 I/O General purpose digital I/O pin PWM0_CH4 O PWM4 output of PWM Unit 0 P0.5 I/O General purpose digital I/O pin PWM0_CH5 O PWM5 output of PWM Unit 0 P0.6 I/O General purpose digital I/O pin - - - 29 20 19 17 16 17 16 15 14 13 12 48 31 - General purpose digital I/O pin PWM1_CH0 O PWM0 output of PWM Unit 1 P1.1 I/O General purpose digital I/O pin PWM1_CH1 O PWM1 output of PWM Unit 1 P1.2 I/O General purpose digital I/O pin PWM1_CH2 O PWM2 output of PWM Unit 1 P1.3 I/O General purpose digital I/O pin PWM1_CH3 O PWM3 output of PWM Unit 1 P1.4 I/O General purpose digital I/O pin PWM1_CH4 O PWM4 output of PWM Unit 1 P1.5 I/O General purpose digital I/O pin PWM1_CH5 O PWM5 output of PWM Unit 1 P1.6 I/O General purpose digital I/O pin - 13 14 15 16 I Brake input pin 0 of PWM Unit 0 I/O General purpose digital I/O pin I Brake input pin0 of PWM Unit 1 P2.0 I/O General purpose digital I/O pin SPI2_MOSI I/O SPI2 MOSI (Master Out, Slave In) pin ACMP2_O AO Analog comparator 2 output pin P2.1 I/O General purpose digital I/O pin 5 - ECAP0_IC2 Jul. 31, 2015 ADC external trigger input I/O PWM1_BRAKE0 49 I P1.0 P1.7 4 General purpose digital I/O pin - PWM0_BRAKE0 8 I/O Brake input pin 1 of PWM Unit 0 M0519 DATASHEET 18 18 I 23 STADC 30 Input 2 of Enhanced Input Capture Unit 1 I/O P0.7 - I Description P0.3 PWM0_BRAKE1 42 Pin Type[1] I Input 2 of Enhanced Input Capture Unit 0 Page 17 of 69 Rev 1.01 M0519 Pin Number Pin Name 100- pin 64-pin 48-pin 47 - - P2.2 ECAP0_IC1 P2.3 46 - Pin Type[1] I/O I I/O Description General purpose digital I/O pin Input 1 of Enhanced Input Capture Unit 0 General purpose digital I/O pin ECAP0_IC0 I Input 0 of Enhanced Input Capture Unit 0 41 28 - P2.4 I/O General purpose digital I/O pin 40 27 - P2.5 I/O General purpose digital I/O pin P2.6 I/O General purpose digital I/O pin SPI0_SS I/O SPI0 slave select pin 39 26 22 UART1_nCTS 38 31 25 19 21 7 M0519 DATASHEET 27 6 5 20 3 - 2 1 UART1 CTS pin P2.7 I/O General purpose digital I/O pin SPI0_CLK I/O SPI0 serial clock pin UART1_nRTS O UART1 RTS pin P3.0 I/O General purpose digital I/O pin 17 UART0_RXD 32 I 18 I Data Receiver input pin for UART0 P3.1 I/O General purpose digital I/O pin UART0_TXD O Data transmitter output pin for UART0 ACMP0_O AO Analog comparator 0 output P3.2 I/O General purpose digital I/O pin INT0 I P3.3 I/O INT1 I P3.4 I/O General purpose digital I/O pin TM0 I/O Timer0 external clock I2C0_SDA I/O I2C0 data input/output pin P3.5 I/O General purpose digital I/O pin TM1 I/O Timer1 external clock I2C0_SCL I/O I2C0 clock output pin External Interrupt 0 input pin General purpose digital I/O pin - - - External Interrupt 1 input pin 4 - - P3.6 I/O General purpose digital I/O pin 3 - - P3.7 I/O General purpose digital I/O pin P4.0 I/O General purpose digital I/O pin 23 - ECAP1_IC0 P4.1 24 - I/O Input 0 of Enhanced Input Capture Unit 1 General purpose digital I/O pin ECAP1_IC1 Jul. 31, 2015 I I Input 1 of Enhanced Input Capture Unit 1 Page 18 of 69 Rev 1.01 M0519 Pin Number Pin Name 100- pin 64-pin 48-pin 25 - - P4.2 ECAP1_IC2 Pin Type[1] I/O I Description General purpose digital I/O pin Input 2 of Enhanced Input Capture Unit 1 26 - - P4.3 I/O General purpose digital I/O pin 21 - - P4.4 I/O General purpose digital I/O pin 22 - - P4.5 I/O General purpose digital I/O pin P4.6 I/O General purpose digital I/O pin 28 - TM2 I/O Timer2 external clock P4.7 I/O General purpose digital I/O pin TM3 I/O Timer3 external clock P5.0 I/O General purpose digital I/O pin SPI0_MOSI I/O SPI0 MOSI (Master Out, Slave In) pin UART0_nRTS O UART0 RTS pin P5.1 I/O General purpose digital I/O pin SPI0_MISO I/O SPI0 MISO (Master In, Slave Out) pin 33 36 37 - 23 24 - 19 20 UART0_nCTS 50 51 53 15 14 69 68 67 33 34 - 11 10 42 41 40 Jul. 31, 2015 - UART0 CTS pin P5.2 I/O General purpose digital I/O pin SPI2_MISO I/O SPI2 MISO (Master In, Slave Out) pin ACMP1_O AO Analog comparator 1 output pin P5.3 I/O General purpose digital I/O pin SPI2_CLK I/O SPI2 serial clock pin P5.4 I/O General purpose digital I/O pin SPI2_SS I/O SPI2 slave select pin P5.5 I/O General purpose digital I/O pin CLKO O Frequency Divider output pin P5.6 I/O General purpose digital I/O pin PWM2_CH0 I/O PWM0 output of PWM unit 2 P5.7 I/O General purpose digital I/O pin PWM2_CH1 I/O PWM1 output of PWM unit 2 P6.0 I/O General purpose digital I/O pin ADC0_CH0 AI ADC analog input 0 for sample-and-hold A P6.1 I/O General purpose digital I/O pin ADC0_CH1 AI ADC analog input 1 for sample-and-hold A P6.2 I/O General purpose digital I/O pin - M0519 DATASHEET 52 32 I - - 12 11 31 30 29 Page 19 of 69 Rev 1.01 M0519 Pin Number Pin Name 100- pin 66 65 64 63 62 83 82 81 M0519 DATASHEET 80 79 78 77 76 72 64-pin 39 38 37 36 35 56 55 54 53 52 51 50 49 45 Jul. 31, 2015 48-pin Pin Type[1] Description ADC0_CH2 AI ADC analog input 2 for sample-and-hold A P6.3 I/O General purpose digital I/O pin ADC0_CH3 AI ADC analog input 3 for sample-and-hold A P6.4 I/O General purpose digital I/O pin ADC0_CH4 AI ADC analog input 4 for sample-and-hold A ACMP1_N AI Analog comparator 1 negative input P6.5 I/O General purpose digital I/O pin ADC0_CH5 AI ADC analog input 5 for sample-and-hold A ACMP1_P AI Analog comparator 1 positive input P6.6 I/O General purpose digital I/O pin ADC0_CH6 AI ADC analog input 6 for sample-and-hold A P6.7 I/O General purpose digital I/O pin ADC0_CH7 AI ADC analog input 7 for sample-and-hold A P7.0 I/O General purpose digital I/O pin ADC1_CH0 AI ADC analog input 0 for sample-and-hold B P7.1 I/O General purpose digital I/O pin ADC1_CH1 AI ADC analog input 1 for sample-and-hold B P7.2 I/O General purpose digital I/O pin ADC1_CH2 AI ADC analog input 2 for sample-and-hold B P7.3 I/O General purpose digital I/O pin ADC1_CH3 AI ADC analog input 3 for sample-and-hold B P7.4 I/O General purpose digital I/O pin ADC1_CH4 AI ADC analog input 4 for sample-and-hold B ACMP2_N AI Analog comparator 2 negative input P7.5 I/O General purpose digital I/O pin ADC1_CH5 AI ADC analog input 5 for sample-and-hold B ACMP2_P AI Analog comparator 2 positive input P7.6 I/O General purpose digital I/O pin ADC1_CH6 AI ADC analog input 6 for sample-and-hold B P7.7 I/O General purpose digital I/O pin ADC1_CH7 AI ADC analog input 7 for sample-and-hold B P8.0 I/O General purpose digital I/O pin OP0_P AI OP Amplifier 0 positive input 28 27 26 25 24 44 43 42 41 40 39 38 37 34 Page 20 of 69 Rev 1.01 M0519 Pin Number Pin Name 100- pin 64-pin 48-pin 71 44 33 70 85 84 43 - - Pin Type[1] Description P8.1 I/O General purpose digital I/O pin OP0_N AI OP Amplifier 0 negative input P8.2 I/O General purpose digital I/O pin OP0_O AO OP Amplifier 0 output P8.3 I/O General purpose digital I/O pin ACMP0_N AI Analog comparator negative input pin P8.4 I/O General purpose digital I/O pin ACMP0_P AI Analog comparator positive input pin 32 - - 91 - - P8.5 I/O General purpose digital I/O pin 59 - - P8.6 I/O General purpose digital I/O pin P8.7 I/O General purpose digital I/O pin 58 - ACMP0_O O Analog comparator output pin P9.0 I/O General purpose digital I/O pin OP1_O AO OP Amplifier 1 output P9.1 I/O General purpose digital I/O pin OP1_N AI OP Amplifier 1 negative input P9.2 I/O General purpose digital I/O pin OP1_P AI OP Amplifier 1 positive input P9.3 I/O General purpose digital I/O pin 86 87 88 92 57 58 59 - 45 46 47 PWM1_BRAKE1 99 100 2 13 12 - - - - 9 8 P9.4 I/O General purpose digital I/O pin SPI1_CLK I/O SPI1 serial clock pin P9.5 I/O General purpose digital I/O pin SPI1_MISO I/O SPI1 MISO (Master In, Slave Out) pin P9.6 I/O General purpose digital I/O pin SPI1_MOSI I/O SPI1 MOSI (Master Out, Slave In) pin P9.7 I/O General purpose digital I/O pin SPI1_SS I/O SPI1 slave select pin PA.0 I/O General purpose digital I/O pin UART1_TXD O Data transmitter output pin for UART1 I2C0_SDA I/O I2C0 data input/output pin PA.1 I/O General purpose digital I/O pin - - - - 10 9 UART1_RXD Jul. 31, 2015 Brake input pin 1 of PWM Unit 1 M0519 DATASHEET 98 I I Data Receiver input pin for UART1 Page 21 of 69 Rev 1.01 M0519 Pin Number Pin Name 100- pin 64-pin 48-pin I2C0_SCL Pin Type[1] I/O Description I2C0 clock output pin Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power M0519 DATASHEET Jul. 31, 2015 Page 22 of 69 Rev 1.01 M0519 5 BLOCK DIAGRAM Timer / PWM Memory APROM 128/64 KB ARM® Cortex® -M0 72 MHz Analog Interface 32-bit Timer x 4 EPWM Timer x 12 2 sets of 12-bit ADC x 8 Watchdog Timers ICAP Timer x 2 Operating Amp. x 2 LDROM 8 KB Data Flash 4 KB BPWM Timer x 2 SRAM 16 KB Comparators x 3 Bridge AHB Bus Power Control APB Bus Clock Control GPIO Connectivity PLL General Purpose I/O UART x 2 Reset Pin SPI x 3 External Interrupt I²C LDO Power-on Reset HS Osc. 22.1184 MHz HS Ext. Crystal Osc. 4~24 MHz LVR Brown-out Detection LS Osc. 10 kHz ® Figure 5-1 NuMicro M0519 Series Block Diagram M0519 DATASHEET Jul. 31, 2015 Page 23 of 69 Rev 1.01 M0519 6 6.1 FUNCTIONAL DESCRIPTION ARM® Cortex® -M0 Core ® The Cortex -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug ® functionality. The processor can execute Thumb code and is compatible with other Cortex -M profile processor. The profile supports two modes -Thread mode and Handler mode. Handler mode is entered as a result of an exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset, and can be entered as a result of an exception return. Figure 6-1 shows the functional controller of processor. CortexTM-M0 Components CortexTM-M0 processor Nested Vectored Interrupt Controller (NVIC) Interrupts Debug CortexTM-M0 Processor Core Wakeup Interrupt Controller (WIC) Bus Matrix Breakpoint and Watchpoint Unit Debugger Interface AHB-Lite Interface Debug Access Port (DAP) Serial Wire or JTAG Debug Port Figure 6-1 Functional Controller Diagram M0519 DATASHEET The implemented device provides the following components and features:   Jul. 31, 2015 A low gate count processor: ® - ARMv6-M Thumb instruction set - Thumb-2 technology - ARMv6-M compliant 24-bit SysTick timer - A 32-bit hardware multiplier - System interface supported with little-endian data accesses - Ability to have deterministic, fixed-latency, interrupt handling - Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to facilitate rapid interrupt handling - C Application Binary Interface compliant exception model. This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers - Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or the return from interrupt sleep-on-exit feature NVIC: Page 24 of 69 Rev 1.01 M0519   - 32 external interrupt inputs, each with four levels of priority - Dedicated Non-maskable Interrupt (NMI) input - Supports for both level-sensitive and pulse-sensitive interrupt lines - Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Sleep mode Debug support - Four hardware breakpoints - Two watchpoints - Program Counter Sampling Register (PCSR) for non-intrusive code profiling - Single step and vector catch capabilities Bus interfaces: - Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all system peripherals and memory - Single 32-bit slave port that supports the DAP (Debug Access Port) M0519 DATASHEET Jul. 31, 2015 Page 25 of 69 Rev 1.01 M0519 6.2 System Manager 6.2.1 Overview System management includes the following sections: 6.2.2  System Resets  System Power Distribution  System Memory Map  System management registers for Part Number ID, chip reset and on-chip controllers reset , multi-functional pin control  System Timer (SysTick)  Nested Vectored Interrupt Controller (NVIC)  System Control registers System Reset The system reset can be issued by one of the following listed events. For these reset event flags can be read by RSTSRC register.   Hardware Reset  Power-on Reset (POR)  Low level on the Reset pin (nRESET)  Watchdog Time-out Reset (WDT)  Low Voltage Reset (LVR)  Brown-out Detector Reset (BOD) Software Reset M0519 DATASHEET  SYS Reset - SYSRESETREQ (AIRCR[2])  Cortex -M0 Core One-shot Reset - CPU_RST (IPRSTC1[1])  Chip One-shot Reset - CHIP_RST (IPRSTC1[0]) ® Power-on Reset or CHIP_RST (IPRST1[0]) reset the whole chip including all peripherals, external crystal circuit and BS (ISPCON[1]) bit. SYSRESETREQ (AIRCR[2]) reset the whole chip including all peripherals, but does not reset external crystal circuit and BS (ISPCON[1]) bit. Jul. 31, 2015 Page 26 of 69 Rev 1.01 M0519 6.2.3 System Power Distribution In this chip, the power distribution is divided into two segments.  Analog power from AVDD and AVSS provides the power for analog components operation.  Digital power from VDD and VSS supplies the power to the I/O pins and internal regulator which provides a fixed 1.8V power for digital operation. The output of internal voltage regulators, LDO_CAP, requires an external capacitor which should be located close to the corresponding pin. Analog power (AVDD) should be the same voltage level of the digital power (VDD). AVDD AVSS 12-bit SAR-ADC Analog Comparator Temperature Seneor FLASH Brownout Detector OPA Low Voltage Reset Internal 22.1184 MHz & 10 kHz Oscillator Digital Logic LDO_CAP 1.8V LDO PLL IO cell GPIO POR50 VSS 4~24MHz Crystal M0519 DATASHEET PVDD XT1_OUT 1uF POR18 VDD XT1_IN ® Figure 6-2 NuMicro M0519 Series Power Distribution Diagram Jul. 31, 2015 Page 27 of 69 Rev 1.01 M0519 6.2.4 System Memory Map ® The NuMicro M0519 Series provides 4G-byte addressing space. The memory locations assigned to each on-chip controllers are shown in Table 6-1. The detailed register definition, memory space, and programming detailed will be described in the following sections for each on-chip ® peripheral. The NuMicro M0519 Series only supports little-endian data format. Address Space Token Controllers 0x0000_0000 – 0x0001_FFFF FLASH_BA FLASH Memory Space (128 KB) 0x2000_0000 – 0x2000_3FFF SRAM_BA SRAM Memory Space (16 KB) Flash and SRAM Memory Space AHB Controllers Space (0x5000_0000 – 0x501F_FFFF) 0x5000_0000 – 0x5000_01FF GCR_BA System Global Control Registers 0x5000_0200 – 0x5000_02FF CLK_BA Clock Control Registers 0x5000_0300 – 0x5000_03FF INT_BA Interrupt Multiplexer Control Registers 0x5000_4000 – 0x5000_7FFF GPIO_BA GPIO Control Registers 0x5000_C000 – 0x5000_FFFF FMC_BA Flash Memory Control Registers 0x5001_4000 – 0x5001_7FFF HDIV_BA Hardware Divider Register APB1 Controllers Space (0x4000_0000 ~ 0x400F_FFFF) M0519 DATASHEET 0x4000_4000 – 0x4000_7FFF WDT_BA Watchdog Timer Control Registers 0x4000_4100 – 0x4000_7FFF WWDT_BA Window Watchdog Timer Control Registers 0x4001_0000 – 0x4001_3FFF TMR01_BA Timer0/Timer1 Control Registers 0x4002_0000 – 0x4002_3FFF I2C0_BA I2C0 Interface Control Registers 0x4003_0000 – 0x4003_3FFF SPI0_BA SPI0 with master/slave function Control Registers 0x4003_4000 – 0x4003_7FFF SPI1_BA SPI1 with master/slave function Control Registers 0x4004_0000 – 0x4004_3FFF BPWM0_BA Basic PWM0 Control Registers 0x4005_0000 – 0x4005_3FFF UART0_BA UART0 Control Registers 0x400D_0000 – 0x400D_3FFF ACMP_BA Analog Comparator Control Registers 0x400E_0000 – 0x400E_3FFF EADC_BA Enhanced Analog-Digital-Converter (EADC) Control Registers 0x400F_0000 – 0x400F_3FFF OPA_BA Operation Amplifier Control Registers APB2 Controllers Space (0x4010_0000 ~ 0x401F_FFFF) 0x4011_0000 – 0x4011_3FFF TMR23_BA Timer2/Timer3 Control Registers 0x4013_0000 – 0x4013_3FFF SPI2_BA SPI2 with master/slave function Control Registers 0x4015_0000 – 0x4015_3FFF UART1_BA UART1 Control Registers Reserved Reserved Reserved 0x4019_0000 – 0x4019_3FFF EPWM0_BA Enhanced PWM0 Control Registers 0x4019_4000 – 0x4019_7FFF EPWM1_BA Enhanced PWM1 Control Registers Jul. 31, 2015 Page 28 of 69 Rev 1.01 M0519 Address Space Token Controllers 0x401B_0000 – 0x401B_3FFF ECAP0_BA Enhanced Input Capture 0 Control Registers 0x401B_4000 – 0x401B_7FFF ECAP1_BA Enhanced Input Capture 1 Control Registers Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved System Controllers Space (0xE000_E000 ~ 0xE000_EFFF) 0xE000_E010 – 0xE000_E01F SYST_BA System Timer Control Registers 0xE000_E100 – 0xE000_E4EF NVIC_BA External Interrupt Controller Control Registers 0xE000_ED00 – 0xE000_ED3F SCS_BA System Control Registers Table 6-1 Address Space Assignments for On-Chip Controllers M0519 DATASHEET Jul. 31, 2015 Page 29 of 69 Rev 1.01 M0519 6.2.5 System Timer (SysTick) ® The Cortex -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the counter transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0 before enabling the feature. This ensures the timer will count from the SYST_RVR value rather than an arbitrary value when it is enabled. If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded with this value. This mechanism can be used to disable the feature independently from the timer enable bit. ® ® For more detailed information, please refer to the “ARM Cortex -M0 Technical Reference ® Manual” and “ARM v6-M Architecture Reference Manual”. M0519 DATASHEET Jul. 31, 2015 Page 30 of 69 Rev 1.01 M0519 6.2.6 Nested Vectored Interrupt Controller (NVIC) ® The Cortex -M0 provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core and provides following features:  Nested and Vectored interrupt support  Automatic processor state saving and restoration  Reduced and deterministic interrupt latency The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of the interrupts and most of the system exceptions can be configured to different priority levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched from a vector table in memory. There is no need to determine which interrupt is accepted and branch to the starting address of the correlated ISR by software. While the starting address is fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the normal execution. Thus it will take less and deterministic time to process the interrupt request. The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the higher one without delay penalty. Thus it advances the real-time capability. Jul. 31, 2015 Page 31 of 69 ® ® Cortex -M0 Technical Reference M0519 DATASHEET For more detailed information, please refer to the “ARM ® Manual” and “ARM v6-M Architecture Reference Manual”. Rev 1.01 M0519 6.2.6.1 Exception Model and System Interrupt Map ® Table 6-2 lists the exception model supported by the NuMicro M0519 Series. Software can set four levels of priority on some of these exceptions as well as on all interrupts. The highest userconfigurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority of all the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”. Exception Name Vector Number Priority Reset 1 -3 NMI 2 -2 Hard Fault 3 -1 Reserved 4 ~ 10 Reserved SVCall 11 Configurable Reserved 12 ~ 13 Reserved PendSV 14 Configurable SysTick 15 Configurable Interrupt (IRQ0 ~ IRQ31) 16 ~ 47 Configurable Table 6-2 Exception Model Exception Number Vector Address 1 ~ 15 Interrupt Number (Bit In Interrupt Registers) Interrupt Name Source Module - - - Exception Description System exceptions Power Down Wake-Up - M0519 DATASHEET Brown-out low voltage detected interrupt Yes WDT Watchdog Timer interrupt Yes EINT0_INT P3.2 External signal interrupt from P3.2 pin Yes 3 EINT1_INT P3.3 External signal interrupt from P3.3 pin Yes 0x50 4 GPG0_INT 21 0x54 5 GPG1_INT 22 0x58 6 23 0x5C 24 16 0x40 0 BOD_INT Brown-out 17 0x44 1 WDT_INT 18 0x48 2 19 0x4C 20 P0~P4 except External interrupt from GPIO group 0 P3.2 and P3.3 (P0~P4) except P3.2 and P3.3 Yes P5~PA External interrupt from GPIO group 1 (P5~PA) Yes BPWM0_INT BPWM0 Basic PWM0 interrupt No 7 EADC0_INT EADC0 EADC0 interrupt No 0x60 8 TMR0_INT TMR0 Timer 0 interrupt No 25 0x64 9 TMR1_INT TMR1 Timer 1 interrupt No 26 0x68 10 TMR2_INT TMR2 Timer 2 interrupt No 27 0x6C 11 TMR3_INT TMR3 Timer 3 interrupt No 28 0x70 12 UART0_INT UART0 UART0 interrupt Yes Jul. 31, 2015 Page 32 of 69 Rev 1.01 M0519 Exception Number Vector Address Interrupt Number (Bit In Interrupt Registers) Interrupt Name Source Module 29 0x74 13 UART1_INT UART1 30 0x78 14 SPI0_INT 31 0x7C 15 32 0x80 33 Exception Description Power Down Wake-Up UART1 interrupt Yes SPI0 SPI0 interrupt No SPI1_INT SPI1 SPI1 interrupt No 16 SPI2_INT SPI2 SPI2 interrupt No 0x84 17 Reserved Reserved Reserved - 33 0x84 17 Reserved Reserved Reserved No 34 0x88 18 I2C0_INT I2C0 I C0 interrupt Yes 35 0x8C 19 CKD_INT CKD CKD interrupt No 36 0x90 20 Reserved Reserved Reserved - 36 0x90 20 Reserved Reserved Reserved - 37 0x94 21 EPWM0_INT EPWM0 Enhanced PWM0 interrupt No 38 0x98 22 EPWM1_INT EPWM1 Enhanced PWM1 interrupt No 39 0x9C 23 ECAP0_INT ECAP0 Enhanced input capture 0 interrupt No 40 0xA0 24 ECAP1_INT ECAP1 Enhanced input capture 1 interrupt No 41 0xA4 25 ACMP_INT ACMP Analog Comparator 0 or 1, or OP Amplifier digital output interrupt 42 0xA8 26 Reserved Reserved Reserved - 43 0xAC 27 Reserved Reserved Reserved - 42 0xA8 26 Reserved Reserved Reserved - 43 0xAC 27 Reserved Reserved Reserved - 44 0xB0 28 PWRWU_INT CLKC Clock controller interrupt for chip wake up from power-down state - 45 0xB4 29 EADC1_INT EADC1 EADC1 interrupt No 46 0xB8 30 EADC2_INT EADC2 EADC2 interrupt No 47 0xBC 31 EADC3_INT EADC3 EADC3 interrupt No 2 Yes (only by analog comparator) Jul. 31, 2015 Page 33 of 69 Rev 1.01 M0519 DATASHEET Table 6-3 System Interrupt Map Vector Table M0519 6.2.6.2 Vector Table When an interrupt is accepted, the processor will automatically fetch the starting address of the interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base address is fixed at 0x00000000. The vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. The vector number on previous page defines the order of entries in the vector table associated with exception handler entry as illustrated in previous section. Vector Table Word Offset (Bytes) Description 0 SP_main – The Main stack pointer Vector Number Exception Entry Pointer using that Vector Number Table 6-4 Vector Table 6.2.6.3 Operation Description NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt SetEnable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become Pending, however, the interrupt will not be activated. If an interrupt is Active when it is disabled, it remains in its Active state until cleared by reset or an exception return. Clearing the enable bit prevents new activations of the associated interrupt. NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current pended state of the corresponding interrupts. The Clear-Pending Register has no effect on the execution status of an Active interrupt. NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register supporting four interrupts). M0519 DATASHEET The general registers associated with the NVIC are all accessible from a block of memory in the System Control Space and will be described in next section. Jul. 31, 2015 Page 34 of 69 Rev 1.01 M0519 6.3 Clock Controller 6.3.1 Overview The clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and clock divider. The chip enters ® Power-down mode when Cortex -M0 core executes the WFI instruction only if the SLEEPDEEP (SCR[2]) bit is set to 1. After that, chip enters Power-down mode and wait for wake-up interrupt source triggered to leave Power-down mode. In the Power-down mode, the clock controller turns off the 4~24 MHz external high speed crystal oscillator and 22.1184 MHz internal high speed RC oscillator to reduce the overall system power consumption. Figure 6-3 shows the clock generator and the overview of the clock source control. The clock generator consists of 4 clock sources as listed below:  4~24 MHz external high speed crystal oscillator (HXT)  Programmable PLL output clock frequency (PLL_FOUT), PLL source can be selected from 4~24 MHz external high speed crystal oscillator (HXT) or 22.1184 MHz internal high speed RC oscillator (HIRC)  22.1184 MHz internal high speed RC oscillator (HIRC)  10 kHz internal low speed RC oscillator (LIRC) Clock Source Clock Stable Count Value HXT 4096 HXT clock PLL 6144 PLL source (PLL source is HXT if PLL_SRC(PLLCON[19]) = 0, or HIRC if PLL_SRC(PLLCON[19]) = 1) HIRC 256 HIRC clock LIRC 1 LIRC Table 6-5 Clock Stable Count Value Table Jul. 31, 2015 Page 35 of 69 Rev 1.01 M0519 DATASHEET Each of these clock sources has certain stable time to wait for clock operating at stable frequency. When clock source is enabled, a stable counter start counting and correlated clock stable index (OSC22M_STB(CLKSTATUS[4]), OSC10K_STB(CLKSTATUS[3]), PLL_STB(CLKSTATUS[2]) and XTL12M_STB(CLKSTATUS[0])) are set to 1 after stable counter value reach a define value as Table 6-5. System and peripheral can use these clock as its operating clock only when correlate clock stable index is set to 1. The clock stable index will auto clear when user disables the clock source (OSC10K_EN(PWRCON[3]), OSC22M_EN(PWRCON[2]), XTL12M_EN(PWRCON[0]) and PD(PLLCON[16])). Besides, the clock stable index of HXT, HIRC and PLL will auto clear when chip enter power-down and clock stable counter will re-counting after chip wake-up if correlate clock is enabled. M0519 XTL12M_EN (PWRCON[0]) XT1_OUT HXT 4~24 MHz HXT PLL_SRC (PLLCON[19]) XT1_IN 0 OSC22M_EN (PWRCON[2]) PLL PLL FOUT 1 22.1184 MHz HIRC HIRC OSC10K_EN (PWRCON[3]) LIRC 10 kHz LIRC Legend: HXT = 4~24 MHz external high speed crystal oscillator HIRC = 22.1184 MHz internal high speed RC oscillator LIRC = 10 kHz internal low speed RC oscillator Figure 6-3 Clock Generator Block Diagram M0519 DATASHEET Jul. 31, 2015 Page 36 of 69 Rev 1.01 M0519 22.1184 MHz 22.1184 MHz 111 10 kHz 4~12 MHz CPUCLK CPU 011 PLLFOUT 010 Reserved 1/(HCLK_N+1) ACMP I2C TMR0 TMR1 TMR2 TMR3 BPWM0 EPWM0 EPWM1 ECAP0 ECAP1 OPA QEI0 QEI1 MDU HCLK 001 10 kHz 4~24 MHz PCLK 000 CLKSEL0[2:0] 22.1184 MHz 4~24 MHz 1 PLLFOUT 0 PLLCON[19] 22.1184 MHz 11 HCLK 10 FRQDIV Reserved 01 4~24 MHz 22.1184 MHz HCLK 4~24 MHz 1/2 111 1/2 011 1/2 010 00 CPUCLK CLKSEL2[3:2] 1 SysTick 0 SYST_CSR[2] Reserved CLKSEL2[17:16] 001 4~24 MHz 10 kHz 000 11 WWDT 10 CLKSEL0[5:3] 10 kHz HCLK HCLK HCLK PLLFOUT 4~24 MHz CLKSEL1[25:24] 11 01 00 HCLK PLLFOUT 10 1/512 01 1/128 00 WDT 10 kHz 22.1184 MHz CLKSEL1[1:0] BOD FMC 1 SPI0 SPI1 SPI2 0 CLKSEL1[4] CLKSEL1[5] CLKSEL1[6] PCLK 1/(UART_N+1) UART0-1 1/(EADC_N+1) EADC Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6-4 Clock Generator Global View Diagram Jul. 31, 2015 Page 37 of 69 Rev 1.01 M0519 DATASHEET 22.1184 MHz 11 1/2048 M0519 6.4 Flash Memory Controller (FMC) 6.4.1 Overview ® The NuMicro M0519 Series is equipped with 128/64 KB on-chip embedded flash for application program memory (APROM) and data flash, and with 8K bytes for ISP loader program memory (LDROM) that could be programmed boot loader to update APROM and data flash through In System Programming (ISP) procedure. ISP function enables user to update embedded flash ® when chip is soldered on PCB. After chip is powered on, Cortex -M0 CPU fetches code from ® APROM or LDROM decided by boot select CBS (Config0[7:6]). By the way, the NuMicro M0519 Series also provides data flash for user to store some application dependent data before chip power off. For 128 KB APROM device, the data flash is shared with original 128 KB program memory and its start address is configurable in Config1. For 64 KB APROM device, the data flash is fixed at 4K bytes. 6.4.2 Features  Runs up to 72 MHz and optional up to 50 MHz with zero wait state for continuous address read access  Supports 512 bytes page erase for all embedded flash  Supports 128/64 Kbytes application program ROM (APROM)  Supports 8 KB loader ROM (LDROM)  Supports 4KB data flash for 64 Kbytes APROM device  Supports configurable data flash size for 128KB APROM device  Supports 8 bytes User Configuration block to control system initiation  Support In-System-Programming (ISP) / In-Application-Programming (IAP) to update embedded flash memory M0519 DATASHEET Jul. 31, 2015 Page 38 of 69 Rev 1.01 M0519 6.5 General Purpose I/O (GPIO) 6.5.1 Overview ® The NuMicro M0519 Series has up to 82 General Purpose I/O pins to be shared with other function pins depending on the chip configuration. These 82 pins are arranged in 10 ports named as P0, P1, P2, P3, P4, P5, P6, P7, P8, P9 and PA. The P0/1/2/3/4/5/6/7/8/9 port has the maximum of 8 pins and PA port has the maximum of 2 pins. Each of the 82 pins is independent and has the corresponding register bits to control the pin mode function and data. The I/O type of each of I/O pins can be configured by software individually as input, output, opendrain or Quasi-bidirectional mode. After reset, the I/O mode of all pins are stay at input mode. In Quasi-bidirectional mode, I/O pin has a very weak individual pull-up resistor which is about 110~300 K for VDD is from 5.0 V to 2.5 V. 6.5.2  Features Four I/O modes:  Quasi-bidirectional  Push-Pull output  Open-Drain output  Input only with high impendence  TTL/Schmitt trigger input selectable by Px_TYPE[7:0] in Px_MFP[23:16]  I/O pin configured as interrupt source with edge/level setting  I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode  Enabling pin interrupt function will also enable the pin wake-up function M0519 DATASHEET Jul. 31, 2015 Page 39 of 69 Rev 1.01 M0519 6.6 Timer Controller (TIMER) 6.6.1 Overview The Timer controller includes four 32-bit timers, Timer0 ~ Timer3, allowing user to easily implement a timer control for applications. The timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins. 6.6.2 Features  Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter  Independent clock source for each timer  Provides one-shot, periodic, toggle-output and continuous counting operation modes  24-bit up counter value is readable through TDR (TDR[23:0])  Supports event counting function  Supports external capture pin event for interval measurement  Supports external capture pin event to reset 24-bit up counter M0519 DATASHEET Jul. 31, 2015 Page 40 of 69 Rev 1.01 M0519 6.7 Basic PWM Generator and Capture Timer (BPWM) 6.7.1 Overview ® The NuMicro M0519 series has 1 set of BPWM group (BPWM0), supporting 1 set of BPWM generators that can be configured as 2 independent BPWM outputs, BPWM0_CH0 and BPWM0_CH1, or as 1 complementary BPWM pairs, (BPWM0_CH0, BPWM0_CH1) with programmable dead-zone generator. The BPWM generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two BPWM Timers including two clock selectors, two 16-bit BPWM down-counters for BPWM period control, two 16-bit comparators for BPWM duty control and one dead-zone generator. The BPWM generator provides two independent BPWM interrupt flags which are set by hardware when the corresponding BPWM period down counter reaches zero. Each BPWM interrupt source with its corresponding enable bit can cause CPU to request BPWM interrupt. The BPWM generators can be configured as one-shot mode to produce only one BPWM cycle signal or auto-reload mode to output BPWM waveform continuously. BPWM can be used to trigger EADC when operation in center-aligned mode. 6.7.2 6.7.2.1 Features BPWM Function:  Up to 1 BPWM group to support 2 BPWM channels or 1 BPWM paired channels.  Supports 8-bit prescaler from 1 to 255  Up to 16-bit resolution BPWM timer  PWM timer supports edge-aligned and center-aligned operation type  One-shot or Auto-reload mode BPWM  PWM Interrupt request synchronized with BPWM period or duty  Supports dead-zone generator with 8-bit resolution for BPWM paired channels  Supports trigger EADC M0519 DATASHEET 6.7.2.2 Capture Function:  Supports 2 Capture input channels shared with 2 BPWM output channels  Supports rising or falling capture condition  Supports rising or falling capture interrupt Jul. 31, 2015 Page 41 of 69 Rev 1.01 M0519 6.8 Enhanced PWM Generator (EPWM) 6.8.1 Overview This device has two built-in PWM units with the same architecture whose function is specially designed for driving motor control applications. 6.8.2 Features Each unit supports the features below:  Three independent 16-bit PWM duty control units with maximum 6 port pins:  3 independent PWM output: EPWM0_CH0, EPWM0_CH2 and EPWM0_CH4 for Unit 0 EPWM1_CH0, EPWM1_CH2 and EPWM1_CH4 for Unit 1  3 complementary PWM pairs, with each pin in a pair mutually complement to each other and capable of programmable dead-time insertion: (EPWMx_CH0, EPWMx_CH1), (PWMx_CH2, EPWMx_CH3) and (EPWMx_CH4, EPWMx_CH5) where x=0~1.  3 synchronous PWM pairs, with each pin in a pair in-phase: (EPWMx_CH0, EPWMx_CH1), (EPWMx_CH2, EPWMx_CH3) and (EPWMx_CH4, EPWMx_CH5) where x=0~1 M0519 DATASHEET  Group control bits: EPWMx_CH2 and EPWMx_CH4 are synchronized with EPWMx_CH0  Supports Edge aligned mode and Center aligned mode  Programmable dead-time insertion between complementary paired PWMs  Each pin of EPWMx_CH0 to EPWMx_CH5 has independent polarity setting control  Mask output control for Electrically Commutated Motor operation  Tri-state output at reset and brake state  Hardware brake protection  Two Interrupt Sources:  Interrupt is synchronously requested at PWM frequency when up/down counter comparison matched (edge and center aligned modes) or underflow (center aligned mode).  Interrupt is requested when external brake pins asserted  PWM signals before polarity control stage are defined in the view of positive logic. The PWM ports is active high or active low are controlled by polarity control register.  High Source/Sink current.  Supports trigger EADC Jul. 31, 2015 Page 42 of 69 Rev 1.01 M0519 6.9 Enhanced Input Capture Timer (ECAP) 6.9.1 Overview This device provides up to two units of Input Capture Timer/Counter which capture function can detect the digital edge changed signal at channel inputs. Each unit has three input capture channels. The timer/counter is equipped with up counting, reload and compare-match capabilities. 6.9.2 Features  Up to two Input Capture Timer/Counter Units, Input Capture 0 and Input Capture 1.  Each unit has own interrupt vector  24-bit Input Capture up-counting timer/counter  With noise filter in front end of input ports  Edge detector with three options  Rising edge detection  Falling edge detection  Both edge detection  Each input channel is supported with one capture counter hold register  Captured event reset/reload capture counter option  Supports the compare-match function M0519 DATASHEET Jul. 31, 2015 Page 43 of 69 Rev 1.01 M0519 6.10 Watchdog Timer (WDT) 6.10.1 Overview The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer supports the function to wake-up system from Idle/Power-down mode. 6.10.2 Features  18-bit free running up counter for WDT time-out interval  Selectable time-out interval (2 ~ 2 ) and the time-out interval is 1.6 ms ~ 26.214 s if WDT_CLK = 10 kHz  System kept in reset state for a period of (1 / WDT_CLK) * 63  Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK reset delay period  Supports to force WDT enabled after chip powered on or reset by setting CWDTEN in Config0 register  Supports WDT time-out wake-up function only if WDT clock source is selected as 10 kHz 4 18 M0519 DATASHEET Jul. 31, 2015 Page 44 of 69 Rev 1.01 M0519 6.11 Window Watchdog Timer (WWDT) 6.11.1 Overview The Window Watchdog Timer is used to perform a system reset within a specified window period to prevent software from running to uncontrollable state by any unpredictable condition usually generated by external interferences or unexpected logical conditions. When the window function is used to trim the watchdog behavior to match the application perfectly, software must refresh the counter before time-out. 6.11.2 Features  6-bit down counter value WWDTCVAL (WWDTCVR[5:0]) and 6-bit compare value WINCMP (WWDTCR[21:16]) to make the WWDT time-out window period flexible  Supports 4-bit value PERIODSEL (WWDTCR[11:8]) to programmable maximum 11-bit prescale counter period of WWDT counter  WWDT counter suspends in Idle/Power-down mode M0519 DATASHEET Jul. 31, 2015 Page 45 of 69 Rev 1.01 M0519 6.12 Universal Asynchronous Receiver Transmitter (UART) 6.12.1 Overview ® The NuMicro M0519 series provides two channels of Universal Asynchronous Receiver/Transmitters (UART). UART Controller performs Normal Speed UART and supports flow control function. The UART Controller performs a serial-to-parallel conversion on data received from the peripheral and a parallel-to-serial conversion on data transmitted from the CPU. Each UART Controller channel supports seven types of interrupts. The UART controller also supports IrDA SIR, RS-485 and LIN. 6.12.2 Features  Full duplex, asynchronous communications  Separates receive / transmit 16 bytes entry FIFO for data payloads  Supports hardware auto-flow control/flow control function (nCTS, nRTS) and programmable nRTS flow control trigger level  Programmable receiver buffer trigger level  Supports programmable baud-rate generator for each channel individually  Supports nCTS wake-up function  Supports 8-bit receiver buffer time out detection function  Programmable transmitting data delay time between the last stop and the next start bit by setting DLY (UA_TOR [15:8]) register  Supports break error, frame error, parity error and receive / transmit buffer overflow detect function  Fully programmable serial-interface characteristics M0519 DATASHEET   Programmable data bit length, 5-, 6-, 7-, 8-bit character  Programmable parity bit, even, odd, no parity or stick parity bit generation and detection  Programmable stop bit length, 1, 1.5, or 2 stop bit generation IrDA SIR function mode    Supports 3-/16-bit duration for normal mode LIN function mode  Supports LIN master/slave mode  Supports programmable break generation function for transmitter  Supports break detect function for receiver RS-485 function mode  Supports RS-485 9-bit mode  Supports hardware or software direct enable control provided by nRTS pin Jul. 31, 2015 Page 46 of 69 Rev 1.01 M0519 6.13 I2C Serial Interface Controller (I²C) 6.13.1 Overview I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control 2 the bus simultaneously. I C controller supports Power-down wake-up function. 6.13.2 Features The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the bus are: Master/Slave mode  Bidirectional data transfer between masters and slaves  Multi-master bus (no central master)  Arbitration between simultaneously transmitting masters without corruption of serial data on the bus  Serial clock synchronization allows devices with different bit rates to communicate via one serial bus  Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer  A built-in a 14-bit time out counter requested the I2C interrupt if the I2C bus hangs up and timer-out counter overflows.  External pull-up resistors are needed for high output  Programmable clocks allow versatile rate control  Supports 7-bit addressing mode  Supports multiple address recognition ( four slave address with mask option) Jul. 31, 2015 Page 47 of 69 M0519 DATASHEET  Rev 1.01 M0519 6.14 Serial Peripheral Interface (SPI) 6.14.1 Overview The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bi® direction interface. The NuMicro M0519 series contains up to three sets of SPI controllers performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. Each set of SPI controller can be configured as a master or a slave device. 6.14.2 Features  Up to three sets of SPI controllers  Supports Master or Slave mode operation  Configurable bit length of a transaction word from 8 to 32-bit  Provides separate 8-layer depth transmit and receive FIFO buffers  Supports MSB first or LSB first transfer sequence  Supports the Byte Reorder function  Supports 3-wire, no slave select signal, bi-direction interface M0519 DATASHEET Jul. 31, 2015 Page 48 of 69 Rev 1.01 M0519 6.15 Hardware Divider (HDIV) 6.15.1 Overview The hardware divider is useful to the high performance application. The hardware divider is a signed, integer divider with quotient and remainder outputs. 6.15.2 Features  Supports Signed (two’s complement) integer calculation.  Supports 32-bit dividend with 16-bit divisor calculation capacity.  Supports 32-bit quotient and 16-bit remainder outputs.  Supports divided by 0 warning flag.  7 HCLK clocks taken for one cycle calculation.  Software triggered with finish flag. M0519 DATASHEET Jul. 31, 2015 Page 49 of 69 Rev 1.01 M0519 6.16 Enhanced Analog-to-Digital Converter (EADC) 6.16.1 Overview ® The NuMicro M0519 Series contains two 12-bit successive approximation analog-to-digital converters (SAR A/D converter) with 16 input channels. The two A/D converters ADCA and ADCB can be sampled with Simultaneous or Single Sampling mode. The A/D converters can be started by software, PWM triggers, timer0~3 overflow pulse triggers, ADINT0, ADINT1 interrupt EOC pulse trigger and external STADC pin input signal. Note: The analog input port pins must be configured as input type before the EADC function is enabled. 6.16.2 Features  Analog input voltage range: 0~VREF(Max to 5.0V).  12-bit resolution and 10-bit accuracy is guaranteed.  Up to 16 single-end analog input channels.  Two SAR ADC converters.  Four EADC interrupts with individual interrupt vector addresses.  Maximum EADC clock frequency: 16MHz.  Up to 1.6M SPS conversion rate, each of ADC converter conversion time less than 1.25μs.  Two operating modes   Single sampling mode: two ADC converters run at normal operation.  Simultaneous sampling mode: Allow two ADC converters can be sampled simultaneously. An A/D conversion can be started by: M0519 DATASHEET  Writing 1 to ADST(ADSSTR[n]) bit ( n = 0~15) through software  External pin STADC  Timer0~3 overflow pulse triggers  ADINT0, ADINT1 interrupt EOC pulse triggers  PWM triggers  Conversion results are held in 16 data registers with valid and overrun indicators.  SAMPLEA0~7 ADC control logic modules, each of them is configurable for ADCA converter channel AINA0~7 and trigger source.  SAMPLEB0~7 ADC control logic modules, each of them is configurable for ADCB converter channel AINB0~7 and trigger source.  Channel AINA0 supports 2 input sources: external analog voltage and internal OP0 Amplifier output voltage.  Channel AINB0 supports 2 input sources: external analog voltage and internal OP1 Amplifier output voltage.  Channel AINA7 supports 4 input sources: external analog voltage, internal fixed band-gap voltage, internal temperature sensor output, and analog ground. Jul. 31, 2015 Page 50 of 69 Rev 1.01 M0519 6.17 Analog Comparator (ACMP) 6.17.1 Overview ® The NuMicro M0519 Series contains three comparators. The comparator output is logic 1 when positive input voltage is greater than negative input voltage; otherwise the output is logic 0. Each comparator can be configured to cause an interrupt when the comparator output value changes. The block diagram is shown in 錯誤! 找不到參照來源。. 6.17.2 Features  Analog input voltage range: 0~ AVDD  Supports hysteresis function  Supports wake-up function  Supports comparator output inverse function  Supports the comparator output can be the brake source for EPWM function  ACMP0 supports     2 positive sources: ACMP0_P and OP0_O  2 negative sources: ACMP0_N and Internal band-gap voltage (VBG) ACMP1 supports  2 positive sources: ACMP1_P and OP1_O  2 negative sources: ACMP1_N and Internal band-gap voltage (VBG) ACMP2 supports  1 positive sources: ACMP2_P  2 negative sources: ACMP2_N and Internal band-gap voltage (VBG) Shares one ACMP interrupt vector for all comparators M0519 DATASHEET Jul. 31, 2015 Page 51 of 69 Rev 1.01 M0519 6.18 OP Amplifier (OPA) 6.18.1 Overview This device integrated two operational amplifiers. It can be enabled through OP0_EN (OPACR[0]) and OP1_EN (OPACR[1]) bit. User can measure the output of the OP amplifier through the integrated A/D converter. 6.18.2 Features  Analog input voltage range: 0~AVDD  Supports two analog OP amplifiers  Supports OP output voltage measurement by A/D converter  Supports Schmitt trigger buffer outputs and generate interrupt  OP amplifier 0 output can be an optional input source of integrated comparator 0 positive input  OP amplifier 1 output can be an optional input source of integrated comparator 1 positive input M0519 DATASHEET Jul. 31, 2015 Page 52 of 69 Rev 1.01 M0519 7 7.1 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings SYMBOL PARAMETER MIN MAX UNIT VDDVSS -0.3 +6.3 V VIN VSS-0.3 VDD+0.3 V 1/tCLCL 4 24 MHz Operating Temperature TA -40 105 C Storage Temperature TST -55 +150 C - 120 mA Maximum Current out of VSS 120 mA Maximum Current sunk by a I/O pin 35 mA Maximum Current sourced by a I/O pin 35 mA Maximum Current sunk by total I/O pins 100 mA Maximum Current sourced by total I/O pins 100 mA DC Power Supply Input Voltage Oscillator Frequency Maximum Current into VDD Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device. M0519 DATASHEET Jul. 31, 2015 Page 53 of 69 Rev 1.01 M0519 7.2 DC Electrical Characteristics SPECIFICATION PARAMETER Operation voltage Power Ground SYM. VDD VSS/ AVSS TEST CONDITIONS MIN. TYP. MAX. UNIT 2.5 - 5.5 V -0.3 - - V LDO Output Voltage VLDO 1.62 1.8 1.98 V Analog Operating Voltage AVDD 2.5 - VDD V Analog Reference Voltage VREF 1.2 - AVDD V Operating Current IDD1 VDD =2.5V ~ 5.5V VDD >= 2.5V HIRC PLL All digital module 5.5V 12MHz Χ   VDD 38.7 HXT mA Normal Run Mode At 72MHz while(1){} executed IDD2 17.9 mA 5.5V 12MHz Χ  Χ from flash IDD3 37.2 mA 3.3V 12MHz Χ   IDD4 16.4 mA 3.3V 12MHz Χ  Χ IDD5 32.9 mA 5.5V 12MHz Χ   IDD6 15.5 mA 5.5V 12MHz Χ  Χ IDD7 31.4 mA 3.3V 12MHz Χ   VLDO =1.8V IDD8 14.0 mA 3.3V 12MHz Χ  Χ Operating Current IDD9 29.1 mA 5.5V 12MHz Χ   IDD10 14.5 mA 5.5V 12MHz Χ  Χ IDD11 27.6 mA 3.3V 12MHz Χ   VLDO =1.8V IDD12 13.0 mA 3.3V 12MHz Χ  Χ Operating Current IDD13 28.1 mA 5.5V 12MHz Χ   IDD14 14.0 mA 5.5V 12MHz Χ  Χ IDD15 26.6 mA 3.3V 12MHz Χ   VLDO =1.8V IDD16 12.5 mA 3.3V 12MHz Χ  Χ Operating Current IDD17 19.9 mA 5.5V 12MHz Χ   IDD18 10.4 mA 5.5V 12MHz Χ  Χ IDD19 18.4 mA 3.3V 12MHz Χ   IDD20 8.9 mA 3.3V 12MHz Χ  Χ VLDO =1.8V Operating Current Normal Run Mode At 60MHz while(1){} executed from flash Normal Run Mode M0519 DATASHEET At 50MHz while(1){} executed from flash Normal Run Mode At 48MHz while(1){} executed from flash Normal Run Mode At 32MHz while(1){} executed from flash VLDO =1.8V Jul. 31, 2015 Page 54 of 69 Rev 1.01 M0519 SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. Operating Current Normal Run Mode At 22.1184MHz while(1){} executed TYP. MAX. UNIT IDD21 11.7 mA 5.5V Χ  Χ  IDD22 5.3 mA 5.5V Χ  Χ Χ IDD23 11.6 mA 3.3V Χ  Χ  IDD24 5.2 mA 3.3V Χ  Χ Χ IDD25 8.6 mA 5.5V 12MHz Χ Χ  IDD26 4.9 mA 5.5V 12MHz Χ Χ Χ IDD27 7.2 mA 3.3V 12MHz Χ Χ  IDD28 3.4 mA 3.3V 12MHz Χ Χ Χ LIRC PLL All digital module from flash VLDO =1.8V Operating Current Normal Run Mode At 12MHz while(1){} executed from flash VLDO =1.8V Operating Current Normal Run Mode VDD IDD29 0.13 LXT mA At 10kHz while(1){} executed HXT/ 5.5V Χ 10KHz Χ  IDD30 0.12 mA 5.5V Χ 10KHz Χ Χ IDD31 0.11 mA 3.3V Χ 10KHz Χ  IDD32 0.11 mA 3.3V Χ 10KHz Χ Χ VDD HXT HIRC PLL IIDLE1 30.1 mA All digital module 5.5V 12MHz Χ   from flash VLDO =1.8V Operating Current Idle Mode At 72MHz IIDLE2 9.2 mA 5.5V 12MHz Χ  Χ from flash IIDLE3 28.6 mA 3.3V 12MHz Χ   IIDLE4 7.7 mA 3.3V 12MHz Χ  Χ IIDLE5 25.7 mA 5.5V 12MHz Χ   IIDLE6 8.2 mA 5.5V 12MHz Χ  Χ IIDLE7 24.2 mA 3.3V 12MHz Χ   IIDLE8 6.7 mA 3.3V 12MHz Χ  Χ IIDLE9 23.0 mA 5.5V 12MHz Χ   IIDLE10 8.4 mA 5.5V 12MHz Χ  Χ IIDLE11 21.5 mA 3.3V 12MHz Χ   IIDLE12 6.9 mA 3.3V 12MHz Χ  Χ VLDO =1.8V Operating Current Idle Mode At 60MHz while(1){} executed from flash VLDO =1.8V Operating Current Idle Mode At 50MHz while(1){} executed from flash VLDO =1.8V Jul. 31, 2015 Page 55 of 69 Rev 1.01 M0519 DATASHEET while(1){} executed M0519 SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. TYP. MAX. UNIT IIDLE13 22.3 mA 5.5V 12MHz Χ   IIDLE14 8.1 mA 5.5V 12MHz Χ  Χ IIDLE15 20.8 mA 3.3V 12MHz Χ   IIDLE16 6.7 mA 3.3V 12MHz Χ  Χ IIDLE17 16.0 mA 5.5V 12MHz Χ   IIDLE18 6.4 mA 5.5V 12MHz Χ  Χ IIDLE19 14.5 mA 3.3V 12MHz Χ   VLDO =1.8V IIDLE20 4.9 mA 3.3V 12MHz Χ  Χ Operating Current IIDLE21 8.6 mA 5.5V Χ  Χ  IIDLE22 2.2 mA 5.5V Χ  Χ Χ IIDLE23 8.6 mA 3.3V Χ  Χ  IIDLE24 2.2 mA 3.3V Χ  Χ Χ IIDLE25 7.2 mA 5.5V 12MHz Χ Χ  IIDLE26 3.4 mA 5.5V 12MHz Χ Χ Χ IIDLE27 5.7 mA 3.3V 12MHz Χ Χ  IIDLE28 1.9 mA 3.3V 12MHz Χ Χ Χ LIRC PLL All digital module Operating Current Idle Mode At 48MHz while(1){} executed from flash VLDO =1.8V Operating Current Idle Mode At 32MHz while(1){} executed from flash Idle Mode At 22.1184MHz while(1){} executed from flash VLDO =1.8V Operating Current Idle Mode At 12MHz while(1){} executed from flash VLDO =1.8V M0519 DATASHEET VDD Operating Current IIDLE29 0.13 HXT/ LXT mA Idle Mode 5.5V Χ 10KHz Χ  At 10kHz while(1){} executed IIDLE30 0.12 mA 5.5V Χ 10KHz Χ Χ IIDLE31 0.11 mA 3.3V Χ 10KHz Χ  IIDLE32 0.11 mA 3.3V Χ 10KHz Χ Χ VDD HXT HIRC LIRC All digital module 5.5V  Χ Χ Χ from flash VLDO =1.8V IPWD1 Standby Current Power-down Mode Jul. 31, 2015 - A IPWD2 - A 5.5V Χ  Χ Χ IPWD3 - A 5.5V Χ Χ  Χ IPWD4 - A 3.3V  Χ Χ Χ IPWD5 - A 3.3V Χ  Χ Χ Page 56 of 69 Rev 1.01 M0519 SPECIFICATION PARAMETER SYM. TEST CONDITIONS MIN. IPWD6 TYP. MAX. UNIT A - 3.3V Χ Χ Logic 0 Input Current (Quasibidirectional mode) IIL - - -75 A Input Leakage Current (input only) ILK - - 2 A Logic 1 to 0 Transition Current (Quasi-bidirectional mode) ITL[3] - - -660 A Internal Pull-High Resistor of /RESET[1] RRST 15 - - kΩ Input Low Voltage (TTL input) VIL -0.3 - 0.2VDD-0.1 V Input Low Voltage (Schmitt input) VIL1 -0.3 0.3VDD V Input Low Voltage (/RESET, XTAL in) VIL2 -0.3 0.15VDD V Input High Voltage (TTL input) VIH 0.2VDD+0.9 - VDD +0.3 V Input High Voltage (Schmitt input, /RESET, XTAL in) VIH1 0.7VDD - VDD +0.3 V Hysteresis voltage of (Schmitt input) VHY - 0.2VDD - V -360 - - A VDD = 4.5V, VS = 2.4V -60 - - A VDD = 2.7V, VS = 2.2V -50 - - A VDD = 2.5V, VS = 2.0V -25 - - mA VDD = 4.5V, VS = 2.4V -4 - - mA VDD = 2.7V, VS = 2.2V -3 - - mA VDD = 2.5V, VS = 2.0V 16 - - mA VDD = 4.5V, VS = 0.45V 10 - - mA VDD = 2.7V, VS = 0.45V 9 - - mA VDD = 2.5V, VS = 0.45V Source Current (Quasibidirectional Mode) Sink Current (Quasibidirectional and Push-pull Mode) IOH1 IOL Χ VDD = 5.5V, VIN 2.5 V Input Voltage VDD 2.5 Output Voltage 1.62 1.8 1.98 V Operating Temperature -40 25 105 ℃ - 1 - F Cbp NOTE RESR = 1 Ω Note: 1. It is recommended that a 10 uF or higher capacitor and a 100 nF bypass capacitor are connected between V DD and the closest VSS pin of the device. 2. To ensure power stability, a 1 F or higher capacitor must be connected between LDO_CAP pin and the closest V SS pin of the device. Jul. 31, 2015 Page 60 of 69 Rev 1.01 M0519 7.4.3 Low Voltage Reset PARAMETER CONDITION MIN. TYP. MAX. UNIT Operation Voltage - 0 - 5.5 V Quiescent Current AVDD=5.5 V - 1 5 A Operation Temperature - -40 25 105 ℃ Threshold Voltage - 1.6 2.0 2.4 V Hysteresis - 0 0 0 V CONDITION MIN. TYP. MAX. UNIT Operation Voltage - 0 - 5.5 V Temperature - -40 25 105 ℃ AVDD=5.5 V - - 125 μA BOD_VL[1:0]=11 4.2 4.4 4.6 V BOD_VL [1:0]=10 3.5 3.7 3.9 V BOD_VL [1:0]=01 2.6 2.7 2.8 V BOD_VL [1:0]=00 2.1 2.2 2.3 V - 30 - 150 mV CONDITION MIN. TYP. MAX. UNIT - -40 25 105 ℃ V+ - 2 - V Vin > reset voltage - 1 - nA 7.4.4 Brown-out Detector PARAMETER Quiescent Current Brown-out Voltage Hysteresis 7.4.5 Power-On Reset (5V) Operation Temperature Reset Voltage Quiescent Current Jul. 31, 2015 Page 61 of 69 Rev 1.01 M0519 DATASHEET PARAMETER M0519 7.4.6 Temperature Sensor PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Operation Voltage[1] 2.5 - 5.5 V Operation Temperature -40 - 105 ℃ Current Consumption 6.4 - 10.5 μA Gain Temp=0 ℃ Offset Voltage 7.4.7 -1.76 mV/℃ 720 mV Comparator PARAMETER CONDITION MIN. Operation Voltage AVDD - 2.5 Operation Temperature - -40 MAX. UNIT 5.5 V 25 85 ℃ VDD=3.0 V - 20 40 μA Input Offset Voltage - - 5 15 mV Output Swing - 0.1 - VDD-0.1 V Input Common Mode Range - 0.1 - VDD-1.2 V DC Gain - - 70 - dB VCM=1.2 V and VDIFF=0.1 V - 200 - ns 10 20 - mV - ±10 - mV - - 2 μs Operation Current Propagation Delay TYP. M0519 DATASHEET 20 mV at VCM=1 V Comparison Voltage 50 mV at VCM=0.1 V 50 mV at VCM=VDD-1.2 10 mV for non-hysteresis Hysteresis Wake-up Time Jul. 31, 2015 VCM=0.4 V ~ VDD-1.2 V CINP=1.3 V CINN=1.2 V Page 62 of 69 Rev 1.01 M0519 7.4.8 OP Amplifier PARAMETER CONDITION MIN. TYP. MAX. UNIT AVDD - 3.0 3.3 5.5 V Input offset voltage - - 2 5 mV - - 1 uV/℃ Input offset average drift Output swing - 0.1 - VDD-0.1 V Input common mode range - 0.1 - VDD-1.2 V DC gain - - 80 - dB Unity gain freq. AVDD=5V - - 5 MHz - 50° - ° Phase margin PSRR+ AVDD=5V - 90 - dB CMRR AVDD=5V - 90 - dB Slew rate AVDD=5V, RLOAD=33K, CLOAD=50p 6.0 - - V/us Wake up time - - 1 us Quiescent current - - 2 mA M0519 DATASHEET Jul. 31, 2015 Page 63 of 69 Rev 1.01 M0519 7.5 Flash DC Electrical Characteristics SYMBOL PARAMETER VDD CONDITIONS MIN. TYP. MAX. UNIT Supply Voltage 1.62 1.8 1.98 V[2] NENDUR Endurance 10000 cycles[1] TRET Data Retention 100 year TERASE Page Erase Time 20 ms TMER Mass Erase Time 40 ms TPROG Program Time 40 μs IDD1 Read Current IDD2 Program/Erase Current At 25℃ - 0.15 0.5 mA/MHz 7 mA Note : This table is guaranteed by design, not test in production. [1] Number of program/erase cycles. [2] VDD is source from chip LDO output voltage. M0519 DATASHEET Jul. 31, 2015 Page 64 of 69 Rev 1.01 M0519 8 8.1 PACKAGE DIMENSIONS LQFP 100V (14x14x1.4 mm footprint 2.0mm) HD D 7 5 A A2 51 7 6 50 100 26 A1 HE E L 1 25 e L1 c b  Y Controlling Dimension : Millimeters Symbol Dimension in inch Min Nom Max A1 A 2b c 0.063 0.002 0.053 0.007 0.004 D 0.547 E 0.547 0.551 0.551 0.057 0.011 0.05 1.35 0.17 0.008 0.10 0.556 0.556 13.90 13.90 e HD 0.622 0.630 0.638 15.80 HE L 0.622 0.018 0.630 0.024 0.638 0.030 15.80 0.020 L1 y  Jul. 31, 2015 0.055 0.009 0.006 0.45 0.039 7 1.45 14.00 14.10 14.00 14.10 0.50 16.00 16.00 0.60 1.00 0.27 0.20 16.20 16.20 0.75 0.10 0.004 0 1.40 0.22 0.15 M0519 DATASHEET A Dimension in mm Min Nom Max 1.60 0 Page 65 of 69 7 Rev 1.01 M0519 8.2 LQFP 64S (7x7x1.4 mm footprint 2.0 mm) M0519 DATASHEET Jul. 31, 2015 Page 66 of 69 Rev 1.01 M0519 8.3 LQFP 48L (7x7x1.4mm footprint 2.0mm) H 36 25 37 24 48 13 H 12 1  Controlling dimension : Millimeters A A1 A2 b c D E e HD HE L L1 Y 0 Jul. 31, 2015 Dimension in inch Dimension in mm Min Nom Max Min Nom Max 0.002 0.004 0.006 0.05 0.053 0.055 0.057 1.35 1.40 1.45 0.006 0.008 0.010 0.15 0.20 0.25 0.004 0.006 0.008 0.10 0.15 0.20 0.272 0.276 0.280 6.90 7.00 7.10 0.272 0.276 0.280 6.90 7.00 7.10 0.020 0.026 0.35 0.50 0.65 0.014 0.10 0.15 0.350 0.354 0.358 8.90 9.00 9.10 0.350 0.354 0.358 8.90 9.00 9.10 0.018 0.024 0.030 0.45 0.60 0.75 1.00 0.039 0.004 0 M0519 DATASHEET Symbol 7 Page 67 of 69 0.10 0 7 Rev 1.01 M0519 9 REVISION HISTORY Date Revision Description 2015.06.11 1.00 Preliminary version. 2015.07.31 1.01 Added “Flash DC Electrical Characteristics” in section 7.5. M0519 DATASHEET Jul. 31, 2015 Page 68 of 69 Rev 1.01 M0519 Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. Jul. 31, 2015 Page 69 of 69 Rev 1.01 M0519 DATASHEET Important Notice