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1.1
2
AS8501
Data Sheet
3
High precision voltage and current measurement sensor interface
DATA SHEET
2
3
16 bits resolution
Differential inputs
Single + 5V supply
Low power 15 mW
SOIC16 package
Self- and system-calibration
with auto-calibration on power up
16 kHz maximum sampling frequency
Internal temperature measurement
Internal factory trimmed precision reference
Programmable current sources
Digital comparator
Active wake-up
PGA gains 1, 6, 24, 50, 100
Zero offset
Zero offset TC
Extremely low noise
Internal oscillator with comparator for active wake up
3-wire serial interface, !P compatible
Temperature range – 40 to + 125 °C
Individual 24-bit serial number
Applications
Battery management for automotive systems
Power management
mV/µ V-meter
High-precision voltage and current measurement
General description
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The AS8501 is a complete, low power data acquisition system
for very small signals (i.e. voltages from shunt resistors,
thermocouples) that operates on a single 5 V power supply. The
chip powers up with a set of default conditions at which time it
can be operated as a read-only-converter. Reprogramming is at
any time possible by just writing into two internal registers via
the serial interface.
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The AS8501 has four ground refering inputs which can be
switched separately to the internal PGA. Two input channels can
also be operated as a fully differential ground free input. The
system can measure both positive and negative input signals.
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The PGA amplification ranges from 6 to 100 which enables the
system to measure signals from 7mV to 120 mV full scale range
with high accuracy, linearity and speed.
The chip contains a high precision bandgap reference and an
active offset compensation that makes the system offset free
(better than 0,5 !V) and the offset-TC value negligible. The builtin programmable digital filter allows an effective noise
suppression if the high speed is not necessary in the application.
The input noise density is only 35 nV / Hz and due to
Revision 1.1, 04-April-06
INTERNAL TEMPERATURE
ETR
ETS
VBAT
DSP
CONTROLLER
FILTER
INT. CLOCK
TIMER
16 BIT - CONVERTER
PROTECTION
RSHH
PGA
and
LEVEL SHIFT
CURRENT
SOURCES
VDDD
CALIBRATION
DATA
INPUT MUX
RSHL
VSSA
1.26 V
REFERENCE
BUF
CHOPPER
VDDA
VSSD
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AGND
REF
CLK
COMPARATOR
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Features
SERIAL INTERFACE / CONTROL REGISTERS
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SCLK
SDAT
INTN
Figure 1: Functional Block Diagram
the high internal chopping frequency the system is free of 1/f-noise down
to DC.The 0-10 Hz noise is typical below 1 µ V i.e. as good or better than
any other available chopper amplifier.
For high speed synchronous measurements the chip can run in an
automatic switching mode between two input channels with preprogrammed parameter sets.
The circuit has been optimised for the application in battery management
systems in automotive systems. As a front end data acquisition system it
allows an high quality measurement of current, voltage and temperature
of the battery.
With a high quality 100 !" resistor the system can handle the starter
current of up to 1500 A, a continuous current of # 300 A as well as the
very low idle current of a few mA in the standby mode.
For external temperature measurement the chip can use a wide variety of
different temperature sensors such as RTD, PTC, NTC, thermocouples or
even diodes or transistors. A built-in programmable current source can be
switched to any input and activate these sensors without the need of
other external components.
The measurement of the chip temperature with the integrated internal
temperature sensor allows in addition the temperature compensation of
sensitive parameters which increases the total accuracy considerably.
Sensor specific data can be stored in the internal Zener-Zap memory and
are used to calibrate each measurement in the internal data processing
unit before transmission to the external µ C via the serial SDI interface.
The flexibility of the system is further increased by a digital comparator
that can be assigned to any measured property
(current, voltage, temperature) and an active wake-up in the sleep-mode.
All analog input-terminals can be checked for wire break via the SDIinterface.
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EZPRG
austriamicrosystems
AS8501 - Data Sheet
CONTENTS
1
FEATURES ........................................................................................................................................................................................ 1
2
APPLICATIONS................................................................................................................................................................................. 1
3
GENERAL DESCRIPTION ................................................................................................................................................................ 1
4
PIN FUNCTION DESCRIPTION FOR SOIC 16 PACKAGE.............................................................................................................. 3
5
ABSOLUTE MAXIMUM RATINGS.................................................................................................................................................... 4
6
ELECTRICAL CHARACTERISTICS ................................................................................................................................................. 5
7
FUNCTIONAL DESCRIPTION .......................................................................................................................................................... 9
POWER ON RESET ........................................................................................................................................................................... 9
ANALOG PART, GENERAL DESCRIPTION ............................................................................................................................................ 9
7.2.1
Reference voltage ............................................................................................................................................................ 10
7.2.2
Current sources ................................................................................................................................................................ 11
7.2.3
Internal temperature sensor ............................................................................................................................................. 12
7.3 DIGITAL PART ................................................................................................................................................................................ 12
7.3.1
Sampling rate ................................................................................................................................................................... 12
7.3.2
Calibration ........................................................................................................................................................................ 13
7.4 MODES OF OPERATION .................................................................................................................................................................. 13
7.5 REGISTER DESCRIPTION ................................................................................................................................................................ 15
7.5.1
OPM operation mode register ( 4 bits ) ............................................................................................................................ 16
7.5.2
CRG general configuration register ( 28 bits ) .................................................................................................................. 16
7.5.3
CRA measurement channel A configuration register ( 17 bits ) ..................................................................................... 17
7.5.4
CRB measurement channel B configuration register ( 17 bits ) ...................................................................................... 19
7.5.5
ZZR Zener-Zap register (188 bits ).................................................................................................................................. 20
7.5.6
CAR calibration register ( 110 bits )................................................................................................................................. 22
7.5.7
TRR trimming register ( 20 bits ) ...................................................................................................................................... 22
7.5.8
THR alarm (Wake-up) threshold register ( 17 bits )......................................................................................................... 25
7.5.9
MSR measurement result register ( 18 bits )................................................................................................................... 25
8
DIGITAL INTERFACE DESCRIPTION............................................................................................................................................ 25
8.1 CLK ............................................................................................................................................................................................. 25
8.2 INTN............................................................................................................................................................................................ 25
8.3 SDI BUS OPERATION...................................................................................................................................................................... 26
8.4 DATA TRANSFERS .......................................................................................................................................................................... 27
8.5 SDI BUS TIMING............................................................................................................................................................................. 28
8.6 SDI ACCESS TO OTP MEMORY ....................................................................................................................................................... 29
8.6.1
ZZR register bit mapping .................................................................................................................................................. 29
8.6.2
Stored ZZR-register mapping ........................................................................................................................................... 33
9
GENERAL APPLICATION HINTS................................................................................................................................................... 34
9.1 GROUND CONNECTION, ANALOG COMMON....................................................................................................................................... 34
9.2 THERMAL EMF.............................................................................................................................................................................. 34
9.3 NOISE CONSIDERATIONS ................................................................................................................................................................ 35
9.4 SHIELDING, GUARDING ................................................................................................................................................................... 35
10 TYPICAL PERFORMANCE CHARACTERISTICS.......................................................................................................................... 36
12
13
REVISION HISTORY ....................................................................................................................................................................... 38
ORDERING INFORMATION............................................................................................................................................................ 38
CONTACT........................................................................................................................................................................................ 39
14.1
HEADQUARTERS ...................................................................................................................................................................... 39
14.2
SALES OFFICES ....................................................................................................................................................................... 39
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PACKAGE DIMENSIONS................................................................................................................................................................ 38
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7.1
7.2
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austriamicrosystems
AS8501 - Data Sheet
4
PIN function description for SOIC 16 package
PIN
Name
description
1
RSHL
anlalog input from shunt resistor low side
2
RSHH
anlalog input from shunt resistor high side
3
ETS
analog input with reference to RSHL
Comment
analog common for VBAT, ETS and ETR; return for internal
current source
analog input for differential input ETS-VBAT
analog output for current-source
VBAT
analog input with reference to RSHL
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4
analog input for differential input ETS-VBAT
analog output for current-source
VSS
0V-power supply for analog part
6
EZPRG
digital power input for programming Zener fuses.
7
VSSD
0V-power supply and ground reference point for digital part
This input must be open or connected to VDDD. It is not intended,
that OTP content is modified by the user.
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5
CLK
digital input for external clock, master clock input
9
SCLK
serial port clock input for SDI-port
the user must provide a serial clock on this input
10
SDAT
serial data in- and output
11
INTN
Digital I/O for interrupt from comparator
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8
external clock typical 8.192 MHz; during MWU-mode external
connection must be high impedance or connected to VDDD to
reduce current consumption
signal wake-up to external µ C
conversion ready flag for external interupt and synchronisation in normal mode
12
VDDD
+ 5V digital power supply
13
VDDA
+ 5V analog power supply
14
REF
reference input/output
15
AGND
analog ground, ground reference for ADC
16
ETR
analog input with reference to RSHL
must be connected to VSS with a 30 nF capacitor
this PIN must be connected with a 50-100nF-capacitor to VSS;
no direct connection to VSSD/VSS allowed
analog output for current-source
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Table 1: Pin Description
Figure 2: Schematic Package outline SOIC 16
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Page 3 of 40
austriamicrosystems
AS8501 - Data Sheet
5
Absolute Maximum Ratings
Stress beyond those listed under “Absolute Maximum Ratings“ may cause permanent damage to the device. These are stress ratings only. Functional
operation of the device at these or any other conditions beyond those indicated under “Operating Conditions” is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability. All voltages are defined with respect to VSS and VSSD. Positive currents
flow into the IC.
Absolute maximum ratings (TA = -40°C to 125°C unless otherwise specified)
3
Input current
(latch-up immunity)
Electrostatic discharge
4
Ambient temperature
5
6
7
8
9
Storage temperature
Soldering conditions
Humidity, non-condensing
Thermal resistance
Power dissipation
MIN
-0.3
Vin
TYP
MAX
7.0
UNIT
V
-0.3
VDD +0.3
V
ISCR
-100
100
mA
ESD
-2
2
kV
TA
-40
125
OC
TSTRG
TLEAD
-55
150
260
85
75
350
OC
5
RthJA
PTOT
NOTE
Polarity inversion externally
protected
JEDEC 17
1)
(Tj = 150°C)
°C
%
K/W
mW
2)
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SYMBOL
VDD
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PARAMETER
Supply voltage
Analogue VDDA and digital VDDD
Input pin voltage
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0
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Notes:
1) MIL 883 E method 3015, HBM: R =1.5 k", C =100pF.
2) Jedec Std – 020C, lead free
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austriamicrosystems
AS8501 - Data Sheet
6
Electrical characteristics
1)
2)
3),4)
2)
3) 4)
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VDDA=5V +/-0.1 V, fclk=8.192 MHz, chopping ratio MM=4 (see 7.5.3), oversampling frequency=2.048 MHz, oversampling ratio=128
temperature range : -40 to 125°C if not otherwise noted
symbol
parameter
conditions
min
typ
max
units
input characteristics
for gain 1 the input signal is connected directly to th input of the converter, this is not possible for the RSHH-RSHL
G1
input
Gain
gains of PGA
6, 24, 50, 100
AC_g6
Accuracy at gain 6
0 to 85 °C
1.0
% @-120mV
-40 to 125°C
1.5
% @-120mV
AC_g24
Accuracy at gain 24
0 to 85 °C
0.5
0.08
% @+-20mV
-40 to 125°C
1.5
0.3
% @+-20mV
AC_g50
Accuracy at gain 50
0 to 85 °C
1.0
% @+-10mV
AC_g100
Accuracy at gain 100
0 to 85 °C
1.0
% @+-5mV
Vin
input voltage ranges
G1
-350
-300 to + 800
900
mV
(with reference to RSHL)
G6
-200
+/- 120
160
mV
G24
-40
+/- 30
40
mV
G50
-20
+/- 15
20
mV
G100
-10
+/- 7.5
10
mV
4)
4)
5) 6)
5) 7)
5) 7)
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5) 8)
5) 8)
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Notes:
1) the absolute gain values are subjected to a manufacturing spread of +/-30% max in the full temperature range. all gain values can be digitally
calibrated together with the external circuitry with a resolution better than 0.065%
2) Current measurement paths for G6 and G24 are trimmed for minimum Temperature coefficient. The trimm algorithm is based on a 2 temperature
measurement at 23°C and 60°C.
Accuracy is mainly determined by bandgap characteristic and gain variation over temperature.
A TC shift of typically -15 ppm/K will occure during solder process which is compensated by a systematic offset during trimming.
3) due to a nonlinear behaviour of the gain and reference voltage over temperature the accuracy is lower for the extended temperature range.
4) The minimum limits for G50, G100 are derived from device characterization and not tested. Towards 125°C the TC values are higher.
therefore it is recommended to use these gain settings only for applications in the temperature range 0 to 85°C.
5) if not otherwise specified the ranges are calibrated to the typical values. The maximum and minimum value represent the maximum usable span
accepting linearity deviation up to 1000 digits. Min, max limits are tested at room temperature only!
6) this gain range is not using the internal PGA, the input is directely connected to the AD-converter. Therefore the input resistance is lower then for
other gain ranges.
It has been designed mainly for positive input voltages up to 0.8 V i.e. for measurements of temperature with transistors and diodes.
The limitation for negative input voltages is due to the onset of conduction of the input protection diodes.
7) the ASSP is optimised for G6 and G24 concerning linearity, speed and TC, therefore these ranges are recommended whenever possible.
8) because of higher TC value at elevated temperature G50 and G100 are recommended for applications in the temperature range 0 to 85°C
Revision 1.1, 04-April-06
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austriamicrosystems
AS8501 - Data Sheet
Electrical characteristics (continued)
VDDA=5V +/-0.1 V, fclk=8.192 MHz, chopping ratio MM=4 (see 7.5.3), oversampling frequency=2.048 MHz, oversampling ratio=128
temperature range : -40 to 125°C if not otherwise noted
lin_err
nonlinearity
lin_errTC
TC of linearity error
offset voltage:
RSHH_RSHL
offset voltage: ETS, ETR,
VBAT
Vos
Offset voltage drift: RSHHRSHL
input bias/leakage current,
all channels
voltage noise density
(G=24)
current noise density
(G=24)
voltage noise, peak (G=24)
dVos/dT
typ
0.1
max
0.2
units
%
0.1
0.03
0.05
0.05
1
0.3
0.05
0.07
0.1
5
% or 30 digits
% or 10 digits
% or 15 digits
% or 20 digits
ppm/K
1)
Vndin
Indin
en p_p
en_RMS
voltage noise, RMS (G=24)
signal to noise (G=24,
G4.8)
signal to distortion (G24,
G4.8)
chanel to chanel insulation
power supply rejection ratio
SNR
SDR
CCI
PSRR
2)
2)
2)
2)
3)
-40 to 125°C
-0.5
0.2
0.5
µV
4)
-40 to 85°C
85 to 125°C
-2
-4
0.5
1
1
2
µV
µV
4)
-40 to 85 °C
room temperature
0.002
-1
0.2
f=0 to 1 kHz
4)
µ V/K
1
nA
5)
35
50
nV//Hz
6)
100
5
1.5
2
fA//Hz
µV
µV
µV
6)
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conditions
min
G1, 720 mV
G6, 120 mV
G24, 30 mV
G50, 15 mV
G100, 7.5 mV
gain 6 @ room temp
gain 24 @ room temp
gain 50 @ room temp
gain 100 @ room temp
all gains
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parameter
calibration error
for 30 000 digits output at
full range
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symbol
cal_err
f=10 Hz
0 to 100 Hz
0 to 10 Hz
1000 Hz
5
2
0.5
20
3
1
1.5
room temperature
90
100
dBmin
room temperature
room temperature
4.9 to 5.1 V
80
-70
-50
100
-90
-60
dBmin
dBmax
dBmax
6)
6)
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Notes:
1) at room temperature / corresponding calibration factors are stored within the ZZR-register
2) whatever is lower. Maximum limits for gains 50 and 100 are derived from device characterization and are not tested.
3) this value measured in raw mode at room temperature and at 60°C. Maximum limits over temperature range are derived from device characterization.
4) TC variations are included in the above given maximum limit of linearity error. Max value is derived from device characterization and not tested
5) Leakage current is specified for all gain settings (except G1) for positive input voltages below 200 mV. Test is done at different input voltages with
subsequent extrapolation for 200mV. In the temperature range 85-125°C it may be as high as 5 nA at the upper limit. In normal operation a
temperature independent digital offset of -0.7 digits is present due to internal rounding.
6) This parameter is not measured directly. It is measured indirectly via gain measurement of the whole path at room temperature
Revision 1.1, 04-April-06
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Page 6 of 40
austriamicrosystems
AS8501 - Data Sheet
Electrical characteristics (continued)
1) 2)
3)
4)
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VDDA=5V +/-0.1 V, fclk=8.192 MHz, chopping ratio MM=4 (see 7.5.3), oversampling frequency=2.048 MHz, oversampling ratio=128
temperature range : -40 to 125°C if not otherwise noted
symbol
parameter
conditions
min
typ
max
units
data conversion
RES
resolution
all channels
16
bits
Vref
reference voltage
room temperature
1.13
1.21
1.30
V
Vref_TC
temperature coefficient of Vref
-50
50
ppm/K
Vref_Ri
internal resistance of Vref
Rload > 50 kOhm
200
Ohm
fovs
clock frequency
4.096
MHz
R1
oversamplig ratio
64
128
MM
conversions during chopper cycle
4
8
BW
bandwidth
7.8
1000
16000
Hz
av
internal averaging
1
4
1024
cycles
fclk
external clock frequency
0.05
8.192
10
MHz
CLK_extdiv
clock division factor
2
4
DR_clk
duty ratio of external clock
50
%
int_fclk
internal clock frequency
180
250
330
kHz
analog inputs
RSHH, VBAT, ETS, ETS
Rin
input resistance
Ue < 150 mV
50
100
MOhm
Cin
input capacitance at gain 24
8
15
30
pF
internal temperature sensor
T_out20
output at 23°C
G 6, typical
22500
23 000
23500
digits
T_sl
slope
-20 to 100°C
73
75
77
digits/degC
Terr85
error of temperature measurement 0 to 85°C
0.5
2
degC
Terr125
-40 to 125°C
1
3
degC
current source
output to RSHH, RSHL
Icurr_rshh
1.5
2
3
µA
5)
6)
7)
7)
7)
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Notes:
1) with external averaging the resolution can be increased up to 21 bits with an effective sampling rate below 10 Hz
2) the system works in overflow condition without degradation of accuracy up to 1.4 * range width.
This means that the overflow bit can work as bit no.17 in this range.
3) the absolute value will be trimmed digitally to (1.28*/-0.01) V at 23°C, if not otherwise specified
4) the TC-value will be trimmed digitally to end up with a typical TC-value of the output ( total measurement path) at G24 better than 20 ppm/K the
TC- value of the
reference voltage after trimming may be typically as high as 50 ppm/K due to manufacturing spread. Min,max limits are not tested but derived
from device
characterization
5) in the temperature range 0 - 85°C the clock frequency can be increased to 12 MHz
6) value trimmed to +/- 30 digits during final test and stored into ZZR
7)The slope of the sensor is measured on sample basis per lot and not tested per device. The specified limits are derived from device
characterization.
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austriamicrosystems
AS8501 - Data Sheet
Electrical characteristics (continued)
1)
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VDDA=5V +/-0.1 V, fclk=8.192 MHz, chopping ratio MM=4 (see 7.5.3), oversampling frequency=2.048 MHz, oversampling ratio=128
temperature range : -40 to 125°C if not otherwise noted
symbol
parameter
conditions
min
typ
max
units
programmable current source
output to Vbat, ETS, or ETR
Icurr_ON
current level
0
248
µA
I_steps
current steps
6
8
10
µA
Dcurr
accuracy, room temperature
248 µ A
0.2
0.5
%
TC_CS
temperature coefficient
830
900
1000
ppm/K
Icurr_OFF
current when off
room temperature
0.001
0.01
µA
Icurr_Ri
internal resistance of current source Ua < 2 V
10
MOhm
digital CMOS inputs with pull up and schmidt-trigger
input PINs CLK and SCLK
Vih
high level input voltage
VDDD=5V
3.5
V
Vil
low level input voltage
VDDD=5V
1.5
V
Iih
current level
VDDD=5V, Vih=5V
-1
1
µA
Iil
current level
VDDD=5V, Vil=0
30
120
µA
digital CMOS outputs
output PINs SDAT and INTN
Voh
high level output voltage
VDDD=5V, -633uA
4.5
V
Vol
low level output voltage
VDDD=5V, 564uA
0.4
V
Cl
capacitive load
20
pF
Tristate digital I/O
Voh
high level output voltage
VDDD=5V, -633uA
4.5
V
Vol
low level output voltage
VDDD=5V, 564uA
0.4
V
tristate leakage current to
Ioz
VDDD,VSSD
VDDD=5V
-1
1
µA
Vih
high level input voltage
VDDD=5V
3.5
V
Vil
low level input voltage
VDDD=5V
1.5
V
EZPRG input
programming voltage - for factory
Vprg
programming only
VDDD=5V
V
supply current
Isup
normal operation
VDDD=VDDA=5V
3
5
mA
Iaw
active wake-up
VDDD=VDDA=5V
40
100
µA
supply voltage
VDDA
positive analog supply voltage
4.7
5.0
5.3
V
VDDD
positive digital supply voltage
4.5
5.0
5.5
V
VSS, VSSD
negative supply voltage
0
V
Power On Reset
Vporhi
Power on reset Hi
2.5
4.1
V
Vhyst
Hysteresis
0.1
0.3
V
2)
3)
4)
5)
5)
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Notes:
1) not tested, derived from device characterization
2) for factory calibration only. During normal operation this PIN must be connected to VDDD.
3) the average current is dependent on the on-time of the measurement system i.e. it can be programed via the CRA register
4) stability of analog supply should be within +/- 0.1 V
5) tested at room temperature only
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austriamicrosystems
AS8501 - Data Sheet
7
Functional Description
7.1
Power on Reset
The power on reset is iniciated during each power up of the ASSP and can be triggered purpously by reducing the analog supply voltage (VDDA) to a
value lower than Vporlo for a time interval longer than 0.5 µ sec.
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During power on reset sequence the following steps are performed automatically:
The chip goes to mode MZL (see 7.4)
Internal clock is enabled
The calibration constants are loaded from Zener-zap memory to the appropriate registers (ZTR=>TRR, ZCL=>CAR). The load procedure is
directed by the internal clock and can be monitored on INTN pin. 188 clock pulses are generated from the internal oscillator source. Pulse period
is equal to internal clock period.
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After the power-on reset sequence is finished:
the operation continues with internal clock if no external clock is detected. In this case the ASSPs switches to mode MWU with default value of
threshold register ( 214 )
If external clock is available the ASSP switches to mode current measurement MMS (default measurement with default configuration: gain=100,
fovs=4.096MHz, R1=64, MM=4, R2=1, NTH=214).
The microcontroller can communicate via SDI interface whenever appropriate, i.e. CAR and TRR register can be rewritten from the µ C if
necessary.
Because the automatic selected calibration factor (CGI4) is loaded with zeros, the ASSP delivers constant zero at the output to allow the µ C to
check for an unwanted POR. To bring the ASSP back into normal operation for current
measurement with gain100 the µ C has to copy the CAU4 content into the CGI4 factor in the CAR-register.
(see also 7.5.5 and 8.6.2)
7.2
Analog part, general description
The input signals are level shifted to AGND (+ 2.5 V) then switched by the special high quality MUX- which contains also the chopper – to the input of
the programmable gain amplifier (PGA). This low noise amplifier is optimised for best linearity, TC- value and speed at gain 24.
The systems contains an internal bandgap reference with high stability, low noise and low TC-value. The output of a programmable current source can
be switched to the analog inputs VBAT, ETS and ETR for testing the sensor connections
or for external activation of resistors, bridges or sensors (RTD, NTC). The voltage drop generated by the current is measured at the corresponding
input/output PIN.
For the wire break test of the RSHH and RSHL inputs special low noise current sources are implemented.
The integrated temperature sensor can also be switched to the PGA by the MUX and measured any time. The chip temperature can be used for the
temperature compensation of
the gain of the different channels in the external µ C, which increases the absolute accuracy considerably.
M7
CURRENT
SOURCE
ni
M6
ca
The offset of the amplifier itself is already fairly low, but to guarantee the full dynamic range it can be trimmed via the digital interface to nearly zero
independent of the autozero chopping function.
In the same way the manufacturing spread of the absolute value of the reference voltage can be eliminated and the TC-value set to nearly zero by a
trimming process via the SDI interface.
For more details of the input multiplexer see the following schematic. The position of all switches is defined by writing into the registers CRA, CRB and
CRG via the SDI bus, which is explained in 7.5.2 through 7.5.4.
ETR
M9
M8
ETS
INTERNAL
TEMPERATURE
M 15
ch
M2
M 14
VBAT
Te
M 10
M4
M3
M5
RSHH
RSHL
M1
PGA
ADCONVERTER
M 12
M 13
AUXILIARY
CURRENT
SOURCE
Figure 3: Multiplexer
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austriamicrosystems
AS8501 - Data Sheet
7.2.1
Reference voltage
The ASSP contains a highly sophisticated precision reference voltage. Its typical temperature dependence is a slight parabola shaped curve and is
shown in figure 21. This reference voltage is used mainly for the internal AD-converter, but can also be used for external purposes if the impedance of
the external circuitry is high enough.
1 ,2 6
1 ,2 2
al
id
1 ,2 0
1 ,1 8
1 ,1 6
m e a s u re m e n t
o p e n lo o p v a lu e
1 ,1 4
1 ,1 2
30
50
70
90
110
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10
lv
reference voltage in V
1 ,2 4
re s is ta n c e lo a d in k O h m
Figure 4: Reference voltage as function of resistance load
The absolute value and its temperature coefficient (TC) is given by the content of the TRR register. This opens the possibility to calibrate the reference
voltage to the optimum absolute value (i.e. 1.28 V) and the TC value to zero thus eliminating fully the production spread.
Writing into subregister TRIMBV of TRR changes the absolute value linearly by 5.1 mV per digit as shown in the following graph and described in full
detail in 7.5.7
1 ,3 6
1 ,2 8
7 5 °C
1 ,2 4
2 4 °C
ca
reference voltage in V
1 ,3 2
ni
1 ,2 0
ch
1 ,1 6
0
5
10
15
20
25
30
c o n t e n t o f T R IM B V in b its
Te
Figure 5: Reference voltage as function of temperature
Trimming the TC value is similarly done by writing into subregister TRIMBTC. Since the TC trimming is also changing the absolute value it is important
to trim the TC first and then the absolute value.
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austriamicrosystems
AS8501 - Data Sheet
200
100
50
0
c h a n g e 1 2 .7 p p m /K
p e r s te p
-5 0
-1 0 0
-1 5 0
-2 0 0
-2 5 0
5
10
15
20
25
s e ttin g o f s u b r e g is te r T R IM B T C o f T R R
Figure 6: Temperature coefficient as function of TRIMBTC setting
30
35
lv
0
al
id
temperature coefficient in ppm/K
150
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The TC trimming also opens the unique possibility to change the TC-value within the time of reprogramming of the TRR-register (i.e. within µ sec) to
allow the compensation of
different TC-values of the external circuitry for different channels.
In addition it can be used for very fast autocalibration of the total TC of a given channel. An external reference voltage is applied to the channel to be
checked. Then all numbers from 0 to 31 are written into subregister TRIMBTC and a reading is done for the input voltage and the internal temperature
as well. The same is repeated at any temperature above RT. From these data the TRIMBTC setting for a minimum drift can be easily calculated.
7.2.2
Current sources
The AS8501 contains several current sources which can be used for checking all input lines for wire brake, to control external circuitry or to activate
external sensors.
Main current source
The main current source can be digitally controlled via the content of the CRG register in 31 steps of 8 µ A in the range of 0 to 248 µ A. Its absolute
value can be calibrated by writing in the subregister TRIMC of TRR.
The current source can be switched to the inputs VBAT, ETR or ETS to activate external sensors like RTDs, NTCs or resistance briges and strain
gages. It can also be used to detect a wire breake of external connected sensors. Performing a measurement with a high and a low (or zero) current
opens the possiblity to eliminate thermal EMF voltages in external sensors.
Te
ch
ni
ca
Secondary current sources
The ASSP contains two other high quality current sources supplying a current of approx. 2µ A at the inputs RSHL and RSHH. These current sources
can be switched on and off at any time to check the correct connection of both terminals. During off state they must not interfere with the high sensitive
voltage inputs, especially the noise level should not be increased. If one of the terminals is an open connection the amplifier goes into saturation and
the overflow bit is set.
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austriamicrosystems
AS8501 - Data Sheet
7.2.3
Internal temperature sensor
The ASSP contains a high sensitive precision temperature sensor which can be used at any time. The sensor supplies a very linear voltage signal with
an offset at 23 degC, which is calibrated and stored in the ZZR-register. The voltage can be measured using the internal circuitry with gain 6, with free
selection of all other parameters defining the sampling rate.
35000
100
50
25
25000
0
-25
20000
-50
linearity deviation
-75
cubic fit
15000
lv
output signal
al
id
30000
inearity deviation in digits
Internal temperature in digits
75
-100
-50
-25
0
25
50
75
100
125
150
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Temperature in deg C
175
Figure 7: Measurement of internal temperature sensor over oil bath temperature
The slope of the curve is approx. 75 digits per degC.
The calculation of the temperature has to be done in the external µ C acc. to the following simple formula:
Tint=( Uint(T)-Uint(23) ) / 75 + 23°C
Uint(T) is the measured result and Uint(23) is the reference value at 23°C, which is stored as an 11 bit-word in the ZZR-register.
Bits 15, 14 ,13 and 12 will always be the same at room temperature (0101 bin or 20480 dec), therefore it makes no sense to store them for each single
part. In addition we dont need the high resolution of one digit, which means 1/71.3 = 14 milli Kelvin. Therefore we cut the last bit and achieve a word of
11 bit length, which finally is stored in the ZZR-register as shown in the ‚stored ZZR-register mapping‘ given in 8.6.2
Example:
value stored in the ZZR-register:
1060 dez or 10000100100 bin
0
= 22600 dec
ca
Uint(23) = 0101 10000100100
Add register content Add
If your measured value is : Uint(T) = 23767 dec
Digital part
ch
7.3
ni
Ti[°C]= ((23767-22600) / (75 digits / °C)) + 23 °C
= 15.6 °C + 23 °C = 38.6 °C
Te
In the digital part the result of the AD-converter is processed, i.e. calibration, active offset cancellation and filtering is done. In addition the
communication via the serial SDI interface is handled and all circuit functions (like voltage and current path settings, chopping, dechopping) are
controlled.
Whenever the power supply line returns from below 2.0 V to above 3.5 V a power-up circuitry is activated which loads the internal calibration registers
from the Zener-Zap memory into the working register and starts the chip in a special default mode.
7.3.1
Sampling rate
the sampling rate (SR) is defined by the setting of parameters in register CRA or CRB. The oversampling frequency (OSF), the oversampling ratio
(OSR), the chopping ratio (MM) and the averaging number (AV). The sampling rate can be calculated acc. to the following formula:
SR= OSF/(OSR*MM*AV)
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AS8501 - Data Sheet
For an clock frequency of 8.192 MHz it can vary between
16 000 kHz and 1.95 Hz.
In the dual mode the ASSP is switching automatically between the two channels and it needs at least one measurement for each polarity to get a valid
measurement. In addition the ASSP needs some time to reprogram the internal registers and switches. Therefore the maximum sampling frequency is
limited to 7.5 kHz for the above given clock frequency. The internal averaging is not working in the dual mode, but the sampling frequency can be
different for each channel.
7.3.2
Calibration
The calibration of the ASSP is done by a test setup as follows:
room temperature calibration of the internal temperature sensor
absolute input-output calibration for all gain settings
TC calibration for the measurement path for gain 24
input/mV
output/digits
1
6
24
50
100
720
120
30
15
7.5
30 000
30 000
30 000
30 000
30 000
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gain
lv
Table 7.2.2
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id
The absolute input-output calibration of the gain ranges is done that way that for a given input voltage 30 000 digits at the output are produced:
In addition the ASSP receives an individual 24-bit serial number.
The TC-value of the output (total measurement path) for G24 is trimmed to a minimum value by selecting the best setting of the TRIMBTC subregister
of the TRR register (see 7.5.7).
A similar calibration is done for the other subregisters TRIMBV, TRIMA and TRIMC for the absolute value of the reference voltage, the offset of the PGA
and the current source respectively.
All these data are stored in the ZZR register according to the ‚stored ZZR-register mapping‘ given in 8.6.2
7.4
Modes of operation
The AS8501 can run in different operation modes, which are selected and activated via the serial interface.
Detailed description:
Mode 0: MZL
In power-on reset sequence, which is initiated by the on-chip power-on reset circuit whenever the power is connected , the registers are loaded from the
Zener-Zap memory.
ca
Mode 1: MMS
Measurement mode where the definition is taken from the registers CRA and CRG defined later on. The measurements are continuous and measured
results are available after the ready flag (INTN pin) is set to LO. The result can be read by the µ C any time after this bit is set to LO. However, to obtain
the best noise performances the result should be read when INTN pin is at LO state. All modules are in power-up.
ch
ni
Mode 2: MMD
Dual channel measurement mode. Two consecutive different measurements are performed according to the settings in the configuration registers CRA,
CRB and CRG defined later (usually CRA defining current measurements and CRB voltage measurement). One complete measurement is performed
with each setting. CRG register holds common settings.
The measurements are continuous (A,B,A,B). The 17th bit in the output register defines, which measurement has been executed according to the
definition LO=A, HI=B.
The number of consecutive measurements with equal configuration is defined in register CRG (bits s3,s2,s1,s0). All modules are in power-up.
Te
Mode 3: MWU
In this wake-up mode the internal clock finclk=256kHz is running and one complete measurement is performed in the period from 1 to 1.5 s with the
parameter settings of the CRA register. Before the actual measurement is performed the logic powers up all internal circuits especially the AGND and
the Vref. If the external load is higher than 70 kOhms both signals can be used for external triggering or even as interrupt for the µ C.
If the external clock is not running, this input should be high impedance. To achieve a stable low idle current the oversampling ratio should be set to
R1=128 and the CFG register must be programmed to x00003, see also 7.5 ‘Register description’. It is assumed that the threshold level in the THR
register is defined within the 16 bit range, if not the default value is 210
After one measurement is finished all modules except the on- board oscillator and divider are switched into power down condition to save power. The
MSR register is updated with the last measurement result. Whenever this value exceeds the digital threshold the (wake-up) INTN pin goes LO for one
clock cycle to trigger the wake-up event in the external µ C.
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austriamicrosystems
AS8501 - Data Sheet
After that the circuit returns in power-down for approximately 1s. During this time the last measurement (MSR register) is available on the SDI interface.
In this intermediate sleep-mode all modules except internal oscillator and divider are in power-down mode. The SDI interface works independent which
means that the measurement result is available by reading the MSR register. At any time the microprocessor can start any other mode via SDI. In such
a case the external clock must be switched on first.
The chip goes in MWU mode (mode 3) after it received the command for that. After that command 6 or more additional CLK pulses are needed before
external clock may go to power down mode (no CLK pulses, high level because of internal pull-up resistors). This 6 CLK pulses are needed for
synchronisation. On the way back to normal mode this restriction is not needed.
Mode 5: MZP
Zener-Zap programming/reading. This mode for factory programming only and should not be used by the customer.
al
id
Mode 4: MAM
In this alarm mode the measurement defined in CRA is going on. The channel bit in the THR register must be cleared (channel A). The threshold value
may be positive or negative. Whenever the measured value exceeds the digital threshold value in the THR register the pin INTN (in this mode its
function is to signal alarm-condition) goes LO for one clock cycle. For negative threshold value the signed measurement result must be more negative
than the THR value to activate the alarm. During measurements the signal INTN is high. All modules are in power-up, measurements are continuously
going on.
lv
Mode 6: MPD
Power down mode. Individual analog blocks can be disabled/enabled. The data acquisition system is not running during this mode is activated.
am
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Mode 7: MSI
The operation in this mode is exactly the same as in MMS mode except that the internal clock is used.
The SDI interface signals can become active whenever appropriate. This mode can be used if no external clock CLK is available. The measuring speed
is reduced by a factor of 16.
Te
ch
ni
ca
Modes 8-15: These modes are reserved for testing purposes and should not be used by the customer. Reading and writing of some registers is only
possible in these higher modes. Write to registers CAR (calibration register) and TRR (trimming register) is allowed only in test modes.
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austriamicrosystems
AS8501 - Data Sheet
Modes of operation, register OPM
Description
Power on, loading from Zener-Zap
memory
Single measurement
mo3
0
mo2
0
mo1
0
mo0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
MMS
2
MMD
3
MWU
Double measurement
(A,B,A,B …)
Wake-up
4
MAM
Alarm
0
1
0
0
5
MZP
Zener program/read
0
1
0
1
6
MPD
Power down
0
1
1
0
7
MSI
0
1
1
1
1
x
x
x
8-15
Reserved for testing
1)
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Name
MZL
7.5
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Notes:
1) Register addresses 12, 13, 14 and 15 are reserved for testing and future options; operations on these
registers must be avoided
lv
Mode
0
Register description
REGISTER
ADDRESS
SIZE
OPM
0
4
Operating mode register
7.5.1
1
17
Measurement A configuration register
7.5.3
2
17
Measurement B configuration register
7.5.4
3
28
General configuration register
7.5.2
4
18
Measurement result register
7.5.9
5
188
Zener-Zap register
7.5.5
6
110
Calibration register
7.5.6
ca
In the following sections the register contents and their functions are described in detail. Since the length of some
registers is too long to present clearly, the registers are logically subdivided according to their functions and described
separately.
All internal functions are controlled by the contents of these registers which can be reloaded via the serial SDI interface at
any time. The AS8501 contains the following registers:
7
20
Trimming register
7.5.7
8
17
Alarm or wake-up threshold register
7.5.8
9
20
Test and special configuration register
10-12
Test registers
CRA
CRB
CRG
MSR
ZZR
CAR
TRR
THR
reserved
1)
Detailled description see
1)
This register is reserved for testing modes. Writing is possible only in mode 8. In order to assure
stable conditions in power-down modes MWU(3), MPD(6), TMSS(8) and MSI(13) the default
setting of the CFG register must be changed to x00003. It is not necessary to change this value
during normal operation.
Te
ch
Note:
ni
CFG
Contents
Write commands not supported in a certain mode can be released immediately after the register address. The ASSP will
resume operation with the next start condition. Registers CAR and TRR are not buffered. Any read operation of the CAR
or TRR register may generate transients in the analog circuitry; further accurate measurements require a delay time for
settling.
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austriamicrosystems
AS8501 - Data Sheet
7.5.1
no.
0
1)
OPM operation mode register ( 4 bits )
Bit
default
mo3
0
mo2
0
mo1
0
mo0
0
Note
1)
This register has been described in detail under 7.4
7.5.2
no.
0
CRG general configuration register ( 28 bits )
CRG bits
27-22
CRS
21-11
CRI
10-7
CRV
6-0
CRP
NOTE
Nr.
0
1
Bits
CRS bit
names
Default
5
s3
4
s2
3
s1
2
s0
1
d
0
c
0
0
0
1
1
1
al
id
subregister CRS: Sequence length, dechop and chop ( 6 bits )
NOTE
1)
2)
lv
Notes:
1) This register defines the sequence length, chopping (c) and dechopping (d) of the input signal
2) Default power-up state before any setting
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Sequence length bits ( 4bits)
Nr.
0
No. of measurements
16
s3
0
s2
0
s1
0
s0
0
1
1
0
0
0
1
…
…
…
…
…
…
14
14
1
1
1
0
15
15
1
1
1
1
NOTE
1)
default
Notes:
1)Number of consecutive measurements of A and B with settings defined in CRA,CRB
and other settings in CRG register. This setting is used only for mode MMD.
DECHOPPING BIT
Dechopping
No dechopping
d
0
1
Dechopping
1
CHOPPING BIT
NOTE
ca
Nr.
0
Chopping
No chopping
c
0
1
chopping
1
NOTE
ni
Nr.
0
ch
subregister CRI: Current configuration ( 11 bits )
10
M14
9
M13
8
M12
7
M11
6
M8
5
M6
4
i4
3
i3
2
I2
1
i1
0
i0
1
Bits
CRI bit
names
Default
0
0
0
0
0
0
0
0
0
0
0
2
output
VBAT
RSHL
RSHH
no
ETS
ETR
Te
Nr.
0
NOTE
1),3)
2)
Notes:
1) whenever M1=1 in (CRA,CRB) it is good practice to set all M6 to M14 to zero, but it is not mandatory
2) default logic state after power up and before any setting
3) All bits with names M14 to M1 represent control signals of the multiplexer with positive logic (for example M14=1
means that corresponding switch is closed).
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AS8501 - Data Sheet
Current source setting bits (5 bits)
Current [uA]
0
i4
0
i3
0
i2
0
i1
0
i0
0
1
8
0
0
0
0
1
2
16
0
0
0
1
0
3
24
0
0
0
1
1
4
32
0
0
1
0
0
…
…
…
…
…
…
31
248
1
1
1
1
1
NOTE
al
id
Nr.
0
subregister CRV: Voltage configuration (4 bits )
3
M15
2
M10
1
M9
0
M7
1
Bits
CRV bit
names
Defaults
NOTE
0
0
0
0
2
channel
VBATRSHL
VBAT-ETS
differential
ETS-RSHL
ETRRSHL
lv
1),3)
2)
am
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Nr.
0
Notes:
1) This register defines the connection of the analog voltage- bus to the input-PINs and to the A/D converter
2) Default logic state after power-up and before any setting
subregister CRP: Power down configuration ( 7 bits )
Nr.
0
1
Bits
CRP bit
names
Defaults
2
block
p6
pdosc
p5
pda
p4
pdm
p3
pdb
p2
pdc
p1
pdi
p0
pdg
0
0
0
0
1
0
0
modulator
ref. bias
current
source
internal
temp.
analog
GND
oscillator amplifier
NOTE
1),3)
2)
Notes:
1) This register defines the power-down signals of the building blocks
2) Default power-up state before any setting
3) The logic is positive (pdosc=1 means the corresponding block is in power-down)
CRA measurement channel A configuration register ( 17 bits )
1
Bits
CRA bit
names
Defaults
2
subreg.
16
cu2
15
cu1
14
cu0
13
M5
12
M4
11
M3
10
M2
9
M1
8
g1
7
g0
6
f
5
r
0
0
0
0
0
0
0
1
1
1
1
0
0
OSF
OSR
MM
ni
Nr.
0
ca
7.5.3
CRU
CRM
GN
4
3 2
mm n3 n2
0
0
1
n1
0
n0
0
0
NOTE
1), 3)
2)
CRN
Te
ch
Notes:
1) This register defines the measurement channel A configuration
2) Default power-up state before any setting
3) Bit M1 is control signal of the multiplexer for current input
(for example M1=1 means that corresponding switch is closed).
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AS8501 - Data Sheet
subregister CRU: calibration constant selection for voltage path ( 3 bits) in registers CRA,CRB
Calibration const. U
CAU0
cu2 cu1 cu0
0
0
0
1
CAU1
0
0
1
2
CAU2
0
1
0
3
CAU3
0
1
1
4
CAU4
1
0
0
5
CAU5
1
0
1
6
1548
1
1
0
7
1548
1
1
1
NOTE
al
id
Nr.
0
Bits
CRA bit
names
Defaults
1
13
M5
12
M4
11
M3
10
M2
9
M1
0
0
0
0
1
measurement RSHH-RSHL
1
0
0
0
voltage bus
1
0
1
0
voltage bus, internal temperature
1
1
0
0
voltage bus, reference low=RSHL
0
0
0
0
voltage bus, gain=1
0
0
1
0
voltage bus,gain=1, internal temperature
0
1
0
0
voltage bus, gain=1, reference low=RSHL
2
0
3
0
4
0
5
1
6
1
7
1
NOTE
1), 2)
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Nr.
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subregister CRM: measurement path for registers CRA,CRB
Notes:
1) these bits define the inner part of the voltage path settings
2) only the listed combinations are allowed
subregister GN: gain definition bits, Registers CRA,CRB
Nr.
0
1
g1
0
g0
0
24
0
1
50
1
0
ca
2
GAIN
6
3
100
1
NOTE
1
Nr.
0
Fovs (fclk=8MHz)
2.048MHz
Fovs (internal osc)
132kHz
f
0
4.096MHz
264kHz
1
ch
1
ni
subregister OSF: oversampling frequency bit, Registers CRA,CRB
NOTE
1)
1)
Te
Notes:
1) For internal oscillator typical values
subregister OSR: oversampling ratio bit, Registers CRA, CRB
Nr.
0
R1
64
r
0
1
128
1
Revision 1.1, 04-April-06
NOTE
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austriamicrosystems
AS8501 - Data Sheet
subregister MM: chopping ratio bit, Registers CRA, CRB
Nr.
0
MM
4
mm
0
1
8
1
2
1
x
NOTE
1)
Notes:
1) For c=0 and d=0 , chopping and dechopping is switched off and every cycle is active regardless
of mm, i.e. the sampling frequenzy is higher by a factor of 4
R2
1
n3
0
n2
0
n1
0
n0
0
NOTE
1
2
0
0
0
1
2
4
0
0
1
0
3
8
0
0
1
1
4
16
0
1
0
0
5
32
0
1
0
1
64
0
1
1
0
128
0
1
1
1
256
1
0
0
0
512
1
0
0
1
1024
1
0
1
0
11-14
Reserved for test
1
x
x
x
1)
15
raw mode
1
1
1
1
2)
am
lc s
on A
te G
nt
st
il
lv
Nr.
0
al
id
subregister CRN: averaging bits ( 4 bits), registers CRA,CRB
6
7
8
9
10
Note:
1) combinations from B to E are reserved for test
2) this mode delivers the AD-values without calibration and averaging but multiplied by a factor which is dependent on the
setting of the oversampling ratio. It can be used for high resolution measurements of very low signals since it eliminates
the internal rounding error.
The ratio between raw result (Nr) and normal result (Nn) is given by: Nr/Nn = 2^(11+x)/CAL where x=6 for R=128 and x=3
for R=64. CAL is the calibration constant used.
2
subreg.
16
cu2
15
cu1
14
cu0
13
M5
ni
1
Bits
CRB bit
names
Defaults
0
0
CRU
0
0
12
M4
11
M3
10
M2
9
M1
8
g1
7
g0
6
f
5
r
4
mm
3
n3
2
n2
1
n1
0
n0
1
1
0
0
0
1
1
0
0
0
0
0
0
OSF
OSR
MM
CRM
GN
NOTE
1), 3)
2)
CRN
ch
Nr.
0
CRB measurement channel B configuration register ( 17 bits )
ca
7.5.4
Te
Notes:
1) This register defines the measurement channel B configuration, the functions of the subregisters are the same as
described above for measurement channel A
2) Default power-up state before any setting
3) In this mode the chip cannot measure the current sensing input RSHH-RSHL, therefore M1=0 for all settings
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AS8501 - Data Sheet
7.5.5
ZZR Zener-Zap register (188 bits )
Nr.
0
ZZR bits
183-187
ZLO
163-182
ZTR
53-162
ZCL
0-52
ZTC1)
NOTE
2)
Notes:
1) 5 bits are reserved for:
- 1 bit eventually destroyed during testing,
- 2 bits for testing programmed 0 and 1
- 2 bits reserved for locking
2) due to a limited driving capability of the ZZR-cells the maximum reading speed is limited to 500 kHz
Nr.
1
Name
Reserved bits
SYMBOL
ZLO
WORD WIDTH
5
Default Hex
F
subregister ZTR: trimming bits (20 bits)
SYMBOL
Default
Dec1)
0
UNIT
TC of reference
TRIMBTC
1
absolute value of reference
TRIMBV
5
0
Bits
2
amplifier offset
TRIMA
5
0
Bits
3
current source for external
temperature
∑ trim bits
TRIMC
5
0
Bits
TRIMREG
20
Bits
NOTE
lv
0
WORD
WIDTH
5
4
PARAMETER
am
lc s
on A
te G
nt
st
il
Nr.
al
id
subregister ZLO: Zener spare bits ( 5 bits )
Bits
Notes:
1) Default values must be written before start of the test
subregister ZCL: calibration bits ( 110 bits )
PARAMETER
SYMBOL
0
Calibration G=6, I
CGI1
WORD
WIDTH
11
1
Calibration G=24, I
CGI2
11
1548
Bits
1),4)
2
Calibration G=50, I
CGI3
11
1548
Bits
1),4)
3
Calibration G=100, I
CGI4
11
1548
Bits
1),4)
4
Calibration U0
CAU0
11
1548
Bits
1),4)
5
Calibration U1
CAU1
11
1548
Bits
1),4)
6
Calibration U2
CAU2
11
1548
Bits
1),4)
7
Calibration U3
CAU3
11
1548
Bits
1),4)
8
Calibration U4
CAU4
11
1548
Bits
1),4)
9
Calibration U5
CAU5
11
1548
Bits
2),4)
10
∑ cal. Bits
ZCL
110
ch
ni
ca
Nr.
Default
Dec3)
1548
UNIT
NOTE
Bits
1),4)
Bits
Te
Notes:
1) Decimal default value of the calibration constant for voltage and current is calculated
using formula: CGdef=Nmax/NADdef=(Vref*1024)/(Vin*Gmax)=1548
2) Default calibration constant for absolute value of the voltage proportional to absolute
temperature is the same as for any other range because it uses the same amplifier and
max voltage at max. temperature is approx. 150mV and the gain selected must be g0.
3) Default values must be written before start of the test
4) Calibration constants are selected dependent on state of M1 ( see table below). For M1=1 one of
CGI1 to CGI4 is selected according to selected gain of amplifier. For M1=0 the selection of the
calibration constants is defined by bits (cu2,cu1,cu0), which are part of CRA and CRB registers and
are defined via SDI interface independently of any other selection.
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AS8501 - Data Sheet
CAL CONST
CGI1
1)
NOTE
x
x
x
1
0
1
CGI2
1)
2
x
x
x
1
1
0
CGI3
1)
3
x
x
x
1
1
1
CGI4
1)
4
0
0
0
0
x
x
CAU0
2)
5
0
0
1
0
x
x
CAU1
2)
6
0
1
0
0
x
x
CAU2
2)
7
0
1
1
0
x
x
CAU3
2)
8
1
0
0
0
x
x
CAU4
2)
9
1
0
1
0
x
x
CAU5
2)
10
1
1
0
0
x
x
1548
11
1
1
1
0
x
x
1548
am
lc s
on A
te G
nt
st
il
1
al
id
g0
0
lv
Calibration constant selection truth table
Nr.
cu2 cu1 cu0 M1 g1
x
x
x
1
0
0
Notes:
1) CGIx calibration constants are selected when M1=1 according to selected gain
2) CGUx calibration constants are selected when M1=0 according to bits cu2 to cu0 defined via SDI in CRA and/or CRB
registers.
Te
ch
ni
ca
Subregister ZTC: see register mapping 8.2.6
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austriamicrosystems
AS8501 - Data Sheet
7.5.6
CAR calibration register ( 110 bits )
The calibration register holds the calibration constants that are used by the internal DSP for the correction of each
measurement. At power-up sequence the Zener-Zap subregister ZCL is copied into the CAR register as shown in fig.
7.4.6.1. The register can be read or written in mode 8 via the SDI bus at any time. In particular it is possible to write
preliminary calibration constants with CAR or overwrite the loaded ZCL data, if a calibration has been changed.
1
CAR bits 109-99 98-88
Subregister CGI1 CGI2
default
1548
87-77
CGI3
76-66
CGI4
65-55
CAU0
54-44
CAU1
43-33
CAU2
32-22
CAU3
21-11
CAU4
10-0
CAU5
1548
1548
1548
1548
1548
1548
1548
1548
1548
NOTE
1), 2)
Notes:
1)
Calibration register is composed of the following constants each having 11 bits:
CGI1, CGI2, CGI3, CGI4, CAU0, CAU1, CAU2, CAU3, CAU4, CAU5
2) This register can be read or written at any time via the SDI bus. In particular it is possible to write
preliminary
calibration constants with CAR or overwrite the loaded ZCL data, if a calibration has been
changed.
7.5.7
TRR trimming register ( 20 bits )
al
id
Nr.
0
Nr.
0
TRR bits
Subregister
1
default
am
lc s
on A
te G
nt
st
il
lv
In the TRR register the calibration constants for the reference voltage, for the amplifier-offset trim and for the current source setting are stored.
At power-up sequence the Zener-Zap subregister ZTR is loaded into the TRR register. This register can be read or written in mode 8 via the
SDI bus. In particular it is possible to write preliminary calibration constants into TRR or overwrite the loaded ZTR data, if a calibration has been
changed. The trimming of the TRR-registors is usually done at the factory before supplying the part.
19-15
TRIMC
14-10
TRIMA
9-5
TRIMBV
4-0
TRIMBTC
0
0
0
0
NOTE
1)
Notes:
1)writing into TRR register is done as usual with the MSB first
subregister TRIMC
change of current source output with TRIMC bits
trimcs
trimc3
trimc2
trimc1
trimc0
dI/Io
%
Notes
0
0
0
0
0
0
0
1),2)
1
0
0
0
0
1
-1*2.3
1),2)
2
0
0
0
1
0
-2*2.3
1),2)
..
..
..
..
..
..
..
14
0
1
1
1
0
–14*2.3
1),2)
15
0
1
1
1
1
–15*2.3
1),2)
16
17
1
1
0
0
0
0
0
0
0
1
16*2.3
15*2.3
1),2)
18
1
0
0
1
0
14*2.3
1),2)
..
..
..
..
..
..
..
30
1
1
1
1
0
2*2.3
31
1
1
1
1
1
1*2.3
ch
ni
ca
Nr.
1),2)
Te
Notes:
1) Io is the current in µ A at TRIMC = 00000
2) The output current of the internal current source can be controlled in a wide range via the bit setting in CRG. In some applications it may be
necessary to trim the current in the rang of +/- 30% for an optimum result of the external temperature measurement. This trimming is achieved
with writing into subregister TRIMC of the TRR register. The trimming is done in % for all ranges selected in CRG register.
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AS8501 - Data Sheet
subregister TRIMA
change of amplifier offset with TRIMA bits
The offset of the PGA should be trimmed to a mimimum absolute value to guarantee the
full dynamic range with all gain settings.
trima3
trima2
trima1
trima0
Voffset
mV
Notes
0
0
0
0
0
0
Uos
1),2) ,3)
1
0
0
0
0
1
Uos -1*1.34
1),2)
2
0
0
0
1
0
Uos -2*1.34
1),2)
..
..
..
..
..
..
..
14
0
1
1
1
0
Uos –14*1.34
1),2)
15
0
1
1
1
1
Uos –15*1.34
1),2)
16
17
1
1
0
0
0
0
0
0
0
1
Uos
Uos +1*1.34
1),2)
18
1
0
0
1
0
Uos +2*1.34
1),2)
..
..
..
..
..
..
..
30
1
1
1
1
0
Uos +14*1.34
31
1
1
1
1
1
Uos +15*1.34
am
lc s
on A
te G
nt
st
il
1),2)
al
id
trimas
lv
Nr.
Notes:
1) Uos is the input offset voltage in mV at TRIMA = 00000
2) Every step of TRIMA settings brings $offset=1.34 mV change in absolute value of the input offset voltage.
If the measured value is Uos then the number that should be written into the TRIMA for minimum
final absolute value is calculated as TRIMA=int((Uos)/1.34) for Uos above zero and
TRIMA=16+int(-Uos)/1.34) for Uos below zero.
3) The input offset voltage can be measured with chopping and dechopping bits being cleared in register CRG.
Any input channel as well as gain settings can be used. The input should be shorted to avoid any external voltages to interfere with the
measurement. If the measured output voltage is Va then the offset voltage is calculated acc. Vos = Va/gain.
subregister TRIMBV
Nr.
trimbvs
trimbv3
trimbv2
trimbv1
trimbv0
VREF
mV
0
0
0
0
0
0
Ua
1),2)
1
0
0
0
0
1
Ua -1*5.1
1),2)
2
0
0
0
1
0
Ua -2*5.1
1),2)
..
..
..
ca
change of reference voltage Uo with TRIMBV bits
..
0
..
..
1
1
1
0
Ua –14*5.1
1),2)
15
0
1
1
1
1
Ua –15*5.1
1),2)
16
17
1
1
0
0
0
0
0
0
0
1
Ua
Ua +1*5.1
1),2)
18
1
0
0
1
0
Ua +2*5.1
1),2)
..
..
..
..
..
..
..
30
1
1
1
1
0
Ua +14*5.1
31
1
1
1
1
1
Ua +15*5.1
1),2)
Te
ch
ni
..
14
Notes
Notes:
1) Ua is the reference voltage in mV at TRIMBTC = 00000, the optimum value is 1.232V.
2) Every step of TRIMBV settings brings $BV=5.1 mV change in absolute value of the reference voltage.
For trimming the TC value and absolute value of the reference voltage it is recommended to trim the TC
value first and then trim the absolute value since TRIMBTC is changing both TC and absolute value, whereas
TRIMBV is changing only the absolute value.
If the measured absolute value is Uam then the number that should be written into the TRIMBV for optimum
final absolute value is calculated as TRIMBV=int((Uam-1.231)/0.0051) for Uam above the ideal value and
TRIMBV=16+int(-(Uam-1.232)/0.0051) for Uam below the ideal value.
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AS8501 - Data Sheet
subregister TRIMBTC
change of reference voltage Uo and TC-value with TRIMBTC bits
trimbtcs
trimbtc3
trimbtc2
1
trimbtc1
1
trimbtc0
VREF
mV
TC
ppm/K
Notes
0
0
0
0
0
0
Uo
TCo
1),2)
1
0
0
0
0
1
Uo -1*5.2
TCo -1*12.7
1),2)
2
0
0
0
1
0
Uo -2*5.2
TCo -2*12.7
1),2)
..
..
..
..
..
..
..
14
0
1
1
1
0
Uo –14*5.2
TCo -14*12.7
1),2)
15
0
1
1
1
1
Uo –15*5.2
TCo -15*12.7
1),2)
16
17
1
1
0
0
0
0
0
0
0
1
Uo
Uo +1*5.2
TCo +1*12.7
18
1
0
0
1
0
Uo +2*5.2
TCo -2*12.7
..
..
..
..
..
..
..
..
30
1
1
1
1
0
Uo +14*5.2
TCo -14*12.7
31
1
1
1
1
1
Uo +15*5.2
TCo -15*12.7
1),2)
1),2)
lv
1),2)
al
id
Nr.
am
lc s
on A
te G
nt
st
il
Notes:
1) Uo is the reference voltage in mV and TCo is the TC value in ppm/K at TRIMBV = 00000
2) Every step of TRIMBTC settings brings $BTC=5.2 mV change in absolute value of the reference voltage and
S=12.7 ppm/K change in the slope of temperature dependence. So for trimming the temperature coefficient of
the band-gap reference 2 measurements are recommended ( at T1=25oC and at T2=125oC ). If the measured TC
value is TCm then the number that should be written into the TRIMBTC for minimum final TC is calculated as
trimBTC=int(TCM/12.7) for positive values and trimBTC=16+int(-TCM/12.7) for negative values.
The absolute voltage is also changed in this way, which must be compensated by bringing back the absolute value by changing the TRIMBV
register. Usually the TRIMBVx=-TRIMBTCx+1 is sufficient. If further accuracy or change of absolute value is necessary it can be adjusted by
making some more measurements and adjustments.
ZZR REGISTER:
ZTR
ZCL
ZTC
5
20
110
53
R/W
TRR
CAR
reg.7
reg.6
Te
bit0
188
bit0
CAR
ch
data in
ni
bit0
ca
ZLO
TRR
ZLO
bit0
Figure 8: Copying of ZCL and ZTR registers into CAR and TRR registers
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austriamicrosystems
AS8501 - Data Sheet
THR alarm (Wake-up) threshold register ( 17 bits )
Nr.
MR16
MR15
MR14
0
A/B
s
Msb
default
0
0
1
MR13
MR12
MR11 … MR1
MR0
NOTE
lsb
0
0
0
1)
Notes:
1) _ All measurements are performed in channel A therefore MR16 must be set to zero. When channel B is selected
no interrupt will be generated.
- The signed value is used. For positive THR values the ASSP will initiate an interrupt whenever the measured
value is bigger than the THR value. For negtive THR values the interrupt will be generated for a negative
result with an absolute value bigger than the absolute value of the THR register.
MSR measurement result register ( 18 bits )
Nr.
MR17
MR16
MR15
MR14
Overflow/un
derflow
A/B
S
msb
MR13
MR12
MR11 … MR1
MR0
lsb
8
am
lc s
on A
te G
nt
st
il
Notes:
1) - Result word length is 16 bits because of calibration accuracy
and to maintain all possible resolutions ( different setting ).
- A/B bit signifies which measurement was performed: the one defined in CRA or CRB:
MR16=0 -> A
MR16=1 -> B
- Overflow/underflow bit is set whenever the result after multiplication by calibration
constant is bigger than 32767 or smaller than –32767.
In Wake-up or Alarm mode the overflow/underflow always sets INTN signal to LO.
NOTE
1)
lv
7.5.9
al
id
7.5.8
Digital interface description
The digital interface of the AS8501 consists of two input pins (CLK and SCLK) and two I/O pins (INTN and SDAT). The SCLK and SDAT pins
are used as universal serial data interface (SDI). SDI operates only if external clock signal (CLK) is running.
8.1
CLK
In all operating modes except the Wake-up mode this pin must be connected to 8 MHz clock signal. In the Wake-up mode (MWU) the CLK pin
must be connected to logic HI or float.
8.2
INTN
The INTN pin is used to signal various conditions to the microcontroller, depending on the operating mode.
Signal
Load clock (internal)
Direction
Output
Purpose
Indicates progress of the Zener-Zap load process
1, 2,7
SDI clock disable
Output
3
idle / wake-up not
Output
Signals new result and suggests when to disable SCLK in
high-precision measurement phase
Signals the wake-up condition
4
idle / alarm not
Output
Signals the alarm condition
5
PW1
Input
Shows the programming pulse width
Logic ‘0’
Output
No purpose
10
t12
Output
Test mode
10
t18
Output
Test mode
ch
Mode
0
ni
ca
application modes of the INTN pin
Te
6,8,9
Note
1)
2)
Notes:
1) 188 clock pulses are generated from the internal oscillator source during the loading time.
2) In measurement modes (MMS and MMD) the INTN pin is used to synchronize the SDI bus operations (See Fig. 9).
The trailing edge of INTN signals the start of a new measurement.
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AS8501 - Data Sheet
i-1
start measurement i
i+1
Tcnv
i-2
i-1
i
lv
available
results on SDI
al
id
INTN
Tres
am
lc s
on A
te G
nt
st
il
Figure 9: INTN pin in modes 1 and 2
The determination of Tcnv and Tres from the parameter settings is:
Tcnv % R1/(fovs*2)
8.3
Tres = MM*Tcnv*R2*2
with R1=OSR and R2=number of averages
SDI bus operation
SDI bus is a 2-line bi-directional interface between one master and one slave unit. Typically the master unit is a microcontroller with softwareimplemented SDI protocol. The ASSP is always the slave unit. SDI bus operation is presented on Figure 10.
During data transfers the sdat signal changes while sclk is low. The sdat signal can change while sclk is high only to generate start or
exception conditions.
Direction
Register data
ca
sclk
Address
ch
ni
SDAT
Start
Data transfer
Exception
Te
Figure 10: SDI bus operation
Strobe ASSP
The master unit always generates the sclk signal.
The master unit generates the sdat signal in start, direction, address, master-write data and exception conditions. The master sdat pin is in
high-impedance state in master-read data condition.
The slave unit drives the sdat signal only in master-read data condition. In all other cases the slave sdat pin is in high-impedance state. During
data transfer in read condition the internal AD-conversion in continuing but the data in the MSR-register is not updated and the output of the
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AS8501 - Data Sheet
INTN signal is suppressed. Only after the completion of the reading cycle the ASSP returns to the normal condition and updates the MSRregister immediately if a new AD-conversion has been finished during data transfer.
The master unit does not detect any bus conditions since it generates them. Data transfer conditions (direction, register address and register
data) must not be changed until the current condition is over. The slave unit does not detect start and exception condition when master-read is
in progress.
The exception condition is reserved for future use and should be avoided.
8.4
Data transfers
al
id
Generally the SDI interface is active in all ASSP modes. For security reasons some write operations are restricted to certain modes. Read
operations are never disabled in order to keep consistent sdat driving conditions.
Writing to the result, trimming and calibration registers (MSR, CAR and TRR) is allowed only in test modes.
Writing to the Zener-Zap register is allowed only in mode MZP.
lv
The first data bit after the start condition in each data transfer defines the data direction: sdat=high is used for master-read data (mr) condition
and sdat=low for master-write data (mw) condition.
sclk
mr
sdat
am
lc s
on A
te G
nt
st
il
Data is transferred with the most significant bit (MSB) first. Data bits are composed of register address and register data bits. Register address
is transmitted first, followed by the register data bits. The register address is always 4 bits long. The number of register data bits in table 7.5 is
implied by the register address.
a3
mw
Direction
a2
a1
a0
MSB
Register address
LSB
Register data
Figure 11: SDI Data transfer
ca
The ASSP supports the data transfers presented in Table 8.1.
master read-write operations
ADDRESS
Contents
read
write allowed in
allowed in
modes
modes
All
All
0
operating mode
CRA
ni
REGISTER
1
measurement set-up A
All
All
CRB
2
measurement set-up B
All
All
CRG
3
general measurement conditions
All
All
MSR
4
measurement result
All
>7
ZZR
5
Zener-Zap data
All
5
CAR
6
calibration register
All
>7
TRR
7
trimming register
All
>7
THR
8
alarm or wake-up threshold register
All
All
Te
ch
OPM
Revision 1.1, 04-April-06
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page
Page 27 of 40
austriamicrosystems
AS8501 - Data Sheet
8.5
SDI bus timing
Timing definitions for SDI bus are based on software-implemented master unit protocol
MDE
DV_m
PW_sclk
DV_m
TS_m
LO_sclk
TS_m
sclk
master sdat
HI - Z
(uP)
slave sdat
DV_s
am
lc s
on A
te G
nt
st
il
TS_s
lv
HI - Z
(ASIC)
al
id
(uP)
TS
CDD
strobe ASSP
strobe µC
Te
ch
ni
ca
Figure 12: SDI Bus timing
Revision 1.1, 04-April-06
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Page 28 of 40
austriamicrosystems
AS8501 - Data Sheet
SDI bus timing
PARAMETER
SYMBOL
MIN
0
SCLK pulse width
PW_sclk
1
SCLK low
LO_sclk
2
5
Master SDAT exception
after SCLK
Master SDAT valid
before/after SCLK
Slave SDAT not valid
after SCLK
Master 3-state ON/OFF
6
Slave 3-state ON/OFF
TS_s
Bus condition detection
disabled in slave unit
CDD
3
4
7
TYP
Unit
Conditions
120
ns
All
120
ns
All
MDE
120
ns
All
DV_m
120
ns
All
ns
Master read
ns
Master read
ns
Master read
ns
Master read
TSW
DV_s
TS_m
MAX
120
TS_s
TSW
120
1)
3)
am
lc s
on A
te G
nt
st
il
8.6
5), 6)
lv
Notes:
1)TSW is typical time required by the microcontroller program to change or to read the state of
the I/O pin
3) Start detection is disabled when slave unit transmits data
5) LO_sclk>300ns and PW_sclk> 2µ sec required to read ZZR.
6) LO_sclk > (3/2)*TCLK = (3/2)/f CLK = (3/2)/8MHz=187.5ns required for results synchronisation in MSR.
NOTE
al
id
Nr.
SDI access to OTP memory
SDI can read the OTP memory in any mode by reading the register ZZR.
8.6.1
ZZR register bit mapping
Cell index
Purpose
0
pos A 1)
ZZR field
ZLO
ZZR bit
187 (msb)
1) Always
1
pos B 2)
2
pos C 3)
ZLO
ZLO
186
185
3
lock A
4
lock B 5)
5
trimcs
6
trimc3
7
trimc2
ZLO
ZLO
ZTR
ZTR
ZTR
184
183
182
181
180
4)
programmed to '0' during the production test
programmed to '0' during the production test
3) Always programmed to '1' during the production test
4) Reserved
5) Reserved
Te
ch
ni
ca
2) Always
Revision 1.1, 04-April-06
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Page 29 of 40
austriamicrosystems
AS8501 - Data Sheet
8
trimc1
9
trimc0
10
trimas
11
trima3
12
trima2
13
trima1
14
trima0
15
trimbvs
ZZR field
ZTR
ZTR
ZTR
ZTR
ZTR
ZTR
ZTR
ZTR
ZZR bit
179
178
177
176
175
174
173
172
Cell index
Purpose
16
trimbv3
17
trimbv2
18
trimbv1
19
trimbv0
20
trimbtcs
21
trimbtc3
22
trimbtc2
23
trimbtc1
ZZR field
ZTR
ZTR
ZTR
ZTR
ZTR
ZTR
ZTR
ZTR
ZZR bit
171
170
169
168
167
166
165
164
Cell index
Purpose
24
trimbtc0
25
cgi1_10
26
cgi1_9
27
cgi1_8
28
cgi1_7
29
cgi1_6
30
cgi1_5
31
cgi1_4
ZZR field
ZTR
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZZR bit
163
162
161
160
159
158
157
156
Cell index
Purpose
32
cgi1_3
33
cgi1_2
34
cgi1_1
35
cgi1_0
36
cgi2_10
37
cgi2_9
38
cgi2_8
39
cgi2_7
ZZR field
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
154
153
152
151
150
149
148
41
cgi2_5
42
cgi2_4
43
cgi2_3
44
cgi2_2
45
cgi2_1
46
cgi2_0
47
cgi3_10
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
146
145
144
143
142
141
140
49
cgi3_8
50
cgi3_7
51
cgi3_6
52
cgi3_5
53
cgi3_4
54
cgi3_3
55
cgi3_2
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
138
137
136
135
134
133
132
57
cgi3_0
58
cgi4_10
59
cgi4_9
60
cgi4_8
61
cgi4_7
62
cgi4_6
63
cgi4_5
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
Cell index
Purpose
40
cgi2_6
ZZR field
ZCL
ZZR bit
147
Cell index
Purpose
48
cgi3_9
ZZR field
ZCL
ZZR bit
139
Cell index
Purpose
56
cgi3_1
ZZR field
ZCL
lv
am
lc s
on A
te G
nt
st
il
155
ni
ca
ZZR bit
al
id
Cell index
Purpose
131
130
129
128
127
126
125
124
64
cgi4_4
65
cgi4_3
66
cgi4_2
67
cgi4_1
68
cgi4_0
69
cau0_10
70
cau0_9
71
cau0_8
ZZR field
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZZR bit
123
122
121
120
119
118
117
116
ZZR bit
Te
ch
Cell index
Purpose
Revision 1.1, 04-April-06
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Page 30 of 40
austriamicrosystems
AS8501 - Data Sheet
75
cau0_4
76
cau0_3
77
cau0_2
78
cau0_1
79
cau0_0
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZZR bit
115
114
113
112
111
110
109
108
Cell index
Purpose
ZZR field
80
cau1_10
ZCL
81
cau1_9
ZCL
82
cau1_8
ZCL
83
cau1_7
ZCL
84
cau1_6
ZCL
85
cau1_5
ZCL
86
cau1_4
ZCL
87
cau1_3
ZCL
ZZR bit
107
106
105
104
103
102
101
100
Cell index
Purpose
88
cau1_2
89
cau1_1
90
cau1_0
91
cau2_10
92
cau2_9
93
cau2_8
94
cau2_7
95
cau2_6
ZZR field
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZZR bit
99
98
97
96
95
94
93
92
Cell index
Purpose
96
cau2_5
97
cau2_4
98
cau2_3
99
cau2_2
100
cau2_1
101
cau2_0
102
cau3_10
103
cau3_9
ZZR field
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZZR bit
91
90
89
88
87
86
85
84
Cell index
Purpose
104
cau3_8
105
cau3_7
106
cau3_6
107
cau3_5
108
cau3_4
109
cau3_3
110
cau3_2
111
cau3_1
ZZR field
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZZR bit
83
82
81
80
79
78
77
76
Cell index
Purpose
112
cau3_0
113
cau4_10
114
cau4_9
115
cau4_8
116
cau4_7
117
cau4_6
118
cau4_5
119
cau4_4
ZZR field
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZZR bit
75
74
73
72
71
70
69
68
Cell index
Purpose
120
cau4_3
121
cau4_2
122
cau4_1
123
cau4_0
124
cau5_10
125
cau5_9
126
cau5_8
127
cau5_7
ZZR field
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZZR bit
67
66
65
64
63
62
61
60
128
cau5_6
129
cau5_5
130
cau5_4
131
cau5_3
132
cau5_2
133
cau5_1
134
cau5_0
135
tcu1_8
ZZR field
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZCL
ZTC
ZZR bit
59
58
57
56
55
54
53
52
ni
Te
ch
Cell index
Purpose
al
id
cau0_6
74
cau0_5
lv
ZZR field
73
am
lc s
on A
te G
nt
st
il
72
cau0_7
ca
Cell index
Purpose
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Page 31 of 40
austriamicrosystems
AS8501 - Data Sheet
139
tcu1_4
140
tcu1_3
141
tcu1_2
142
tcu1_1
143
tcu1_0
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZZR bit
51
50
49
48
47
46
45
44
Cell index
Purpose
144
tcu0_8
145
tcu0_7
146
tcu0_6
147
tcu0_5
148
tcu0_4
149
tcu0_3
150
tcu0_2
151
tcu0_1
ZZR field
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZZR bit
43
42
41
40
39
38
37
36
Cell index
Purpose
152
tcu0_0
153
trt0_10
154
trt0_9
155
trt0_8
156
trt0_7
157
trt0_6
158
trt0_5
159
trt0_4
ZZR field
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZZR bit
35
34
33
32
31
30
29
28
Cell index
Purpose
160
trt0_3
161
trt0_2
162
trt0_1
163
trt0_0
164
tcn3_7
165
tcn3_6
166
tcn3_5
167
tcn3_4
ZZR field
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZZR bit
27
26
25
24
23
22
21
20
Cell index
Purpose
168
tcn3_3
169
tcn3_2
170
tcn3_1
171
tcn3_0
172
tcn2_7
173
tcn2_6
174
tcn2_5
175
tcn2_4
ZZR field
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZZR bit
19
18
17
16
15
14
13
12
Cell index
Purpose
176
tcn2_3
177
tcn2_2
178
tcn2_1
179
tcn2_0
180
tcn1_7
181
tcn1_6
182
tcn1_5
183
tcn1_4
ZZR field
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZTC
ZZR bit
11
10
9
8
7
6
5
4
Cell index
Purpose
184
tcn1_3
185
tcn1_2
186
tcn1_1
187
tcn1_0
ZZR field
ZTC
ZTC
ZTC
ZTC
3
2
1
0
ni
Te
ch
ZZR bit
al
id
tcu1_6
138
tcu1_5
lv
ZZR field
137
am
lc s
on A
te G
nt
st
il
136
tcu1_7
ca
Cell index
Purpose
Revision 1.1, 04-April-06
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Page 32 of 40
austriamicrosystems
AS8501 - Data Sheet
8.6.2
Stored ZZR-register mapping
ZZR-Register
ZCL
ZTC
TRIMC
TRIMA
TRIMBV
TRIMBTC
CGI1
CGI2
CGI3
CGI4
CAU0
CAU1
CAU2
CAU3
CAU4
CAU5
TCU1
TCU0
TRT0
TCN3
TCN2
TCN1
c0
c1
c2
0
c1
1
1
c4
c3
ct
c0
c1
c2
0
c1
1
1
c4
c3
ct
8
c0
c1
c2
0
c1
1
1
c4
c3
ct
1
1
t
bit no. in subregister
7
6
5
4
3
c0
c1
c2
0
c1
1
1
c4
c3
ct
cs
1
t
n23
n
n
c0
c1
c2
0
c1
1
1
c4
c3
ct
cs
1
t
n
n
n
c0
c1
c2
0
c1
1
1
c4
c3
ct
cs
fi
t
n
n
n
x
x
x
x
x
c0
c1
c2
0
c1
1
1
c4
c3
ct
cs
fi
t
n
n
n
x
x
x
x
x
c0
c1
c2
0
c1
1
1
c4
c3
ct
cs
fi
t
n
n
n
ZZR-bits
2
x
x
x
x
x
c0
c1
c2
0
c1
1
1
c4
c3
ct
cs
fi
t
n
n
n
1
x
x
x
x
x
c0
c1
c2
0
c1
1
1
c4
c3
ct
cs
fi
t
n
n
n
0
lsb
x
x
x
x
x
c0
c1
c2
0
c1
1
1
c4
c3
ct
cs
fi
t
n
n
n0
187
182
177
172
167
162
151
140
129
118
107
96
85
74
63
52
43
34
23
15
7
183
178
173
168
163
152
141
130
119
108
97
86
75
64
53
44
35
24
16
8
0
remarks
current source calibration
PGA offset calibration
reference voltage calibration
TC calibration
gain 6
currrent 1500A
gain 24
current 300 A
gain 50
current 150 A
gain100
current 75 A
calibration factor for gain 24
calibration factor for gain 1
calibration factor for gain 100
calibration factor for internal temperature
8 bits for checksum
6 bits for internal clock
11 bits for internal temperature at 23°C
high byte for serial number
medium byte for serial number
low byte for serial number
am
lc s
on A
te G
nt
st
il
ZLO
ZTR
9
al
id
10
msb
lv
ZZR subregister
t
t
1)
2)
x
= these fields are written during calibration
c0 = these fields are written during calibration of G6
c1 = these fields are written during calibration of G24 (i.e. 30 mV = 30 000 digits)
0
= Zero value of calibration constant for detection of unwanted POR
ct = calibration factor for slope of Tint : 75 digits/deg
cs =
8-Bit checksum for ZZR-register
fi =
6-bit for calibration of internal clock
t
= 11 bits for Tint value at 23 °C
nr = 24 bits serial number
Te
ch
ni
ca
Notes:
1) The checksum contains the added value of all bits in the ZZR register without the 6 checksum bits
2) Tthe internal clock frequency can be calculated int_fclk= (240 + 6-bit fi-number) kHz
Revision 1.1, 04-April-06
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Page 33 of 40
austriamicrosystems
AS8501 - Data Sheet
9
General application hints
Since the AS8501 is optimised for low voltage applications extreme care should be taken that the signal is not disturbed by influences like bad ground
reference, external noise pick-up, thermal EMFs generated at the transition of different materials or ground loops. The influence of these error sources
can be quite high and they may completely shadow the excellent properties of the device if not handled properly. The following sections are supposed
to supply additional informations to the design engineer how to get around some of these problems.
9.1
Ground connection, analog common
The analog common terminal where all voltages are referring to is RSHL. All ground lines of the external circuitry of VBAT, ETS and ETR as well as the
al
id
voltage sense line of the low ohmic current sensing resistor should be connected to each other in a star like ground point. It is recommended that this
point is as close as possible situated to the low side sense terminal of the current sensing resistor. It should also be connected to the VSS and VSSD
terminal, but the return line of both must leave this point separately. Also the power decoupling capacitors should be connected to the analog common.
To give an example of the magnitude of possible errors consider that the ground return of the power supply is not connected properly and 5 mm of a
copper track 35µ m thick and 0.1 mm wide are within the measuring circuit with a current flow of 5 mA. This will result in an offset of 120 µ V which is
lv
more than 500 times higher than the typical offset of the ASSP. In addition the current fluctuations will act as an extra noise voltage which is also way
above that of the device itself.
Thermal EMF
am
lc s
on A
te G
nt
st
il
9.2
another major source of error for low level measurements are thermal voltages (electromotive force, thermal EMF) or Seebeck voltages which are
principally produced by any junction of two dissimilar materials. On PC-boards pairs of dissimilar materials may consist of the copper tracks and the
solder, the leads of different components or different materials used in the construction within the components. Any temperature difference between
two connection produces a voltage which is superimposed to the measuring voltage.
A number of strategies are known to detect or minimise their influence on the measuring result:
-
in cases were a current has to be measured directly or a current is to be used to activate a resistive sensor (like
Ohm-meter or temperature measurement with RTDs, NTC or PTC) a switch in the circuit could be used to interrupt or invert the current thus
producing a current change dI. In the difference of the two voltage states dU the EMFs as well as the Offset voltages of the amplifier are fully
eliminated. For resistance measurements this method is known as ‘true Ohm’ measurement.
-
in applications were this is not possible and the problematic device (i.e. the input resistor of an amplifier) can be located it may help to place a
dummy device of the same type in the circuit as close and thermally connected as good as possible to compensate the influence of the first one.
-
Since the thermal EMFs are proportional to the temperature difference it is important to maintain a homogeneous temperature distribution in the
vicinity of the sensitive area. This is possible by keeping this area as small as possible, by avoiding any heat sources nearby or by increasing the
heat conductivity of the substrate, i.e. wide and thick copper tracks, multilayer board or even metal substrate.
The best solution of all however is to avoid the thermal EMFs by using only components which are matched to the copper world which means
that their thermo-electrical power against copper is zero. This is specially important for current measurements in the range of 10- 1000A. In this
ca
-
case the resistance value has to be very low (down to 100µ Ohms) to limit the measuring power and avoid an overheating of the sensing resistor.
ni
On the other hand the voltages to be detected are extremely low if a high resolution is required. If for instance a current of 10 mA has to be
measured with a 100µ Ohm resistor, the resolution of the measuring system must be better than 1µ V and the error voltages due to thermal EMFs
must be below this limit. Quite often people are trying to use the well known Konstantan (CuNi44) for current sensing resistors. This is a bad
ch
choice since the thermal EMF versus copper is very high.
With –40µ V/deg already a temperature difference of
Te
2.5 K is enough to produce an error which is 100 times lager than the required resolution. Or vice versa a temperature fluctuation of only 1/100 K
produces a ‘thermal noise’ which is equivalent to the required resolution.
With such materials and high currents of 10A and above the other thermoelectric effect, the so called Peltier-effect, can also play an important
role. Under current flow this effect generates heat in one junction and destroys the same amount of heat in the other junction. The amount of
heat is proportional to the current and its direction. The result is a temperature difference which in turn generates a thermal EMF proportional to it.
Finally this means that such a resistor produces its own error voltage and it is never possible to measure better than 1-2% with such badly
matched materials. The precision resistance materials Manganin, Zeranin and Isaohm are perfectly matched to the copper world and resistors
made from these materials can achieve the high quality that is necessary for low
Revision 1.1, 04-April-06
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Page 34 of 40
austriamicrosystems
AS8501 - Data Sheet
level measurements and high resolution.
9.3
Noise considerations
for every low level measuring system it is essential to know the origin of noise and to accept the limitations given by it. Three major sources of noise
have to be considered. The input voltage noise and the input current noise of the amplifier and the thermal noise (Johnson noise) of resistors in the
external circuitry around the amplifier. Due to the fact that these three sources are not correlated they can be added in the well known square root
equation.
In most applications the input resistor or input divider is low ohmic (i.e. below 10 kOhms) which mean that the noise voltage produced by the input
current noise is negligible compared to the input voltage noise. The input noise density (En) of the AS8501 is with only 35 nV/sqr(Hz) extremely low.
This could be achieved with a special internal analog and digital chopper circuitry which eliminates the CMOS typical 1/f-noise completely. Even though
The total noise voltage generated at a given frequency resp. in a given frequency band (BW) is given by:
Un= En*sqr(BW)
al
id
the overall noise will be dominated by the input amplifier as long as the external resistors are below 10 kOhm.
lv
This square root dependence can be seen very nicely in fig. 9.10. The typical square-root shaped dependence is found for both the peak to peak noise
as well as for the equivalent RMS noise.
The bandwidth resp. the sampling frequency of the AS8501 can be adapted to the requirements of the application by programming the internal digital
reached.
am
lc s
on A
te G
nt
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filter via the SDI bus. For a sampling frequency of 16kHz the input voltage RMS noise is less than 5µ V, whereas at 500 Hz already 1µ V (or 1LSB) is
If the customer needs even higher resolution at a lower measuring speed the internal integration time can be further increased but due to the limitation
of the digital noise ( 1LSB) it is better to perform an external averaging in the attached µ C. In this way the resolution of the system can be considerably
increased to less than 0.1 µ V for sampling rates of 5 Hz and below which corresponds to an effective AD-converter width of more than 20 bits. (see fig.
9.10)
9.4
Shielding, guarding
In many applications it is difficult to gain full benefit from the AS8501 performance since a number of external error sources can disturb the
measurement. To achieve the maximum performance the design engineer has to take care specially of the layout of the PC-board and the sense
connections to the external components. To avoid noise pick-up from external magnetic fields all tracks on the PC-board should be parallel strip lines
and they should be traced as close as possible to each other. External sensing cables should be twisted and kept away from current carrying cables as
far as possible. For longer cables a shielding is sometimes helpful but care should be taken that the shield is not connected to one of the sense leads.
For an optimum performance it should be open on one side, the other side should be connected to the central (star like) analog common point.
In very sensitive applications it may be wise to use a guard ring around both inputs and it should be connected again to the analog common point. This
procedure minimises leakage currents and parasitic capacitances between different terminals and components on the PC-board.
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EMV interferences can be affectively avoided in most cases by using standard SMD-type high frequency filters in the analog input lines
as well as in the digital output lines.
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AS8501 - Data Sheet
Typical performance characteristics
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Package Dimensions
Thermal Resistance junction / ambient.: 66 K/W (typ.) in still air
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Revision History
Revision
Date
Description
Feb.10,2006
Initial Revision
1.1
March 23, 2006
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12 Ordering Information
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Delivery in Tape and Reel (1 reel = 1500 devices)
Order AS8501-ASOT
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AS8501 - Data Sheet
13
Contact
13.1
Headquarters
austriamicrosystems AG
A 8141 Schloss Premstätten, Austria
Phone: +43 3136 500 0
Fax:
+43 3136 525 01
industry.medical@austriamicrosystems.com
www.austriamicrosystems.com
austriamicrosystems USA, Inc.
Tegernseer Landstrasse 85
8601 Six Forks Road
D-81539 München, Germany
Suite 400
Phone:
+49 89 69 36 43 0
Fax:
+49 89 69 36 43 66
Raleigh, NC 27615, USA
austriamicrosystems Italy S.r.l.
Via A. Volta, 18
Fax:
+39 02 4585 773
Suite 116
San Jose, CA 95117, USA
124, Avenue de Paris
F-94300 Vincennes, France
+33 1 43 74 00 90
Fax:
+33 1 43 74 20 98
+41 55 220 9008
austriamicrosystems UK, Ltd.
88, Barkham Ride,
Finchampstead, Wokingham
Tsim Sha Tsui East, Kowloon, Hong Kong
Tokyo 141-0022, Japan
austriamicrosystems AG
Klaavuntie 9 G 55
ch
FI 00910 Helsinki, Finland
Phone:
+358 9 72688 170
Fax:
+358 9 72688 171
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austriamicrosystems AG
Bivägen 3B
S 19163 Sollentuna, Sweden
Phone:
+46 8 6231 710
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+852 2268 6799
Higashi-Gotanda, Shinagawa-ku
ca
+44 118 973 5117
+852 2268 6899
Fax:
AIOS Gotanda Annex 5th Fl., 1-7-11,
ni
+44 118 973 1797
Fax:
Phone:
austriamicrosystems AG
Berkshire RG40 4ET, United Kingdom
Phone:
+1 509 696 2713
East Wing, 66 Mody Road
CH 8640 Rapperswil, Switzerland
+41 55 220 9001
+1 408 345 1790
Fax:
Suite 811, Tsimshatsui Centre
Rietstrasse 4
Fax:
Phone:
austriamicrosystems AG
austriamicrosystems Switzerland AG
Phone:
+1 509 696 2713
4030 Moorpark Ave
austriamicrosystems France S.A.R.L.
Phone:
+1 919 676 5292
Fax:
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+39 02 4586 4364
Phone:
austriamicrosystems USA, Inc.
I-20094 Corsico (MI), Italy
Phone:
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Sales Offices
austriamicrosystems Germany GmbH
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13.2
Phone:
+81 3 5792 4975
Fax:
+81 3 5792 4976
austriamicrosystems AG
#805, Dong Kyung Bldg.,
824-19, Yeok Sam Dong,
Kang Nam Gu, Seoul
Korea 135-080
Phone:
+82 2 557 8776
Fax:
+82 2 569 9823
austriamicrosystems AG
Singapore Representative Office
83 Clemenceau Avenue, #02-01 UE Square
239920, Singapore
Phone:
+65 68 30 83 05
Fax:
+65 62 34 31 20
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AS8501 - Data Sheet
Disclaimer
Devices sold by austriamicrosystems AG are covered by the warranty and patent identification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the
right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current
information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability
applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application.
The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any
damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind,
in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of
austriamicrosystems AG rendering of technical or other services.
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Devices sold by austriamicrosystems are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems reserves the right
to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems for current
information. This product is intended for use in normal commercial applications.
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Copyright © 2004 austriamicrosystems. Trademarks registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior
written consent of the copyright owner. To the best of its knowledge, austriamicrosystems asserts that the information contained in this publication is accurate and correct. However,
austriamicrosystems shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of
business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation
or liability to recipient or any third party shall arise or flow out of austriamicrosystems rendering of technical or other services.
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